FL7733A [ONSEMI]
Primary-Side-Regulated LED Driver;
| 型号： | FL7733A |
| 厂家： | 
ONSEMI |
| 描述： | Primary-Side-Regulated LED Driver |
| 文件： | 总15页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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December 2014
FL7733A
Primary-Side-Regulated LED Driver with Power Factor
Correction
Features
Description
Performance
The FL7733A is a highly-integrated PWM controller
with advanced Primary-Side Regulation (PSR)
technique to minimize components in low-to-mid-power
LED lighting converters.
.
< 3% Total Constant Current Tolerance Over All
Conditions
< 1% Over Universal Line Voltage Variation
< 1% from 50% to 100% Load Voltage Variation
< 1% with 20% Magnetizing Inductance Variation
Using an innovative TRUECURRENT® technology to
provide tight tolerance constant-current output, this LED
driver enables designs with constant current (CC)
tolerance of less than 1% over the universal line voltage
range to meet stringent LED brightness requirements.
.
Primary-Side Regulation (PSR) Control for Cost-
Effective Solution without Requiring Input Bulk
Capacitor and Secondary Feedback Circuitry
By minimizing turn-on time fluctuation, high power factor
and low THD over the universal line range are obtained
in the FL7733A. An integrated high-voltage startup
circuit implements fast startup and high system
efficiency. During startup, adaptive feedback loop
control anticipates the steady-state condition and sets
initial feedback condition close to the steady state to
ensure no overshoot or undershoot of LED current.
.
.
Application Input Voltage Range: 80 VAC - 308 VAC
High PF of >0.9, and Low THD of < 10% Over
Universal Line Input Range
.
.
Fast < 200 ms Start-up (at 85 VAC) using Internal
High-Voltage Startup with VDD Regulation
Adaptive Feedback Loop Control for Startup without
Overshoot
The FL7733A also provides powerful protections, such
as LED short / open, output diode short, sensing
resistor short / open, and over-temperature for high
system reliability.
System Protection
.
.
.
.
.
.
.
.
LED Short / Open Protection
Output Diode Short Protection
The FL7733A controller is available in an 8-pin Small-
Outline Package (SOP).
Sensing Resistor Short / Open Protection
VDD Over-Voltage Protection (OVP)
VDD Under-Voltage Lockout (UVLO)
Over-Temperature Protection (OTP)
All Protections are Auto Restart (AR)
Cycle-by-Cycle Current Limit
Related Product Resources
FL7733A Product Folder
.
Applications
.
Low to Mid Power LED Lighting Systems of 5 W to
greater than 60 W Compatible with Analog
Dimming function
Ordering Information
Part Number Operating Temperature Range
Package
Packing Method
FL7733AMX
-40°C to +125°C
8-Lead, Small Outline Package (SOP-8)
Tape & Reel
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
Application Diagram
DC Output
AC Input
2
GATE
8
6
1
4
HV
CS
VDD
COMI
VS
3
5
GND
NC
7
Figure 1.
Typical Application
Block Diagram
Shutdown
Max. Duty
Controller
8
HV
Gate Driver
+
2
GATE
250 ms
Timer
EAV
S
R
Q
OCP
1.35 V
Current Limit
Control
VDD
Good
SRSP
Monitor
4
+
VDD
SRSP
VCS-CL
+
VOVP
0.1 V
LEB
1
CS
Sawtooth
Generator
+
VDD
OVP
Internal
Bias
OSC
COMI
6
EAI
+
S
R
Q
3
GND
Error
Amp.
VREF
Line
Compensator
SLP
OCP
DCM
Controller
VDD Good
OTP
SRSP
VS OVP
tDIS
Detector
TRUECURRENT®
Calculation
3 V
VS OVP
SLP
+
7
N.C
EAV
5
Sample & Hold
VS
SLP
Monitor
+
0.3 V
Figure 2.
Functional Block Diagram
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
2
Marking Information
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP)
M: Manufacture Flow Code
ZXYTT
7733A
TM
Figure 3.
Top Mark
Pin Configuration
CS
HV
1
2
3
4
8
7
GATE
GND
VDD
NC
COMI
6
5
VS
Figure 4.
Pin Configuration (Top View)
Pin Descriptions
Pin #
Name
Description
Current Sense. This pin connects a current-sense resistor to detect the MOSFET current for
constant output current regulation.
1
CS
PWM Signal Output. This pin uses the internal totem-pole output driver to drive the power
MOSFET.
2
GATE
Ground
3
4
GND
VDD
Power Supply. IC operating current and MOSFET driving current are supplied using this pin.
Voltage Sense. This pin detects the output voltage and discharge time information for CC
regulation. This pin is connected to the auxiliary winding of the transformer via a resistor divider.
5
6
VS
Constant Current Loop Compensation. This pin is connected to a capacitor between COMI
and GND for compensating the current loop gain.
COMI
7
8
NC
HV
No Connect
High Voltage. This pin is connected to the rectified input voltage via a resistor.
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
HV
VVDD
VVS
HV Pin Voltage
700
30
V
V
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
COMI Pin Input Voltage
GATE Pin Input Voltage
Power Dissipation (TA＜50°C)
-0.3
-0.3
-0.3
-0.3
6.0
V
VCS
6.0
V
VCOMI
VGATE
PD
6.0
V
30.0
633
150
150
260
V
mW
°C
°C
°C
TJ
Maximum Junction Temperature
Storage Temperature Range
TSTG
TL
-55
Lead Temperature (Soldering) 10 Seconds
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Thermal Impedance
TA=25°C, unless otherwise specified.
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Impedance
Junction-to-Case Thermal Impedance
Value
158
Unit
°C/W
°C/W
θJC
39
Note:
3. Referenced the JEDEC recommended environment, JESD51-2, and test board, JESD51-3, 1S1P with minimum
land pattern.
ESD Capability
Symbol
ESD
Parameter
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012
Charged Device Model, JESD22-C101
Value
Unit
5
2
kV
Note:
4. Meets JEDEC standards JESD22-A114 and JESD 22-C101.
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15 V, TJ=-40 to +125°C, unless otherwise specified. Currents are defined as positive into the device and
negative out of device.
Symbol
VDD-ON
Parameter
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
Conditions
Min.
14.5
6.75
3
Typ.
16.0
7.75
4
Max.
17.5
8.75
5
Unit
V
VDD-OFF
V
IDD-OP
CL=1 nF, f=fMAX-CC
mA
μA
V
IDD-ST
Startup Current
VDD=VDD-ON–1.6 V
30
50
VVDD-OVP
VDD Over-Voltage Protection Level
23
24
25
GATE SECTION
TA=25°C, VDD=20 V,
IDD_GATE=1 mA
VOL
Output Voltage Low
Output Voltage High
1.5
V
V
TA=25°C, VDD=10 V,
IDD=1 mA
VOH
5
ISOURCE
ISINK
Peak Sourcing Current(5)
Peak Sinking Current(5)
VDD=10 ~ 20 V
VDD=10 ~ 20 V
-60
mA
mA
180
TA=25°C, VDD=15 V,
CLOAD =1 nF
tR
Rising Time
100
20
150
60
200
100
18
ns
ns
V
TA=25°C, VDD=15 V,
CLOAD=1 nF
tF
Falling Time
VDD=20 V, VCS=0 V,
VVS=0 V, VCOM=0 V
VCLAMP
Output Clamp Voltage
12
15
HV STARTUP SECTION
TA=25°C, VIN=90 VAC
VDD =0 V
,
IHV
Supply Current From HV Pin
9
mA
μA
ms
IHV-LC
tR-JFET
Leakage Current after Startup
1
10
JFET Regulation Time after
Startup(5)
TA=25°C
190
250
310
VJFET-HL
VJFET-LL
JFET Regulation High Limit Voltage
JFET Regulation Low Limit Voltage
17.5
11.5
19.0
13.0
20.5
14.5
V
V
CURRENT-ERROR-AMPLIFIER SECTION
gM
Transconductance(5)
TA=25°C
11
12
17
18
23
24
μmho
μA
TA=25°C, VEAI=2.55 V,
VCOMI=5 V
ICOMI-SINK
COMI Sink Current
TA=25°C, VEAI=0.45 V,
VCOMI=0 V
ICOMI-SOURCE |COMI Source Current|
12
18
24
μA
VCOMI-HGH
VCOMI-LOW
COMI High Voltage
COMI Low Voltage
VEAI=0 V
VEAI=5 V
4.7
V
V
V
0.1
VCOMI_INT.CLP Initial COMI Clamping Voltage(5)
tCOMI_INT.CLP
Time for Initial COMI Clamping(5)
1.2
15
ms
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
VDD=15 V, TJ=-40 to +125°C, unless otherwise specified. Currents are defined as positive into the device and
negative out of device.
Symbol
VOLTAGE-SENSE SECTION
tDIS-BNK tDIS Blanking Time of VS
IVS-BNK
Parameter
Conditions
Min.
Typ.
Max.
Unit
(5)
0.85
-75
1.15
-90
1.45
-105
μs
VS Current for VS Blanking
μA
VS Level for Output Over-Voltage
Protection
VVS-OVP
VVS-LOW-CL-EN
VVS-HIGH-CL-DIS
VVS-SLP-TH
2.95
0.25
0.54
0.25
3.00
0.30
0.60
0.30
15
3.15
0.35
0.66
0.35
V
V
VS Threshold Voltage to Enable Low
Current Limit(5)
VS Threshold Voltage to Disable
Low Current Limit(5)
V
VS Threshold Voltage for Output
Short-LED Protection
V
VS Detection Disable Time after
Startup(5)
tSLP-BNK
TA=25°C
ms
CURRENT-SENSE SECTION
VRV
tLEB
Reference Voltage
TA=25°C
1.485
1.500
300
500
100
1.0
1.515
V
ns
ns
ns
V
Leading-Edge Blanking Time(5)
Minimum On Time in CC(5)
tMIN
VCOMI=0 V
tPD
Propagation Delay to GATE Output
High Current Limit Threshold
Low Current Limit Threshold
50
0.9
150
1.1
VCS-HIGH-CL
VCS-LOW-CL
0.16
0.20
0.24
V
Low Current Mode Operation Time
at Startup(5)
tLOW-CM
VCS-SRSP
VCS-OCP
VCS / IVS
20
ms
V
VCS Threshold Voltage for Sensing
Resistor Short Protection
0.1
VCS Threshold Voltage for Over-
Current Protection
TA=25°C
1.20
1.35
21.5
1.50
V
Relation of Line Compensation
Voltage and VS Current(5)
V/A
OSCILLATOR SECTION
fMAX-CC
fMIN-CC
tON-MAX
Maximum Frequency in CC
TA=25°C, VS=3.0 V
TA=25°C, VS=0.3 V
TA=25°C, f=fMAX-CC
65
70
75
kHz
kHz
μs
Minimum Frequency in CC
Maximum Turn-On Time
23.0
11.0
26.5
13.0
30.0
15.0
OVER-TEMPERATURE-PROTECTION SECTION
TOTP
Threshold Temperature for OTP(5)
150
10
oC
oC
Restart Junction Temperature
Hysteresis(5)
TOTP-HYS
Note:
5. These parameters, although guaranteed by design, are not production tested.
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
6
Typical Performance Characteristics
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-40
-40
-40
-20
0
0
0
25
50
75
100
125
125
125
-40
-40
-40
-20
0
0
0
25
50
75
100
125
125
125
Temperature (℃)
Temperature (℃)
Figure 5.
VDD-ON vs. Temperature
Figure 6.
VDD-OFF vs. Temperature
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-20
25
50
75
100
-20
25
50
75
100
Temperature (℃)
Temperature (℃)
Figure 7.
IDD-OP vs. Temperature
Figure 8.
VDD-OVP vs. Temperature
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-20
25
50
75
100
-20
25
50
75
100
Temperature (℃)
Temperature (℃)
Figure 9.
fMAX-CC vs. Temperature
Figure 10. fMIN-CC vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-40
-20
0
25
50
75
100
125
125
125
-40
-40
-40
-20
0
25
50
75
100
125
125
125
Temperature (℃)
Temperature (℃)
Figure 11. VVR vs. Temperature
Figure 12. Gm vs. Temperature
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-40
-20
0
25
50
75
100
-20
0
25
50
75
100
Temperature (℃)
Temperature (℃)
Figure 13. ICOMI-SOURCE vs. Temperature
Figure 14. ICOMI-SINK vs. Temperature
1.5
1.3
1.1
0.9
0.7
0.5
1.5
1.3
1.1
0.9
0.7
0.5
-40
-20
0
25
50
75
100
-20
0
25
50
75
100
Temperature (℃)
Temperature (℃)
Figure 15. VVS-OVP vs. Temperature
Figure 16. VCS-OCP vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
8
Functional Description
VDD = VDD_ON
FL7733A is AC-DC PWM controller for LED lighting
applications. TRUECURRENT® technology regulate
accurate constant LED current independent of input
voltage, output voltage, and magnetizing inductance
variations. The DCM control in the oscillator reduces
conduction loss and maintains DCM operation over a
wide range of output voltage, which implements high
power factor correction in a single-stage flyback or
buck-boost topology. A variety of protections, such as
LED short / open protection, sensing resistor short /
open protection, over-current protection, over-
temperature protection, and cycle-by-cycle current
limitation stabilize system operation and protect external
components.
High Line
VIN
Low line
Current Mode
Voltage Mode
VCS
0.2 V
VCOMI
Low line
High Line
1.0 V
15 ms
Startup Time 20 ms
ILED
Startup
Time
At startup, an internal high-voltage JFET supplies
startup current and VDD capacitor charging current, as
shown in Figure 17. When VDD reaches 16 V, switching
begins and the internal high-voltage JFET continues to
supply VDD operating current for an initial 250 ms to
maintain VDD voltage higher than VDD-OFF. As the output
voltage increases, the auxiliary winding becomes the
dominant VDD supply current source.
Figure 18. Startup Sequence
PFC and THD
In the flyback or the buck-boost topology, constant turn-
on time and constant frequency in Discontinuous
Conduction Mode (DCM) operation can achieve high PF
and low THD, as shown in Figure 19. Constant turn-on
time is maintained by the internal error amplifier and a
large external COMI capacitor (typically over 1 µF) at
COMI pin. Constant frequency and DCM operation are
managed by DCM control.
VDC
RVS1
CVDD
RVS2
Primary current
peak envelope
Secondary current
peak envelope
HV
VDD
Average
input current
8
4
VS
250 ms
Timer
5
VDD Good
Internal
Bias
16 V /
7.75 V
Constant tON
Constant tOFF
Figure 17. Startup Block
Figure 19. Power Factor Correction
Switching is controlled by current-mode for 20 ms after
VDD-ON. During current-mode switching with the flyback
or buck-boost topology, output current is only
determined by output voltage. Therefore, the output
voltage increases with constant slope, regardless of line
voltage variation. Short-LED Protection (SLP) is enabled
after the 15 ms SLP blanking time so that the output
voltage is higher than SLP threshold voltage and
successful startup is guaranteed without SLP in normal
condition.
Constant-Current Regulation
The output current can be estimated using the peak
drain current and inductor current discharge time
because output current is the same as the average of
the diode current in steady state. The peak value of the
drain current is determined by the CS peak voltage
detector. The inductor current discharge time (tDIS) is
sensed by a tDIS detector. With peak drain current,
inductor current discharging time and operating
switching period information, the TRUECURRENT®
calculation block estimates output current as follows:
During current-mode switching, COMI voltage, which
determines turn-on time in voltage mode, is adjusted
close to the steady state level. The COMI capacitor is
charged to 1.2 V for 15 ms and adjusted to a modulated
level inversely proportional to VIN peak value for 5 ms.
Turn-on time right after 20 ms startup time can be
controlled close to steady state on time so that voltage
mode is smoothly entered without LED current
overshoot or undershoot.
tDIS
1
2
1
Io
VCS nPS
t
RS
S
tDIS
VCS 0.25
t
S
nPS
Io 0.125
RS
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
9
where, nPS is the primary-to-secondary turn ratio
and RS is a sensing resistor connected between the
source terminal of the MOSFET and ground.
Gate
Driver
GATE
2
CC
Control
OSC
VCS
Ipk
=
RS
ID.pk
VOUT
tDIS
Detector
IO
VS
5
DCM
Controller
S/H
ID
IDS
Figure 21. DCM and BCM Control
Na
Ns
VF ·
IpkTdis
nVo
Iavg
Na
Ns
T
Lm
Vo ·
Ipk
Ipk
Ipk
T
Tdis
Ipk
4/3
T
Tdis
3
Iavg
n
Vo
4/3
4
tDIS
tON
Lm
tS
Figure 20. Key Waveforms for Primary-Side
Regulation
4
3
4
T
Tdis
3
Ipk
5/3
Tdis
3
5
Iavg
n
Vo
The output of the current calculation is compared with
an internal precise voltage reference to generate an
error voltage (VCOMI), which determines the MOSFET’s
turn-on time in voltage-mode control. With this
Fairchild’s innovative TRUECURRENT® technology,
constant-current output can be precisely controlled.
Although the output current is calculated with accurate
method the output current at high input voltage may still
be higher than that at low input voltage due to
MOSFET's turn off propagation delay caused by high
Qg. To maintain tight CC regulation over the entire input
voltage range, a line compensation resistor of 100 ~
500 can be inserted between the CS pin and the
source terminal of the MOSFET. The voltage across by
compensation resistor is dependent on current flow out
of the CS pin for MOSFET turn-on and it is proportional
to input voltage.
5/3 T
Lm
5
3
5
3
T
Tdis
Figure 22. Primary and Secondary Current
BCM Control
The end of secondary diode conduction time could
possibly be behind the end of a switching period set by
DCM control. In this case, the next switching cycle starts
at the end of secondary diode conduction time since
FL7733A doesn’t allow CCM. Consequently, the
operation mode changes from DCM to Boundary
Conduction Mode (BCM).
Analog Dimming Function
DCM Control
Analog dimming function can be implemented by
controlling COMI voltage which determines the turn-on
time of main power MOSFET. Figure 23 shows an
example analog dimming circuit for the FL7733A which
uses a photo-coupler so the LED current can be
controlled by the dimming signal, A-Dim, from the
secondary side of the isolation transformer.
As mentioned above, DCM should be guaranteed for
high power factor in flyback topology. To maintain DCM
across a wide range of output voltage, the switching
frequency is linearly adjusted by the output voltage in
linear frequency control in the whole Vs range. Output
voltage is detected by the auxiliary winding and the
resistive divider connected to the VS pin, as shown in
Figure 21. When the output voltage decreases,
secondary diode conduction time is increased and the
DCM control lengthens the switching period, which
retains DCM operation over the wide output voltage
range, as shown in Figure 22. The frequency control
lowers the primary rms current with better power
efficiency in full-load condition.
COMI
VDC
ICOMI
CCOMI
A-Dim Signal
(0 ~ VDC
)
Figure 23. Analog Dimming Control
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
10
Short-LED Protection (SLP)
8
4
HV
-
VDD
In case of a short-LED condition, the secondary diode is
stressed by high current. When VS voltage is lower than
0.3 V due to a short-LED condition, the cycle-by-cycle
current limit level changes to 0.2 V from 1.0 V and SLP
is triggered if the VS voltage is less than 0.3 V for four
(4) consecutive switching cycles. Figure 24 and Figure
25 show the SLP block and operational waveforms
during LED-short condition. To set enough auto-restart
time for system safety under protection conditions, VDD
is maintained between 13 V and 19 V, which is higher
than UVLO, for 250 ms after VDD-ON. SLP is disabled for
an initial 15 ms to ensure successful startup in normal
LED condition.
+
19 V /
13 V
250 ms
Timer
+
-
VDD
VDD
Good
16 V /
7.75 V
VDD OVP
VDD-OVP
EAV
S/H
5
VS
VS OVP
VS-OVP
8
HV
VDD
-
Figure 26. Internal OVP Block
+
19 V /
13 V
LED Open
VOUT
Ns
250 ms
Timer
V
DD-OVP x
Na
VDD
Good
+
-
4
VDD
16 V /
7.75 V
15 ms
Timer
EAV
3 V
SLP is disabled
for initial 15 ms
S/H
0.3 V
SLP
5
VS
VDD
VDD-OVP
19 V
VDD ON
Figure 24. Internal SLP Block
13 V
VDD OFF
LED short
250 ms JFET regulation
VIN
Gate
VCS
Figure 27. Waveforms in LED Open Condition
Sensing Resistor Short Protection (SRSP)
0.2 V
VDD
In a sensing resistor short condition, the VCS level is
almost zero and pulse-by-pulse current limit or OCP is
not effective. The FL7733A is designed to provide
sensing resistor short protection for both current and
voltage mode operation. If the VCS level is less than
0.1 V in the first switching cycle, the GATE output is
stopped by current-mode SRSP. After 20 ms startup
time, the GATE is shut down by the voltage-mode
SRSP if VCS level is less than 0.1 V at over 60% level of
peak VIN.
19 V
VDD-ON
13 V
VDD OFF
250 ms JFET regulation
Gate
15 ms
15 ms
Figure 25. Waveforms in Short-LED Condition
Under-Voltage Lockout (UVLO)
Open-LED Protection
The VDD turn-on and turn-off thresholds are fixed
internally at 16 V and 7.75 V, respectively. During
startup, the VDD capacitor must be charged to 16 V
through the high-voltage JFET to enable the FL7733A.
The VDD capacitor continues to supply VDD until auxiliary
power is delivered from the auxiliary winding of the main
transformer. VDD should remain higher than 7.75 V
during this startup process. Therefore, the VDD capacitor
must be adequate to keep VDD over the UVLO threshold
until the auxiliary winding voltage is above 7.75 V.
FL7733A protects external components, such as output
diodes and output capacitors, during open-LED
condition. During switch turn-off, the auxiliary winding
voltage is applied as the reflected output voltage.
Because the VDD and VS voltages have output voltage
information through the auxiliary winding, the internal
voltage comparators in the VDD and VS pins can trigger
output Over-Voltage Protection (OVP), as shown in
Figure 26 and Figure 27.
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
11
regulated properly. If the sensing resistor is damaged
open-circuit, the parasitic capacitor in the CS pin is
charged by internal CS current sources. Therefore, the
VCS level is built up to the OCP threshold voltage and
then switching is shut down immediately.
Over-Current Protection (OCP)
When an output diode or secondary winding are
shorted, switch current with extremely high di/dt can
flow through the MOSFET even by minimum turn-on
time. The FL7733A is designed to protect the system
against this excessive current. When the CS voltage
across the sensing resistor is higher than 1.35 V, the
OCP comparator output shuts down GATE switching.
Over-Temperature Protection (OTP)
The temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 150°C. The
hysteresis temperature after OTP triggering is 10°C.
In a sensing resistor open condition, the sensing resistor
voltage can’t be detected and output current is not
PCB Layout Guidance
PCB layout for a power converter is as important as
circuit design because PCB layout with high parasitic
inductance or resistance can lead to severe switching
noise with system instability. PCB should be designed to
minimize switching noise into control signals.
3. Control pin components; such as CCOMI, CVS, and
RVS2; should be placed close to the assigned pin
and signal ground.
4. High-voltage traces related to the drain of MOSFET
and RCD snubber should be kept far way from
control circuits to avoid unnecessary interference.
1. The signal ground and power ground should be
separated and connected only at one position
(GND pin) to avoid ground loop noise. The power
ground path from the bridge diode to the sensing
resistors should be short and wide.
5. If a heat sink is used for the MOSFET, connect this
heat sink to power ground.
6. The auxiliary winding ground should be connected
closer to the GND pin than the control pin
components’ ground.
2. Gate-driving current path (GATE – RGATE – MOSFET
– RCS – GND) must be as short as possible.
DC Output
Power
ground
5
AC Input
2
RCS
4
FL7733A
CS
HV
GATE NC
CCOMI
CVS
COMI
VS
GND
VDD
1
3
RVS2
CVDD
Signal
ground
6
RVS1
Figure 28. Layout Example
© 2014 Fairchild Semiconductor Corporation
FL7733AMX • Rev. 1.2
www.fairchildsemi.com
12
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