FL7740_18 [ONSEMI]
Constant-Voltage Primary-Side-Regulation PWM Controller;
| 型号： | FL7740_18 |
| 厂家： | 
ONSEMI |
| 描述： | Constant-Voltage Primary-Side-Regulation PWM Controller |
| 文件： | 总14页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FL7740
Constant-Voltage Primary-Side-
Regulation PWM Controller for
Power Factor Correction
The FL7740 provides accurate CV regulation in the steady state with
differentiated dynamic function to minimize overshoot and undershoot of
output voltage in line and load transient condition. Standby power is less
than 0.3 W for smart lighting application and power factor is higher than
0.9 even at half load condition when enabling PF optimizer for wide
output power scalability.
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Startup time is less than 0.2 sec with built-in high voltage startup circuit
and output voltage quickly reaches to the target CV level by loop gain
transition technique during startup.
Various protections such as over load, output diode short, sensing resistor
short, output short and output over voltage protection guarantee high
system reliability.
SO 10L
NB
MARKING DIAGRAM
ZXYKK
FL7740
MA
Features
•
•
•
•
•
•
•
•
•
•
•
•
Wide universal input range (90 VAC ~ 305 VAC)
Precise CV regulation in the steady state : < ± 3 %
CV regulation in the load transient : < ±10 %
Overshoot-less fast HV start up time ( < 0.2 sec )
Low standby power
Z
X
Y
= Plant code
= 1 digit year code
= 1 digit week code
PF higher than 0.9 at high-line and half load by PF optimizer
Pulse-by-pulse current limit
KK = 2 digit lot traceability code
M = Package code
A
= Product version
Output short protection
Output over voltage protection
PIN CONNECTIONS
Output diode short protection
VDD
GND
GATE
CS
HV
Sensing resistor short & open protection
Over load protection
NC
COMV
BIAS
PF
VS
Typical Applications
•
•
•
LED Lighting System
AC-DC Adapters, TVs, Monitors
ORDERING INFORMATION
Off Line Appliances Requiring Power Factor Correction
See detailed ordering and shipping information in the
package dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
February 2018 - Rev. 3
FL7740
FL7740
VOUT.MAIN
Secondary
DC-DC
VAC
Converter
Dimming
Signal
FL7740
VOUT.BIAS
HV
VDD
GND
Dimming
Control
Module
NC
GATE COMV
0-10, DALI,
Wireless, etc.
CS
VS
BIAS
PF
Figure 1. Application Schematic
Dynamic
control
GND
VDYN-REF1,2,3
HV
NC
GM amp.
VREF
VEAV
JFET
S/H
VS
VDD
Gain control at startup
COMV
Digital Duty Control
Driver
GATE
CS
5V regulator
BIAS
PF
Protection
VIN.PK
VOUT open/short protection
RCS open/short protection
Over current protection
Over load protection
Digital PF
optimizer
VDD
EAV
Thermal shutdown
VDYN-REF
control
CPF detector
Shutdown
Figure 2. Simplified Block Diagram
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2
FL7740
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
VDD
GND
GATE
CS
Function
IC Supply
Description
1
2
IC operating current and MOSFET driving current are supplied using this pin.
Controller ground pin.
Ground
3
PWM Driver Output
Current Sense
Voltage Sense
Power Factor
This pin uses the internal totem-pole output driver to drive the power MOSFET.
Connected to a current sense resistor to detect the MOSFET current for pulse-by-
pulse current limit.
4
This pin is connected to the auxiliary winding of the transformer via a resistor
divider to detect the output voltage.
5
VS
6
PF
This pin is connected to a resistor to optimize power factor.
7
BIAS
COMV
NC
Internal Circuit BIAS
Loop Compensation
No Connection
High Voltage
Bypass pin for the internal supply, which powers all control circuitry on the IC.
This pin is connected to a capacitor between COMV and GND for compensation.
8
9
10
HV
This pin is connected to the rectified input voltage via a resistor for fast startup.
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3
FL7740
MAXIMUM RATINGS (Note 1)
Rating
Symbol
VHV(MAX)
VMV(MAX)
VLV(MAX)
VLV(PULSE)
PD(MAX)
TJ(max)
Value
560
Unit
V
HV Pin Voltage Range
VDD, GATE Pin Voltage Range
COMV, PF, BIAS, VS, CS Pin Voltage Range
-0.3 to 30
-0.3 to 6
-1.5
V
V
V
VS, CS Pin Negative Pulse Voltage at ILV < 0.2 A and tPULSE < 300 ns
Maximum Power Dissipation (TA < 50°C)
Maximum Junction Temperature
663
mW
°C
150
Storage Temperature Range
TSTG
-55 to 150
158
°C
RθJA
Junction-to-Ambient Thermal Impedance
Junction-to-Case Thermal Impedance
°C/W
°C/W
RθJC
39
ESDHBM
ESDCDM
2
2
kV
kV
ESD Capability, Human Body Model (Note 3)
ESD Capability, Charged Device Model (Note 3)
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114)
ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
RECOMMENDED OPERATING RANGES (Note 4)
Rating
Symbol
Min
Max
Unit
Ambient Temperature
TA
-40
125
°C
4. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
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4
FL7740
ELECTRICAL CHARACTERISTICS
VDD = 18 V and TJ = -40 ~ 125°C unless otherwise specified
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VDD Section
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
VDD-ON
VDD-OFF
IDD-OP
14.5
6.75
3
16.0
7.75
5
17.5
8.75
6.5
1
V
V
CLOAD = 1 nF, VDD = 18V
mA
mA
V
Operating Current during Auto Restart
VDD Over-Voltage-Protection
VBIAS Voltage
IDD-AR
0.3
24
VDD-OVP
VBIAS
25
26
4.85
5.00
5.15
V
GATE Section
Output Voltage Low
VOL
VOH
0.2
V
V
Output Voltage High
VDD = 18 V
17.8
Peak Sourcing Current
Design guaranteed
Isource
mA
CLOAD = 1 nF, VDD = 20 V
CLOAD = 1 nF, VDD = 23 V
180
210
Peak Sinking Current
Design guaranteed
mA
Isink
CLOAD = 1 nF, VDD = 20 V
385
435
CLOAD = 1 nF, VDD = 23 V
Rising Time
CLOAD = 1 nF
CLOAD = 1 nF
tr
tf
110
40
150
60
190
80
ns
ns
Falling Time
HV Section
Supply Current From HV Pin
Leakage Current after Startup
JFET Regulation Time at Startup
VDD High Limit during JFET Regulation
VDD Low Limit during JFET Regulation
PWM Section
VHV = 560 V, VDD = 0 V
Design guaranteed
IHV
3
9
mA
μA
ms
V
IHV-LC
1
10
tR-JFET
400
17.5
15.5
500
19.0
17.0
600
20.5
18.5
VDD-JFET-HL
VDD-JFET-LL
V
Min. Turn-on Time Min. Limit
Min. Turn-on Time Max. Limit
Max. Turn-on Time
Design guaranteed
Design guaranteed
Design guaranteed
TON-MIN-MIN
TON-MIN-MAX
TON-MAX
0.40
2.0
μs
μs
μs
23.3
Oscillator Section
Max. Frequency
fMAX
fMIN
60
65
70
kHz
kHz
Min. Frequency
0.72
0.80
0.88
Current Sense Section
Leading-Edge Blanking Time
Propagation Delay to GATE
Voltage Sense Section
tDIS Blanking Time at VS Sampling
VS Clamping Voltage
Design guaranteed
Design guaranteed
tLEB
tPD
300
100
ns
ns
50
150
Design guaranteed
IVS=1 mA
tDIS-BNK
0.95
-0.1
1.00
1.05
μs
VVS-CLAMP
V
I
VS=10 µA
0.35
Feedback Section
Reference voltage
VREF
3.465
3.5
3.535
V
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5
FL7740
ELECTRICAL CHARACTERISTICS (CONTINUED)
VDD = 18 V and TJ = -40 ~ 125°C unless otherwise specified
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
CV Regulation Tolerance
CVREGULATION
%
VVS = 3.5 V, TJ = 25 °C
-0.7
-1.2
+0.7
+1.2
VVS = 3.5 V, TJ = -40~125 °C
Transconductance
gM
16
8
20
10
10
24
12
12
μmho
μA
μA
V
COMV Sink Current
COMV Source Current
COMV High Voltage
COMV Low Voltage
Start Sequence Section
Soft Start Time
VVS = 4 V
VVS = 3 V
ICOMV-SINK
ICOMV-SOURCE
VCOMV-HGH
VCOMV-LOW
8
4.7
0.1
V
Design guaranteed
Design guaranteed
Design guaranteed
Design guaranteed
Design guaranteed
tSOFT-START
tSS1-MIN
tSS1-MAX
tSS21
25.6
2
ms
ms
ms
ms
ms
SS1 Minimum Time
SS1 Maximum Time
SS21 Time
100
45
SS22 Maximum Time
Dynamic Section
tSS22
30
DYN Reference Set Threshold
DYN Reference Set Time
OV Reference 5
VDYN-REF-SET
tDYN-REF-SET
VOV-REF5
VOV-REF4
VOV-REF3
VOV-REF2
VOV-REF1
VUV-REF1
VUV-REF2
VUV-REF3
0.72
0.80
5
0.88
V
μs
%
%
%
%
%
%
%
%
Design guaranteed
Design guaranteed
+20
+15
+10
+5.7
+2.86
-2.86
-5.7
-10
OV Reference 4
+14
+9
+16
+11
OV Reference 3
OV Reference 2
+4.7
+1.86
-3.86
-6.7
+6.7
+3.86
-1.86
-4.7
OV Reference 1
UV Reference 1
UV Reference 2
UV Reference 3
Design guaranteed
Design guaranteed
Protection Section
Auto Restart Delay Time
VS Ouptut Short Hys. Voltage 'H'
VS Ouptut Short Hys. Voltage 'L'
OSP Delay Time
tAR
3
s
V
VVS-OS-H
0.85
0.65
0.90
0.70
35
0.95
0.75
VVS-OS-L
V
Design guaranteed
tOSP-DELAY
VCS-HIGH-CL
VCS-LOW-CL
VCS-OCP
ms
V
High Current Limit Threshold
Low Current Limit Threshold
Over Current Protection Voltage
CS Threshold Voltage for SRSP
Max. Turn-on Time for SRSP
1.13
0.15
1.20
0.20
1.8
1.27
0.25
V
V
VCS-SRSP
tTON-MAX-SRSP
0.040
0.075
0.125
V
μs
IVS = 100 uA
VS = 700 uA
7.5
1.3
10.0
1.6
12.5
1.9
I
Threshold Temperature for OTP
Junction Temperature Hysteresis
Design guaranteed
Design guaranteed
TOTP
150
30
oC
oC
TOTP-HYS
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6
FL7740
T
Y
P
I
C
A
L
C
H
A
R
A
C
T
E
R
I
S
T
I
C
S
20
19
18
17
16
15
14
13
12
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e
3
V
v s . T e m p e r a t u r e
F i g u r e
4
V
v s . T e m p e r a t u r e
D D - O N
B I A S
9.00
8.75
8.50
8.25
8.00
7.75
7.50
7.25
7.00
6.75
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
6.50
-40
1.00
-40
-20
0
20
40
60
80
100
120
140
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e
5
V D D - O F F v s . T e m p e r a t u r e
F i g u r e 6 V C S - H I G H - C L v s . T e m p e r a t u r e
3.60
3.58
3.56
3.54
3.52
3.50
3.48
3.46
3.44
3.42
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
3.40
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e
7
V
v s . T e m p e r a t u r e
F i g u r e
8
V C S - O C P v s . T e m p e r a t u r e
R
E F
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7
FL7740
T
Y
P
I
C
A
L
C
H
A
R
A
C
T
E
R
I
S
T
I
C
S
1.0
0.8
10.5
10.4
10.3
10.2
10.1
10.0
9.9
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
9.8
9.7
9.6
9.5
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e 9 C V R E G U L A T I O N v s . T e m p e r a t u r e
F i g u r e 1 0 V O V - R E F 3 v s . T e m p e r a t u r e
-2.10
-2.25
-2.40
-2.55
-2.70
-2.85
-3.00
-3.15
-3.30
-3.45
-3.60
3.60
3.45
3.30
3.15
3.00
2.85
2.70
2.55
2.40
2.25
2.10
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e 1 1 V O V - R E F 1 v s . T e m p e r a t u r e
F i g u r e 1 2 V U V - R E F 1 v s . T e m p e r a t u r e
-5.2
-5.3
-5.4
-5.5
-5.6
-5.7
-5.8
-5.9
-6.0
-6.1
-6.2
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TJ, JUNCTION TEMPERATURE (ºC)
TJ, JUNCTION TEMPERATURE (ºC)
F i g u r e 1 3 V O V - R E F 2 v s . T e m p e r a t u r e
F i g u r e 1 4 V U V - R E F 2 v s . T e m p e r a t u r e
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FL7740
APPLICATION INFORMATION
General
FL7740 is high power factor flyback controller with
accurate primary side constant voltage regulation for
smart LED lighting and AC-DC adapter, TV & monitors
application. Precise output voltage detection and
dynamic function manage good CV regulation. Startup is
fast with internal HV biasing circuit with overshoot-less
gain control. It guarantees high system reliable
protection functions such as output over voltage, output
short, over load, over current and thermal shut down
protections.
Output Over Voltage Protection
When VEAV is higher than VVS-OVP threshold or VDD is
higher than VDD-OVP, output over voltage protection is
triggered.
Output Diode Short Protection
Once output diode is short circuited, high di/dt in the
primary winding is occurred by leakage inductance.
Once CS pin voltage reaches to 1.7 V, switching is shut
down.
Sensing Resistor Short Protection
Constant Voltage Regulation
At first switching, sensing resistor short condition is
monitored by detecting CS pin voltage. If CS is less than
75 mV during first GATE turn-on time, sensing resistor
short protection is triggered.
VS pin detects output voltage information (=VEAV
during secondary side diode conduction time and
internal gm amplifier regulates the detected voltage at
3.5 V.
)
Over Load Protection
Dynamic Response at Load Transient
When output is over loaded, pulse-by-pulse current limit
event is occurred. If this event lasts for 60 half line
cycles, over load protection is triggered.
At load transient condition, VEAV is shortly out of
regulation due to the narrow PFC loop bandwidth. When
VEAV is far from 3.5 V regulation reference, duty is
quickly changed to bring the VEAV back to 3.5 V by
dynamic control function.
Thermal Shut Down
If internal junction temperature is higher than 150ºC,
protection is triggered and released with 30ºC hysteresis.
HV biasing at startup
Internal HV biasing circuit quickly charges external
VDD capacitor to begin IC operation at plug-in. After
500 ms initial time, HV biasing stops for low standby
power.
Overshoot-less gain control at startup
Once IC operation starts, feedback loop is dominantly
controlled in proportional gain to speed up the output
capacitor charging. Once output voltage is settled down
close to the regulation target, gain control is smoothly
changed to integration gain with no output voltage
overshoot.
Digital PF optimizer
FL7740 compensates input current phase shift caused by
EMI filter capacitor current in a half line period. With
sophisticated digital PF optimizer, FL7740 significantly
improves power factor in the wide load range.
Pulse-by-pulse current limit
When CS pin voltage reaches to 1.2 V current limit
reference, GATE turn-on is terminated to limit primary
peak current.
Auto Restart at Protection
Once protection is triggered, IC operation stops for 3 sec
and begin the operation for auto restart.
Output Short Protection
When VEAV is less than 0.7 V continuously for 35 ms,
output short protection is triggered.
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FL7740
Primary Side Constant Voltage Regulation
FL7740 utilizes auxiliary winding to detect output
voltage during secondary side diode conduction time
(=TDIS). The true output voltage level without secondary
diode forward voltage drop is at the end of secondary
diode conduction time. In order to detect the right output
voltage, 85% of TDIS at previous switching cycle is
sampling time for VEAV detection at current switching
cycle.
during startup sequence (SS1 + SS2) by using internal
resistive load at the output of the error amplifier.
In SS1, CCM prevent operation is enabled for the initial
2 ms. When output voltage is 0 V, deep CCM could be
entered at initial startup and CS could touch OCP level
with startup failure. So, pulse-by-pulse current limit is
0.2 V and switching frequency is 22 kHz during the 2 ms
CCM prevent time. Also, duty is gradually increased for
26 ms for soft startup. Once 5 V pulled-up COMV
voltage drops less than 4.5 V as VEAV is close to VREF
,
SS1 is ended. Maximum SS1 time is limited up to 100
ms.
TDIS
detection
Error
Amp.
In SS2, VCOMV drops from 5 V and goes into p-gain
steady state in which VEAV is little bit lower than VREF
due to the error amplifier input error in p-gain. Once p-
gain steady state is settled down in 45 ms, SS2 is
finished at min. VCOMV range not to make overshoot
when transitioning to i-gain after SS2. FL7740 ends SS2
by monitoring VIN 1.5 ms after VIN.PK detection moment
where VCOMV is generally in the min. range.
VREF
VEAV
VS
S/H
NAUX
COMV
Duty
Control
VIN.PK
VIN.PK
Figure 15. Primary Side Regulation
VIN
1.5 ms
VCOMV
GATE
VS
5.0 V
4.5 V
26 ms soft start
Duty
VEAV
VEAV sampling
2 ms CCM prevent
VREF
85% TDIS
at previous
switching
45 ms
SS2
SS1
Startup time by P-gain
I-gain
TDIS
Figure 17. Startup Sequence
Dynamic CV Regulation
Due to the narrow loop bandwidth, PFC controller
generally does not guarantee good CV regulation at load
transient. Especially in secondary side regulation,
primary side controller does not know the output voltage
level and it only monitors the output of feedback signal
through opto-coupler. Therefore, output voltage
Figure 16. VEAV Detection
The sampled VEAV is compared with 3.5 V VREF at the
input of the error amplifier. Several hundreds nF
capacitor is connected to the output of the error amplifier
at COMV pin to keep feedback loop slow in PFC control.
COMV voltage controls duty to regulate VEAV same as
VREF in the system.
Turn-on time is controlled by both COMV voltage and
VIN.PK information in line feedforward operation in order
to keep the constant COMV voltage in the wide input
voltage range. So, turn-on time is proportional to COMV
undershoot is severely happened at no to full load
transient in the conventional SSR PFC control.
In order to overcome this, FL7740 utilizes the benefit of
PSR with ON semiconductor’s proprietary dynamic duty
control by monitoring the output voltage. For example,
when VEAV is less than VUVD.EN (Under Voltage Dynamic
Enable threshold), duty is quickly increased not to allow
undershoot anymore. Once VEAV rises higher than
VUVD.DIS (Under Voltage Dynamic Disable threshold),
duty quickly drops and follows COMV voltage. During
the VEAV hiccup operation, COMV voltage slowly
increases and dynamic operation is terminated when
COMV voltage is close to steady state level.
voltage and inversely proportional to VIN.PK
.
Startup
After plug-in, external VDD capacitor is quickly
charged by internal HV biasing supply. Even after VDD
is higher than 16 V VDD-ON, internal HV biasing is still
enabled for 500 ms, so HV biasing can relieve VDD
capacitor discharging until auxiliary winding builds up
VDD voltage.
In order to speed up large output capacitor charging
without overshoot, FL7740 starts with proportional gain
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10
FL7740
In case of OVD (Over Voltage Dynamic) function, it
has two enable levels (VOVD.EN1 and VOVD.EN2). If output
voltage overshoot at load transient is too high, VEAV
increases to VOVD.EN2 passing by VOVD.EN1. Duty quickly
drops when reaching VOVD.EN1 and drops to min. level at
once not to allow severe output over voltage when VEAV
COMV
VREF
Duty
Generator
GATE
VEAV
GM amp.
VOVD.EN2
increases higher than VOVD.EN2
.
FL7740 provides two sets of dynamic triggering
threshold. When user prefers narrow output voltage
variation at load transient with large output capacitor,
SET0 can be selected without capacitor at PF pin. If
wider output voltage variation is allowed and output
capacitor should be small due to system size, SET1 can
be selected with connection of capacitor around 0.5 nF at
PF pin. FL7740 detects capacitance at PF pin at the
beginning of switching startup and maintains the SET#
until UVLO is triggered. During the 1st switching, PF
pin is pulled down to 0 V. In the 2nd switching, PF pull
down is disabled and PF voltage is monitored 5 us after
2nd switching period begins. If the PF voltage is higher
than 0.8 V VDYN-REF-SET, SET0 is decided. If not, SET1 is
determined.
Over
VOVD.EN1
Voltage
Dynamic
(OVD)
VOVD.DIS
VUVD.EN
Under
Voltage
Dynamic
(UVD)
VUVD.DIS
Figure 18. Dynamic Function Block
Dynamic Threshold at SET0 and SET1
VEAV
VVS.OVP VOVD.EN2 VOVD.EN1 VOVD.DIS VUVD.DIS VUVD.EN
VREF
VOV-REF5
SET1
+20%VREF
VUVD.DIS
VOV-REF4
SET0
SET1
SET0
+15%VREF
VUVD.EN
VOV-REF3
+10%VREF
SET1
SET0
VCOMV
VOV-REF2
SET1
SET0
+5.7%VREF
VOV-REF1
+2.9%VREF
Duty
VUV-REF1
SET0
SET1
-2.9%VREF
VUV-REF2
-5.7%VREF
SET0
SET1
Figure 19. No to full load transient
VUV-REF3
-10%VREF
VEAV
VOVD.EN2
Digital PF Optimizer
As line voltage increases and output load decreases, PF
is degraded due to the effect of EMI filter capacitor
charging/discharging current. Input current is the sum of
EMI Filter capacitor current and flyback input current.
Whether the flyback input current is exactly in-phase
sinusoidal current with line voltage, 90º phase shifted
EMI filter cap current worsens displacement factor of the
overall system input current.
VOVD.EN1
VOVD.DIS
VREF
VCOMV
The ON semiconductor’s proprietary PF optimizer
accurately compensates the EMI filter capacitor current
and improves PF more than 0.1 at high line and half load
condition.
Duty
The calculation coefficient in the PF optimizer is
externally programmable by supplying a certain level of
voltage at PF pin with external resistive divider from 5 V
Figure 20. Full to no load transient
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11
FL7740
BIAS pin. Before 1st switching, FL7740 converts the PF
voltage into digital value without switching noise and
keeps the digital value for the coefficient until UVLO is
triggered.
Recommended VPF is in Equation 1, where LM is
magnetizing inductance and CEMI is total EMI filter
capacitance.
with released protection. When VDD voltage is up again
to 16 V VDD-ON, FL7740 begins startup sequence.
VDD regulation
VDD
for 3 sec
19 V
17 V
16 V
7.75 V
VPF = 5×109 × LM ×CEMI +1.5
(eq. 1)
GATE
As VPF increases, the coefficient in the PF optimizer
calculation is larger with better PF, but THD is worse
due to the input current distortion at input voltage zero
cross. Therefore, VPF adjustment by changing PF
resistors is recommended to bring the best PF and THD
performance to meet user’s target. When VPF is lower
than 1.5 V, PF optimizer is disabled.
IC
restart
IC
reset
Protection
triggered
Figure 23. Auto Restart
•
Output Over Voltage Protection
Output over voltage is hardly triggered due to the
powering limit by dynamic function. But, in the
abnormal condition, output OVP is triggered when VEAV
is higher than 4.0 V @ SET0 / 4.2 V @ SET1 for 4
switching cycles or VDD voltage is higher than 25 V for
10 us delay.
VIN
IFLYBACK
•
Output Short Protection
IIN
At output short condition, VEAV is less than 0.7 V. If this
condition lasts for continuous 35 ms switching time,
OSP is triggered.
Ideal IIN
IEMI.CAP
•
Over Current Protection
When CS voltage is higher than 1.8 V over the 1.2 V
pulse-by-pulse current limit, protection is immediately
triggered. OCP protects output diode short, sensing
resistor open and transformer saturation condition.
GATE
TON
•
Sensing Resistor Short Protection
Figure 21. With PF Optimizer
1st switching is 0.2 V current mode. If CS doesn’t reach
over 75 mV threshold during 1st turn-on time, SRSP is
triggered. Max. turn-on time at 1st switching is inversely
proportional to input voltage to limit the primary peak
current.
VIN
IFLYBACK
(=Ideal IIN)
•
Over Load Protection
IIN
At over load condition, CS reaches to 1.2 V pulse-by-
pulse current limit. FL7740 generates internal ZC (Zero
Cross) signal and OLP is triggered if the event (1.2V
current limit event between the two close ZC signals) is
occurred for consecutive 60 ZC signals.
Leading
phase
IEMI.CAP
VIN
GATE
TON
1.2 V
current limit
event
CS
ZC
OLP Count
Figure 22. Without PF Optimizer
Protection
60
59
58
3
57
2
1
0
0
OLP
•
Auto-restart
Once protection is triggered, FL7740 terminates
Figure 24. Over Load Protection
Thermal Shut Down
When internal junction temperature is higher than
150ºC, TSD is triggered and protection is released when
the junction temperature drops under 120ºC.
•
switching and internal 3 sec counter makes delay time.
In 3 sec, VDD voltage is regulated between 17 V and 19
V by internal HV biasing not to fall in UVLO. After 3
sec, VDD falls down to 7.75 V VDD-OFF and IC is reset
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12
FL7740
Single layer PCB layout guidance
Bridge
diode
AC Input
Secondary
DC-DC
Converter
Dimming
Signal
RHV1
PG
PG line goes
(Power GND)
under RHV1
RHV2
5
VDD line goes
under RHV2
MCU
SG
module
RHV3
(Signal GND)
FL7740
SG line goes
under RHV3
4
HV
VDD
3
NC
GND
2
1
COMV GATE
1
2
3
G-GATE and S-GND distance should be short.
SG and PG are connected close at GND pin.
RGATE
CS
VS
BIAS
PF
CS line goes
under RGATE
COMV,BIAS,PF,VS circuit ground and aux. winding
VDD circuit ground are connected close at GND pin.
4
5
SMD filter cap is connected close at VDD and GND pin.
Powering lines (Drain and PG) are closely placed and
away from FL7740 control circuits.
ORDERING INFORMATION
Device
Package
Shipping
FL7740MX
10 Lead SOIC, JDEC MS-012, 150” Narrow Body
Tape and Reel
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13
FL7740
PACKAGE DIMENSIONS
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