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November 2014

FL7734

Single-Stage Primary-Side-Regulation PWM Controller

for PFC and Phase Cut Dimmable LED Driving

Features

Description

.

Excellent Dimmer Compatibility by Active Dimming

Control

The FL7734 is a highly integrated PWM controller with

advanced Primary-Side-Regulation (PSR) technique to

minimize components for low power LED lighting

solutions. Using the innovative TRUECURRENT^®

technology for tight constant-current control, it enables

designs with constant-current (CC) tolerance of less

than 1% in the wide line voltage range to meet

stringent LED brightness requirements.

Programmable Dimming Curve and Input Current

Management

Constant LED Current Regulation in Large Phase

Angle Range

Cost-Effective Solution without Input Bulk Capacitor

and Feedback Circuitry

FL7734 can operate with all types of phase cut

dimmers. Phase cut dimming is managed smoothly by

Fairchild’s proprietary constant input current control and

bleeding current control to achieve excellent dimmer

compatibility without visible flicker.

Accurate Constant-Current (CC) Control,

Independent on Line Voltage, Output Voltage,

Magnetizing Inductance Variation

.

Power Factor Correction (PFC)

Fast Startup utilizing Bleeding Circuit

Open-LED Protection

The controller can automatically detect whether there is

a dimmer connection. In non dimming mode, the

operating mode is set to optimize power factor and THD

by enabling linear frequency control and voltage mode

based on DCM.

Short-LED Protection

Sensing Resistor Short Protection

Cycle-by-Cycle Current Limiting

Over-Temperature Protection with Auto Restart

An external high-voltage bleeding circuit is utilized to

implement fast startup and high system efficiency. The

FL7734 also provides powerful protections, such as

LED open / short, sensing resistor shorted, and over-

temperature for high system reliability. The FL7734 is

available in 16-pin Small-Outline Package (SOP).

Applications

.

LED Lighting System

Related Resources

FL7734 Product Folder

Ordering Information

Packing

Part Number Operating Temperature Range

Package

Method

FL7734MX

-40°C to +125°C

16-Lead, Small Outline Package (SOP-16)

Tape & Reel

FL7734 • Rev. 1.0

www.fairchildsemi.com

Application Diagram

FL7734

VDD

VS

TCIC

MOD

HOLD

DIM

FB

PG

GATE

CS

BIAS

BLD

MBLD RBLD

SG

VIN

Figure 1.

Typical Application

Internal Block Diagram

BLD RBLD

BIAS

12

VDD

16

MBLD

7

11

10

VDD.ON

10.6 V /

7.75 V

9

VIN

Biasing

Management

Phase Angle

Detection

Protections

Short LED Protection

Open LED Protection

VDD Over-Voltage Protection

Thermal Shutdown

Over-Current Protection

5

3

DIM

MOD

FB

Error

Amp.

Sensing Resistor Short Protection

6

Auto-recovery Mode

Active DIM

Control

V_EAI

R

S

I_TCIC

Gate

Driver

14

GATE

Q

2

4

TCIC

Linear Frequency

Controller

OSC

I_HOLD

Line

Compensation

TrueCurrent^®

Calculation

HOLD

V_EAI

8

1

15

PG

13

SG

VS

CS

Figure 2.

Functional Block Diagram

FL7734 • Rev. 1.0

www.fairchildsemi.com

2

Marking Information

F: Fairchild Logo

Z: Plant Code

X: 1-Digit Year Code

Y: 1-Digit Week Code

TT: 2-Digit Die Run Code

T: Package Type (M=SOP)

P: Z: Pb free, Y: Green package

M: Manufacture Flow Code

ZXYTT

7734

TPM

Figure 3.

Top Mark

Pin Configuration

VS

1

2

3

4

5

6

7

8

16

15

14

13

VDD

PG

TCIC

MOD

HOLD

DIM

GATE

CS

12 BIAS

FB

11

10

9

BLD

RBLD

VIN

MBLD

SG

Figure 4.

Pin Configuration

Pin Definitions

Pin #

Name

Description

Voltage Sense. VS pin detects the output voltage for linear frequency control and discharge

time for output current regulation. VS voltage detection protects LED open and short conditions.

1

VS

Constant Input Current. TCIC manages switching mode control.

Modulation. Min. FB is clamped by MOD voltage.

2

3

4

TCIC

MOD

HOLD

Holding Current. External HOLD resistor sets the level of constant input current.

Phase Angle Sense. DIM voltage indicates the amount of phase angle. It is the reference

voltage of the error amplifier in the feedback loop.

5

DIM

Feedback. FB is the output of the error amplifier.

6

7

8

9

FB

MBLD

SG

Maximum Bleeding. Resistor connected to MBLD determines maximum bleeding current.

Signal Ground.

Input Voltage Sense. VIN pin detects input voltage for phase angle detection.

VIN

Bleeding Control Resistor. RBLD current set by external resistor decides the amount of

bleeding current.

10

11

12

RBLD

BLD

Bleeding Control. BLD flows current into RBLD.

Bleeding Circuit BIAS. External bleeding switch is biased by an internal clamping circuit via

BIAS pin.

BIAS

Current Sense. CS pin connects a current-sense resistor to detect the MOSFET current for the

output current regulation. Over-current protection and sensing resistor short protection are

triggered by this pin.

13

CS

PWM Signal Output. Gate driver in this pin switches power MOSFET.

Power Ground.

14

15

GATE

PG

Power Supply. Connects to a decoupling capacitor. IC operating current and MOSFET driving

current are supplied from this pin.

16

VDD

FL7734 • Rev. 1.0

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

V_VDD

V_DIM

V_MOD

V_HOLD

V_TCIC

V_FB

DC Supply Voltage^(1,2)

DIM Pin Input Voltage

MOD Pin Input Voltage

HOLD Pin Input Voltage

TCIC Pin Input Voltage

FB Pin Input Voltage

RBLD Pin Input Voltage

BIAS Pin Input Voltage

BLD Pin Input Voltage

MBLD Pin Input Voltage

VS Pin Input Voltage

CS Pin Input Voltage

GATE Pin Input Voltage

VIN Pin Input Voltage

-0.3

30

6.0

V

6.0

V

6.0

V

6.0

V

6.0

V

V_RBLD

V_BIAS

V_BLD

V_MBLD

V_VS

6.0

V

30.0

6.0

V

6.0

V

V_CS

6.0

V

V_GATE

V_VIN

P_D

30.0

909

V

Power Dissipation (T_A＜50°C)

mW

θ_JA

T_J

Thermal Resistance (Junction to Air)

Maximum Junction Temperature

Storage Temperature Range

110

150

260

°C /W

°C

T_STG

T_L

-55

°C

Lead Temperature (Soldering, 10 Seconds)

°C

Human Body Model,

ANSI/ESDA/JEDEC JS-001-2012

5

2

Electrostatic Discharge

Capability

ESD

kV

Charged Device Model, JESD22-C101

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

2. All voltage values, except differential voltages, are given with respect to the GND pin.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Operating Ambient Temperature

Min.

Max.

Unit

T_A

-40

125

°C

FL7734 • Rev. 1.0

www.fairchildsemi.com

4

Electrical Characteristics

V_DD=20 V and T_J=-40 ~ 125°C unless otherwise specified.

Symbol

VDD Section

V_DD-ON

Parameter

Condition

Min.

Typ.

Max.

Unit

Turn-On Threshold Voltage

Turn-Off Threshold Voltage

Operating Current

9.1

6.75

4

10.6

7.75

5

12.1

8.75

6

V

V_DD-OFF

I_DD-OP

C_LOAD=1 nF

mA

μA

V

I_DD-ST

Startup Current

V_DD=6 V

-

2

10

V_DD-OVP

V_DDOver-Voltage-Protection

25

27

29

V_IN⁽³⁾=30 V,

V_BIAS-VDD-OFFBIAS Clamp Voltage at VDD-OFF

21.3

17.6

24.4

19.5

27.5

21.4

V

R_BIAS=20 k

V_IN⁽³⁾=30 V,

V_BIAS-VDD-ONBIAS Clamp Voltage at VDD-ON

R_BIAS=20 k

Gate Section

V_OL

V_OH

Output Voltage Low

Output Voltage High

I_GATE=-1 mA

1.5

V

I_GATE=+1 mA,

V_DD=10 V

5

I_source

I_sink

t_r

Peak Sourcing Current⁽⁴⁾

Peak Sinking Current⁽⁴⁾

Rising Time

60

180

150

60

mA

ns

V

C_LOAD=1 nF

V_DD=20 V

100

20

200

100

18

t_f

Falling Time

V_GATE-CLAMPGATE Clamp Voltage

12

15

Oscillator Section

f_D

Operating Frequency at D.Mode

T_J=25°C

V_FB=0 V

65

70

75

kHz

s

f_ND-MAX

f_ND-MIN

t_ON-MAX

t_ON-MIN

Max. Frequency at ND.Mode

Min. Frequency at ND.Mode

Maximum Turn-On Time

Minimum Turn-On Time⁽⁴⁾

26

29.5

12.4

600

33

10.4

14.4

ns

Current Sense Section

t_LEB

Leading-Edge Blanking Time⁽⁴⁾

t_PD

300

100

21.5

ns

Propagation Delay to GATE

Line Compensation Ratio⁽⁴⁾

50

150

V_CS/I_VS

V/A

Voltage Sense Section

t_DIS-BNK

t_DISBlanking Time at VS Sampling⁽⁴⁾

I_VS-BNK

1.5

80

μs

μA

V

VS Current for VS Blanking

VS Clamping Voltage

67

93

I_VS=1 mA

I_VS=10 µA

-0.1

V_VS-CLAMP

0.35

V

Notes:

3. V_INis external voltage source and R_BIASis connected between V_INand BIAS pin.

4. This parameter, although design-guaranteed, is not tested in production.

FL7734 • Rev. 1.0

www.fairchildsemi.com

5

Electrical Characteristics

V_DD=20 V and T_J=-40 ~ 125°C unless otherwise specified.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Feedback Section

g_M

Transconductance

FB Sink Current

14

18

22

μmho

μA

T_J=25°C, V_EAI=2 V,

V_FB=2.5 V

I_FB-SINK

I_FB-SOURCE

V_FB-HGH

FB Source Current

FB High Voltage⁽⁴⁾

FB Low Voltage⁽⁴⁾

V_EAI=0 V, V_FB=2.5 V

14

μA

V

4.7

V_FB-LOW

0.1

V

Start Sequence Section

t_SS1-MINMinimum Start Sequence Time 1

t_SS3-MINMinimum Start Sequence Time 3

10.8

13.5

1.26

12.0

15.0

1.40

13.2

16.5

1.54

ms

V

V_FB-ADJ-NDMFB Adjustment Voltage in ND.MODE

Protection Section

V_CS-HIGH-CLHigh Current Limit Threshold

V_CS-LOW-CLLow Current Limit Threshold

1.08

0.15

1.20

0.20

1.8

1.32

0.25

V

V_CS-OCP

Over Current Protection Voltage

V

V_VS-LOW-CL-HLow Current Limit Hys. Voltage 'H'⁽⁴⁾

V_VS-LOW-CL-LLow Current Limit Hys. Voltage 'L'⁽⁴⁾

0.45

0.35

2.9

0.50

0.40

3.0

0.55

0.45

3.1

V

V_VS-SLP-TH

V_VS-OVP

t_AR-DELAY

V_CS-SRSP

T_OTP

VS Threshold Voltage for SLP

VS Threshold Voltage for OVP

Auto Restart Delay Time⁽⁴⁾

V

4.0

s

CS Threshold Voltage for SRSP

Threshold Temperature for OTP⁽⁴⁾⁽⁵⁾

Junction Temperature Hysteresis⁽⁴⁾

0.05

0.10

150

10

0.15

V

^oC

T_OTP-HYS

Dimming Control Section

I_DIM

DIM Sourcing Current

DIM Current On/Off Voltage⁽⁴⁾

V_DIM=3 V

36

40

44

μA

V

V_VIN-DIM

3.00

3.25

V_DIM-CLAMPDIM Clamping Voltage

V

T_J=25°C, V_CS=0.5 V,

R_HOLD=31.5 k

K_HOLD

HOLD Conversion Coefficient

510

/mA

I_HOLD

I_TCIC

HOLD Sourcing Current

TCIC Sourcing Current

V_HOLD=3.5 V

36

13.5

0.9

40

15.0

1.0

44

16.5

1.1

μA

V

V_TCIC-MIN-DISMinimum TCIC Discharging Voltage

V_RBLD-CLAMPClamped RBLD Voltage

V_VIN=5 V,

R_RBLD=40 

0.45

36

0.50

40

0.55

44

V

I_MBLD

Note:

MBLD Current

V_MBLD=3.5 V

μA

5. If over-temperature protection is activated, the power system enters Auto Recovery Mode and output is disabled.

Device operation above the maximum junction temperature is NOT guaranteed.

FL7734 • Rev. 1.0

www.fairchildsemi.com

6

Typical Performance Characteristics

1.5

1.3

1.1

0.9

0.7

0.5

1.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

70

90

110

130

Temperature ( ºC )

Figure 5.

V_DD-ONvs. Temperature

Figure 6.

V_DD-OFFvs. Temperature

1.5

1.3

1.1

0.9

0.7

0.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

70

90

110

130

Temperature ( ºC )

Figure 7.

I_DD-OPvs. Temperature

Figure 8.

V_DD-OVPvs. Temperature

1.5

1.3

1.1

0.9

0.7

0.5

1.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

Temperature ( ºC )

70

90

110

130

Temperature ( ºC )

Figure 9.

f_ND-MAXvs. Temperature

Figure 10. f_ND-MINvs. Temperature

FL7734 • Rev. 1.0

www.fairchildsemi.com

7

Typical Performance Characteristics

1.5

1.3

1.1

0.9

0.7

0.5

1.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

70

90

110

130

Temperature ( ºC )

Figure 11. f_Dvs. Temperature

Figure 12. V_CS-HIGH-CLvs. Temperature

1.5

1.3

1.1

0.9

0.7

0.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

70

90

110

130

Temperature ( ºC )

Figure 13. V_VS-SLP-THvs. Temperature

Figure 14. V_VS-OVPvs. Temperature

1.5

1.3

1.1

0.9

0.7

0.5

1.5

1.3

1.1

0.9

0.7

0.5

-45

-30

-15

0

25

50

70

90

110

130

-45

-30

-15

0

25

50

70

90

110

130

Temperature ( ºC )

Figure 15. K_HOLDvs. Temperature

Figure 16. I_HOLDvs. Temperature

FL7734 • Rev. 1.0

www.fairchildsemi.com

8

Functional Description

FL7734 is a phase-cut dimmable PWM controller for

LED lighting applications. Accurate LED current

regulation independent of input voltage, output voltage

and magnetizing inductance variations is implemented

by TRUECURRENT^®technique. The controller features

programmable dimming curve which ensures that the

constant maximum LED current can be met at the

various maximum phase angle conditions of each

dimmer and low LED current can be set at the minimum

phase angle condition with wide dimming range.

Fairchild’s proprietary constant input current control

provides excellent dimmer compatibility by maintaining

input current higher than TRIAC holding current. The

linear frequency control and DCM operation with

minimized turn-on time ripple implements best power

factor and THD in a single-stage topology. A variety of

protections; such as short-LED protection, open-LED

protection, sensing resistor open/short protection, over-

temperature protection, and cycle-by-cycle current

limitation stabilize system operation and protect external

components.

set as either dimming mode or non-dimming mode. SS3

time is set longer than t_SS3-MINwhich is counted except

for phase-cut time and finishes synchronized with V_IN

zero crossing. 0.2 V current-mode is activated during

SS3 so that output voltage reaches a level higher than

threshold for short-LED protection, which is enabled

after SS3. In the mean time, FB voltage is clamped to

1.4 V at non-dimming mode or

a

certain level

proportional to phase angle at dimming mode to set the

voltage closer to steady-state level. The maximum

bleeding current is disabled after SS3 and voltage mode

control is enabled at non-dimming mode and constant

input current control is enabled at dimming mode.

Constant-Current Regulation

The output current is estimated using the peak drain

current and inductor current discharge time because

output current is same as the average of the diode

current in steady-state. The peak value of the drain

current is determined by the CS pin. The inductor

discharge time (t_dis) is sensed by a t_disdetector. Using

three sources of information; peak drain current,

inductor discharging time, and operating switching

period, the TRUECURRENT^®block calculates the

estimated output current. The output of the calculation is

compared with an internal precise reference to generate

an error voltage (V_FB). With Fairchild’s innovative

TRUECURRENT^®technique, constant LED current can

be precisely controlled.

Startup

An external bleeding MOSFET is utilized for fast startup.

Once power is on, BIAS voltage is quickly lifted to V_BIAS-

(24.4 V) so the bleeding MOSFET can charge

VDD-OFF

the VDD capacitor higher than V_DD-ONvoltage (10.6 V).

Once V_DDis higher than V_DD-ON, Startup Sequence

(SS1) begins with maximum bleeding current to stabilize

dimmer operation. SS1 ends when V_INreaches the line

voltage zero crossing after t_SS1-MIN(12 ms).

Constant Input Current Control

Fairchild’s proprietary Constant Input Current (CIC)

control generates switching duty to form input current

proportional to the external resistor value at HOLD pin.

Filtered switch current is the system input current and

the system input current is adjusted by the calculation of

CS average voltage. Input current is determined by

equation (1) where K_HOLDis coefficient of internal

calculation.

SS1

SS3

*SS =

Startup Sequence

SS2

t_SS1-MIN

t_SS3-MIN

V_IN

Power

on

V_DD

ꢃ_ꢄꢅꢆꢇ

V_DD-ON

ꢀꢁ

ꢂ

(1)

ꢃ_ꢈꢉꢊ ꢋ_ꢄꢅꢆꢇ

Fairchild’s CIC control offers superior accurate and

stable current management than other input current

control technologies.

V_FB

1.4 V

Dimming Control

V_CS

Phase angle is detected by comparing VIN voltage and

3 V threshold voltage (V_VIN-DIM). When VIN voltage is

higher than 3 V, DIM sourcing current (I_DIM) is connected

to the DIM pin and the current flows into external

0.2 V

resistors (R_DIM1and R_DIM2) and capacitor (C_DIM).

Therefore, the DIM voltage filtered by C_DIMindicates the

amount of phase angle controlled by phase-cut dimmer.

I_LED

ꢓꢔ

ꢕꢖꢗ^ꢘ

ꢎ

ꢒ

ꢊ

ꢌ_ꢇꢀꢍꢂ _ꢇꢀꢍꢊ ꢃ_ꢇꢀꢍꢏꢐ ꢃ_ꢇꢀꢍꢑ

(2)

Time

Figure 17. Startup Sequence

During SS2 which is defined as a half line period,

FL7734 determines whether phase-cut dimmer is

connected in the line. From SS3, internal operation is

FL7734 • Rev. 1.0

www.fairchildsemi.com

9

As a function of dimming reference modulation shown in

Figure 18, output current is constantly regulated with

constant V_REFwhen V_DIMis higher than 3 V and V_REFis

set lower than V_EAI(TRUECURRENT^®calculation

result) when V_DIMis lower than 2.25 V. Once V_DIMis less

than 2.25 V, the error amplifier always pulls down

current in the output and FB voltage is clamped by MOD

voltage so that open loop control starts for stable LED

current control at low phase angle range.

In order to optimize PF and THD in the single stage

flyback topology, constant turn-on time and constant

frequency in Discontinuous Conduction Mode (DCM)

are the best method to make the input current

proportional to the input voltage as shown in Figure 19.

FL7734 basically adopts the DCM operation with

constant turn-on and frequency in a half line cycle.

Once dimmer absence is detected during startup

sequence, FL7734 selects voltage mode in which

constant turn-on time is maintained by an internal error

amplifier and a large external capacitor (typically

>1 µF) at the FB pin. Constant frequency and DCM

operation are managed by linear frequency control.

Input

Voltage

R_VIN1

VIN

I_DIM

Linear Frequency Control

V_VIN-DIM

(3 V)

R_VIN2

DCM should be guaranteed for high power factor in

flyback topology. To maintain DCM in the wide range of

output voltage, frequency is linearly adjusted by output

voltage in linear frequency control. Output voltage is

detected by auxiliary winding and resistive divider

connected to the VS pin, as shown in Figure 20. When

output voltage decreases, secondary diode conduction

time is increased and the linear frequency control

lengthens switching period, which retains DCM

operation in the wide output voltage range. The

frequency control lowers primary rms current for better

power efficiency in full-load condition.

V_DIM-CLAMP

(3.25 V)

DIM

Dimming

Reference

Modulation

R_DIM1

MOD

C_DIM

V_EAI

V_REF

R_DIM2

Error

Amp.

FB

BCM

t_DIS

C_FB

OSC

Detector

Figure 18. Dimming Control

V_OUT

DCM

High dimmer compatibility is implemented by bleeding

current generated through BLD to RBLD and having the

switching mode management by TCIC.

Linear Frequency

Controller

VS

freq.

PFC and THD

In

a

conventional boost converter, Boundary

V_VS

Conduction Mode (BCM) is generally used to keep

input current in phase with input voltage for Power

Factor (PF) and Total Harmonic Distortion (THD).

However, BCM switching distorts input current in the

single stage flyback / buck boost converter because

power inductor current is not the same as input

current. Moreover, it becomes more difficult to meet

PF and THD once passive bleeder (resistor and

capacitor in the driver input) is added for successful

firing in the single stage TRIAC dimming system.

Figure 20. Linear Frequency Control

BCM Control

The end of secondary diode conduction time (t_DIS) can

be over a switching period set by linear frequency

control. In this case, FL7734 doesn’t allow CCM and

operation mode changes from DCM to BCM. Therefore,

magnetizing inductance can be largely designed to add

BCM for better efficiency if PF and THD meet

specification with enough margin.

I_IN

I_{IN_AVG}

GATE

Constant Frequency

Figure 19. PFC Control in DCM

FL7734 • Rev. 1.0

www.fairchildsemi.com

10

SS2

SS3

Short-LED Protection

V_VIN

In a short-LED condition, the switching MOSFET and

secondary diode are usually stressed by the high

powering current.

1.5 V

LEB

CS

V_CS-HIGH-CL(1.2 V)

Max. t_ON

V_GATE

V_CS-LOW-CL(0.2 V)

V_CS

0.1 V

GATE Turn-off

V_VS-LOW-CL-H(0.5 V) /

V_VS-LOW-CL-L(0.4 V)

SRSP

Time

VS

S/H

Debounce

Count

Short-LED

Protection

V_VS-SLP-TH(0.4 V)

Figure 22. Sensing Resistor Short Protection

Figure 21. Short LED Protection

Under-Voltage Lockout (UVLO)

FL7734 changes the current-limit level in a short-LED

condition. When sampled VS voltage is lower than V_VS-

_LOW-CL-L(0.4 V), the current-limit level is reduced to 0.2 V

from 1.2 V, as shown in Figure 21 so that powering is

limited and external components’ current stress is

relieved. When the sampled VS voltage is continuously

lower than V_VS-SLP-TH(0.4 V) for 3 consecutive switching

cycles, short-LED protection is triggered with gate

shutdown. After all types of protection including short-

LED protection is triggered, FL7734 internally counts 4

seconds for auto restart and begins startup sequence

again.

The turn-on and turn-off thresholds are fixed internally at

10.6 V and 7.75 V, respectively. During startup, the

VDD capacitor must be charged higher than 10.6 V

through the external bleeding MOSFET. The bleeding

MOSFET supplies VDD operating current until power

can be delivered from the auxiliary winding of the main

transformer. Generally at small phase angle range, V_DD

supply time from auxiliary winding is short and V_DDcould

reach to V_DD-OFF(7.75 V). If V_DDdrops below V_DD-OFF

,

VDD hiccup occurs with a certain hiccup frequency

determined by VDD capacitor value and VDD supply

current from auxiliary winding. This hiccup mode could

cause LED flicker. In order to remove the unstable

mode of operation, external bleeding circuit never allows

V_DDvoltage to fall down less than V_DD-OFF(7.75 V) once

input power is supplied.

Open-LED Protection

When output load is open as high impedance, the

output capacitor should be protected by limiting the

capacitor voltage less than its maximum rating. FL7734

can detect the output over-voltage condition by sensing

both VDD and VS voltages. When VDD voltage is

higher than V_DD-OVP(27 V typical) or sampled VS voltage

is higher than V_VS-OVP(3 V typical), protection is

triggered. The protection mode is auto restart so normal

operation resumes when the fault condition is removed.

Over-Temperature Protection (OTP)

The built-in temperature-sensing circuit shuts down

PWM output if the junction temperature exceeds 150°C.

After Over-Temperature Protection (OTP) is triggered,

FL7734 repeats auto-restart time counting until the

junction temperature is lowered less than 140°C.

Different from Short/Open-LED protection and SRSP,

startup sequence doesn’t appear every 4 seconds of

auto-restart delay time because the temperature is

detected by monitoring internally, not by checking

external pin information. Normal startup sequence is

started again when the junction temperature is out of the

hysteresis temperature (140°C).

Sensing Resistor Short Protection

During SS3, the controller operates in current-mode

control and the peak CS voltage is 0.2 V during

switching mode. When a sensing resistor is short

circuited, CS voltage cannot reach 0.2 V and turn on

time is maximized with potential damage of switching

MOSFET. In order to provide protection against the

failure, FL7734 compares CS voltage with V_CS-SRSP

(0.1 V) during the initial two switching operation. When

VCS doesn’t reach 0.1 V for the two switching, Sensing

Resistor Short Protection (SRSP) is triggered. In normal

condition, input voltage corresponding to 1.5 V V_VINis

high enough to make V_CShigher than 0.1 V with turn-on

time shorter than maximum turn-on time.

FL7734 • Rev. 1.0

www.fairchildsemi.com

11

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1


型号：	FL7734
厂家：	ONSEMI
描述：	Single-Stage Primary-Side-Regulation PWM Controller
文件：	总14页 (文件大小：380K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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