FAN6290QH [ONSEMI]
Compact Secondary-Side Adaptive Charging Controller;
| 型号： | FAN6290QH |
| 厂家： | 
ONSEMI |
| 描述： | Compact Secondary-Side Adaptive Charging Controller |
| 文件： | 总20页 (文件大小：920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FAN6290QF/FAN6290QH
Compact Secondary-Side
Adaptive Charging Controller
Synchronous Rectifier Control
FAN6290QF/FAN6290QH are highly integrated, secondary-side power
adaptor controllers compatible with the Quick Charge 3.0 (QC3.0)
protocol. Internally adopted synchronous rectifier control helps for less
BOM counts as well as for easy design.
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10
The internal two operational amplifiers control adaptive constant output
voltage and adaptive constant output current. The outputs of the two
amplifiers are tied together in open-drain configuration.
FAN6290QF/FAN6290QH enables adaptor output voltage and current
adjustment when Quick Charge 3.0 protocol is acknowledged. According
to request from a battery charger of a Portable Device, output voltage is
adjusted up to 12 V. When a portable device that implements non-
compliant protocols is attached, it just maintains the default output, (5 V)
for safety of the portable device.
1
SOP-10
MARKING DIAGRAM
FAN6290QF/FAN6290QH incorporates adaptive output over-voltage and
under-voltage protections to improve system reliability.
ZXYTT
6290QX
MF
Features
Compatible with Quick Charge 3.0 (QC3.0) Protocol
Auto-detection supporting 2.4 A Apple products
Internal Synchronous Rectifier Control Circuit
1st Line:
F: Corporate Logo
Z: Assembly Plant Code
X: Year Code
Secondary-Side Constant Voltage (CV) and Constant Current (CC)
Regulation with Two Operational Amplifiers
Y: Week Code
TT: Die Run Code
Small Current Sensing Resistor (30 mΩ) for High Efficiency
2nd Line:
3rd Line:
Protections for Safe Operation ; Output Over-Voltage-Protection,
Output Under-Voltage-Protection for QC2.0, Data line (D+/D-)
Over-Voltage-Protection
6290Q: IC Part Name
X: Series Line-up Name
Built-in output capacitor bleeding function for fast discharging
during change of output mode
MF
PIN CONNECTIONS
Built-in Cable-Drop Compensation
DP
DN
1
2
3
4
5
10 CS
Typical Applications
9
8
7
6
LPC
GND
GATE
VIN
Battery Chargers for Smart Phones, Feature Phones, and Tablet PCs
AC-DC Adapters for Portable Devices that Require CV/CC Control
VREF
IREF
SFB
(TOP View)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
December 2016- Rev. 1.0
FAN6290QF/D
FAN6290QF/FAN6290QH
Std-A
VBUS
Micro-B
L
Transformer
D-
RSNU CSNU
USB Cable
DN
DP
TH
COUT
Lm
SR
MOSFET
D+
BD
RSENSE
CIN1 CIN2
GND
AC IN
DSNU
RHV
Fuse
CS
GND
VIN
RGATE
Q1
GATE
LPC
DP
1
HV
Gate
4
3
RF
RCS
VREF
SFB
FAN6290
2
9
NC
FB
CS
RVSH
DVDD
VDD
VS
5
6
7
DP
10 GND
CVDD
RVSL
CVS
DN
IREF
DN
8
IMIN
FMAX
FAN602
Figure 1 FAN6290QF and FAN6290QH Typical Application Schematic
VIN
DP
DN
Internal Bias (VDD)
Mode
Protocol
Communication
(auto-detection)
Mode Change
Cable Fault
Mode Change
OVP
UVP
OVP
Protection
UVP
Protection
Cable Fault
Data line OVP
VDD-ON / VDD-OFF
Mode
Mode
Cable
Fault
IREF
VLPC-EN
Green
Mode
Calculate
VLPC-EN
GATE
Driver
VDD
CS
XAVCCR
S
R
Q
PWM
Block
GND
LPC
Cable Drop
Compensation
VLPC-TH
VCCR
RESET
Mode
Mode
Line
Detection
Function
VDD
VREF
SR Off-time
Decision
VIN
Σ
VCVR
SFB
GATE
Figure 2. FAN6290QF and FAN6290QH Function Block Diagram
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2
FAN6290QF/FAN6290QH
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
2
DP
Communication Interface Positive Terminal. This pin is tied to the USB D+ data line input.
Communication Interface Negative Terminal. This pin is tied to the USB D- data line input.
DN
Output Voltage Sensing Terminal. Non-inverting terminal of the internal CV loop amplifier. This pin
is used for constant voltage regulation.
3
4
5
6
VREF
IREF
SFB
VIN
Constant Current Amplifying Signal. The voltage on this pin represents the amplified current sense
signal, also used for constant current regulation. It is tied to the internal CC loop amplifier's non-
inverting terminal.
Secondary Feedback. Common output of the open-drain operation amplifiers. Typically an opto-
coupler is connected to this pin to provide feedback signal to the primary-side PWM controller.
Input Voltage. This pin is tied to the output of the adaptor not only to monitor output voltage but
also to supply internal bias. IC operating current, and MOSFET gate-drive current are supplied
through this pin.
7
8
GATE
GND
Gate Drive Output. Totem-pole output to drive an external SR MOSFET.
Ground.
SR MOSFET Drain Voltage Detection. This pin detects the voltage on the secondary winding for
Synchronous Rectifier control.
9
LPC
CS
Current Sensing Amplifier Negative Terminal. Output current is sensed through this terminal for
green mode control, cable drop compensation, and constant current control.
10
Series Line-up Table
Name
Output Voltage and its Nominal Output Current
UVP Operation
VO = 3.6 ~ 6 V
VO = 6.2 ~ 9 V
2.0 A
VO = 9.2 ~ 12 V
1.5 A
FAN6290QF
FAN6290QH
3.0 A
3.0 A
Pull-down SFB
Reduce CC
3.0 A
2.0 A
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3
FAN6290QF/FAN6290QH
MAXIMUM RATINGS (Note 1,2,3)
Rating
Symbol
VIN
Value
20
Unit
V
VIN Pin Input Voltage
SFB Pin Input Voltage
VSFB
VIREF
VVREF
VCS
20
V
IREF Pin Input Voltage
-0.3 to 6
-0.3 to 6
-0.3 to 6
-0.3 to 14
-0.3 to 14
-0.3 to 6.5
-0.3 to 6
0.68
V
VREF Pin Input Voltage
CS Pin Input Voltage
V
V
DP Pin Input Voltage
VDP
V
DN Pin Input Voltage
VDN
V
LPC Pin Input Voltage
VLPC
VGATE
V
GATE Pin Input Voltage
Power Dissipation (TA=25C)
Operating Junction Temperature
Storage Temperature Range
Lead Temperature, (Soldering, 10 Seconds)
V
PD
TJ
W
C
C
C
kV
kV
-40 to 150
-40 to 150
260
TSTG
TL
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 (Note 4)
Charged Device Model, JESD22-C101 (Note 4)
ESDHBM
ESDCDM
3
1.75
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
4. Meets JEDEC standards JS-001-2012 and JESD 22-C101.
THERMAL CHARACTERISTICS (Note 5)
Rating
Symbol
Value
Unit
Thermal Characteristics,
RθJA
RψJT
Thermal Resistance, Junction-to-Air
Thermal Reference, Junction-to-Top
142
21
°C/W
5. TA=25°C unless otherwise specified.
RECOMMENDED OPERATING RANGES (Note 6)
Rating
Symbol
VIN
Min
0
Max
16
16
1
Unit
V
VIN Pin Input Voltage
SFB Pin Input Voltage
IREF Pin Input Voltage
VREF Pin Input Voltage
CS Pin Input Voltage
DP Pin Input Voltage
DN Pin Input Voltage
LPC Pin Input Voltage
GATE Pin input Voltage
VSFB
VIREF
VVREF
VCS
0
V
0
V
0
3.5
0
V
-0.1
0
V
VDP
6
V
VDN
0
6
V
VLPC
VGATE
0
5
V
0
5.5
V
6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
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4
FAN6290QF/FAN6290QH
ELECTRICAL CHARACTERISTICS
VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VIN Section
Continuous Operating Voltage(7)
Operating Supply Current
Operating Supply Current
VIN-OP
IIN-OP-5V
IIN-OP-12V
IIN-Green
16
V
VIN=5 V, VCS= -60 mV
VIN=12 V, VCS= -60 mV
8
8
mA
mA
mA
5 V Green Mode Operating Supply Current VIN=5 V, VCS=0 mV
1.2
1.6
VIN-UVP Section
Voltage difference between GND and CS
Only for FAN6290QH
VCS- UVP
3.0
6.5
10.0
mV
for fixed UVP current (IO-UVP.typ=217 mA)
VIN Under-Voltage-Protection Enable, 9 V
VIN Under-Voltage-Protection Enable, 12 V For QC2.0 12 V Mode
VIN Under-Voltage-Protection Disable, 9 V For QC2.0 9 V Mode
For QC2.0 9 V Mode
VIN-UVP-L-9V
VIN-UVP-L-12V
VIN-UVP-H-9V
VIN-UVP-H-12V
tD-VIN-UVP
5.00
7.50
5.50
8.00
45
5.50
8.00
6.00
8.50
60
6.00
8.50
6.50
9.00
75
V
V
V
VIN Under-Voltage-Protection Disable, 12 V For QC2.0 12 V Mode
CC Mode UVP Debounce Time
V
ms
VIN-OVP Section
Output Over-Voltage Protection through VIN
Pin at VO=3.6 ~ 5 V
VIN-OVP-5V
VIN-OVP-6V
VIN-OVP-9V
5.5
8.1
6.0
8.4
6.5
8.7
V
V
V
Output Over-Voltage Protection through VIN
Pin at VO=5.2 ~ 6 V
Output Over-Voltage Protection through VIN
Pin at VO=6.2 ~ 9 V
10.3
10.8
11.3
Output Over-Voltage Protection through VIN
Pin at VO=9.2 ~ 12 V
VIN-OVP-12V
tD-OVP
13.6
22
14.4
33
15.0
44
V
OVP Debounce Time
μs
Internal Bias Section
Turn-On Threshold Voltage
VIN Increases
VIN-ON
2.9
2.8
3.2
2.9
0.3
3.4
3.0
V
V
Turn-Off Threshold Voltage
VIN Decreases after VIN=VIN-ON
VIN Decreases after VIN=VIN-ON
VIN-OFF
Hysteresis of Turn-Off Threshold Voltage
Turn-On Debounce Time
VIN-OFF-HYS
tVIN-on-debounce
tVIN-off-debounce
VLATCH-OFF
V
50
200
2.5
µs
µs
V
Turn-Off Debounce Time
Output Voltage Releasing Latch Mode(8)
Constant Current Sensing Section
Current-Sense Amplifier Gain(7)
1.5
2.0
VIN=5 V, VCS= -60 mV
AV-CCR
10
V/V
mV
Voltage difference between GND and CS at
IO-NOMINAL=3.0 A of FAN6290QF(8)
IO=3.0~3.4 A, IOTYP=3.2 A (3 mV Offset)
VCS-3.0A-QF
90.0
59.5
43.5
90.0
93.0
96.0
64.5
48.5
96.0
67.5
Voltage difference between GND and CS at
IO-NOMINAL=2.0 A of FAN6290QF(8)
IO=2.0~2.3 A, IOTYP=2.15 A (3 mV Offset) VCS-2.0A-QF
IO=1.5~1.8 A, IOTYP=1.65 A (3 mV Offset) VCS-1.5A-QF
62.0
46.0
93.0
65.0
mV
mV
mV
Voltage difference between GND and CS at
IO-NOMINAL=1.5 A of FAN6290QF(8)
Voltage difference between GND and CS at
IO-NOMINAL=3.0 A of FAN6290QH(8)
IO=3.0~3.4 A, IOTYP=3.2 A (3 mV Offset)
IO=2.0~2.4 A, IOTYP=2.2 A (3 mV Offset)
VCS-3.0A-QH
Voltage difference between GND and CS at
IO-NOMINAL=2.0 A of FAN6290QH(8)
Current-Sensing Input Impedance(8)
VCS-2.0A-QH
ZCS
62.5
4
mV
MΩ
mV
Voltage difference between GND and CS
for Green Mode
RCS=30 mΩ
VCS-Green
2
5
8
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5
FAN6290QF/FAN6290QH
ELECTRICAL CHARACTERISTICS (CONTINUED)
VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Constant Current Sensing Section (continued)
Voltage difference between GND and CS
for Green Mode
Only for under 4.8 V Mode of QC3.0,
RCS=30 mΩ
VCS-Green-
LowQC3.0
34
39
44
100
16
mV
µs
TGreen-EN-
Debounce
Green Mode Enable Debounce Time
Green Mode Disable Debounce Time
After VCS<VCS-Green
After VCS>VCS-Green
TGreen-DIS-
Debounce
8
12
ms
Constant Voltage Sensing Section
Reference Voltage at 5 V
VIN=5 V, VCS=0 V, VDP=0.6 V, VDN=0 V
VIN=9 V, VCS=0 V, VDP=0.6 V, VDN=0 V
VIN=12 V, VCS=0 V, VDP=0.6 V, VDN=0 V
VCVR-5V
VCVR-9V
VCVR-12V
0.98
1.76
1.00
1.80
1.02
1.84
V
V
V
Reference Voltage at 9 V
Reference Voltage at 12 V
2.335
2.400
2.465
Reference Voltage of Increment Step via
continuous mode of QC3.0 protocol
VIN=12 V, VCS=0 V, VDP=0.6 V,
VDN=3.3 V
VCVR-STEP-INC
VCVR-STEP-DEC
35
35
40
45
45
mV
Reference Voltage of Decrement Step via
Continuous Mode of QC3.0 Protocol
VIN=12 V, VCS=0 V, VDP=0.6 V,
VDN=3.3 V
40
40
mV
ms
Reference Voltage Soft-drop Time(7)
Cable Drop Compensation Section
Cable Compensation Voltage(8)
During Mode change from VIN to Low VIN tCVR-Soft-drop
VCS=-60 mV
VCS=-60 mV
VCOMR-CDC
VCOMR-OVP
64.5
360
68.0
510
71.5
660
mV
mV
OVP Cable Compensation Voltage(8)
Constant Current Amplifier Section
Disable Constant Current Amplifier Time
during Startup
After VIN>VIN-ON
tStart-Dis-CC
1.3
2.5
6.0
ms
Internal Amplifier Transconductance(7)
Internal Amplifier Dominant Pole(7)
GmCC
fP-CC
3.5
10
Ʊ
kHz
Internal CC Amplifier Input Resistor
RCC-IN
8.50
13.75
19.00
30
kΩ
Constant Voltage Amplifier Section
Internal Amplifier Dominant Pole(7)
CV Bias Current(7)
fP-CV
10
kHz
nA
IBias-CV
Bleeder Section
Voltage difference between GND and CS to
enable Bleeding (IO-EN-BLD.typ=0.42 A)(7)
Debounce time to decide enable Bleeding(7) Decreasing VCS, RCS=30 mΩ
Decreasing VCS, RCS=30 mΩ
VCS-EN-BLD
tCS-EN-BLD
IVIN -Sink
8
12
16
mV
ms
mA
0.6
1.0
VIN Pin Sink Current through when
VIN=9 V
200
Bleeding(7)
VIN Pin Internal MOSFET Parasitical
Resistor(7)
RDS_on_BLD
tBLD-MAX
40
Ω
Maximum Discharging Time when
Disabling OVP & SR Gate
Bleeding(7)
275
2
320
365
ms
Feedback Section
Feedback Pin Maximum Sink Current
ISFB-Sink-MAX
mA
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6
FAN6290QF/FAN6290QH
ELECTRICAL CHARACTERISTICS (CONTINUED)
VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Protocol Section_Quick Charge 2.0 Interface
DP Low Threshold Voltage
VDPL
VDPH
0.24
1.95
0.30
1.95
1.0
0.25
2.05
0.35
2.05
1.2
0.28
2.15
0.40
2.15
1.4
V
V
DP High Threshold Voltage
DN Low Threshold Voltage
VDNL
V
DN High Threshold Voltage
VDNH
V
DP and DN High Debounce Time
DP Disconnect Debounce Time
DN Low Debounce Time, VDN < VDNL
Mode-Change Debounce Time
Blanking Time after Mode Change
DP Pull Low Resistance
tBC1.2
s
tDISCONNECT
tTOGGLE
tV_CHANGE
tV_REQUEST
RDP
5
10
15
ms
ms
ms
ms
kΩ
kΩ
1.0
20
60
40
60
100
1500
24.80
300
14.25
1120
DN Pull Low Resistance
RDN
19.53
Protocol Section_Quick Charge 3.0 Interface
Mode-Change Debounce Time
VDP=0.6, VDN=3.3 V
For TACTIVE and TINACTIVE
tV_CHANGE
20
40
60
ms
µs
Mode-Change Debounce Time for
Continuous Mode
100
150
200
tCONT_CHANGE
VIN_CONT_
VIN Voltage Range for Continuous Mode(7)
3.6
12
V
RANGE
Table 1.
Quick Charge 3.0 & 2.0 Output Modes
Mode
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
VDP (Typ.)
0.6 V
VDN (Typ.)
VOUT
0 V
5 V
9 V
3.3 V
0.6 V
0.6 V
3.3 V
3.3 V
0.6 V
12 V
0.6 V
Continuous Mode
Reserved
3.3 V
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7
FAN6290QF/FAN6290QH
ELECTRICAL CHARACTERISTICS (CONTINUED)
VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Protocol Section_Auto Detection
Default DP Voltage when floating
Default DN Voltage when floating
DP Pin Output Impedance in Default Mode
DN Pin Output Impedance in Default Mode
2.75 V Supply Mode
VDP_2.75V
VDN_2.75V
RDP_2.75V
RDN_2.75V
2.65
2.65
23
2.75
2.75
28
2.85
2.85
33
V
V
2.75 V Supply Mode
2.75 V Supply Mode
2.75 V Supply Mode
kΩ
kΩ
23
28
33
Increment of VDP for exiting 2.75 V Supply
Mode
Increment from VDP_2.75V
VDP_INC
115
170
225
mV
Debounce time for exiting 2.75 V Supply
Mode
tEXIT_MODE1
tREC_MODE1
3
3
4
4
5
5
ms
Delay time to recover to 2.75 V Supply Mode VDP< VDPL in BC1.2 Mode
sec
Output Driver Section
Output Voltage Low
Output Voltage High
VIN=5 V, IGATE=100 mA
VIN=5 V
VOL
VOH
0.16
0.25
35
V
V
4.5
VIN=5 V, CL=3300 pF,
GATE=1 V ~ 4 V
Rising Time(7)
Falling Time(7)
tR
tF
20
9
ns
ns
ns
VIN=5 V, CL=3300 pF,
GATE=4 V~ 1 V
Propagation Delay to OUT High (LPC
Trigger)
VIN=5 V, GATE=1 V
VIN=5 V, GATE=4 V
tPD-HIGH-LPC
44
80
Propagation Delay to OUT Low (LPC
Trigger)(7)
Gate Inhibit Time(7)
Internal RES Section
Internal RES Ratio(7)
tPD-LOW-LPC
tINHIBIT
30
ns
µs
1.4
VIN=5~12 V
KRES
0.150
5.5
V/V
%
VIN Dropping Protection Ratio with Two
Cycle
LPC Width=5 µs, VIN=5 V to 3.5 V
KVIN-DROP
70
90
Debounce Time for Disable SR when VIN
Dropping Protection
tSR_OFF
3.8
7.2
ms
LPC Section
Linear Operation Range of LPC Pin
Voltage(7)
VIN -OFF < VIN ≤ 5 V
VLPC
0.5
VIN -1
1.58
V
LPC Sink Current
VLPC=1 V
ILPC-SINK
100
nA
V
SR Enabled Threshold Voltage @High-Line
VLPC-HIGH-H
Threshold Voltage on LPC Rising Edge
@High-Line(7)
VLPC-HIGH-H *0.875=VLPC-TH-H
VLPC-TH-H
VLPC-HIGH-L-5.5V
VLPC-TH-L-5.5V
VLPC-HIGH-L-9V
VLPC-TH-L-9V
1.31
V
V
V
V
V
V
V
SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-5.5V=VLPC-TH-L-5.5V / 0.875
0.86
1.06
1.23
Threshold Voltage on LPC Rising Edge @
Spec.=0.45+0.05*VIN, VIN=5.5 V
Low-Line(7)
0.725
0.90
SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-9V=VLPC-TH-L-9V / 0.875
Threshold Voltage on LPC Rising Edge @
Spec.=0.45+0.05*VIN, VIN=9 V
Low-Line(7)
SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-12V=VLPC-TH-L-12V / 0.875
VLPC-HIGH-L-12V
VLPC-TH-L-12V
VLPC-TH-TRIG
VLINE-H-5.5V
Threshold Voltage on LPC Rising Edge @
Spec.=0.45+0.05*VIN, VIN=12 V
Low-Line(7)
1.05
70
Falling Edge Threshold Voltage to Trigger
SR(7)
mV
V
Low-to-High Line Threshold Voltage on LPC
Pin
VIN=5.5 V
1.84
1.93
2.02
www.onsemi.com
8
FAN6290QF/FAN6290QH
ELECTRICAL CHARACTERISTICS (CONTINUED)
VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LPC Section (continued)
High-to-Low Line Threshold Voltage on
LPC Pin
VIN=5.5 V
VLINE-HYS-5.5V=VLINE-H-5.5V - VLINE-L-5.5V
VIN=9 V
VLINE-L-5.5V
VLINE-HYS-5.5V
VLINE-H-9V
1.75
1.83
0.1
1.91
V
V
V
Line Change Threshold Hysteresis
Low-to-High Line Threshold Voltage on
LPC Pin
2.05
1.96
2.14
2.23
2.12
High-to-Low Line Threshold Voltage on
LPC Pin
VIN=9 V
VLINE-L-9V
VLINE-HYS-9V
VLINE-H-12V
2.04
0.1
V
V
V
Line Change Threshold Hysteresis
VLINE-HYS-9V=VLINE-H-9V - VLINE-L-9V
VIN=12 V
Low -to-High Line Threshold Voltage on
LPC Pin
2.23
2.14
2.32
2.41
2.30
High-to-Low Line Threshold Voltage on
LPC Pin
VIN=12 V
VLINE-L-12V
2.22
V
Line Change Threshold Hysteresis
Higher Clamp Voltage
VLINE-HYS-12V=VLINE-H-12V - VLINE-L-12V
VLINE-HYS-12V
VLPC-CLAMP-H
0.1
6.2
V
V
5.4
7.0
LPC Threshold Voltage to Disable SR Gate
Switching
VIN=5 V. LPC=3 V↑
VLPC-DIS
VIN - 0.6
V
Enable VLPC-DIS
Disable VLPC-DIS
Increasing VIN
Decreasing VIN
VEN-LPC-DIS
VDIS-LPC-DIS
4.30
4.10
4.45
4.25
4.60
4.40
V
V
Line Change Debounce from Low-Line to
High-Line
tLPC-LH-debounce
tLPC-HL-debounce
15
23
15
31
ms
µs
Line Change Debounce from High-Line to
Low-Line(7)
Internal Timing Section
Ratio between VLPC & VRES
VIN=5.5 V, FLPC=50 kHz, KRES=0.15
VLPC=3 V
RatioLPC-RES
tLPC-EN-H
3.88
150
4.09
250
4.30
350
Minimum LPC Time to Enable the SR Gate
@ High-Line
ns
ns
Minimum LPC Time to Enable the SR Gate
@ Low-Line
VLPC=1.5 V
tLPC-EN-L
520
620
720
Minimum Gate Width(7)
tMIN
0.35
0.6
0.50
1.0
0.65
1.4
µs
µs
ns
Minimum Gate Limit On-time
ton-SR(n+1)- ton-SR(n) < tgate-limit
tgate-limit-min
tgate-limit
500
Limitation between LPC Rising Edge to
next LPC Rising Edge Max. Period
Forced internal CT Reset Time(7)
tMAX-PERIOD
tCT-RESET
28
40
10
52
µs
ns
Reverse Current Mode Section
Reverse Current Mode Entry Debounce
Time
VIN=5 V, VLPC=0 V
VIN=5 V, VLPC=0 V
Treverse-debounce
IOP.reverse
350
500
650
1.7
ms
Operating Current during Reverse Current
Mode
mA
Data Line Over-Voltage Protection
DP Pin Over-Voltage Protection
DN Pin Over-Voltage Protection
Excepting 2.75 V Supply Mode
Excepting 2.75 V Supply Mode
VDP-OVP
VDN-OVP
4.10
4.10
4.35
4.35
4.60
4.60
V
V
tDN-DP-OVP-
Debounce
DP/DN Pin OVP Debounce Time
VDN > VDN-SD
1.5
3.0
4.5
ms
7. Guaranteed by Design.
8. Guaranteed at -5° ~ 85°C.
www.onsemi.com
9
FAN6290QF/FAN6290QH
TYPICAL CHARACTERISTICS
Figure 3 Turn-On Threshold Voltage (VIN-ON
)
Figure 4 Turn-Off Threshold Voltage (VIN-OFF
vs. Temperature
)
vs. Temperature
Figure 5 Reference Voltage at 5 V (VCVR-5V
)
Figure 6 Reference Voltage at 9 V (VCVR-9V
)
vs. Temperature
vs. Temperature
Figure 7 Reference Voltage at 12 V (VCVR-12V
)
Figure 8 VIN Under-Voltage-Protection Enable,
9 V (VIN-UVP-L-9V) vs. Temperature
vs. Temperature
www.onsemi.com
10
FAN6290QF/FAN6290QH
TYPICAL CHARACTERISTICS
Figure 9 VIN Under-Voltage-Protection Enable,
Figure 10 Minimum LPC Time to Enable the SR
Gate @ Low-Line (tLPC-EN-L) vs. Temperature
12 V (VIN-UVP-L-12V) vs. Temperature
Figure 11 Minimum LPC Time to Enable the SR
Gate @ High-Line (tLPC-EN-H) vs. Temperature
Figure 12 Ratio between VLPC & VRES (RatioLPC-RES
)
vs. Temperature
Figure 14 Reference Voltage of Decrement Step
via Continuous Mode of QC3.0 Protocol
(VCVR-STEP-DEC) vs. Temperature
Figure 13 Reference Voltage of Increment Step
via Continuous Mode of QC3.0 Protocol
(VCVR-STEP-INC) vs. Temperature
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11
FAN6290QF/FAN6290QH
APPLICATIONS INFORMATION
Table 2.
Series
Device Line-up Table
Quick Charge 3.0 (QC3.0) and Quick Charge 2.0
(QC2.0) Protocols
As described on Table 3, FAN6290Q supports up to
12 V (Class A) through QC3.0 protocol.
Output Voltage and its Nominal
Output Load
UVP
Operation
Name
3.6~6.0 V 6.2~9.0 V 9.2~12.0 V
Pull-down
SFB
FAN6290QF
FAN6290QH
3.0 A
3.0 A
2.0 A
3.0 A
1.5 A
2.0 A
Table 3.
Output Mode of FAN6290Q according to Quick
Charge 3.0
Reduce
CC
VDP
VDN
HVDCP Output Mode
5 V Mode
(Backward compatible with QC2.0)
FAN6290QF and FAN6290QH implement different
operation methods when the UVP is triggered.
0.6 V
0 V
9 V Mode
(Backward compatible with QC2.0)
FAN6290QH reduces constant current level after
triggering UVP. When a foldback level is performed on
the system, resistive load is normally used. Since this
reduced constant current is lower than the resistive load
in the UVP, the output voltage is collapsed and foldback
can be achieved. FAN6290QF pulls-down the SFB pin
after UVP is triggered. And then, it enters Latch Mode
Operation (Refer to Figure 22 and Figure 23). According
to Latch Mode Operation, the output voltage is collapsed
and foldback can be achieved.
3.3 V
0.6 V
0.6 V
0.6 V
12 V Mode
(Backward compatible with QC2.0)
0.6 V
3.3 V
3.3 V
3.3 V
Continuous Mode
Reserve (Keep previous status)
Within continuous mode, output-voltage can be
increased or decreased with 200 mV step per an
increment or decrement protocol, respectively. (Refer to
Figure 16 and Figure 17 which are examples of
increment and decrement). FAN6290Q can enter
continuous mode from any of 5 V, 9 V and 12 V modes.
However, it can return to 5 V mode from continuous
mode.
Protocols (Auto-detection)
2.75 V Supply Mode
Some Apple products charge higher current when a
dedicated charging port sources specific voltage on D+
and D- lines. FAN6290Q supports 2.75 V on D+ and D-
lines, respectively. Apple products regard it as the
attached charging port supports 2.4A, and it charges with
maximum 2.4 A. Once FAN6290Q is enabled, D+ and
D- supplies 2.75 V as default. Fairchild intelligent auto-
detection acknowledges BC1.2. As soon as BC1.2 gets
started, FAN6290Q leaves 2.75 V supply mode
immediately. After acknowledging QC3.0 or QC2.0,
FAN6290Q does not return 2.75 V supply mode as long
as a portable device is not detached.
TGLITCH_CONT_CHANGE
DP
3.3V
0.6V
4 high/low pulses = 0.2V*4 = 0.8V
DN
3.3V
0.6V
BUS
5.8V
5V
Start of communication
End of communication
Power on Reset
Figure 16 Example of Increment Timing Diagram
(800 mV Increment from 5 V)
TGLITCH_CONT_CHANGE
DP
3.3V
2.75V supply mode
Acknowledge
(DPà2.75V, DNà2.75V)
QC3.0 or QC2.0
0.6V
DN
3 high/low pulses = 0.2V*3 = 0.6V
∆VDP > VDP_INC for tEXIT_MODE1
OR VDP < VDPH for tEXIT_MODE1
OR VDN < VDNH for tEXIT_MODE1
VDP < VDPH
for tDISCONNECT
3.3V
h
c
VDPL > VDP
for tREC_MODE1
a
t
e
D
0.6V
BC1.2 mode
HVDCP mode
BUS
(DP & DN short)
(DPàRDP, DNàRDN
)
VDPL < VDP < VDPH
for tBC1.2
5.8V
5.2V
Figure 15 Sequence of Auto-detection
Start of communication
End of communication
Figure 17 Example of Decrement Timing Diagram
(600 mV Decrement from 5.8 V)
www.onsemi.com
12
FAN6290QF/FAN6290QH
Communication Function Description
Constant Voltage Control
Vo
RCS
-
The internal constant voltage control block regulates
adaptive output voltages. Output voltage is sensed
through an external resistor divider. The sensed output
voltage is connected to the VREF which is the non-
inverting input terminal of the internal operational
amplifier. The inverting input terminal is connected to
the internal voltage reference (VCVR) which can be
adjusted according to the requested output voltage via
Quick Charge 3.0 protocol. The amplifier and an internal
switch operate as a shunt regulator. The output of the
shunt regulator is connected to the external opto-coupler,
and this pin is named as Secondary Feedback (SFB). To
compensate output voltage regulation being stable, one
capacitor and one resistor are connected typically
between the SFB and VREF pins as shown in Figure 18.
The output voltage can be derived as shown in equation
(1) and the recommended ratio of the resistor divider is
5.
GND
CS
FB
IREF
SFB
VCCR
RF1
VREF
RF2
VCVR
Figure 18 Constant Voltage and Constant Current
Circuit
Green Mode Operation
In order to reduce power consumption at light-load
conditions, FAN6290Q enters the green mode. When
VCS which is the voltage between CS and GND pins is
smaller than VCS-Green with longer duration than tGreen-EN-
Debounce, FAN6290Q enters the green mode. Typical
output current entering the green mode is 170 mA. While
it operates in the green mode, some internal blocks are
disabled such as Synchronous Rectifier control block.
Therefore, the operating current can be reduced to
1.2 mA (typ.). It leaves green mode when VCS is larger
RF1 RF 2
VO VCVR
(1)
RF 2
Constant Current Control
In order to support adaptive constant output current,
FAN6290Q incorporates the constant-current control
circuit internally. Output current is sensed via a current-
sense resistor, RCS, which is connected between the CS
pin and GND pin. The sensed signal is internally
than VCS-Green with longer duration that tGreen-DIS-Debounce
.
amplified, and this amplified voltage is connected to the
non-inverting input of the internal operation amplifier.
Likewise the constant voltage amplifier circuit, it also
plays a role as a shunt regulator to regulate the constant
output current. In order to compensate output current
regulation, one capacitor and one resistor are connected
between IREF and SFB pins typically as the Figure 18.
The constant output current is decided by the equation
(2). 30 mΩ is typically used for the sense resistor.
Cable Drop Compensation
To regulate the output voltage constantly at the end of a
cable regardless of output current, the cable drop
compensation function is implemented. The weight of
compensation is internally fixed. The compensated
output voltage is described in equation (3).
RF1 RF 2 IOUT
VOUT -COMPENSATION VCOMR-CDC
(3)
RF 2
2
VCCR
1
IO _CC
(2)
AV -CCR RCS
Output OVP also implements cable drop compensation.
Ratio of cable drop compensation for output OVP is
different with cable drop compensation for constant
voltage regulation shown in equation (4).
Since CS pin senses small amounts of voltage, the
sensing resistor should be positioned as close as possible
to CS pin. Shown in Figure 18, an RC low pass filter can
be added on the CS pin to be immunized from noise.
IOUT
VOVP VIN -OVP VCOMR-OVP
(4)
2
www.onsemi.com
13
FAN6290QF/FAN6290QH
UVP-L longer than tD-VIN-UVP, the constant current level is
RCable-BUS
VBUS
reduced to 220 mA (typ.). FAN6290Q leaves UVP when
VIN voltage is higher than VIN-UVP-H. While the UVP is
operated, the synchronous rectifier control is disabled to
avoid shoot-through. Some option versions enter the
latch mode instead of reducing output current after
triggering UVP. The UVP function is only enabled when
QC2.0 protocol is accepted. For QC3.0 mode, UVP
function is disabled.
VBUS
@PCB End
@Cable End
COUT
RCable-GND
RCS
IO
VIN
CS
GND
USB
USB
OVP
Σ
Cable Drop
Compensation
Mode
Table 3. Under-Voltage Protection Threshold Level
RF1
VREF
Symbol
VIN-UVP-L-9V
VIN-UVP-H-9V
VIN-UVP-L-12V
VIN-UVP-H-12V
VOUT Range
UVP Level (Typ.)
RF2
Σ
5.50 V
9 V of QC2.0
VCVR
Mode
6.00 V
8.00 V
12 V of QC2.0
Figure 19 Cable-Drop Compensation Block
Output Over-Voltage Protection
8.50 V
Figure 20 shows the output Over-Voltage Protection
(OVP) block, which is adaptive according to output
voltage status. Once the sensed output voltage via VIN
pin is larger than VIN-OVP longer than tD-OVP, the internal
OVP switch is enabled with latch mode. And the latch
COUT
VBUS
RCS
IO
IREF
CS
GND
VIN
mode of FAN6290Q is reset when VIN < VLATCH-OFF
.
When FAN6290Q is compatible with FAN602, VS-UVP of
FAN602 can be triggered after releasing latch mode of
FAN6290Q. According to protection mode of VS-UVP of
FAN602, VIN-OVP of FAN6290Q is operated as Extended
Auto-Restart mode or latch mode.
SFB
Table 2. Over-Voltage Protection Threshold Level
UVP
Protection
VCCR
Symbol
VOUT Range
3.6 V ~ 5.0 V
5.2 V ~ 6.0 V
6.2 V ~ 9.0 V
9.2 V ~ 12.0 V
OVP Level (Typ.)
Mode
VIN-OVP-5 V
VIN-OVP-6 V
VIN-OVP-9 V
VIN-OVP-12 V
6.0 V
8.4 V
10.8 V
Figure 21 Output Under-Voltage Protection Block
D+/D- Data Line Over-Voltage Protection
14.4 V
Even though severe fault is occurred between BUS and
Ground, monitoring data line status also can protect USB
fault condition indirectly because data lines (D+/D-) may
be polluted at the same time with BUS line pollution.
Therefore, FAN6290Q implements data line Over-
Voltage-Protection. It can protect when the BUS and
D+/D- are short-circuited with small impedance. When
voltage on D+ line and/or D- line is higher than VDP-OVP
and/or VDP-OVP longer than VDN-DP-OVP-Debounce, Over-
Voltage Protection is triggered. After detecting fault
condition, FAN6290Q enters latch mode. When
FAN6290Q releases the latch mode, FAN602 enters VS-
UVP.
COUT
VBUS
RCS
VIN
OVP
OVP
Q
D
RST
Latch-OFF
VIN-OVP
Mode
Figure 20 Output Over-Voltage Protection Block
Latch Mode Operation
Output Under-Voltage Protection
FAN6290Q implements latch mode operation to deliver
fault conditions which are detected on secondary-side to
primary-side. When one fault condition is triggered
among cable fault Protections, over-voltage protection
and under-voltage protection, SFB is started to be
In order to support foldback level of each output mode,
the output Under-Voltage Protection (UVP) function is
incorporated. The UVP function can reduce power
delivery during output soft-short fault. Figure 21 shows
its implementation. Once VIN voltage is lower than VIN-
www.onsemi.com
14
FAN6290QF/FAN6290QH
Reset Circuit on VREF and IREF
pulled-down with latch mode. This latch mode is
VREF and IREF pins are connected to VIN through
compensation circuits. When CV and CC amplifiers are
not enabled, VREF and IREF pin voltages are also
increased according to increased VIN voltage (dot lines
on Figure 24). The voltages on VREF and IREF are
higher than target threshold levels. The Reset circuit on
VREF and IREF are implemented as each pin is
connected to ground through internal switches. The
released when VIN voltage is lower than VLatch-off which
is lower than VIN-OFF. As shown on Figure 23, after the
Latch Mode is released, the primary-side controller
leaves burst mode and starts switching again. Since the
VLatch-off is much lower than output voltage level which
triggers VS-UVP of the primary-side controller, after
releasing latch mode, the primary-side controller triggers
VS-UVP. Therefore, throughout implementing the latch
mode operation, the primary-side controller can trigger
VS-UVP, and the system can enter latch mode. When not
only VIN-OVP and cable fault protection are triggered, but
also VIN voltage is lower than VIN-OFF, the latch mode is
enabled, either. The latch mode operation for VIN-OFF
avoids that system becomes open-loop when VIN < VIN-
IREF pin is additionally reset during tStart-Dis-CC
.
Reset circuit pulls-down current, and these currents
(IRESET_VREF and IRESET_IREF) can flow through
compensation circuits. If current flowing through the
opto-coupler is large enough, the primary controller
enters burst mode and triggers VS-UVP-H, because of
this startup may fail. Rbias helps to decrease current
flowing through the opto-coupler, to avoid startup failure.
The Rbias design depends on compensation design,
typically 2~6 kΩ is recommended.
.
OFF
CO1
CO2
VBUS
RCS
VIN
Primary
FB
VIN-ON
tStart-Dis-CC
Enable Reset
circuit
VIN
time
Without reset circuit
VREF
Cable Faults
VIN-OVP
VIN-UVP
SFB
Q
D
VCVR-5V
VIN-OFF
RST
time
Without reset circuit
IREF
VIREF@CC
VLatch-off
time
Figure 24 Reset Circuit Operation
Figure 22 Conceptual Latch Mode Block
VOUT
VSFB
VBUS
VOUT @VS-UVP
VLatch-off
RCS
-
GND
CS
FB
VDD.pri
Latch Mode
Rbias
IREF
VFB
IDS
SFB
VBURST
Fault
VCCR
RF1
Reset
VREF
VS-UVP
RF2
VCVR
Figure 23 Waveform of Latch Mode Operation
IRESET_IREF
IRESET_VREF
Figure 25 Reset Circuit and Rbias
www.onsemi.com
15
FAN6290QF/FAN6290QH
PCB Layout Guidelines
Printed Circuit Board (PCB) layout and design are very
important for switching mode power supplies where the
voltage and current change with high speed. Good PCB
layout minimizes Electro-Magnetic Interference (EMI)
and prevents excessive noise from surge or Electro-Static
Discharging (ESD). As shown in Figure 27 COUT1 and
COUT2 are the output capacitors; Q2 is the secondary-side
SR MOSFET. The following guidelines are
COUT1
COUT2
VO
RSENSE
CS
GND
Good connection
COUT1
COUT2
recommended for layout designs.
VO
.
The main power flows through Q2, COUT1, COUT2
and RCS. This power path should be separated with
signal grounds which are connected to FAN6290Q.
In addition, it is recommended that power ground is
directly connected to Y-cap. Refer to Figure 26.
RSENSE
Rpattern
Rpattern
CS
Bad connection;
CS & GND should be closed to Rcs
GND
.
The sensed voltage via RCS is very small value. In
order to avoid offset voltage or avoid inducing
switching noise on the sensed voltage, RCS should be
connected between ground of COUT2 and power
ground. And RCS should be positioned as close as
possible to CS pin and GND pin. Refer to Figure 27.
COUT1
COUT2
VO
RSENSE
CS
Bad connection;
Rcs should not be connected before Cout2
GND
.
To avoid switching noise interference to
Synchronous Rectifier operation, RLPC-H and RLPC-L
should be close to FAN6290Q. And power path
should be apart from LPC path.
COUT1
COUT2
VO
VBUS
RSENSE
COUT
SR
MOSFET
RSENSE
Signal GND
Power GND
CS
Wrong connection;
Rcs must not connected between Cout1 and Cout2
GND
CS
GND
GATE
LPC
DP
VIN
Figure 27 Examples of Sensing Resistor Connection
VREF
IREF
SFB
FAN6290Q
DP
DN
Signal GND
DN
Figure 26 Power and Signal Ground on the
Secondary-Side
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16
FAN6290QF/FAN6290QH
ORDERING INFORMATION
Operating
Temperature Range
Part Number
Package
Packing Method
FAN6290QFMX
FAN6290QHMX
10-Lead, SOP
10-Lead, SOP
Tape & Reel
Tape & Reel
-40C to +125C
-40C to +125C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
www.onsemi.com
17
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