FAN6300A [FAIRCHILD]
Highly Integrated Quasi-Resonant PWM Controller; 高度集成的准谐振PWM控制器
| 型号： | FAN6300A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Highly Integrated Quasi-Resonant PWM Controller |
| 文件： | 总13页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AN-6300
FAN6300 / FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant PWM Controller
Abstract
This application note describes a detailed design strategy for
higher-power conversion efficiency and better EMI using a
Quasi-Resonant PWM controller compared to the
range line voltage and reduces switching loss to minimize
switching voltage on drain of the power MOSFET.
To minimize standby power consumption and improve light-
load efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency and
perform extended valley voltage switching to keep to a
minimum switching voltage.
conventional, hard-switched converter with
a
fixed
switching frequency. Based on the proposed design
guideline, a design example with detailed parameters
demonstrates the performance of the controller.
FAN6300/A/H controller provides many protection
functions. Pulse-by-pulse current limiting ensures the fixed
peak current limit level, even when short-circuit occurs.
Once an open-circuit failure occurs in the feedback loop, the
internal protection circuit disables PWM output
immediately. As long as VDD drops below the turn-off
threshold voltage, the controller also disables the PWM
output. The gate output is clamped at 18V to protect the
power MOS from high gate-source voltage conditions. The
minimum tOFF time limit prevents the system frequency from
being too high. If the DET pin reaches OVP level, internal
OTP is triggered, and the power system enters latch-mode
until AC power is removed.
Introduction
The highly integrated FAN6300/A/H PWM controller
provides several features to enhance the performance of
flyback converters. FAN6300/A are applied on Quasi-
Resonant flyback converter where maximum operating
frequency is below 100kHz and FAN6300H is suitable for
high frequency operation that is around 190kHz. A built-in
High Voltage (HV) startup circuit can provide more startup
current to reduce the startup time of the controller. Once the
VDD voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce power
consumption. An internal valley voltage detector ensures
power system operates in quasi-resonant operation in wide-
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
AN-6300
APPLICATION NOTE
Figure 1. Basic Quasi-Resonant Converter
HV
8
VDD
6
Internal
Bias
OVP
IHV
Two Steps
UVLO
16V/10V/8V
4.2V
2R
27V
Latched
Soft-Start
5ms
2
3
FB
FB OLP
Timer
55ms
R
2ms
30µs
Starter
DRV
Blanking
Circuit
SET
CLR
S
R
Q
Q
5
GATE
CS
PWM
Current Limit
18V
Over-Power
Compensation
IDET
(3µs/13µs)
for H version
Latched
0.3V
VDET
tOFF-MIN
(8µs/38µs)
Valley
Detector
tOFF-MIN
+9µs
t
OFF-MIN +5µs
1st
Valley
for H version
VDET
tOFF
Blanking
(4µs)
S/H
Latched
2.5V
(1.5µs) for H version
DET OVP
1
DET
Internal
OTP
0.3V
Latched
IDET
5V
7
4
GND
NC
Figure 2. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
2
AN-6300
APPLICATION NOTE
Design Procedure for the Primary-Side Inductance of Transformer
In this section, a design procedure is described using the
schematic of Figure 1 as a reference.
designed to turn on the MOSFET when Vds reaches its
minimum voltage Vin-n(Vo+Vd).
[a] Define the System Specifications
Line voltage range (Vin,min and Vin,max
Maximum output power (Po).
Output voltage (Vo) and maximum output current (Io)
)
n:1
+
+
-
+
-
Estimated efficiency (η)
Vd
Vin
The power conversion efficiency must be estimated to
calculate the maximum input power. In the case of NB
adaptor applications, the typical efficiency is 85%~90%.
n(Vo+Vd)
Vo
-
+
-
+
With the estimated efficiency, the maximum input power
is given by:
Coss
Vds
-
P
o
(1)
P =
in
η
Vds
[b] Estimate Reflected Output Voltage
n(Vo+Vd)
n(Vo+Vd)
n(Vo+Vd)
n(Vo+Vd)
Vds
Figure 3 shows the typical waveforms of the drain voltage
of quasi-resonant flyback converter. When the MOSFET
is turned off, the DC link voltage (Vo), together with the
output voltage (Vo) and the forward voltage drop of the
Schottky diode (Vd) reflected to the primary, are imposed
on the MOSFET. The maximum nominal voltage across
the MOSFET (Vds) is:
Vin,max
0V
Figure 3. Typical Waveform of MOSFET Drain Voltage
for QR Operation
Vds,max =Vin,max + n(Vo +Vd )
(2)
Ids
where the turns ratio of primary to secondary side of
transformer is defined as n and Vds is as specified in
Equation 2.
pk
Ids
By increasing n, the capacitive switching loss and
conduction loss of the MOSFET is reduced. However, this
increases the voltage stress on the MOSFET as shown in
Figure 3. Therefore, determine n by a trade-off between
the voltage margin of the MOSFET and the efficiency.
Typically, a turn-off voltage spike of Vds is considered as
100V, thus Vds,max is designed around 490~550V
(75~85% of MOSFET rated voltage).
Iin
Id
DTs
Vds
[c] Determine the Transformer Primary-side
Vin+n(Vo+Vd)
Vin-n(Vo+Vd)
Inductance (LP)
n(Vo+Vd)
n(Vo+Vd)
Figure 4 shows the typical waveforms of MOSFET drain
current (Ids), secondary diode current (Id), and the
MOSFET drain voltage (Vds) of a QR converter. During
Vin
t
OFF, the current flows through the secondary side rectifier
tON
tOFF
TS
tF
diode. When Id reduces to zero, Vds begins to drop by the
resonance between the effective output capacitor of the
MOSFET and the primary-side inductance (LP). To
minimize the switching loss, the FAN6300/A/H is
Figure 4. Typical Waveform of QR Operation
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
3
AN-6300
APPLICATION NOTE
To determine the primary-side inductance (LP), the
following variables should be determined beforehand:
[d] Determine the Proper Core and the
Minimum Primary Turns
The minimum switching frequency (fs,min): The
maximum average input current occurs at the
minimum input voltage and full-load condition.
Meanwhile, the switching frequency is at minimum
value during QR operation.
When designing the transformer, consider the maximum
flux density swing in normal operation (Bmax). The
maximum flux density swing in normal operation is
related to the hysteresis loss in the core, while the
maximum flux density in transient is related to the core
saturation.
The falling time of the MOSFET drain voltage (tf):
As shown in Figure 4, the falling time of MOSFET
drain voltage is half of the resonant period of the
MOSFET effective output capacitance and primary-
side inductance. If a resonant capacitor is added to be
paralleled with Coss, tf can be increased and EMI can
be reduced. However, this forces a switching loss
increase. The typical value of tf for NB adaptor
application is about 0.5~1μs.
From Faraday’s law, the minimum number of turns for the
transformer primary side is given by:
pk
LPIds,max
NP,min
=
×106
(9)
Bmax Ae
where:
LP
is
specified
in
Equation
7;
pk
Ids,max is the peak drain current specified in Equation 6;
Ae is the cross-sectional area of the core in mm2; and
Bmax is the maximum flux density swing in tesla.
After determining fs,min and tf, the maximum duty cycle is
calculated as:
Generally, it is possible to use Bmax =0.25~0.30 T.
n(Vo +Vd )
Dmax
=
×(1- fs,min ×tf )
(3)
n(Vo +Vd )+V
in
Determine the Number of Turns for Auxiliary
Winding
where Vin,min is specified at low-line and full-load.
According to Equation 1, the maximum average input
current Iin,max is determined as
The number of turns for auxiliary winding (Na) can be
obtained by:
VoIo
VDD +VD1
Iin,max
=
(4)
Na =
(10)
Vin,minη
Vo +Vd
According to Figure 3, Iin,max can be obtained as:
where:
VDD is the operating voltage for VDD pin;
VD1 is the forward voltage drop of D1 in Figure 5; and
Vo and Vd as determined in Equation 2.
1
pk
Iin,max
=
DmaxIds,max
(5)
2
Ids,maxpk can be determined as:
V
in,minDmax
pk
Ids,max
=
(6)
Lmfs,min
pk
In Equation 5, replace Ids,max by Equation 6, then
combine Equations 4 and 5 to obtain LP:
2
(Vin,minDmax )
LP =
(7)
2P fs,min
in
where Pin, and Dmax are specified in Equations 1 and 3,
respectively, and fs,min is the minimum switching
frequency.
Once LP is determined, the RMS current of the MOSFET
in normal operation are obtained as:
Dmax
rms
peak
(8)
Ids,max
=
Ids,max
3
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
4
AN-6300
APPLICATION NOTE
When the supply current is drawn from the transformer, it
draws a leakage current of about 1μA for the HV pin. The
maximum power dissipation of the RHV is:
Determine the Startup Circuitry
When the power is turned on, the internal current
(typically 1.2mA) charges the capacitor C1 through a
forward diode D2 and a startup resistor RHV. During the
startup sequence, the VAC from the AC terminal provides a
startup current of about 1.2mA and charges the capacitor
C1. RHV and D2 series connections can be directly
connected by VAC to the HV pin. As the VDD pin reaches
the turn-on threshold voltage VDD-ON, the FAN6300/A/H
activates and signals the MOSFET. The HV startup circuit
switches off and D1 is turned on when the energy of the
main transformer is delivered to secondary and auxiliary
winding.
2
P
= IHV -LC(typ.) ×RHV
(12)
RHV
where IHV-LC is the supply current drawn from the HV pin.
P
= 1μA2 x 100KΩ ≅ 0.1μW
(13)
RHV
The FAN6300/A/H has a voltage detector on the VDD pin
to ensure that the chip has enough power to drive the
MOSFET. Figure 7 shows a hysteresis of the turn-on and
turn-off threshold levels.
IDD
VDD-ON
4.5mA
V
AC
D2
80μA
10μA
VDD
tD-ON
RHV
IHV
D1
8V 10V
16V
8
6
4
HV
FAN6300/A/H
GND
VDD
Figure 7. UVLO Specification
C1
The turn-on and turn-off threshold voltage are internally
fixed at 16V and 10V. During startup, C1 must be charged
to 16V to enable the IC. The capacitor continues to supply
the VDD until the energy can be delivered from the
auxiliary winding of the main transformer. The VDD must
not drop below 10V during the startup sequence.
Figure 5. Startup Circuit for Power Transfer
The maximum power-on delay time is determined as:
If the secondary output short circuits or the feedback loop
is open, the FB pin voltage rises rapidly toward the open-
loop voltage, VFB-OPEN. Once the FB voltage remains
above VFB-OLP and lasts for tD-OLP, the FAN6300/A/H stops
emitting output pulses. To further limit the input power
under short-circuit or open-loop conditions, a special two-
step UVLO mechanism has been built in to prolong this
discharge time of the VDD capacitor. In Figure 8, the two-
step UVLO mechanism decreases the operating current
and pulls the VDD voltage toward the VDD-OFF. This sinking
current is disabled after the VDD drops below VDD-OFF. The
VDD voltage is again charged towards VDD-ON. With the
addition of the two-step UVLO mechanism, the average
input power during a short-circuit or open-loop condition
is greatly reduced. When the gate pulses are emitted, the
start-timer tSTARTER with 30μs per cycle is enabled. The
30μs start timer is enabled during startup until the output
voltage is established, when the feedback voltage (VFB) is
larger than 4.2V.
C1 ×VDD−ON
(11)
tD−ON
=
1.2mA
where VDD-ON is the FAN6300/A/H turn-on threshold
voltage and tD-ON is the power-on delay time of the
converter.
If a shorter startup time is required, a two-step startup
circuit, as shown in Figure 6, is recommended. In this
circuit, a smaller C1 capacitor can be used to reduce the
startup time. The energy supporting the FAN6300/A/H
after startup is mainly from a larger capacitor C2.
VDD-ON
VAC
D2
tD-ON
RHV
IHV
D1
D2
8
6
4
HV
FAN6300/A/H
GND
VDD
C1
C2
Figure 6. Two-Step Circuit Providing Power
Figure 8. FAN6300/A/H UVLO Effect
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
5
AN-6300
APPLICATION NOTE
Detection Pin Circuitry
Figure 9 shows the DET pin circuitry. The DET pin is
connected to an auxiliary winding by RDET and RA. The
voltage divider is used for the following purposes:
Detects the valley voltage of the switching waveform
to achieve the valley voltage switching. This ensures
QR operation, minimizes switching losses, and
reduces EMI.
Produces an offset to compensate the threshold
voltage of the peak current limit to provide a constant
power limit. The offset is generated in accordance
with the input voltage with the PWM signal enabled.
Figure 10. Voltage Sampled After 4µs(1.5µs for H
version) Blanking Time After Switch-off
Sequence
A voltage comparator and a 2.5V reference voltage
provide an output OVP protection. The ratio of the
divider determines what output voltage level to stop
gate.
VDET
2.5V
tOFF
Blanking
(4µs)
S/H
Latched
+
RDET
(1.5µs) for H version
DET
DET OVP
VAUX
1
0.3V
-
5V
RA
6
VDD
1
DET
To VDD
Figure 9. Detection Pin Section
+
RDET
First, determine the ratio of the voltage divider resisters.
The ratio of the divider determines what output voltage
level to stop gate. In Figure 10, the sampling voltage VS is:
Vo
RA
-
NA
NS
RA
VS =
⋅VO ⋅
<2.5V
(14)
RDET + RA
where NA is the number of turns for the auxiliary winding
and NS is the number of turns for the secondary winding.
Figure 11. Output Voltage OVP Detection Block
Once the secondary-side switching current discharges to
zero, a valley signal is generated on the DET pin. It
detects the valley voltage of the switching waveform to
achieve the valley voltage switching. When the voltage of
auxiliary winding VAUX is negative (as defined in Figure 9),
the DET pin voltage is clamped to 0.3V. RDET is
recommended as 150kΩ to 220kΩ to achieve valley
voltage switching. After the platform voltage VS in Figure
10 is determined, RA can be calculated by Equation 14.
Figure 11 shows the output voltage OVP detection block
of using auxiliary winding to detect Vo. In normal
condition, VS is designed to be below 2.5V. The nominal
voltage of VS is designed around 80% of the reference
voltage 2.5V; thus, the recommended value for VS is
1.9V~2.1V. The output over-voltage protection works by
the sampling voltage after the switching-off sequence. A
4μs blanking time ignores the leakage inductance ringing.
If the DET pin OVP is triggered, the power system enters
latch mode until AC power is removed.
Figure 12 shows the internal valley detection block of
FAN6300/A/H. The internal timer (minimum tOFF time)
prevents the system frequency from being too high. First
valley switching is activated after minimum tOFF time
8μs(3µs for H version) is counted. Figure 13 shows a
typical drain voltage waveform with first valley switching.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
6
AN-6300
APPLICATION NOTE
To SR F/F
VFB
(3µs/13µs)
for H version
0.3V
tOFF-MIN
(8µs/38µs)
Valley
Detector
tOFF- MIN
+9µs
VDET
1 st
Valley
tOFF-MIN +5µs
for H version
DET
1
0.3V
5V
Figure 14. VFB vs. tOFF-MIN Curve
To VDD
Vin
+
RDET
VAUX
RA
-
Figure 12. Valley Detection Block
Figure 15. QR Operation in Extended Valley Voltage
Detection Mode
Figure 13. First Valley Switching
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 14, once VFB is lower than 2.1V, the tOFF-MIN time
increases linearly with lower VFB. The valley voltage
detection signal does not start until the tOFF-MIN time
finishes. Therefore, the valley detect circuit is activated
until the tOFF-MIN time finishes, which decreases the
switching frequency and provides extended valley voltage
switching. In very light load conditions, it might fail to
detect the valley voltage after the tOFF-MIN expires. Under
this condition, an internal tTIME-OUT signal initiates a new
cycle start after a 9μs(5µs for H version) delay. Figure 15
and Figure 16 show the two different conditions.
Figure 16. Internal tTIME_OUT Initiates New Cycle After
Failure to Detect Valley Voltage (with 5µs Delay for
FAN6300H)
Figure 17 shows the VFB vs. PWM frequency curve, where fs,min
is the minimum switching frequency at the minimum input
voltage and full load condition, fs,max is maximum
switching frequency during first valley switching, and fs,g
is the minimum frequency when a 9μs(5µs for H version)
timer is enabled. When output load is gradually lighter
from maximum load, VFB becomes lower. Once VFB is below
2.1V, the green-mode function is activated; thus tOFF time is
extended linearly. The flyback converter is forced to enter
discontinuous conduction mode (DCM); therefore, the
switching frequency fs can be decreased once the
MOSFET drain voltage is switched at further extended
valley voltage (2nd, 3rd, 4th, 5th …valley, etc.). fs,g is larger
than 20kHz to prevent audio noise. Once the converter
enters deep DCM, VFB is lower than 1.2V. Meanwhile, the
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
7
AN-6300
APPLICATION NOTE
2ms timer tSTARTER is enabled and fs is around 500Hz to
save power.
on the FB pin to the GND can further increase the
stability. The maximum sourcing current of the FB pin is
1.2mA. The phototransistor must be capable of sinking
this current to pull FB level down at no load. The value of
the biasing resistor Rb is determined as:
Switching frequency (Hz)
fs,max
fs,min
VO -VD -VZ
⋅K ≥ 1.2mA
(16)
Rb
where:
VD is the drop voltage of photodiode, approx. 1.2V;
VZ is the minimum operating voltage;
2.5V of the shunt regulator; and
fs,g
20k
K is the current transfer rate (CTR) of the opto-coupler.
2k
For an output voltage VO = 5V, with CTR=100%, the
maximum value of Rb is 860Ω.
VFB
VFB,max
2.1V
1.2V
Figure 17. VFB vs. Switching Frequency Curve
Vo
RDET determines the extended valley switching capability.
A typical value for RDET is 150k-220kΩ. A smaller value
for RDET enhances the extended valley switching
capability, thus further extended valley voltage can be
switched. In different applications, the falling time of the
MOSFET drain voltage (tf, in Figure 4) may cause the
valley switching voltage to be imprecise. Adjust the RDET
value or add a capacitor CA connected from DET pin to
GND may be helpful to the valley switching voltage. The
recommended value for CA is below 22pF.
Rb
RFB
R1
FB
C1 R3
CFB
R2
Figure 18. Feedback Circuit
RDET also affects the H/L line constant power limit. To
compensate this variation for wide AC input range, the
DET pin produces an offset voltage to compensate the
threshold voltage of the peak current limit to provide a
constant-power limit. The offset is generated in
accordance with the input voltage when the PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher.
Leading-Edge Blanking (LEB)
A voltage signal proportional to the MOSFET current
develops on the current-sense resistor RS. Each time the
MOSFET is turned on, a spike induced by the diode
reverse recovery and by the output capacitances of the
MODFET and diode, appears on the sensed signal. A
leading-edge blanking time of about 300ns has been
introduced to avoid premature termination of MOSFET by
the spike. Therefore, only a small-value RC filter (e.g.
100Ω+470pF) is required between the SENSE pin and RS.
A non-inductive resistor for the RS is recommended.
Design the Feedback Control
FAN6300/A/H is designed for peak-current-mode control.
Current-to-voltage conversion is accomplished externally
with a current-sense resistor RS. In normal operation, the
FB level controls the peak inductor current IPK is:
VFB −1.2
3× RS
where VFB is the voltage of FB pin.
IPK
=
(15)
When VFB is less than 1.2V, the start-timer tSTARTER, with
500μs per cycle, is enabled.
Figure 19. Turn-On Spike
Figure 18 is a typical feedback circuit consisting mainly of
a shunt regulator and opto-coupler. R1 and R2 from a
voltage divider are for the output voltage regulation. R3
and C1 are adjusted for control-loop compensation. A
small-value RC filter (e.g. RFB =10Ω, CFB = 10nF) placed
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
8
AN-6300
APPLICATION NOTE
Two kinds of commonly used transformer structure are
introduced as follows:
Output Driver / Soft Driving
The output stage is a fast totem-pole driver that can drive
a MOSFET gate directly. It is also equipped with a
voltage clamping Zener diode to protect the MOSFET
from damage caused by undesirable over-drive voltage.
The output voltage is clamped at 18V. An internal pull-
down resistor is used to avoid a floating state of the gate
before startup. By integrating circuits to control the slew
rate of switch-on rise time, the external resistor RG may
not be necessary to reduce switching noise, improving
EMI performance.
Structure Type A:
Structure type A is sandwiching winding method. The
power supply is mostly used sandwiching the secondary
windings in between halves of the primary, especially
when the output power is large. The auxiliary winding is
at the top layer by increasing thickness between the
primary winding. This course of action can reduce the
leakage inductance and increase the coupling between the
primary and the secondary winding. It can also improve
the conversion efficiency and reduce the voltage spike on
the MOSFET owing to transformer leakage inductance.
However, it reflects the voltage spike on auxiliary winding
easily and causes a large voltage deviation on VDD in
light-load and heavy-load conditions.
Structure Type B:
Another kind of transformer structure is stacked winding
method, usually used in the switching power supplies with
smaller output power. This method produces worse
coupling between primary and secondary winding than
structure A; therefore, the voltage spike on the MOSFET
is higher and the conversion efficiency is lower.
Figure 20. Gate Drive
Transformer Structure
Leakage Inductance Effect
Figure 22 shows the modified structure of type A for
sandwiching winding. The auxiliary and secondary
windings are between halves of the primary windings.
With this method, smaller voltage deviation on VDD in
light load and heavy load can be achieved. Meanwhile, the
output voltage OVP level is more precise. Therefore, the
recommended transformer structure for the adaptor is
shown as Figure 22.
Figure 21 shows the practical waveform on the MOSFET
drain terminal. When the MOSFET turns off, a voltage
spike (Vspike) is produced on the drain terminal owing to
the transformer leakage inductance. The leak inductance is
not easily calculable, but it can be minimized through the
secondary windings between halves of the primary.
Meanwhile, the voltage waveform on the auxiliary
winding is similar to that on the MOSFET drain terminal.
These spike voltages contribute extra energy to the VDD
capacitor, which ruins the relationship between VDD
voltage and the output voltage.
Primary
Winding
Auxiliary
Winding
Secondary
Winding
(Insulated)
Primary
Winding
Figure 22. Sandwiching Winding Structure
Figure 21. MOSFET Drain Voltage Waveform
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
9
AN-6300
APPLICATION NOTE
Lab Note
Before modifying or soldering/desoldering the power
supply, to discharge the primary capacitors through the
external bleeding resistor. Otherwise, the PWM IC may be
destroyed by external high-voltage during the process.
This device is sensitive to electrostatic discharge (ESD).
To improve the production yield, the production line
should be ESD protected as required by ANSI ESD S1.1,
ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1
standards.
Printed Circuit Board Layout
Current/voltage/switching frequency make printed
circuit board layout and design a very important issue.
Good PCB layout minimizes excessive EMI and
prevents the power supply from being disrupted during
surge/ESD tests.
Two suggestions with different pros and cons for ground
connections are recommended:
GND3→2→4→1: Possible method for circumventing the
sense signals common impedance interference.
GND3→2→1→4: Potentially better for ESD testing
where a ground is not available for the power supply. The
charges for ESD discharge path go from secondary
through the transformer stray capacitance to the GND2
first. Then, the charges go from GND2 to GND1 and
back to the mains. Control circuits should not be placed
on the discharge path. Point discharge for common choke
can decrease high-frequency impedance and help increase
ESD immunity.
Guidelines:
To get better EMI performance and reduce line
frequency ripples, the output of the bridge rectifier
should be connected to capacitor Cbulk first, then to
the switching circuits.
The high-frequency current loop is found in Cbulk
–
Transformer – MOSFET – RS – Cbulk. The area
enclosed by this current loop should be as small as
possible. Keep the traces (especially 4→1) short,
direct, and wide. High-voltage drain traces related
the MOSFET and RCD snubber should be kept far
way from control circuits to prevent unnecessary
interference. If a heatsink is used for the MOSFET,
ground the heatsink.
Should a Y-cap between primary and secondary be
required, the Y-cap should be connected to the positive
terminal of the Cbulk (VDC). If this Y-cap is connected to
the primary GND, it should be connected to the negative
terminal of the Cbulk (GND1) directly. Point discharge of
the Y-cap also helps with ESD. However, according to
safety requirements, the creepage between the two
pointed ends should be at least 5mm.
As indicated by 3, the control circuits’ ground
should be connected first, then to other circuitry.
As indicated by 2, the area enclosed by the
transformer auxiliary winding, D1, and C1 should
also be kept small. Place C1 close to the
FAN6300/A/H for good decoupling.
Figure 23. Layout Considerations
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
10
AN-6300
APPLICATION NOTE
Design Example
This section shows a design example of 90W (19V/4.74A)
adaptor using QR PWM controller FAN6300/A/H and
boundary conduction mode PFC controller FAN6961. The
PFC output voltage is 260V at low AC input voltage, 400V
at high AC input voltage. From the specification, all critical
components are treated and final measurement results are
given.
Based on the design guideline, the critical parameters are
calculated and summarized as shown in Table 2.
Table 2. Critical System Parameters
Dmax
0.327
2.429A
260V
533.28V
0.6μs
34T
n
LP
6.8
700µH
400V
0.6V
0.87
5T
pk
Ids,max
Vin,min
Vds,max
tf
Vin,max
Vd
Table 1. System Specification
η
Input
NP
NS
Input Voltage Range
90~264VAC
47~63Hz
Line Frequency Range
NAUX
4T
Output
Output Voltage (Vo)
Output Power (Po)
19V
90W
50kHz
Minimum Switching Frequency (fs,min
)
L
R10
C11
D5
BD1
L1
EMI
Filter
AC
Input
+
PFC STAGE
C2
R2
D6
Vo
C7
C8
C9
R9C10
C1
D2
N
-
D4
D3
R3
D1
R1
C3
R4
R5
IC1
C4
DET
GATE
CS
6
FAN6300/A/H
R11
C12 R14
HV
VDD
8
1
IC2
R12
R6
C5
Q1
7
2
5
3
NC
FB
R7
IC3
C13
GND
4
R13
R8
C6
Figure 24.Complete Circuit Diagram
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
11
AN-6300
APPLICATION NOTE
Table 3. Bill of Materials
Part
Value
Note
Part
Value
Note
Resistor
R1
MOSFET
Q1
100k
68k
1/4W
2W
FDP15N65
15A/650V
Inductor
L1
R2
R3
1/4W
1/4W
1/4W
1/4W
1/4W
2W
3µH
0Ω
R4
180k
27k
IC
R5
IC1
FAN6300/A/H
PC817
R6
IC2
10Ω
100Ω
0.2Ω
47k
R7
IC3
TL431
R8
Diode
D1
R9
1/4W
1/2W
1/4W
1/4W
1/4W
1/4W
0.5A/600V
BYV95C
FR103
R10
R11
R12
R13
R14
D2
33Ω
220Ω
68k
D3
D4
1N4148
10k
D5
20A/100V
20A/100V
4A/600V
Schottky Diode
Schottky Diode
Bridge Diode
1.6k
D6
BD1
Capacitor
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
68µF
450V
630V
50V
C12
C13
22nF
3.3nF
47µF
222P/250V
Y-Capacitor
10µF
50V
470pF
47nF
1000µF
470µF
470µF
470µF
1nF
25V
25V
25V
25V
1kV
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
12
AN-6300
APPLICATION NOTE
Related Datasheets
FAN6300 — Highly Integrated Quasi-Resonant Current PWM Controller
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As used herein:
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
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© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
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