FAN6300AMY [FAIRCHILD]
Highly Integrated Quasi-Resonant Current Mode PWM Controller; 高度集成的准谐振电流模式PWM控制器![FAN6300AMY](http://pdffile.icpdf.com/pdf1/p00174/img/icpdf/FAN63_974985_icpdf.jpg)
型号: | FAN6300AMY |
厂家: | ![]() |
描述: | Highly Integrated Quasi-Resonant Current Mode PWM Controller |
文件: | 总15页 (文件大小:1029K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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December 2009
FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
Description
The highly integrated FAN6300A/H of PWM controller
provides several features to enhance the performance
of flyback converters. FAN6300A is applied on quasi-
resonant flyback converters where maximum operating
frequency is below 100kHz. FAN6300H is suitable for
high-frequency operation (up to 190kHz). A built-in HV
startup circuit can provide more startup current to
reduce the startup time of the controller. Once the VDD
voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce
power consumption. An internal valley voltage detector
ensures power system operates at quasi-resonant
operation over a wide-range of line voltage and any
load conditions, as well as reducing switching loss to
minimize switching voltage on drain of power MOSFET.
High-Voltage Startup
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking (LEB)
Internal Minimum tOFF
Internal 5ms Soft-Start
Over Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Over-Current Protection(FB Pin)
Auto-Recovery Open-Loop Protection(FB Pin)
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
VDD Pin and Output Voltage (DET Pin)
OVP Latched
Low Frequency Operation (below 100kHz) for
FAN6300A
to
a minimum switching voltage. The operating
frequency is limited by minimum toff time, which is 38µs
to 8µs in FAN6300A and 13µs to 3µs in FAN6300H, so
FAN6300H can operate at higher switching frequency
than FAN6300A.
High Frequency Operation (up to 190kHz) for
FAN6300H
FAN6300A/H controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed-peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as VDD drops below
the turn-off threshold voltage, the controller also
disables PWM output. The gate output is clamped at
18V to protect the power MOS from high gate-source
voltage conditions. The minimum tOFF time limit
prevents the system frequency from being too high. If
the DET pin triggers OVP, internal OTP is triggered and
the power system enters latch-mode until AC power is
removed.
Applications
AC/DC NB Adapters
Open-Frame SMPS
The FAN6300A/H controller is available in the 8-pin
Small Outline Package (SOP) and the Dual Inline
Package (DIP).
© 2009 Fairchild Semiconductor Corporation
FAN6300A/H • Rev. 1.0.1
www.fairchildsemi.com
Ordering Information
Operating
Temperature Range
Packing
Method
Part Number
Package
Eco Status
FAN6300AMY
FAN6300HMY
FAN6300ANY
FAN6300HNY
Green
Green
Green
Green
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
8-Lead, Small Outline Package (SOP)
8-Lead, Small Outline Package (SOP)
8-Lead, Dual In-line Package (DIP)
8-Lead, Dual In-line Package (DIP)
Tape & Reel
Tape & Reel
Tube
Tube
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
Application Diagram
Figure 1. Typical Application
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6300A(H) Rev. 1.0.1
2
Internal Block Diagram
HV
8
VDD
6
Internal
Bias
OVP
IH V
Tw o Steps
UVLO
16 V/10 V/8V
4 .2V
27 V
Latched
2R
Soft-Start
2
3
FB
5m s
FB OLP
Tim er
52m s
R
2 .1m s
30 µs
Starter
D RV
Blanking
Circuit
S
E T
S
R
Q
Q
5
GATE
CS
PW M
C urrent Lim it
18V
Over-Power
C om pensation
C
LR
ID ET
Latched
0.3 V
V D ET
Valley
Detector
tO FF
-MIN
tTIME
-O U T
VD ET
tO FF
Blanking
S/H
Latched
2.5V
DET OVP
1
DET
Internal
OTP
0 .3V
Latched
ID ET
5V
4
7
GND
NC
Figure 2. Functional Block Diagram
Marking Information
: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (N = DIP, M = SOP)
P: Y = Green Package
M: Manufacturing Flow Code
Figure 3. Marking Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
3
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:
-
Generates a ZCD signal once the secondary-side switching current falls to zero.
-
Produces an offset voltage to compensate the threshold voltage of the peak current limit to
provide a constant power limit. The offset is generated in accordance with the input voltage
when PWM signal is enabled.
1
DET
-
Detects the valley voltage of the switching waveform to achieve the valley voltage switching
and minimize the switching losses.
A voltage comparator and a 2.5V reference voltage develop a output OVP protection. The ratio
of the divider decides what output voltage to stop gate, as an optical coupler and secondary
shunt regulator are used.
The feedback pin should to be connected to the output of the error amplifier for achieving the
voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.
For the primary-side control application, FB is applied to connect a RC network to the ground
for feedback-loop compensation.
2
FB
The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop-gain attenuation. FAN6300A/H
performs an open-loop protection once the FB voltage is higher than a threshold voltage
(around 4.2V) more than 55ms.
Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit.
3
4
5
6
CS
The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and
GND is recommended.
GND
GATE
VDD
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18V.
Power supply. The threshold voltages for startup and turn-off are 16V and 10V, respectively.
The startup current is less than 20µA and the operating current is lower than 4.5mA.
7
8
NC
HV
No connect
High-voltage startup.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage
HV
VHV
500
25.0
7.0
V
VH
GATE
-0.3
-0.3
V
VL
VFB, VCS, VDET
V
SOP-8
DIP-8
400
800
+150
+150
+270
3.0
PD
Power Dissipation
mW
TJ
TSTG
TL
Operating Junction Temperature
°C
°C
°C
Storage Temperature Range
-55
Lead Temperature (Soldering 10 Seconds)
Human Body Model, JEDEC:JESD22-A114
Charged Device Model, JEDEC:JESD22-C101
ESD
KV
1.5
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
-40
+125
°C
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
5
Electrical Characteristics
Unless otherwise specified, VDD=10~25V, TA=-40°C~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
VDD Section
VOP
Continuously Operating Voltage
Turn-On Threshold Voltage
25
17
11
9
V
V
V
V
VDD-ON
15
9
16
10
8
VDD-PWM-OFF PWM Off Threshold Voltage
VDD-OFF
Turn-Off Threshold Voltage
7
VDD=VDD-ON -0.16V
GATE Open
IDD-ST
Startup Current
10
20
5.5
3.5
90
µA
mA
mA
µA
VDD=15V, fS=60KHz,
CL=2nF
IDD-OP
Operating Current
4.5
Green-Mode Operating Supply Current
(Average)
VDD=15V, fS=2KHz,
CL=2nF
IDD-GREEN
VDD=VDD-PWM-OFF
0.5V
-
IDD-PWM-OFF Operating Current at PWM-Off Phase
70
80
VDD-OVP
tVDD-OVP
IDD-LATCH
VDD Over-Voltage Protection (Latch-Off)
VDD OVP Debounce Time
26
27
150
42
28
V
100
200
µs
µA
VDD OVP Latch-Up Holding Current
VDD=5V
HV Startup Current Source Section
VHV-MIN Minimum Startup Voltage on Pin HV
50
V
VAC=90V(VDC=120V)
DD=0V
IHV
Supply Current Drawn from Pin HV
Leakage Current After Startup
1.5
4.0
mA
V
HV=500V,
DD=VDD-OFF +1V
IHV-LC
1
20
µA
V
Feedback Input Section
AV =ΔVCS/ΔVFB
0<VCS<0.9
AV
Input-Voltage to Current Sense Attenuation
1/2.75 1/3.00 1/3.25
V/V
ZFB
IOZ
Input Impedance
3
5
7
KΩ
mA
V
Bias Current
FB=VOZ
1.2
1.0
4.2
2
VOZ
Zero Duty-Cycle Input Voltage
Open Loop Protection Threshold Voltage
0.8
3.9
1.2
4.5
VFB-OLP
V
Debounce Time for Open-Loop/Overload
Protection
tD-OLP
tSS
46
52
62
ms
Internal Soft-Start Time
5
ms
Continued on the following page...
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
Unless otherwise specified, VDD=10~25V, TA=-40°C ~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
DET Pin OVP and Valley Detection Section
VDET-OVP
Av
Comparator Reference Voltage
Open-Loop Gain(3)
Gain Bandwidth(3)
2.45
2.50
60
1
2.55
V
dB
MHz
V
Bw
VV-HIGH
VV-LOW
tDET-OVP
Output High Voltage
4.5
Output Low Voltage
0.5
200
1
V
Output OVP (Latched) Debounce Time
100
150
µs
mA
V
IDET-SOURCE Maximum Source Current
VDET=0V
VDET-HIGH
VDET-LOW
Upper Clamp Voltage
Lower Clamp Voltage
IDET=-1mA
IDET=1mA
5
0.1
0.3
V
Delay Time from Valley-Signal Detected to
Output Turn-On(3)
tVALLEY-DELAY
tOFF-BNK
200
ns
µs
FAN6300A
FAN6300H
FAN6300A
FAN6300H
4.0
1.5
9
Leading-Edge-Blanking Time for DET when
PWM MOS Turns Off(3)
tTIME-OUT
Time-Out after tOFF-MIN
µs
5
Oscillator Section
tON-MAX Maximum On-Time
38
45
8
54
µs
µs
V
FB≧VN,
FAN6300A
V
FB≧VN
3
µs
µs
FAN6300H
tOFF-MIN
Minimum Off-Time
VFB=VG
FAN6300A
38
VFB=VG
FAN6300H
13
2.10
1.2
µs
V
Beginning of Green-On Mode at FB Voltage
Level
VN
1.95
1.0
2.25
1.4
Beginning of Green-Off Mode at FB Voltage
Level
VG
V
Green-Off Mode VFB Hysteresis Voltage
0.05
1.8
25
0.10
2.1
30
0.20
2.4
45
V
ΔVFBG
VFB<VG
ms
µs
tSTARTER
Start Timer (Time-Out Timer)
VFB>VFB-OLP
Output Section
VDD=15V,
IO=150mA
VOL
VOH
Output Voltage Low
1.5
V
V
VDD=12V,
IO=150mA
Output Voltage High
7.5
tR
tF
Rising Time
145
55
200
120
19.3
ns
ns
V
Falling Time
VCLAMP
Gate Output Clamping Voltage
16.7
18.0
Continued on following page…
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
7
Electrical Characteristics(Continued)
Unless otherwise specified, VDD=10~25V, TA=-40°C ~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Current Sense Section
tPD
Delay to Output
20
150
200
ns
V
I
DET < 74.41µA
0.82
0.85
0.88
Limit Voltage on CS Pin for Over-Power
Compensation
VLIMIT
IDET=550µA
tON=45µs
tON=0µs
0.380 0.415 0.450
V
0.3
0.1
V
VSLOPE
tBNK
VCS-H
tCS-H
Slope Compensation(3)
V
Leading-Edge-Blanking Time
(MOS Turns ON)
525
4.5
625
725
5.0
ns
VCS Clamped High Voltage once CS Pin
CS Pin Floating
CS Pin Floating
V
Floating
Delay Time once CS Pin Floating
150
µs
Internal Over-Temperature Protection Section
TOTP
Internal Threshold Temperature for OTP(3)
TOTP-HYST Hysteresis Temperature for Internal OTP(3)
Note:
+140
+15
°C
°C
3. Guaranteed by design.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
8
Typical Performance Characteristics
Graphs are normalized at TA=25°C.
10.00
9.80
9.60
9.40
9.20
9.00
17.0
16.5
16.0
15.5
15.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(oC)
-40℃ -25℃ -10℃
5℃
20℃
35℃
50℃
65℃
80℃
95℃ 110℃ 125℃
Temperature(°C)
Figure 5. Turn-On Threshold Voltage
Figure 6. PWM-Off Threshold Voltage
8.1
8.0
7.9
7.8
7.7
7.6
7.5
18
16
14
12
10
8
6
-40℃ -25℃ -10℃
5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(°C)
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(oC)
Figure 7. Turn-Off Threshold Voltage
Figure 8. Startup Current
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.50
4.20
3.90
3.60
3.30
3.00
-40℃ -25℃ -10℃
5℃
20℃
35℃
50℃
65℃
80℃
95℃ 110℃ 125℃
-40℃ -25℃ -10℃
5℃
20℃
35℃
Temperature(°C)
50℃
65℃
80℃
95℃ 110℃ 125℃
Temperature(°C)
Figure 9. Operating Current
Figure 10. Supply Current Drawn From HV Pin
0.32
0.31
0.30
0.29
0.28
0.27
0.26
0.25
0.40
0.35
0.30
0.25
0.20
0.15
0.10
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(oC)
Temperature(°C)
Figure 11. Leakage Current After Startup
Figure 12. Lower Clamp Voltage
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA = 25°C.
8.70
2.52
2.51
2.50
2.49
2.48
8.40
8.10
7.80
7.50
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(oC)
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(°C)
Figure 13. Comparator Reference Voltage
Figure 14. Minimum Off Time (VFB>VN)
42.0
40.0
38.0
36.0
34.0
2.50
2.40
2.30
2.20
2.10
2.00
1.90
32.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(°C)
Temperature(oC)
Figure 15. Minimum Off Time (VFB=VG)
Figure 16. Start Timer (VFB<VG)
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
10
Operation Description
The FAN6300A/H PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation across a
wide range of line voltage. The following descriptions
highlight some of the features of the FAN6300A/H.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 19, once VFB is lower than VN, tOFF-MIN increases
linearly with lower VFB. The valley voltage detection
signal does not start until tOFF-MIN finishes. Therefore, the
valley detect circuit is activated until tOFF-MIN finishes,
which decreases the switching frequency and provides
extended valley voltage switching. However, in very light
load condition, it might fail to detect the valley voltage
after the tOFF-MIN expires. Under this condition, an internal
tTIME-OUT signal initiates a new cycle start after a 9μs
delay (with 5µs delay for H version). Figure 20 and
Figure 21 show the two different conditions.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, which are recommended as 1N4007 and 100kΩ.
Typical startup current drawn from the HV pin is 1.2mA
and it charges the hold-up capacitor through the diode
and resistor. When the VDD voltage level reaches VDD-ON
,
the startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6300A/H to maintain VDD
until the auxiliary winding of the main transformer
provides the operating current.
tO F F -M IN
2.1ms
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors RDET and RA. RDET is recommended as
150kΩ to 220kΩ to achieve valley voltage switching.
When VAUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3V.
38/13μs
8/3μs
1.2V
2.1V
VF B
Figure 19. VFB vs. tOFF-MIN Curve
Figure 17. Valley Detect Section
The internal timer (minimum tOFF time) prevents gate
retriggering within 8µs (3µs for H version) after the gate
signal going-low transition. The minimum tOFF limit
prevents system frequency being too high. Figure 18
shows a typical drain voltage waveform with first valley
switching.
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
Figure 21. Internal tTIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage
(with 5µs Delay for FAN6300H version)
Figure 18. First Valley Switching
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
11
Current Sensing and PWM Current Limiting VDD Over-Voltage Protection
VDD over-voltage protection prevents damage due to
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current-sense signal and VFB. When the voltage on CS
reaches around VLIMIT = (VFB-1.2)/3, the switch cycle is
terminated immediately. VLIMIT is internally clamped to a
variable voltage around 0.85V for output power limit.
abnormal conditions. Once the VDD voltage is over the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tVDDOVP, the PWM pulse is disabled until the VDD
voltage drops below the UVLO, then starts again.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs (1.5μs for H version) blanking time
Leading-Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on ignores the leakage inductance ringing. A voltage
spike occurs on the sense resistor. To avoid premature comparator and a 2.5V reference voltage develop an
termination of the switching pulse, lead-edge blanking output OVP protection. The ratio of the divider
time is built in. During the blanking period, the current limit determines the sampling voltage of the stop gate, as an
comparator is disabled; it cannot switch off the gate driver. optical coupler and secondary shunt regulator are used.
If the DET pin OVP is triggered, the power system enters
latch-mode until AC power is removed.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply VDD during startup.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
Figure 23. Voltage Sampled After 4μs
18V Zener diode to protect power MOSFET transistors
(1.5μs for FAN6300H version) Blanking Time
against undesired over-voltage gate signals.
After Switch-Off Sequence
Over-Power Compensation
Short-Circuit and Open-Loop Protection
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher. RDET
also affects the H/L line constant power limit.
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
t
D-OLP, PWM output is turned off. As PWM output is
turned-off, the supply voltage VDD begins decreasing.
When VDD goes below the PWM-off threshold of 10V,
VDD decreases to 8V, then the controller is totally shut
down. VDD is charged up to the turn-on threshold voltage
of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
12
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 24. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H Rev. 1.0.1
www.fairchildsemi.com
13
Physical Dimensions (Continued)
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 25. 8-Pin Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
14
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
www.fairchildsemi.com
15
相关型号:
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FAN6390
Highly Integrated Secondary-Side Adaptive USB Type-C Charging Controller with USB-PD with SR Embedded
ONSEMI
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