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October 2008

FAN6300

Highly Integrated Quasi-Resonant Current Mode

PWM Controller

Features

Description

The highly integrated FAN6300 PWM controller

provides several features to enhance the performance

of flyback converters. A built-in HV startup circuit can

provide more startup current to reduce the startup time

of the controller. Once the V_DDvoltage exceeds the

turn-on threshold voltage, the HV startup function is

disabled immediately to improve power consumption.

An internal valley voltage detector ensures the power

system operates at Quasi-Resonant operation in wide-

range line voltage and any load conditions and reduces

switching loss to minimize switching voltage on drain of

power MOSFET.

High-Voltage Startup

Quasi-Resonant Operation

Cycle-by-Cycle Current Limiting

Peak-Current-Mode Control

Leading-Edge Blanking

Internal Minimum t_OFF

Internal 2ms Soft-Start

Over-Power Compensation

GATE Output Maximum Voltage

Auto-Recovery Short-Circuit Protection (FB Pin)

Auto-Recovery Open-Loop Protection (FB Pin)

VDD Pin & Output Voltage (DET Pin) OVP Latched

To minimize standby power consumption and light-load

efficiency, a proprietary green-mode function provides

off-time modulation to decrease switching frequency

and perform extended valley voltage switching to keep

to a minimum switching voltage.

FAN6300 controller also provides many protection

functions. Pulse-by-pulse current limiting ensures the

fixed peak current limit level, even when a short circuit

occurs. Once an open-circuit failure occurs in the

feedback loop, the internal protection circuit disables

PWM output immediately. As long as V_DDdrops below

the turn-off threshold voltage, controller also disables

PWM output. The gate output is clamped at 18V to

protect the power MOS from high gate-source voltage

conditions. The minimum t_OFFtime limit prevents the

system frequency from being too high. If the DET pin

reaches OVP, internal OTP is triggered, and the power

system enters latch-mode until AC power is removed.

Applications

AC/DC NB Adapters

Open-Frame SMPS

FAN6300 controller is available in 8-pin SOP and DIP

packages.

Ordering Information

Operating

Temperature Range

Part Number

Package

Packing Method

Eco Status

Green

8-Lead, Small Out-line Package

(SOP)

FAN6300SY

FAN6300DY

-40 to +105°C

Tape & Reel

Tube

8-Lead, Dual In-line Package

(DIP)

-40 to +105°C

Green

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

Application Diagram

Figure 1. Typical Application

Internal Block Diagram

HV

8

VDD

6

Internal

Bias

OVP

I_HV

Two Steps

UVLO

16V/10V/8V

4.2V

27V

Latched

2R

Soft-Start

2

3

FB

CS

2ms

R

FB OLP

Timer

55ms

500µs

30µs

Starter

DRV

Blanking

Circuit

SET

CLR

S

R

Q

5

GATE

PWM

Current Limit

18V

Over-Power

Compensation

I_DET

Latched

0.3V

V_DET

t_OFF-MIN

(8µs/38µs)

Valley

Detector

t_OFF-MIN

+9µs

1st

Valley

V_DET

t_OFF

Blanking

(4µs)

S/H

Latched

2.5V

DET OVP

1

DET

Internal

OTP

0.3V

Latched

I_DET

5V

7

4

GND

NC

Figure 2. Functional Block Diagram

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

2

Marking Information

: Fairchild logo

Z: Plant Code

X: Year Code

Y: Week Code

TT: Die Run Code

T: Package type (D =DIP, S = SOP)

P: Y = Green Package

M: Manufacturing flow code

Figure 3. Marking Diagram

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin #

Name

Description

This pin is connected to an auxiliary winding of the transformer via resistors of the divider for

the following purposes:

-

Generates a ZCD signal once the secondary-side switching current falls to zero.

-

Produces an offset voltage to compensate the threshold voltage of the peak current limit to

provide a constant power limit. The offset is generated in accordance with the input voltage

when PWM signal is enabled.

1

DET

-

Detects the valley voltage of the switching waveform to achieve the valley voltage switching

and minimize the switching losses.

A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The

ratio of the divider decides what output voltage to stop gate, as an optical coupler and

secondary shunt regulator are used.

The Feedback pin is supposed to be connected to the output of the error amplifier for achieving

the voltage control loop. The FB should be connected to the output of the optical coupler if the

error-amplifier is equipped at the secondary-side of the power converter.

For the primary-side control application, this pin is applied to connect a RC network to the

ground for feedback-loop compensation.

2

FB

The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected

between the FB and the PWM circuit is used for the loop gain attenuation.

FAN6300 performs an open-loop protection once the FB voltage is higher than a threshold

voltage (around 4.2V) more than 55ms.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

3

Pin #

Name

Description

Input to the comparator of the over-current protection. A resistor senses the switching current

and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The threshold

voltage for peak current limit is 0.8V.

3

CS

The power ground and signal ground. A 0.1µF decoupling capacitor placed between V_DDand

GND is recommended.

4

5

6

GND

GATE

VDD

Totem-pole output generates the PWM signal to drive the external power MOSFET. The

clamped gate output voltage is 18V.

Power supply. The threshold voltages for startup and turn-off are 16V and 10V. The startup

current is less than 20µA and the operating current is lower than 4.5mA.

7

8

NC

HV

No connect.

High-voltage startup.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_DD

V_HV

V_H

Parameter

DC Supply Voltage

Min.

Max.

30

Unit

V

HV Pin

500

25.0

7.0

V

GATE Pin

-0.3

V

V_L

V_FB, V_CS, V_DET

V

P_D

Power Dissipation

400

+150

+270

2.5

mW

°C

T_J

Operating Junction Temperature

Storage Temperature Range

Lead Temperature, Soldering 10 Seconds

Human Body Model, JEDEC:JESD22-A114

Charged Device Model, JEDEC:JESD22-C101

T_STG

T_L

-55

ESD

KV

1.5

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

2. All voltage values, except differential voltages, are given with respect to GND pin.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

Max.

Unit

T_A

Operating Ambient Temperature

-40

+105

°C

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

5

Electrical Characteristics

V_DD=15V, T_A=25℃, unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

VDD SECTION

V_OP

Continuously Operating Voltage

Turn-on Threshold Voltage

25

17

11

9

V

V_DD-ON

15

9

16

10

8

V_DD-PWM-OFFPWM Off Threshold Voltage

V_DD-OFF

Turn-Off Threshold Voltage

7

0V< V_DD< V_DD-ON

GATE Open

I_DD-ST

Startup Current

10

30

µA

V_DD=15V, f_s=60KHz,

C_L=2nF

I_DD-OP

Operating Current

4.5

5.5

mA

I_DD-PWM-OFFOperating Current at PWM-Off Phase

V_DD=V_DD-PWM-OFF-0.5V

70

26

80

27

90

28

µA

V

V_DD-OVP

t_VDD-OVP

V_DDOver-Voltage Protection (Latch-Off)

V_DDOVP Debounce Time

100

150

200

µs

HV STARTUP CURRENT SOURCE SECTION

V_AC=90V (V_DC=120V),

_DD=0V

I_HV

Supply Current Drawn From HV Pin

Leakage Current After Startup

1.2

1

mA

µA

V

HV=500V,

_DD=V_DD-OFF+1V

I_HV-LC

20

V

FEEDBACK INPUT SECTION

Input-voltage to Current Sense

Attenuation

A_V=ΔV_CS/ΔV_FB

0<V_CS<0.9

A_V

1/2.75 1/3.00 1/3.25

V/V

Z_FB

I_OZ

Input Impedance

Bias Current

3

5

1.2

1

7

KΩ

mA

V

FB=V_OZ

2.0

V_OZ

Zero Duty Cycle Input Voltage

Open-Loop Protection Threshold

Voltage

V_FB-OLP

3.9

1.6

4.2

4.5

V

Debounce Time for Open-Loop /

Overload Protection

t_D-OLP

t_SS

55

ms

Internal Soft-Start Time

2.0

2.4

DET PIN OVP AND VALLEY DETECTION SECTION

V_DET-OVP

V_V-HIGH

V_V-LOW

Comparator Reference Voltage

Output High Voltage

2.45

4.5

2.50

150

2.55

V

Output Low Voltage

0.5

200

1

V

t_DET-OVP

Output OVP (Latched) Debounce Time

100

0.1

µs

mA

V

I_DET-SOURCEMaximum Source Current

V_DET-HIGH

V_DET-LOW

Upper Clamp Voltage

Lower Clamp Voltage

5

0.3

4

V

Leading-Edge Blanking Time for DET-

OVP, PWM MOS Turns Off⁽³⁾

t_OFF-BNK

µs

Note:

3. Guaranteed by design.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

6

Electrical Characteristics (Continued)

V_DD=15V, T_A=25℃, unless otherwise specified.

Symbol

OSCILLATOR SECTION

t_ON-MAXMaximum On Time

Parameter

Conditions

Min.

Typ.

Max.

Units

38

7

45

8

52

9

µs

V

_FB≧V_N

Minimum Off Time

t_OFF-MIN

(Maximum Frequency)

V_FB=V_G

38

Beginning of Green-On Mode

at FB Voltage Level

V_N

V_G

1.95

1.05

2.10

1.20

0.1

2.25

1.35

V

Beginning of Green-Off Mode

at FB Voltage Level

Green-Off Mode V_FBHysteresis

Voltage

ΔV_FBG

V_FB<V_G

450

25

550

30

650

35

µs

t_STARTER

t_TIME-OUT

Start Timer (Time-out Timer)

V_FB>V_FB-OLP

Timeout After t_OFF-MIN

(If No Valley Signal)

9

µs

OUTPUT SECTION

V_OL

V_OH

t_R

Output Voltage Low

V_DD=15V, I_O=150mA

V_DD=12V, I_O=150mA

1.5

V

Output Voltage High

Rising Time

7.5

17

120

60

ns

V

t_F

Falling Time

V_CLAMP

GATE Output Clamping Voltage

18

19

CURRENT SENSE SECTION

t_PD

Delay to Output

150

0.78

0.585

0.46

0.3

250

0.82

0.625

0.50

ns

V

I_DET= 60µA

I_DET= 175µA

I_DET= 220µA

t_ON=45µs

0.74

0.545

0.42

Cycle-by-Cycle Current Limit

Threshold Voltage

V_LIMIT

V_SLOPE

t_BNK

Slope Compensation

t

_ON=0µs

0.1

Leading Edge Blanking Time

(MOS Turns On)

225

300

150

375

ns

V_CS-H

t_CS-H

V_CSCamped High Voltage

Delay Time

CS Pin Floating

4.5

5.0

V

100

200

µs

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

7

Typical Performance Characteristics

These characteristic graphs are normalized at T_A= 25°C.

17.0

16.5

16.0

15.5

15.0

10.5

10.3

10.1

9.9

9.7

9.5

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 5. Turn-on Threshold Voltage

Figure 6. PWM Off Threshold Voltage

8.2

8.1

8.0

7.9

7.8

7.7

7.6

10

9

8

7

6

5

4

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 7. Turn-off Threshold Voltage

Figure 8. Startup Current

5.2

5.0

4.8

4.6

4.4

4.2

4.0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 9. Operating Current

Figure 10. Supply Current Drawn From HV Pin

1.0

0.8

0.6

0.4

0.2

0.0

0.30

0.25

0.20

0.15

0.10

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 11. Leakage Current After Startup

Figure 12. Lower Clamp Voltage

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

8

Typical Performance Characteristics

These characteristic graphs are normalized at T_A= 25°C.

2.6

2.5

2.4

9.0

8.5

8.0

7.5

7.0

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 13. Comparator Reference Voltage

Figure 14. Minimum Off Time (V_FB>V_N)

40

39

38

37

36

35

600

575

550

525

500

475

450

-40 -25 -10

5

20

35

50

65

80

95

110 125

-40 -25 -10

5

20

35

50

65

80

95

110 125

Temperature℃

Figure 15. Minimum Off Time (V_FB=V_G)

Figure 16. Start Timer (V_FB<V_G)

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

9

Operation Description

The FAN6300 of PWM controller integrates designs to

enhance the performance of flyback converters. An

internal valley voltage detector ensures power system

operates at Quasi-Resonant (QR) operation in a wide

range of line voltage. The following descriptions highlight

some of the features of the FAN6300 series.

Green-Mode Operation

The proprietary green-mode function provides off-time

modulation to linearly decrease the switching frequency

under light-load conditions. V_FB, which is derived from

the voltage feedback loop, is taken as the reference. In

Figure 19, once V_FBis lower than V_N, the t_OFF-MINtime

increases linearly with lower V_FB. The valley voltage

detection signal does not start until the t_OFF-MINtime

finishes. Therefore, the valley detect circuit is activated

until the t_OFF-MINtime finishes, which decreases the

switching frequency and provides extended valley

voltage switching. However, in very light load condition,

it might fail to detect the valley voltage after the t_OFF-MIN

expires. Under this condition, an internal t_TIME-OUTsignal

initiates a new cycle start after a 9μs delay. Figure 20

and Figure 21 show the two different conditions.

Startup Current

For startup, the HV pin is connected to the line input or

bulk capacitor through an external diode and resistor,

R_HV, which are recommended as 1N4007 and 100kΩ.

Typical startup current drawn from pin HV is 1.2mA and

it charges the hold-up capacitor through the diode and

resistor. When the V_DDvoltage level reaches V_DD-ON, the

startup current switches off. At this moment, the V_DD

capacitor only supplies the FAN6300 to maintain V_DD

until the auxiliary winding of the main transformer

provides the operating current.

Valley Detection

The DET pin is connected to an auxiliary winding of the

transformer via resistors of the divider to generate a

valley signal once the secondary-side switching current

discharges to zero. It detects the valley voltage of the

switching waveform to achieve the valley voltage

switching. This ensures QR operation, minimizes

switching losses, and reduces EMI. Figure 17 shows

divider resistors R_DETand R_A. R_DETis recommended as

150kΩ to 220kΩ to achieve valley voltage switching.

When V_AUX(in Figure 17) is negative, the DET pin

voltage is clamped to 0.3V.

Figure 19. V_FBvs. t_OFF-MINCurve

Figure 17. Valley Detect Section

The internal timer (minimum t_OFFtime) prevents gate

retriggering within 8µs after the gate signal going-low

transition. The minimum t_OFFtime limit prevents the

system frequency being too high. Figure 18 shows a

typical drain voltage waveform with first valley switching.

Figure 20. QR Operation in Extended Valley Voltage

Detection Mode

Figure 21. Internal t_TIME-OUTInitiates New Cycle After

Failure to Detect Valley Voltage (with 9µs Delay)

Figure 18. First Valley Switching

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

10

Current Sensing and PWM Current Limiting V_DDOver-Voltage Protection

V_DDover-voltage protection prevents damage due to

Peak-current-mode control is utilized to regulate output

voltage and provide pulse-by-pulse current limiting. The

switch current is detected by a sense resistor into the

CS pin. The PWM duty cycle is determined by this

current sense signal and V_FB. When the voltage on CS

pin reaches around V_LIMIT= (V_FB-1.2)/3, the switch cycle

is terminated immediately. V_LIMITis internally clamped to

a variable voltage around 0.8V for output power limit.

abnormal conditions. Once the V_DDvoltage is over the

V_DDover-voltage protection voltage (V_DD-OVP) and lasts

for t_VDDOVP, controller enters latch mode and stops all

switching operation.

Output Over-Voltage Protection

The output over-voltage protection works by the

sampling voltage, as shown in Figure 23, after switch-off

sequence. A 4μs blanking time ignores the leakage

Leading Edge Blanking (LEB)

Each time the power MOFFET switches on, a turn-on inductance ringing. A voltage comparator and a 2.5V

spike occurs on the sense resistor. To avoid premature reference voltage develop an output OVP protection.

termination of the switching pulse, lead-edge blanking The ratio of the divider determines the sampling voltage

time is built in. During the blanking period, the current limit of the stop gate, as an optical coupler and secondary

comparator is disabled; it cannot switch off the gate driver. shunt regulator are used. If the DET pin OVP is

triggered, power system enters latch-mode until AC

power is removed.

Under-Voltage Lockout (UVLO)

The turn-on, PWM-off, and turn-off thresholds are fixed

internally at 16/10/8V. During startup, the startup

capacitor must be charged to 16V through the startup

resistor to enable the IC. The hold-up capacitor

continues to supply V_DDuntil energy can be delivered

from the auxiliary winding of the main transformer. V_DD

must not drop below 10V during this startup process.

This UVLO hysteresis window ensures that hold-up

capacitor is adequate to supply V_DDduring startup.

Gate Output

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

18V Zener diode to protect power MOSFET transistors

against undesired over-voltage gate signals.

Figure 23. Voltage Sampled After 4μs Blanking Time

After Switch-off Sequence

Short-Circuit and Open-Loop Protection

The FB voltage increases every time the output of the

power supply is shorted or overloaded. If the FB voltage

remains higher than a built-in threshold for longer than

Over-Power Compensation

To compensate this variation for wide AC input range,

the DET pin produces an offset voltage to compensate

the threshold voltage of the peak current limit to provide

a constant-power limit. The offset is generated in

accordance with the input voltage when PWM signal is

enabled. This results in a lower current limit at high-line

inputs than low-line inputs. At fixed-load condition, the

CS limit is higher when the value of R_DETis higher. R_DET

also affects the H/L line constant power limit.

t

_D-OLP, PWM output is turned off. As PWM output is

turned-off, the supply voltage V_DDbegins decreasing.

When V_DDgoes below the PWM-off threshold of 10V,

V_DDdecreases to 8V, then the controller is totally shut

down. V_DDis charged up to the turn-on threshold voltage

of 16V through the startup resistor until PWM output is

restarted. This protection feature continues as long as

the overloading condition persists. This prevents the

power supply from overheating due to overloading.

Figure 22. H/L Line Constant Power Limit

Compensated by DET Pin

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

11

Physical Dimensions

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

C

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

0.406

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 24. 8-Pin Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

12

Physical Dimensions (Continued)

9.83

9.00

6.67

6.096

8.255

7.61

3.683

3.20

7.62

5.08 MAX

0.33 MIN

3.60

3.00

(0.56)

2.54

0.356

0.20

0.56

0.355

9.957

7.87

1.65

1.27

7.62

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANC

ASME Y14.5M-1994

ES PER

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

Figure 25. 8-Pin Dual Inline Package (DIP-8)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

13

FAN6300 • Rev. 1.0.3

www.fairchildsemi.com

14

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1


型号：	FAN6300SY
厂家：	ONSEMI
描述：	用于反激式转换器的绿色模式 QR PWM 控制器，频率低至 100 KHZ 以下控制器开关光电二极管转换器
文件：	总16页 (文件大小：666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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