ESD8351XV2T5G [ONSEMI]
Unidirectional SCR ESD Protection;
| 型号： | ESD8351XV2T5G |
| 厂家： | 
ONSEMI |
| 描述： | Unidirectional SCR ESD Protection |
| 文件： | 总10页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD8351, SZESD8351
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD8351 Series ESD protection diodes are designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
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MARKING
DIAGRAMS
Features
PIN 1
• Low Capacitance (0.55 pF Max, I/O to GND)
X3DFN2
CASE 152AF
M
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
ISO 10605
2
SOD−323
CASE 477
AE
M
• Low ESD Clamping Voltage
1
1
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
2
SOD−523
CASE 502
AF
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
1
2
Compliant
Typical Applications
• USB 2.0
SOD−923
CASE 514AB
AC M
• eSATA
X, XX = Specific Device Code
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
M
= Date Code
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
PIN CONFIGURATION
AND SCHEMATIC
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ISO 10605 330 pF / 2 kW Contact
ESD
ESD
ESD
15
15
30
kV
kV
kV
1
2
Cathode
Anode
Maximum Peak Pulse Current
I
pp
5.0
A
8/20 ms @ T = 25°C
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
=
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
May, 2015 − Rev. 6
ESD8351/D
ESD8351, SZESD8351
ELECTRICAL CHARACTERISTICS
I
(T = 25°C unless otherwise noted)
A
I
PP
Symbol
Parameter
R
DYN
V
RWM
Working Peak Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
V
BR
V
V
V
RWM HOLD
V
Breakdown Voltage @ I
C
BR
T
I
I
V
R
T
C
I
Test Current
T
I
HOLD
V
Holding Reverse Voltage
Holding Reverse Current
Dynamic Resistance
Maximum Peak Pulse Current
HOLD
HOLD
I
R
DYN
R
DYN
−I
PP
I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
V
C
Clamping Voltage @ I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
3.3
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
5.5
7.0
7.8
V
T
Reverse Leakage Current
Holding Reverse Voltage
Holding Reverse Current
I
V
= 3.3 V, I/O Pin to GND
500
nA
V
R
RWM
V
I/O Pin to GND
I/O Pin to GND
1.15
20
HOLD
HOLD
I
mA
V
Clamping Voltage
TLP (Note 2)
See Figures 1 through 11
V
6.5
I
PP
= 8 A
IEC 61000−4−2 Level 2 equivalent
( 4 kV Contact, 4 kV Air)
C
I
PP
= 16 A
11.2
8.2
IEC 61000−4−2 Level 4 equivalent
( 8 kV Contact, 15 kV Air)
Clamping Voltage (Note 3)
Dynamic Resistance
V
V
W
C
t = 8 x 20 ms
p
I
PP
= 5 A
R
Pin1 to Pin2
Pin2 to Pin1
0.62
0.59
DYN
Junction Capacitance
C
V
R
V
R
= 0 V, f = 1 Mhz
= 0 V, f = 2.5 Ghz
0.37
0.35
0.55
0.45
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 8 and 9 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
3. Non−repetitive current pulse at T = 20°C, per IEC 61000−4−5 waveform.
A
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2
ESD8351, SZESD8351
10
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
9
8
7
6
5
4
3
2
0.1
0
1
0
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
1
1.5
2
2.5
3
3.5
(A)
4
4.5
5
5.5
6
I
Bias
pk
Figure 1. CV Characteristics
Figure 2. Clamping Voltage vs Peak Pulse
Current ( tp = 8/20 ms)
1.0
2
m1
m2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
−2
−4
−6
−8
−10
−12
−14
0.1
0
1E7
1E8
1E9
1E10 3E10
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
FREQUENCY
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
20
10
20
18
16
14
12
10
8
10
18
16
14
12
10
8
8
6
4
8
6
4
6
6
4
2
0
4
2
0
2
0
2
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
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3
ESD8351, SZESD8351
Latch−Up Considerations
stable operating point of the circuit and the system is
therefore latch−up free. In the non−latch up free load line
case, the IV characteristic of the snapback protection device
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap−back, SCR type structure. By using
this technology, the potential for a latch−up condition was
taken into account by performing load line analysis of
common high speed serial interfaces. Example load lines for
latch−up free applications and applications with the
potential for latch−up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch−up free load line case, the IV
characteristic of the snapback protection device intersects
intersects the load−line in two points (V
, I
OPA OPA
) and
(V , I ). Therefore in this case, the potential for
OPB OPB
latch−up exists if the system settles at (V
, I
) after a
OPB OPB
transient. Because of this, ESD8351 Series should not be
used for HDMI applications – ESD8104 or ESD8040 have
been designed to be acceptable for HDMI applications
without latch−up. Please refer to Application Note
AND9116/D for a more in−depth explanation of latch−up
considerations using ESD8000 series devices.
the load−line in one unique point (V , I ). This is the only
OP OP
I
I
I
SSMAX
I
SSMAX
I
I
OPB
I
OP
V
OPA
V
OP
V
DD
V
ESD8351 Latch*up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,
DisplayPort
V
V
V
DD
OPB
OPA
ESD8351 Potential Latch*up:
HDMI 1.4/1.3a TMDS
Figure 7. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
Application
HDMI 1.4/1.3a TMDS
USB 2.0 LS/FS
USB 2.0 HS
3.465
3.301
0.482
2.800
3.600
54.78
1.76
N/A
1.0
1.0
1.0
1.0
1.0
ESD8104, ESD8040
ESD8004, ESD8351
ESD8004, ESD8351
USB 3.0 SS
N/A
ESD8004, ESD8006, ESD8351
ESD8004, ESD8006, ESD8351
DisplayPort
25.00
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4
ESD8351, SZESD8351
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 8. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 9. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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5
ESD8351, SZESD8351
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 10. Simplified Schematic of a Typical TLP
System
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ORDERING INFORMATION
†
Device
Package
Shipping
ESD8351HT1G,
SZESD8351HT1G*
SOD−323
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
8000 / Tape & Reel
15000 / Tape & Reel
ESD8351XV2T1G,
SZESD8351XV2T1G*
SOD−523
(Pb−Free)
ESD8351P2T5G,
SZESD8351P2T5G*
SOD−923
(Pb−Free)
ESD8351MUT5G,
X3DFN2
SZESD8351MUT5G*
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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6
ESD8351, SZESD8351
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN 1
INDICATOR
(OPTIONAL)
MILLIMETERS
DIM MIN
MAX
0.33
0.05
0.28
0.66
0.36
A
A1
b
D
E
0.25
−−−
E
TOP VIEW
0.22
0.58
0.28
e
0.355 BSC
0.23
L2 0.17
0.05
0.05
C
C
A
RECOMMENDED
2X
A1
SIDE VIEW
MOUNTING FOOTPRINT*
SEATING
PLANE
C
2X
0.74
0.30
e
1
2X b
1
2
2X
0.31
DIMENSIONS: MILLIMETERS
M
0.05
C A B
2X L2
See Application Note AND8398/D for more mounting details
M
0.05
C A B
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
ESD8351, SZESD8351
PACKAGE DIMENSIONS
SOD−323
CASE 477−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
H
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS SPECIFIED PER L/F DRAWING
WITH SOLDER PLATING.
D
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
5. DIMENSION L IS MEASURED FROM END OF RADIUS.
1
E
b
2
MILLIMETERS
DIM MIN NOM MAX
0.80
INCHES
NOM MAX
1.00 0.031 0.035 0.040
0.10 0.000 0.002 0.004
0.006 REF
MIN
A
0.90
0.05
A1 0.00
A3
A
A3
0.15 REF
0.32
0.12 0.177 0.003 0.005 0.007
1.70
1.25
b
C
D
E
L
0.25
0.089
1.60
1.15
0.08
2.30
0.4 0.010 0.012 0.016
1.80 0.062 0.066 0.070
1.35 0.045 0.049 0.053
0.003
H
2.50
2.70 0.090 0.098 0.105
E
L
A1
C
NOTE 5
NOTE 3
SOLDERING FOOTPRINT*
0.63
0.025
0.83
0.033
1.60
0.063
2.85
0.112
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
8
ESD8351, SZESD8351
PACKAGE DIMENSIONS
SOD−523
CASE 502
ISSUE E
−X−
D
NOTES:
6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
−Y−
7. CONTROLLING DIMENSION: MILLIMETERS.
8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
E
9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
1
2
2X b
MILLIMETERS
M
0.08
X Y
DIM
A
b
c
D
E
HE
L
MIN
0.50
0.25
0.07
1.10
0.70
1.50
NOM
0.60
0.30
0.14
1.20
MAX
0.70
0.35
0.20
1.30
0.90
1.70
TOP VIEW
0.80
1.60
A
0.30 REF
0.20
L2
0.15
0.25
c
HE
RECOMMENDED
SOLDERING FOOTPRINT*
SIDE VIEW
1.80
2X
0.48
2X
0.40
2X
L
PACKAGE
OUTLINE
DIMENSION: MILLIMETERS
2X
L2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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9
ESD8351, SZESD8351
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE C
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
−Y−
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
E
1
2
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
2X b
MIN
0.08 X
Y
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.37
0.20
0.12
0.80
0.60
0.40
0.25
0.17
0.85
0.65
1.05
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
TOP VIEW
D
E
A
H
1.00
E
L
0.19 REF
0.10
L2 0.05
0.15
0.002 0.004 0.006
c
H
SOLDERING FOOTPRINT*
E
SIDE VIEW
1.20
2X
2X
0.25
0.36
2X
L
PACKAGE
OUTLINE
DIMENSIONS: MILLIMETERS
2X
L2
See Application Note AND8455/D for more mounting details
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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For additional information, please contact your local
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ESD8351/D
相关型号：
ESD8472MUT5G
Ultra-Low Capacitance RF ESD Protection Micro.Packaged Diodes for ESD Protection
ONSEMI
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