ESD8501V5 [ONSEMI]
Transient Voltage Suppressors;
| 型号： | ESD8501V5 |
| 厂家： | 
ONSEMI |
| 描述： | Transient Voltage Suppressors |
| 文件： | 总6页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD8501V5
Transient Voltage
Suppressors
Features
• Protection for the following IEC Standards:
IEC61000−4−2 Level 4: 30 kV Contact Discharge
IEC61000−4−5 (Lightning) 70 A (8/20 ms)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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1
2
Cathode
Anode
MAXIMUM RATINGS
MARKING
DIAGRAM
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
Contact
Air
30
30
kV
UDFN2
CASE 517CZ
A M
Operating Junction and Storage
Temperature Range
T , T
−65 to +150
°C
J
stg
Maximum Peak Pulse Current
I
70
A
PP
A
M
= Specific Device Code
= Date Code
8/20 ms @ T = 25°C
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
Package
Shipping
ESD8501V5MUT5G UDFN2
(Pb−Free)
8000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2014 − Rev. 1
ESD8501V5/D
ESD8501V5
ELECTRICAL CHARACTERISTICS
I
(T = 25°C unless otherwise noted)
A
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
C
V V
BR RWM
V
Working Peak Reverse Voltage
RWM
V
I
V
F
R
T
I
R
Maximum Reverse Leakage Current @ V
I
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
PP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
5.0
9.0
0.1
7.5
9.5
11.5
16
Unit
V
Reverse Working Voltage
Breakdown Voltage (Note 1)
Reverse Leakage Current
Clamping Voltage (Note 2)
Clamping Voltage (Note 2)
Clamping Voltage (Note 2)
Junction Capacitance
V
RWM
V
BR
I = 1 mA
6.0
7.0
V
T
I
R
V
RWM
= 5 V
mA
V
V
I
PP
I
PP
I
PP
= 1 A, t = 8 x 20 ms
p
C
C
C
V
V
= 35 A, t = 8 x 20 ms
V
p
= 70 A, t = 8 x 20 ms
V
p
C
V
R
= 0 V, f = 1 MHz
pF
W
J
Dynamic Resistance
R
TLP Pulse
0.04
DYN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
2. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
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2
ESD8501V5
9
8
7
6
5
4
3
2
1
0
14
12
10
8
6
4
2
0
0
5
10
15
(A)
20
25
30
0
10
20
30
40
(A)
50
60
70
80
I
pk
I
pk
Figure 1. Positive TLP I−V Curve
Figure 2. Clamping Voltage vs. Peak Pulse
Current (tp = 8/20 ms)
50
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
6
V
Bias
(V)
Figure 3. CV Characteristics
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3
ESD8501V5
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 4. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 5 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 4. Simplified Schematic of a Typical TLP
System
Figure 5. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD8501V5
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 6. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 7. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 8. 8 X 20 ms Pulse Waveform
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5
ESD8501V5
PACKAGE DIMENSIONS
UDFN2 1.6x1.0, 1.1P
CASE 517CZ
ISSUE A
A
B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN ONE
MILLIMETERS
REFERENCE
E
DIM MIN
MAX
0.55
0.05
0.95
2X
0.08
C
A
A1
b
D
E
0.45
−−−
0.85
2X
0.08
C
1.60 BSC
1.00 BSC
1.10 BSC
TOP VIEW
e
L
0.35
0.45
A
0.05
0.05
C
C
RECOMMENDED
SOLDERING FOOTPRINT*
2X
1.00
A1
SEATING
PLANE
1.70
C
SIDE VIEW
e
1
e/2
M
0.07
C A B
1
2X
0.58
b
DIMENSIONS: MILLIMETERS
2X
L
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
M
0.07
C A B
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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ESD8501V5/D
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