ESD8504G [ONSEMI]
ESD Protection Diode;
| 型号： | ESD8504G |
| 厂家： | 
ONSEMI |
| 描述： | ESD Protection Diode |
| 文件： | 总9页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD8504G
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8504G is designed to protect high speed data lines from
ESD. Ultra−low capacitance and low ESD clamping voltage make this
device an ideal solution for protecting voltage sensitive high speed
data lines. The flow−through style package allows for easy PCB layout
and matched trace lengths necessary to maintain consistent impedance
between high speed differential lines such as USB 3.0/3.1.
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MARKING
DIAGRAM
UDFN10
CASE 517BB
4GMG
Features
G
• Low Capacitance (0.5 pF Max, I/O to GND)
4G
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
(Note: Microdot may be in either location)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATION
AND SCHEMATIC
Typical Applications
• USB 3.0/3.1
• eSATA
N/C N/C GND N/C N/C
10
9
8
7
6
• DisplayPort
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
1
2
3
4
5
J
I/O I/O GND I/O I/O
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
I/O
I/O
I/O
I/O
Pin 1
Pin 2 Pin 4
Pin 5
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
25
25
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Pins 3, 8
Note: Common GND − Only Minimum of 1 GND connection required
=
ORDERING INFORMATION
Device
Package
Shipping
ESD8504GMUTAG UDFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2017 − Rev. 1
ESD8504G/D
ESD8504G
ELECTRICAL CHARACTERISTICS
A
I
(T = 25°C unless otherwise noted)
I
PP
Symbol
Parameter
V
RWM
Working Peak Voltage
R
DYN
I
R
Maximum Reverse Leakage Current @ V
RWM
V
V
V
BR
Breakdown Voltage @ I
BR
T
V
V
V
RWM HOLD
C
I
I
V
R
T
C
I
T
Test Current
V
Holding Reverse Voltage
Holding Reverse Current
Dynamic Resistance
Maximum Peak Pulse Current
I
HOLD
HOLD
HOLD
I
R
DYN
R
DYN
−I
PP
I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
V
C
Clamping Voltage @ I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
3.0
6.0
1.0
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
4.0
4.5
V
T
Reverse Leakage Current
Holding Reverse Voltage
Holding Reverse Current
Clamping Voltage (Note 1)
I
R
V
RWM
= 3.0 V, I/O Pin to GND
mA
V
V
I/O Pin to GND
1.9
20
HOLD
HOLD
I
I/O Pin to GND
mA
V
V
V
IEC61000−4−2, 8 KV Contact
See Figures 1 and 2
C
Clamping Voltage
TLP (Note 2)
See Figures 5 through 8
4.75
−5.5
V
I
PP
I
PP
= 8 A
= −8 A
IEC 61000−4−2 Level 2 equivalent
( 4 kV Contact, 4 kV Air)
C
I
I
= 16 A
= −16 A
7.0
−8.5
PP
PP
IEC 61000−4−2 Level 4 equivalent
( 8 kV Contact, 15 kV Air)
Dynamic Resistance
R
I/O Pin to GND
GND to I/O Pin
0.3
0.4
W
DYN
Junction Capacitance
(See Figures 9 & 10)
C
V
R
V
R
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
= 0 V, f = 2.5 GHz between I/O Pins and GND
= 0 V, f = 1 MHz, between I/O Pins
0.39
0.5
0.45
0.25
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
90
80
70
60
50
40
30
20
10
0
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
0
20
40
60
TIME (ns)
80
100
120 140
−20
0
20
40
60
80
100
120 140
TIME (ns)
Figure 1. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 2. IEC61000−4−2 −8 kV Contact
Clamping Voltage
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2
ESD8504G
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD8504G
20
15
−20
−15
−10
−5
10
5
0
0
0
1
2
3
4
5
6
7
8
9
0
−1
−2
−3
−4
−5
−6
−7
−8
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage
IEC
0
p
r
1
2
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD8504G
3.0
2.5
2.0
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1.0
0.5
0
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0
5.0E+08
3.5E+09
6.5E+09
9.5E+09
V , VOLTAGE (V)
R
FREQUENCY (Hz)
Figure 9. Junction Capacitance; VR = −3.0 V −
0 V, f = 1 MHz, I/O − GND, dV/dt = 214 mV/s
Figure 10. Junction Capacitance; VR = 0 V,
f = 500 MHz − 10 GHz
Without ESD8504G
With ESD8504G
Figure 11. USB3.0 Eye Diagram with and without ESD8504G. 5 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
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5
ESD8504G
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
10
100
1000
10000
FREQUENCY (MHz)
Figure 12. ESD8504G Insertion Loss
rd
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3
Harmonic Frequency
(GHz)
Interface
ESD8504G Insertion Loss (dB)
USB 3.0
5
2.5 (m1)
5.0 (m2)
7.5 (m3)
15 (m4)
m1 = −0.13
m3 = −1.08
m2 = −0.48
m4 = −10.0
USB 3.1
10
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6
ESD8504G
USB 3.0/3.1 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
ESD8504G
D−
ESD7L5.0
GND_DRAIN
StdA_SSRX+
D+
GND
StdA_SSRX−
Figure 13. USB 3.0/3.1 Standard Layout Diagram
PCB Layout Guidelines
latch-up condition. For more information on latchup
considerations, see below description on Page 8.
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
• Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
♦ In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 14. In this
configuration, no DC current can flow through the
ESD protection device preventing any potential
Figure 14. USB 3.0/3.1 Connection Diagram
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7
ESD8504G
Latch-Up Considerations
therefore latch-up free. Please note that for USB 3.0
applications, ESD8504G latch-up free considerations are
explained in more detail in the above PCB layout guidelines.
In the non-latch up free load line case, the IV characteristic
of the snapback protection device intersects the load-line in
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
two points (V
, I ) and (V
, I
). Therefore in this
OPA OPA
OPB OPB
case, the potential for latch-up exists if the system settles at
(V , I ) after a transient. Because of this, ESD8504G
OPB OPB
should not be used for HDMI applications – ESD8104 or
ESD8040 have been designed to be acceptable for HDMI
applications without latch-up. Please refer to Application
Note AND9116/D for a more in-depth explanation of
latch-up considerations using ESD8000 series devices.
the load-line in one unique point (V , I ). This is the only
stable operating point of the circuit and the system is
OP OP
I
I
ISSMAX
IOPB
ISSMAX
IOP
IOPA
V
V
VOP VDD
VOPB
VOPA VDD
ESD8504G Latch−up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0/3.1 SS,
DisplayPort
ESD8504G Potential Latch−up:
HDMI 1.4/1.3a TMDS
Figure 15. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
VBR (min)
IH (min)
(mA)
VH (min)
ON Semiconductor ESD8000 Series
Recommended PN
(V)
(V)
Application
HDMI 1.4/1.3a TMDS
USB 2.0 LS/FS
USB 2.0 HS
3.465
3.301
0.482
2.800
3.600
54.78
1.76
N/A
1.0
1.0
1.0
1.0
1.0
ESD8104, ESD8040
ESD8504G
ESD8504G
USB 3.0/3.1 SS
DisplayPort
N/A
ESD8504G, ESD8006
ESD8504G, ESD8006
25.00
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8
ESD8504G
PACKAGE DIMENSIONS
UDFN10 2.5x1, 0.5P
CASE 517BB
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
L
L
D
B
E
A
L1
PIN ONE
REFERENCE
DETAIL A
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10 C
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
A1
A3
b
2X
0.10
C
MOLD CMPD
TOP VIEW
EXPOSED Cu
0.13 REF
0.15
0.35
0.25
0.45
b2
D
DETAIL B
2.50 BSC
A3
A
A3
E
1.00 BSC
0.50 BSC
0.10
0.08
C
C
e
L
0.30
---
0.40
0.05
A1
L1
DETAIL B
OPTIONAL
10X
A1
SEATING
PLANE
CONSTRUCTION
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
2X b2
10X
L
10X
0.50
DETAIL A
2X
0.45
5
1
10
6
1.30
e
8X b
PACKAGE
OUTLINE
0.10
0.05
C
C
A
B
8X
0.25
NOTE 3
0.50
PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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◊
ESD8504G/D
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