CS8151YTVA7G [ONSEMI]
5 V / 100 mA 低漏 (LDO) 稳压器，带重置、延迟重置、监督和唤醒;
| 型号： | CS8151YTVA7G |
| 厂家： | 
ONSEMI |
| 描述： | 5 V / 100 mA 低漏 (LDO) 稳压器，带重置、延迟重置、监督和唤醒 局域网 输出元件 电源电路 线性稳压器IC 调节器 |
| 文件： | 总14页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8151
5.0 V, 100 mA Low Dropout
Linear Regulator with
Watchdog, RESET,
and Wake Up
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The CS8151 is a precision 5.0 V, 100 mA micro−power voltage
regulator with very low quiescent current (400 mA typical at 200 mA
load). The 5.0 V output is accurate within 2% and supplies 100 mA
of load current with a typical dropout voltage of 400 mV.
Microprocessor control logic includes Watchdog, Wake Up and
RESET. This unique combination of low quiescent current and full
microprocessor control makes the CS8151 ideal for use in battery
operated, microprocessor controlled equipment.
2
D PAK−7
DPS SUFFIX
CASE 936AB
1
7
SO−16L
DWF SUFFIX
CASE 751G
The CS8151 Wake Up function brings the microprocessor out of
Sleep mode. The microprocessor in turn, signals its Wake Up status
back to the CS8151 by issuing a Watchdog signal.
16
1
The Watchdog logic function monitors an input signal (WDI) from
the microprocessor. The CS8151 responds to the falling edge of the
Watchdog signal which it expects at least once during each wake−up
period. When the correct Watchdog signal is received, a falling edge is
issued on the wake−up signal line.
SOIC−14
D SUFFIX
CASE 751A
14
1
RESET is independent of V and operates correctly to an output
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
IN
voltage as low as 1.0 V. A RESET signal is issued in any of three
situations. During power up the RESET is held low until the output
voltage is in regulation. During operation if the output voltage shifts
below the regulation limits, the RESET toggles low and remains low
until proper output voltage regulation is restored. And finally, a
RESET signal is issued if the regulator does not receive a Watchdog
signal within the Wake Up period.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
The RESET pulse width, Wake Up signal frequency, and Wake Up
delay time are all set by one external capacitor C
.
Delay
The regulator is protected against short circuit, over voltage, and
thermal runaway conditions. The device can withstand 74 V peak
transients, making it suitable for use in automotive environments.
Features
• 5.0 V 2%/100 mA Output Voltage
• Micropower Compatible Control Functions
♦ Wake Up
♦ Watchdog
♦ RESET
• Low Dropout Voltage: 400 mV @ 100 mA
• Low Sleep Mode Quiescent Current (400 mA Typ)
• Protection Features
♦ Thermal Shutdown
♦ Short Circuit
♦ 74 V Peak Transient Capability
♦ Reverse Transient (−50 V)
• Internally Fused Leads in SO−14L and SO−16L Packages
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
October, 2008 − Rev. 18
CS8151/D
CS8151
PIN CONNECTIONS AND MARKING DIAGRAMS
SO−16L
CASE 751G
SO−14L
CASE 751A
2
D PAK−7
CASE 936AB
1
14
1
16
Delay
NC
GND
GND
GND
RESET
Wake Up
GND
GND
GND
WDI
VIN
NC
NC
NC
GND
GND
GND
Delay
RESET
Wake Up
GND
GND
WDI
NC
CS
8151
AWLYWWG
Sense
Sense
V
OUT
V
1
OUT
V
IN
Tab = GND
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Pin 1. V
2. V
OUT
WL
Y, YY
WW
G
IN
3. WDI
4. GND
5. Wake Up
6. RESET
7. Delay
V
OUT
V
IN
Internally
connected
2
on D PAK
Current Source
(Circuit Bias)
Overvoltage
Shutdown
V
OUT
Current
Limit
Wake Up
Sense
Sense
Timing
Circuit
Wake Up
Circuit
Delay
WDI
+ −
Error
Amplifier
Thermal
Shutdown
Watchdog
Circuit
Falling Edge
Detector
Bandgap
Reference
V
OUT
RESET
RESET
Circuit
GND
Figure 1. Block Diagram
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2
CS8151
MAXIMUM RATINGS*
Rating
Value
Internally Limited
Internally Limited
−15
Unit
−
Power Dissipation
Output Current (V
Reverse Battery
, RESET, Wake Up)
OUT
−
V
Peak Transient Voltage (60 V Load Dump @ V = 14 V)
+74
V
IN
Maximum Negative Transient (t < 2.0 ms)
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Machine Model)
Logic Inputs/Outputs
−50
V
2.0
kV
V
200
−0.3 to +6.0
−55 to +150
V
Storage Temperature Range
°C
260 peak
240 peak
°C
°C
Lead Temperature Soldering
Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Notes 2 & 3)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 10 seconds max
2. 60 seconds max above 183°C
3. −5°C / +0°C allowable conditions
*The maximum package power dissipation must be observed
ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C, −40°C ≤ T ≤ 150°C, 6.0 V ≤ V ≤ 26 V, 100 mA ≤ I
≤ 100 mA,
A
J
IN
OUT
C = 47 mF (ESR < 8.0 W), C
= 0.1 mF; unless otherwise specified.)
2
Delay
Characteristic
Output Section
Test Conditions
Min
Typ
Max
Unit
Output Voltage, V
9.0 V < V < 16 V
4.90
4.85
5.0
5.0
5.10
5.15
V
V
OUT
IN
6.0 V < V < 26 V, 0 < I
< 100 mA
IN
OUT
Dropout Voltage (V − V
)
I
I
= 100 mA
= 100 mA
−
−
400
100
600
150
mV
mV
IN
OUT
OUT
OUT
Load Regulation
Line Regulation
V
= 14 V, 100 mA < I
< 100 mA
−
−
10
10
50
50
−
mV
mV
dB
mA
°C
IN
OUT
I
= 1.0 mA, 6.0 V < V < 26 V
IN
OUT
Ripple Rejection
Current Limit
7.0 V < V < 17 V @ f = 120 Hz, I
= 100 mA
60
100
150
50
75
IN
OUT
V
= 4.5 V
250
180
56
−
OUT
OUT
Thermal Shutdown
Overvoltage Shutdown
Quiescent Current
−
210
62
V
< 1.0 V
V
I
I
I
= 200 mA (Sleep)
= 50 mA
= 100 mA (Wake Up)
−
−
−
0.4
4.0
12
0.75
−
20
mA
mA
mA
OUT
OUT
OUT
Reverse Current
RESET
V
OUT
= 5.0 V, V = 0 V
−
1.0
1.5
mA
IN
Threshold High (RTH)
Threshold Low (RTL)
Hysteresis
RTH V
Increasing
Decreasing
V
OUT
− 0.3
−
V − 0.04
OUT
V
V
OUT
RTL V
4.5
150
−
4.7
200
0.2
4.2
4.91
OUT
RTH − RTL
1.0 V < V
250
0.8
5.1
mV
V
Output Low
RTL, I
= 25 mA
OUT
OUT
Output High
I
= 25 mA, V
> RTH
3.8
V
OUT
OUT
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3
CS8151
ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C, −40°C ≤ T ≤ 150°C, 6.0 V ≤ V ≤ 26 V, 100 mA ≤ I
≤ 100 mA,
A
J
IN
OUT
C = 47 mF (ESR < 8.0 W), C
= 0.1 mF; unless otherwise specified.)
2
Delay
Characteristic
RESET
Test Conditions
Min
Typ
Max
Unit
Current Limit
RESET = 0 V, V
RESET = 5.0 V, V
> V
(Sourcing)
0.025
0.1
0.5
12
1.30
80
mA
mA
OUT
RTH
> 1.0 V (Sinking)
OUT
Delay Time
Watchdog Input
Threshold High
Threshold Low
Hysteresis
POR Mode
3.0
5.0
7.0
ms
−
−
−
−
1.4
1.3
100
0
2.0
−
V
V
0.8
25
−
mV
mA
ms
Input Current
Pulse Width
0 < WDI < 6.0 V
−10
5.0
+10
−
50% WDI Falling Edge to
50% WDI Rising Edge and
50% WDI Rising Edge to
50% WDI Falling Edge
(see Figures 2, 3, and 4)
−
Wake Up Output
Wake Up Period
See Figure 2
See Figure 4
30
40
15
40
50
20
50
60
25
ms
%
Wake Up Duty Cycle Nominal
RESET High to
Wake Up Rising Delay Time
50% RESET Rising Edge to
50% Wake Up Edge
ms
(see Figures 2, 3, and 4)
Wake Up Response to
Watchdog Input
50% WDI Falling Edge to
50% Wake Up Falling Edge
−
−
2.0
2.0
10
10
ms
ms
Wake Up Response to
RESET
50% RESET Falling Edge to
50% Wake Up Falling Edge,
V
OUT
= 5.0 V → 4.5 V
Output Low
Output High
Current Limit
I
I
= 25 mA (Sinking)
= 25 mA (Sourcing)
−
0.2
4.2
0.8
5.1
V
V
OUT
OUT
3.8
Wake Up = 5.0 V
Wake Up = 0 V
0.025
0.05
1.0
−
7.0
3.5
mA
mA
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4
CS8151
PACKAGE PIN DESCRIPTION
Package Pin #
Pin
Symbol
2
SO−14L
D PAK
SO−16L
Function
7
8
9
1
2
3
8
9
V
Regulated output voltage 5.0 V 2%.
Supply voltage to the IC.
OUT
V
IN
11
WDI
CMOS/TTL compatible input lead. The Watchdog function monitors the falling
edge of the incoming signal.
3−5,
4
5
6
4, 5, 6, 12, 13*
GND
Ground connection.
10−12
13
14
14
15
Wake Up
RESET
CMOS/TTL compatible output consisting of a continuously generated signal used
to Wake Up the microprocessor from sleep mode.
CMOS/TTL compatible output lead RESET goes low whenever V
drops by
OUT
more than 6.0% from nominal, or during the absence of a correct watchdog
signal.
1
6
7
16
7
Delay
Input lead from timing capacitor for RESET and Wake Up signal.
−
Sense
Kelvin connection which allows remote sensing of the output voltage for im-
proved regulation. If remote sensing is not required, connect to V
.
OUT
*Pin 6 GND is not directly shorted to the fused paddle GND. The fused paddle GND (pins 4, 5, 12, 13) is connected through the substrate.
Pin 6 must be electrically connected to at least one of the fused paddle GND’s on the PC board.
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5
CS8151
TIMING DIAGRAMS
V
IN
RESET
Wake Up
WDI
Wake Up
Duty Cycle = 50%
V
OUT
POR
RESET High
to Wake Up
Delay Time
Power Up
Sleep Mode
Normal Operation with Varying Watchdog Signal
Figure 2. Power Up, Sleep Mode and Normal Operation
V
IN
RESET Delay Time
RESET
Wake Up
WDI
V
OUT
POR
RESET High
to Wake Up
Delay Time
Wake Up
Period
RESET High
to Wake Up
Delay Time
Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued
RESET
Wake Up Period
Wake Up
WDI
RTL
Power Down
V
OUT
Watchdog
Pulse Width
POR
POR
Watchdog Pulse Width
Figure 4. Power Down and Restart Sequence
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6
CS8151
DEFINITION OF TERMS
Dropout Voltage: The input−output voltage differential
techniques such that the average chip temperature is not
significantly affected.
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100mV from the nominal value
obtained at 14V input, dropout voltage is dependent upon
load current and junction temperature.
Input Voltage: The DC voltage applied to the input
terminals with respect to ground.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made
under conditions of low dissipation or by using pulse
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Quiescent Current: The part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.
Ripple Rejection: The ratio of the peak−to−peak input
ripple voltage to the peak−to−peak output ripple voltage.
Current Limit: Peak current that can be delivered to the
output.
CIRCUIT DESCRIPTION
Functional Description
The first falling edge of the watchdog signal causes the
Wake Up to go low within 2.0 ms (Typ) and remain low until
the next Wake Up cycle (see Figure 5). Other watchdog
pulses received within the same cycle are ignored (Figures
2, 3, and 4).
During power up, RESET is held low until the output
voltage is in regulation. During operation, if the output
voltage shifts below the regulation limits, the RESET
toggles low and remains low until proper output voltage
regulation is restored. After the RESET delay, RESET
returns high.
The Watchdog circuitry continuously monitors the input
watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during one
Wake Up cycle will cause a RESET pulse to occur at the end
of the Wake Up cycle (see Figure 3).
The Wake Up output is pulled low during a RESET
regardless of the cause of the RESET. After the RESET
returns high, the Wake Up cycle begins again (see Figure 3).
The RESET pulse width, Wake Up signal frequency and
RESET high to Wake Up delay time are all set by one
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not performing
a main routine. The Wake Up signal is generated
continuously and is used to interrupt a microcontroller that
is in sleep mode. The nominal output is a 5.0 V square wave
with a duty cycle of 50% at a frequency that is determined
by a timing capacitor, C
.
Delay
When the microprocessor receives a rising edge from the
Wake Up output, it must issue a watchdog pulse and check
its inputs to decide if it should resume normal operations or
remain in the sleep mode.
Wake Up
WDI
Wake Up
Response
to WDI
external capacitor C
.
Delay
5
Wake Up Period = (4 × 10 )C
Delay
4
RESET Delay Time = (5 × 10 )C
Delay
5
Figure 5. Wake Up Response to WDI
RESET High to Wake Up Delay Time = (2 × 10 )C
Delay
Capacitor temperature coefficient and tolerance as well as
the tolerance of the CS8151 must be taken into account in
order to get the correct system tolerance for each parameter.
RESET
Wake Up
Wake Up
Response
to RESET
Figure 6. Wake Up Response to RESET (Low Voltage)
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7
CS8151
APPLICATION NOTES
Operation Without Watchdog
connection, a reset would occur because a watchdog signal
on WDI would not occur in the required time frame. The
Wake Up Pin provides the watchdog signal into the
WDI Pin.
The CS8151 can be operated without the watchdog
functionality by connecting the WDI and Wake Up Pins.
This will eliminate false resets from occurring. Without the
Battery
V
IN
V
OUT
V
CC
C1
C2
Microprocessor
CS8151
WDI
C
RESET
RESET
Delay
C
Delay
GND
Wake Up
Figure 7. Device Operation Without Watchdog Function
Stability Considerations
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (see Figure 8).
If the input voltage rises above the overvoltage shutdown
threshold (e.g. load dump), the output shuts down. This
response protects the internal circuitry and enables the IC to
survive unexpected voltage transients.
Should the junction temperature of the power device
exceed 180°C (Typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
The output or compensation capacitor C2 (see Figure 9)
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability.
V
IN
V
OUT
C1*
0.1 mF
C2**
10 mF
R
RST
CS8151
RESET
> 50 V
V
IN
*C1 required if regulator is located far from the power
supply filter.
**C2 required for stability.
V
I
OUT
Figure 9. Test and Application Circuit Showing
Output Compensation
OUT
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
Load
Dump
Short
Circuit
Thermal
Shutdown
Figure 8. Typical Circuit Waveforms for Output
Stage Protection
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8
CS8151
the capacitor will vary considerably. The capacitor
(
)
I
P
+ V
* V
D(max)
IN(max)
) V
OUT(min) OUT(max)
(1)
manufacturers data sheet usually provide this information.
The value for the output capacitor C2 shown in the test and
applications circuit should work for most applications,
however it is not necessarily the optimized solution.
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
I
IN(max) Q
where:
V
V
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
IN(max)
OUT(min)
OUT(max)
I
application, and
is the quiescent current the regulator consumes at
I
Q
I
.
OUT(max)
Once the value of P
permissible value of R
is known, the maximum
can be calculated:
D(max)
qJA
(2)
150C * T
A
R
+
qJA
P
D
The value of R
can then be compared with those in the
qJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
R
qJA
the die temperature below 150°C.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
I
I
IN
OUT
SMART
V
IN
V
OUT
REGULATOR®
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
Control
}
Features
I
Q
Figure 10. Single Output Regulator with Key
Performance Parameters Labeled
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Heat Sinks
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
:
qJA
(3)
R
+ R
) R
) R
qCS qSA
qJA
qJC
where:
R
qJC
R
qCS
R
qSA
R
qJC
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
appears in the package section of the data sheet. Like
and R are
R
qJA
, it too is a function of package type. R
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers.
Calculating Power Dissipation
In a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 10) is:
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9
CS8151
PACKAGE THERMAL DATA
2
Parameter
D PAK−7
SOIC−14
23**
SOIC−16
Unit
°C/W
°C/W
R
Typical
Typical
.
1.8
18
75
q
JC
R
10−50*
116
q
JA
*Depending on thermal properties of substrate. R
= R
+ R
q
q
q
JA
JC
CA
**Junction−Lead (#5)
Battery
V
IN
V
OUT
V
CC
C1
C2
Microprocessor
I/O
CS8151
WDI
C
RESET
RESET
I/O
Delay
C
Delay
GND
Wake Up
Figure 11. Application Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
1000
Unstable Region
C
C
= 47 mF
= 1 mF
VOUT
100
10
VOUT
Stable Region
C
= 1 mF
VOUT
1
C
= 10 mF
= 47 mF
VOUT
C
VOUT
0.1
0.01
Unstable Region
20 30 40 50 60
0
10
70 80 90 100
I
OUTPUT CURRENT (mA)
OUT
Figure 12. CS8151 Output Stability
with Output Capacitor Change
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10
CS8151
ORDERING INFORMATION
Device
†
Package
Shipping
2
CS8151YDPS7G
D PAK−7
50 Units / Rail
750 / Tape & Reel
47 Units / Rail
(Pb−Free)
2
CS8151YDPSR7G
CS8151YDWF16G
CS8151YDWFR16G
CS8151D2G
D PAK−7
(Pb−Free)
SO−16L
(Pb−Free)
SO−16L
(Pb−Free)
1000 / Tape & Reel
55 Units / Rail
SO−14L
(Pb−Free)
CS8151D2R2G
SO−14L
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
CS8151
PACKAGE DIMENSIONS
D2PAK−7 (SHORT LEAD)
DPS SUFFIX
CASE 936AB−01
ISSUE A
NOTES:
TERMINAL 8
1. DIMENSIONS AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
A
K
U
E
INCHES
MILLIMETERS
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
S
MIN
MAX
0.406
0.336
0.180
0.036
0.055
MIN
10.05
8.28
4.31
0.66
1.14
MAX
10.31
8.53
4.57
0.91
1.40
0.396
0.326
0.170
0.026
0.045
0.050 REF
0.539
S
V
B
M
H
1.27 REF
0.579
0.066
0.010
0.110
0.023
0.078
8 °
13.69
1.40
0.00
2.54
0.43
1.47
0 °
14.71
1.68
0.25
2.79
0.58
1.98
8 °
L
0.055
0.000
0.100
0.017
0.058
0 °
P
G
N
D
R
0.095
0.105
2.41
2.67
U
V
0.256 REF
0.305 REF
6.50 REF
7.75 REF
C
SOLDERING FOOTPRINT*
9.5
0.374
2.16
3.25
0.085
0.128
1.27
0.050
C
L
10.54
0.415
C
L
3.8
0.150
1
0.96
0.038
8.26
0.325
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
12
CS8151
PACKAGE DIMENSIONS
SO−16L
DWF SUFFIX
CASE 751G−03
ISSUE C
A
D
q
16
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
10.45
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
10.15
7.40
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
14X
e
q
_
_
C
T
http://onsemi.com
13
CS8151
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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