CS8156YT5 [ONSEMI]
12 V, 5.0 V Low Dropout Dual Regulator with ENABLE; 12 V ， 5.0 V低压降稳压器双用ENABLE
| 型号： | CS8156YT5 |
| 厂家： | 
ONSEMI |
| 描述： | 12 V, 5.0 V Low Dropout Dual Regulator with ENABLE |
| 文件： | 总11页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8156
12 V, 5.0 V Low Dropout
Dual Regulator with ENABLE
The CS8156 is a low dropout 12 V/5.0 V dual output linear regulator.
The 12 V 5.0% output sources 750 mA and the 5.0 V 2.0% output
sources 100 mA.
The on board ENABLE function controls the regulator’s two
outputs. When the ENABLE lead is low, the regulator is placed in
SLEEP mode. Both outputs are disabled and the regulator draws only
200 nA of quiescent current.
The regulator is protected against overvoltage conditions. Both
outputs are protected against short circuit and thermal runaway
conditions.
The CS8156 is packaged in a 5 lead TO−220 with copper tab. The
copper tab can be connected to a heat sink if necessary.
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TO−220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO−220
FIVE LEAD
TVA SUFFIX
CASE 314K
Features
1
• Two Regulated Outputs
− 12 V 5.0%; 750 mA
− 5.0 V 2.0%; 100 mA
• Very Low SLEEP Mode Current Drain 200 nA
• Fault Protection
TO−220
FIVE LEAD
THA SUFFIX
CASE 314A
1
− Reverse Battery
− +60 V, −50 V Peak Transient Voltage
− Short Circuit
5
PIN CONNECTIONS AND
MARKING DIAGRAM
− Thermal Shutdown
• CMOS Compatible ENABLE
• Pb−Free Packages are Available
Tab = GND
Pin 1. V
2. V
IN
CS
8156
OUT1
3. GND
4. ENABLE
5. V
AWLYWWG
OUT2
1
CS8156 = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
WW
G
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
February, 2006 − Rev. 8
CS8156/D
CS8156
V
, 5.0 V
OUT2
V
IN
Anti−saturation
and
Current Limit
+
−
ENABLE
−
+
Pre−Regulator
V
, 12 V
OUT1
Overvoltage
Shutdown
Anti−saturation
and
Current Limit
Bandgap
Reference
+
−
GND
Thermal
Shutdown
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Input Voltage:
Operating Range
Peak Transient Voltage (Note 1)
−0.5 to 26
60
V
V
Internal Power Dissipation
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Soldering:
Internally Limited
−40 to +125
−40 to +150
−65 to +150
260 peak
−
°C
°C
°C
°C
Wave Solder (through hole styles only) (Note 2)
1. Load Dump = 46 V
2. 10 second maximum.
*The maximum package power dissipation must be observed.
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2
CS8156
ELECTRICAL CHARACTERISTICS for VOUT: (V = 14.5 V, I
= 5.0 mA, I
= 5.0 mA, −40°C ≤ T ≤ +150°C,
OUT2 J
IN
OUT1
−40°C ≤ T ≤ +125°C; unless otherwise specified.)
C
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage (V
)
OUT1
Output Voltage, (V
Dropout Voltage
)
13 V ≤ V ≤ 16 V, I
≤ 750 mA
11.2
−
12.0
12.8
V
OUT1
IN
OUT1
I
= 500 mA
= 750 mA
0.4
0.6
0.6
1.0
V
V
OUT1
I
OUT1
Line Regulation
Load Regulation
Quiescent Current
13 V ≤ V ≤ 16 V, 5.0 mA ≤ I
< 100 mA
−
−
15
15
80
80
mV
mV
IN
OUT1
5.0 mA ≤ I
≤ 500 mA
OUT1
I
I
≤ 500 mA, No Load on Standby
≤ 750 mA, No Load on Standby
−
−
45
100
125
250
mA
mA
OUT1
OUT1
Quiescent Current (Sleep Mode)
Ripple Rejection
ENABLE = Low
f = 120 Hz, I
−
0.2
70
50
−
μA
dB
A
= 5.0 mA, V = 1.5 V at 15.5 V
DC
42
OUT
IN
PP
Current Limit
−
0.75
60
1.20
90
2.50
−
Maximum Line Transient
Reverse Polarity Input Voltage, DC
V
V
≤ 13 V
V
OUT1
OUT1
≥ −0.6 V, 10 Ω Load
−18
−50
−30
−80
−
V
Reverse Polarity Input Voltage,
Transient
1.0% Duty Cycle, t = 100 ms, V
10 Ω Load
≥ −6.0 V,
−
V
OUT
Output Noise Voltage
Output Impedance
10 Hz − 100 kHz
−
−
−
500
1.0
45
μVrms
500 mA DC and 10 mA rms, 100Hz
−
0.2
34
Ω
Overvoltage Shutdown
28
V
Standby Output (V
Output Voltage, (V
Dropout Voltage
Line Regulation
Load Regulation
Ripple Rejection
Current Limit
)
OUT2
)
9.0 V ≤ V ≤ 16 V, 1.0 mA ≤ I
≤ 100 mA
4.90
−
5.00
−
5.10
0.60
50
50
−
V
OUT2
IN
OUT2
I
≤ 100 mA
V
OUT2
6.0 V ≤ V ≤ 26 V, 1.0 mA ≤ I
≤ 100 mA
OUT
−
5.0
5.0
70
mV
mV
dB
mA
IN
1.0 mA ≤ I
≤ 100 mA; 9.0 V ≤ V ≤ 16 V
−
OUT2
IN
f = 120 Hz; I
= 100 mA, V = 1.5 V at 14.5 V
DC
42
100
OUT
IN
PP
−
200
−
ENABLE Function (ENABLE)
Input ENABLE Threshold
V
V
Off
On
−
2.00
1.25
1.25
0.80
−
V
V
OUT1
OUT1
Input ENABLE Current
V
≤ V
−10
0
10
μA
ENABLE
THRESHOLD
PACKAGE PIN DESCRIPTION
PACKAGE LEAD #
5 Lead TO−220
LEAD SYMBOL
FUNCTION
1
2
3
4
V
Supply voltage, usually direct from battery.
Regulated output 12 V, 750 mA (typ).
Ground connection.
IN
V
OUT1
GND
ENABLE
CMOS compatible input lead; switches outputs on and off.
When ENABLE is high V and V are active.
OUT1
OUT2
5
V
Regulated output 5.0 V, 100 mA (typ).
OUT2
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3
CS8156
TYPICAL PERFORMANCE CHARACTERISTICS
2000
1800
13
12
11
10
R
= 10 Ω
L
1600
1400
1200
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
1000
800
600
400
200
0
−1.0
−2.0
0
50
100
150
(mA)
200
−40
−20
0
20
40
60
I
Input Voltage (V)
OUT
Figure 2. Dropout Voltage vs. IOUT2
Figure 3. VOUT1 vs. Input Voltage
12.15
12.10
12.05
12.00
11.95
11.90
11.85
11.80
11.75
5.030
5.020
5.010
5.000
4.990
4.980
4.970
−40 −20
0
20 40 60 80 100 120 140 160
−40 −20
0
20 40 60 80 100 120 140 160
Temp (°C)
Temp (°C)
Figure 4. VOUT1 vs. Temperature
Figure 5. VOUT2 vs. Temperature
100
80
60
40
20
5.0
4.0
3.0
2.0
1.0
0
0
0
0
1.0
2.0
3.0
(V)
4.0
5.0
5.0
10
15
(V)
20
25
V
V
ENABLE
ENABLE
Figure 6. ENABLE Current vs.
ENABLE Voltage
Figure 7. ENABLE Current vs. ENABLE
Voltage
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CS8156
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
20
10
10
I
= 100 mA
OUT2
I
= 500 mA
OUT1
5.0
0
0
−5.0
−10
−10
−20
3.0
2.0
1.0
0
3.0
2.0
1.0
0
0
10
20
30
40
50
60
60
90
0
10
20
30
40
50
60
Time (μs)
Time (μs)
Figure 8. Line Transient Response (VOUT1
)
Figure 9. Line Transient Response (VOUT2)
150
100
50
150
100
50
0
0
−50
−100
−150
0.8
0.6
0.4
0.2
0
−50
−100
−150
20
15
10
5.0
0
0
10
20
30
40
50
0
10
20
30
40
50
60
Time (μs)
Time (μs)
Figure 10. Load Transient Response
(VOUT1
Figure 11. Load Transient Response
(VOUT2
)
)
20
18
150
No Load on 5.0 V
140
130
120
110
100
90
80
70
60
50
40
30
20
10
125°C
Infinite Heat Sink
16
14
V
= 14 V
IN
12
25°C
10
8.0
6.0
4.0
2.0
−40°C
10°C/W Heat Sink
No Heat Sink
0
0
0
10
20
30
40
50
60
70
80
0
100
200
300
400
500
600
700 800
Ambient Temperature (°C)
Output Current (mA)
Figure 12. Maximum Power Dissipation
(TO−220)
Figure 13. Quiescent Current vs. Output
Current for VOUT2
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CS8156
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
3.0
2.0
22
20
No Load on 5.0 V
18
1.0
0
25°C
16
V
= 14 V
IN
14
−40°C
−1.0
12
125°C
10
−2.0
−3.0
8.0
6.0
4.0
−40°C
125°C
V
= 6.0−26 V
IN
−4.0
−5.0
−6.0
25°C
2.0
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Output Current (mA)
Output Current (mA)
Figure 14. Quiescent Current vs. Output
Current for VOUT1
Figure 15. Line Regulation vs. Output
Current for VOUT2
25
20
0
−40°C
25°C
125°C
−2.0
−4.0
−6.0
−8.0
−10
−12
−14
−16
−18
15
10
5.0
0
25°C
−5.0
−10
−15
−20
−25
−30
−35
−40
V
= 13−26V
IN
125°C
−40°C
V
= 14 V
IN
0
20
40
60
80
100
120
140
0
100
200
300
400
500 600
700
800
Output Current (mA)
Output Current (mA)
Figure 16. Load Regulation vs. Output
Current fo VOUT2
Figure 17. Line Regulation vs. Output
Current for VOUT1
0
−5.0
−10
−15
−20
−25
−30
−40°C
25°C
125°C
V
= 14 V
IN
−35
−40
0
100
200
300
400
500
600
700
800
Output Current (mA)
Figure 18. Load Regulation vs. Output
Current for VOUT1
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CS8156
DEFINITION OF TERMS
Dropout Voltage − The input−output voltage differential
Load Regulation − The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability − Output voltage stability under
accelerated life−test conditions after 1000 hours with
maximum rated voltage and junction temperature.
Output Noise Voltage − The rms AC voltage at the
output, with constant load and no input ripple, measured
over a specified frequency range.
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100 mV from the nominal value
obtained at 14 V input, dropout voltage is dependent upon
load current and junction temperature.
Input Voltage − The DC voltage applied to the input
terminals with respect to ground.
Input Output Differential − The voltage difference
between the unregulated input voltage and the regulated
output voltage for which the regulator will operate.
Line Regulation − The change in output voltage for a
change in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Quiescent Current − The part of the positive input
current that does not contribute to the positive load current,
i.e., the regulator ground lead current.
Ripple Rejection − The ratio of the peak−to−peak input
ripple voltage to the peak−to−peak output ripple voltage.
Temperature Stability of V
− The percentage
OUT
change in output voltage for a thermal variation from room
temperature to either temperature extreme.
60 V
34 V
26 V
14V
V
14 V
IN
3.0 V
2.0 V
0.8 V
ENABLE
12 V
12 V
12 V
12 V
12 V
2.4 V
0 V
0 V
V
0 V
0 V
OUT1
5.0 V
5.0 V
V
2.4 V
OUT2
Turn
On
Load
Dump
Low V
Line
V
V
OUT1
Thermal
Shutdown
Turn
Off
IN
OUT1
Noise, Etc. Short
Circuit
V
Short
OUT2
Circuit
Figure 19. Typical Circuit Waveform
APPLICATION NOTES
Stability Considerations
recommended value and work towards a less expensive
alternative part for each output.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the
cheapest solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitors C2 and C3 shown in
the test and applications circuit should work for most
applications, however it is not necessarily the best solution.
To determine acceptable values for C2 and C3 for a
particular application, start with a tantalum capacitor of the
connected in series with the capacitor C will simulate the
2
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using the
decade box and vary the load current until oscillations
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7
CS8156
appear. Record the values of load current and ESR that cause
The value of R
can be compared with those in the
ΘJA
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
R
ΘJA
the die temperature below 150°C.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Step 5: If the capacitor is adequate, repeat steps 3 and 4 with
the next smaller valued capacitor. A smaller capacitor will
usually cost less and occupy less board space. If the output
oscillates within the range of expected operating conditions,
repeat steps 3 and 4 with the next larger standard capacitor
value.
I
I
IN
OUT1
Smart
Regulator
V
V
OUT1
IN
I
OUT2
Control
Features
V
OUT2
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
I
Q
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Figure 20. Dual Output Regulator With Key
Performance Parameters Labeled.
Once the minimum capacitor value with the maximum
ESR is found for each output, a safety factor should be added
to allow for the tolerance of the capacitor and any variations
in regulator performance. Most good quality aluminum
electrolytic capacitors have a tolerance of 20% so the
minimum value found should be increased by at least 50%
to allow for this tolerance plus the variation which will occur
at low temperatures. The ESR of the capacitors should be
less than 50% of the maximum allowable ESR found in step
3 above.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
ΘJA
:
R
+ R
QJC
) R
QCS
) R
QSA
(3)
QJA
Repeat steps 1 through 7 with C , the capacitor on the
3
other output.
where:
R
R
R
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
ΘJC
ΘCS
ΘSA
Calculating Power Dissipation in a
Dual Output Linear Regulator
The maximum power dissipation for a dual output
regulator (Figure 20) is
R
ΘJC
appears in the package section of the data sheet. Like
R
, it too is a function of package type. R
and R
NJ
NJ
Nj
I
ΘJA
ΘCS ΘSA
V
V
* V
* V
)
P
+
IN(max)
IN(max)
OUT1(min) OUT1(max)
D(max)
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
Nj
(1)
I
) V
IQ
OUT2(min) OUT2(max)
IN(max)
where:
V
V
V
is the maximum input voltage,
IN(max)
is the minimum output voltage from V
is the minimum output voltage from V
,
,
OUT1(min)
OUT2(min)
OUT1
OUT2
C *
0.1 μF
1
I
is the maximum output current, for the
OUT1(max)
V
IN
V
V
application,
OUT1
OUT2
+
+
CS8156
C **
22 μF
2
I
is the maximum output current, for the
ENABLE
OUT2(max)
application, and
I
I
is the quiescent current the regulator consumes at
.
Q
GND
C **
3
22 μF
OUT(max)
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
ΘJA
* C is required if the regulator is far from power supply filter.
150°C * T
+
1
A
R
QJA
** C C required for stability.
(2)
2,
3
P
D
Figure 21. Test & Application Circuit
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CS8156
ORDERING INFORMATION
Device
†
Package
Shipping
CS8156YT5
TO−220 FIVE LEAD STRAIGHT
50 Units/Rail
50 Units/Rail
CS8156YT5G
TO−220 FIVE LEAD STRAIGHT
(Pb−Free)
CS8156YTVA5
TO−220 FIVE LEAD VERTICAL
50 Units/Rail
50 Units/Rail
CS8156YTVA5G
TO−220 FIVE LEAD VERTICAL
(Pb−Free)
CS8156YTHA5
TO−220 FIVE LEAD HORIZONTAL
50 Units/Rail
50 Units/Rail
CS8156YTHA5G
TO−220 FIVE LEAD HORIZONTAL
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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CS8156
PACKAGE DIMENSIONS
TO−220
FIVE LEAD
T SUFFIX
CASE 314D−04
ISSUE E
SEATING
−T−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
PLANE
C
−Q−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
B
E
A
U
INCHES
DIM MIN MAX
MILLIMETERS
MIN MAX
L
1 2 3 4 5
A
B
C
D
E
G
H
J
0.572
0.390
0.170
0.025
0.048
0.613 14.529 15.570
0.415 9.906 10.541
K
0.180 4.318
0.038 0.635
0.055 1.219
4.572
0.965
1.397
0.067 BSC
1.702 BSC
0.087
0.015
0.990
0.320
0.140
0.105
0.112 2.210 2.845
0.025 0.381 0.635
1.045 25.146 26.543
J
H
G
K
L
D 5 PL
0.365 8.128
0.153 3.556
0.117 2.667
9.271
3.886
2.972
Q
U
M
M
T Q
0.356 (0.014)
TO−220
FIVE LEAD
TVA SUFFIX
CASE 314K−01
ISSUE O
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
ꢀꢁ2. CONTROLLING DIMENSION: INCH.
ꢀꢁ3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
−Q−
E
INCHES
DIM MIN MAX
0.590 14.22
MILLIMETERS
MIN
MAX
14.99
10.54
4.83
W
A
B
C
D
E
F
0.560
0.385
0.160
0.027
0.045
0.530
0.415
0.190
0.037
0.055
9.78
4.06
0.69
1.14
A
0.94
1.40
U
F
0.545 13.46
13.84
L
G
J
0.067 BSC
1.70 BSC
K
0.014
0.785
0.321
0.063
0.146
0.271
0.146
0.460
0.022
0.36
0.800 19.94
0.56
20.32
8.56
1
2
3
4
5
K
L
0.337
0.078
0.156
0.321
0.196
0.475
8.15
1.60
3.71
6.88
3.71
11.68
M
Q
R
S
U
W
1.98
3.96
8.15
4.98
M
12.07
5 °
5 °
J
D
5 PL
G
M
M
T Q
0.356 (0.014)
S
R
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10
CS8156
TO−220
FIVE LEAD
THA SUFFIX
CASE 314A−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
−T−
B
C
−P−
E
Q
OPTIONAL
CHAMFER
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
MIN MAX
A
B
C
D
E
F
0.572
0.390
0.170
0.025
0.048
0.570
A
0.415
0.180
0.038
0.055
9.906 10.541
U
F
4.318
0.635
1.219
4.572
0.965
1.397
L
K
0.585 14.478 14.859
1.702 BSC
0.381 0.635
0.745 18.542 18.923
G
J
0.067 BSC
0.015
0.730
0.320
0.140
0.210
0.468
0.025
K
L
G
5X J
0.365
0.153
0.260
8.128
3.556
5.334
9.271
3.886
6.604
Q
S
U
S
5X D
0.505 11.888 12.827
M
M
T P
0.014 (0.356)
PACKAGE THERMAL DATA
Parameter
TO−220
FIVE LEAD
Unit
R
R
Typical
Typical
2.0
50
°C/W
°C/W
Θ
JC
JA
Θ
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