CM1235_14_技术文档

CM1233

ESD Clamp Array for High

Speed Data Line Protection

Product Description

The CM1233 is ideal for protecting systems with high data and

clock rates or for circuits requiring low capacitive loading and tightly

controlled signal skews (with channel−to−channel matching at 2%

max deviation).

http://onsemi.com

The device is particularly well−suited for protecting systems using

high−speed ports such as DVI or HDMI, along with corresponding

ports in removable storage, digital camcorders, DVD−RW drives and

other applications where extremely low loading capacitance with ESD

protection are required.

The CM1233 also features easily routed “pass−through” pinouts in a

RoHS compliant (lead−free), 16−lead WDFN, small footprint

package.

16

1

WDFN16

DE SUFFIX

CASE 511AY

PINOUT DIAGRAM

Features

• ESD Protection for 4 Pairs of Differential Channels

• ESD Protection to IEC61000−4−2 Level 4 at 8 kV Contact

Discharge

• Pass−through Impedance Matched Clamp Architecture

• Flow−through Routing for High−speed Signal Integrity

• Minimal Line Capacitance Change with Temperature and Voltage

• 100 W Matched Impedance for Each Paired Differential Channel

• Each I/O Pin can Withstand Over 1000 ESD Strikes*

• RoHS Compliant (lead−free) WDFN−16 Package

Out_1+

In_1+

1

Out_1−

Out_2+

Out_2−

Out_3+

Out_3−

Out_4+

Out_4−

In_1−

In_2+

In_2−

In_3+

In_3−

In_4+

In_4−

GND

(Bottom View)

Applications

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

and LCD Displays

• General Purpose High−speed Data Line ESD Protection

*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin

subjected to 8 kV contact discharge for 1000 pulses. Discharges are timed at

1 second intervals and all 1000 strikes are completed in one continuous test run.

The part is then subjected to standard production test to verify that all of the

tested parameters are within spec after the 1000 strikes.

1

Publication Order Number:

January, 2014 − Rev. 4

CM1233/D

CM1233

Figure 1. Electrical Schematic

ESD Protection Architecture

characteristic impedance that helps optimize 100 W load

impedance applications such as the HDMI high speed data

lines.

Conceptually, an ESD protection device performs the

following actions upon an ESD strike discharge into a

protected ASIC (see Figure 2):

NOTE: When each of the channels are used individually

for single−ended signal lines protection, the

1. When an ESD potential is applied to the system

under test (contact or air−discharge), Kirchoff’s

Current Law (KCL) dictates that the Electrical

Overstress (EOS) currents will immediately divide

throughout the circuit, based on the dynamic

impedance of each path.

individual channel provides 50 W characteristic

impedance matching.

The load impedance matching feature of the CM1233

helps to simplify system designer’s PCB layout

considerations in impedance matching and also eliminates

associated passive components.

The route through the architecture enables the CM1233 to

provide matched impedance for the signal path between the

connector and the ASIC. Besides this function, this circuit

arrangement also changes the way the parasitic inductance

interacts with the ESD protection circuit and helps reduce

2. Ideally, the classic shunt ESD clamp will switch

within 1 ns to a low−impedance path and return

the majority of the EOS current to the chassis

shield/reference ground. In actuality, if the ESD

component’s response time (t

than the ASIC it is protecting, or if the Dynamic

Clamping Resistance (R ) is not significantly

) is slower

CLAMP

the I

current to the ASIC.

RESIDUAL

DYN

lower than the ASIC’s I/O cell circuitry, then the

ASIC will have to absorb a large amount of the

EOS energy, and be more likely to fail.

3. Subsequent to the ESD/EOS event, both devices

must immediately return to their original

specifications, and be ready for an additional

strike. Any deterioration in parasitics or clamping

capability should be considered a failure, since it

can then affect signal integrity or subsequent

protection capability. (This is known as

“multi−strike” capability.)

In the CM1233 architecture, the signal line leading the

connector to the ASIC routes through the CM1233 chip

which provides 100 W matched differential channel

Figure 2. Standard ESD Protection Device Block

Diagram

http://onsemi.com

2

CM1233

The Architecture Advantages

leading to the ESD protection element. This limits the speed

that the ESD pulse can discharge through the ESD protection

element.

In the architecture, the inductive elements are in series to

the conduction path leading to the protected device. The

elements actually help to limit the current and voltage

striking the protected device.

Figure 3 illustrates a standard ESD protection device. The

inductor element represents the parasitic inductance arising

from the bond wire and the PCB trace leading to the ESD

protection diodes.

First the reactance of the inductive element, L1, on the

connector side when an ESD strike occurs, acts in the

opposite direction of the ESD striking current. This helps

limit the peak striking voltage. Then the reactance of the

inductive element, L2, on the ASIC side forces this limited

ESD strike current to be shunted through the ESD protection

diodes. At the same time, the voltage drop across both series

element acts to lower the clamping voltage at the protected

device terminal.

Through this arrangement, the inductive elements also

tune the impedance of the ESD protection element by

cancelling the capacitive load presented by the ESD diodes

to the signal line. This improves the signal integrity and

makes the overall ESD protection device more transparent

to the high bandwidth data signals passing through the

channel.

Figure 3. Standard ESD Protection Model

Figure 4 illustrates one of the channels. Similarly, the

inductor elements represent the parasitic inductance arising

from the bond wire and PCB traces leading to the ESD

protection diodes as well.

The innovative architecture turns the disadvantages of the

parasitic inductive elements into useful components that

help to limit the ESD current strike to the protected device

and also improves the signal integrity of the system by

balancing the capacitive loading effects of the ESD diodes.

At the same time, this architecture provides an impedance

matched signal path for 50 W loading applications.

Board designs can take advantage of precision internal

component matching for improved signal integrity, which is

not otherwise possible with discrete components at the

system level. This helps to simplify the PCB layout

considerations by the system designer and eliminates the

associated passive components for load matching that is

normally required with standard ESD protection circuits.

Each ESD channel consists of a pair of diodes in series

which steer the positive or negative ESD current pulse to

either the Zener diode or to ground. This embedded Zener

diode also serves to eliminate the need for a separate bypass

capacitor to absorb positive ESD strikes to ground. The

CM1233 protects against ESD pulses up to 8 kV contact

per the IEC 61000−4−2 standard.

Figure 4. CM1233 ESD Protection Model

CM1233 Inductor Elements

In the CM1233 architecture, the inductor elements and

ESD protection diodes interact differently compared to the

standard ESD model.

In the standard ESD protection device model, the

inductive element presents high impedance against high

slew rate strike voltage, i.e. during an ESD strike. The

impedance increases the resistance of the conduction path

http://onsemi.com

3

CM1233

PIN DESCRIPTIONS

1

Name

In_1+

Description

Bidirectional Clamp to ASIC (inside system)

2

In_1−

3

In_2+

4

In_2−

5

In_3+

6

In_3−

7

In_4+

8

In_4−

9

Out_4−

Out_4+

Out_3−

Out_3+

Out_2−

Out_2+

Out_1−

Out_1+

GND

Bidirectional Clamp to Connector (outside system)

Ground return to shield

10

11

12

13

14

15

16

PAD

http://onsemi.com

4

CM1233

Specifications

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

−40 to +85

−65 to +150

6

Units

°C

Operating Temperature Range

Storage Temperature Range

Breakdown Voltage (Positive)

°C

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 2. ELECTRICAL OPERATING CHARACTERISTICS

(All parameters specified at T = –40°C to +85°C unless otherwise noted.)

A

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

I/O Voltage Relative to GND

−0.5

5.5

IN

I

Continuous Current through signal pins

(IN to OUT) 1000 Hr

100

0.1

mA

I

F

Channel Leakage Current

T = 25°C; V = 5 V

1.0

mA

A

N

V

ESD

ESD Protection − Peak Discharge Voltage

at any channel input, in system:

T = 25°C

A

8

kV

Contact discharge per

IEC 61000−4−2 Standard

I

Residual ESD Peak Current on RDUP

(Resistance of Device Under Protection)

IEC 61000−4−2 8 kV;

3.2

A

V

RES

RDUP = 5 W, T = 25°C;

A

See Figure 7

V

Channel Clamp Voltage

(Channel clamp voltage per

IEC 61000−4−5 Standard)

I

P

= 1 A, T = 25°C,

PP A

CL

t

= 8/20 mS

Positive Transients

Negative Transients

+10

−1.8

R

Dynamic Resistance

Positive Transients

Negative Transients

I

t

= 1 A, T = 25°C,

= 8/20 mS

W

DYN

PP

A

0.9

0.55

P

Zo

Differential Channels pair

characteristic impedance

T

R

T

R

T

R

T

R

= 200 ps

100

W

%

W

%

DZo

Channel−to−Channel Impedance Match

(Differential)

2

Z

Individual Channel Characteristic Imped-

ance in Single−ended Connection

50

2

CHANNEL

DZ

Channel−to−Channel Impedance Match

(Individual)

CHANNEL

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

http://onsemi.com

5

CM1233

Performance Information

Graphical Comparison and Test Setup

Figure 5 shows that the CM1233 (ESD protector) lowers the peak voltage and clamping voltage by 45% across a wide range

of loading conditions in comparison to a standard ESD protection device. Figure 6 also indicates that the DUP/ASIC protected

by the CM1233 dissipates less energy than a standard ESD protection device. This data was derived using the test setups shown

in Figure 7.

V

PEAK

Energy (0−50 ns)

1.2

1.0

0.8

0.6

0.5

0.4

0.3

0.2

STD ESD Device

CM1233

STD ESD Device

CM1233

0.4

0.2

0

0.1

0

5

10

20

5

10

20

RDUP (W)

Figure 5. VPeak (8 KV IEC−61000 4−2 ESD

Figure 6. Energy Dissipated in DUP vs. RDUP*

Contact Strike) and VClamp vs. Loading (RDUP)*

*RDUP is the emulated Dynamic Resistance (load) of the Device Under Protection (DUP). See Figure 7.

IEC 61000−4−2

Test Standards

Voltage

Probe

Voltage

Probe

IEC 61000−4−2

Test Standards

CM1233

Device Under

Protection (DUP)

Device Under

Protection (DUP)

Standard

ESD Device

R

VARIABLE

Current

Probe

Current

Probe

I

RESIDUAL

Standard ESD

Device Test Setup

CM1233 Test Setup

Figure 7. Test Setups: Standard Device (Left) and CM1233 (Right)

http://onsemi.com

6

CM1233

100.0 W

Figure 8. Typical Channel TDR Measured Across Out_x and In_x Per Each

Differential Channels Pair (Typical 200 ps Incident Rise Time)

Application Information

CM1233 Application and Guidelines

As a general rule, the CM1233 ESD protection array should be located as close as possible to the point of entry of expected

electrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal input and the ESD device

to minimize stray series inductance.

Figure 9. Application of Positive ESD Pulse

Between Input Channel and Ground

Additional Information

See also ON Semiconductor Application Note “Design

Considerations for ESD Protection,” in the Applications

section at www.onsemi.com.

Figure 10. Typical PCB Layout

http://onsemi.com

7

CM1233

Ordering Information

PART NUMBERING INFORMATION

Ordering Part Number

(Lead−Free Finish)

Package

WDFN−16

Part Marking

16

CM1233−08DE

CM1233−08

NOTE: Parts are shipped in Tape & Reel form unless otherwise specified.

TAPE AND REEL SPECIFICATIONS ^†

Pocket Size (mm)

Tape Width

W

Reel

Diameter

Qty per

Reel

B X A X K

Part Number

Package Size (mm)

P

0

P

1

0

CM1233

6.00 X 4.00 X 0.75

6.30 X 4.30 X 1.10

12 mm

330 mm (13″)

3000

4 mm 8 mm

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

http://onsemi.com

8

CM1233

PACKAGE DIMENSIONS

WDFN16, 6x4, 0.75P

CASE 511AY−01

ISSUE O

D

A B

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

L1

PIN ONE

DETAIL A

REFERENCE

E

ALTERNATE TERMINAL

CONSTRUCTIONS

2X

0.10

C

MILLIMETERS

DIM MIN

MAX

0.80

0.05

0.10

C

2X

A

A1

A3

b

0.70

0.00

0.20 REF

0.20

6.00 BSC

A3

TOP VIEW

EXPOSED Cu

MOLD CMPD

0.30

(A3)

DETAIL B

D

A

C

0.10

0.08

C

D2

E

E2

e

K

L

5.05

4.00 BSC

1.75

0.75 BSC

0.70 REF

0.35 0.45

−−− 0.15

5.15

A1

1.85

DETAIL B

ALTERNATE

CONSTRUCTIONS

NOTE 4

SEATING

PLANE

A1

SIDE VIEW

D2

L1

DETAIL A

L

16X

1

8

RECOMMENDED

SOLDERING FOOTPRINT*

E2

16X

5.26

0.63

16

9

K

16X b

e

0.10

C

A B

e/2

0.05

NOTE 3

4.30

BOTTOM VIEW

1.96

16X

0.32

0.75

PITCH

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CM1233/D

http://onsemi.com

9


型号：	CM1235_14
厂家：	ONSEMI
描述：	Small Footprint ESD Clamp Array for High Speed Data Line Protection
文件：	总9页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CM1235_14 [ONSEMI]

相关型号：

CM1236

CM1236-08DE

CM1240

CM1240

CM1240-04D4

CM1240-04DE

CM1240-F4SE

CM1240-F4SE

CM1241

CM1241-04D4

CM1241-04D4

CM1242-07CP