MSM9201-01 [OKI]
Fluorescent Display Tube Controller Driver; 荧光显示管控制器驱动程序型号: | MSM9201-01 |
厂家: | OKI ELECTRONIC COMPONETS |
描述: | Fluorescent Display Tube Controller Driver |
文件: | 总35页 (文件大小:354K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PEDL9201-03
This version: Sep. 2000
Previous version: Nov. 1997
¡ Semiconductor
MSM9201-01
Fluorescent Display Tube Controller Driver
GENERAL DESCRIPTION
The MSM9201-01 is a dot matrix fluorescent display tube controller driver IC which displays
characters, numerics and symbols.
Dot matrix fluorescent display tube drive signals are generated by serial data sent from a micro-
controller. A display system is easily realized by internal ROM and RAM for character display.
FEATURES
• Logic power supply (V
)
: 3.3 V±10%/5.0 V±10%
: 3.3 V±10%/5.0 V±10%
: –20 to –60 V
DD
• Fluorescent display tube drive power supply (V
• Fluorescent display tube drive power supply (V
• VFD driver output current
)
DISP
)
FL
(VFD driver output can directly be connected to the fluorescent display tube. No pull-down
resistor is required.)
- Segment driver (SEG1 to SEG35)
- Segment driver (AD1 to AD8)
- Grid driver (COM1 to COM16)
• General output port output current
- Output driver (P1-4)
: –5.0 mA (V =–60V)
FL
: –10.0 mA (V =–60V)
FL
: –20.0 mA (V =–60V)
FL
: ±1.0 mA (V =3.3V±10%)
DD
±2.0 mA (V =5.0V±10%)
DD
• Content of display
- CGROM
- CGRAM
- ADRAM
- DCRAM
- General output port
• Display control function
- Display digit
5¥7 dots, 240 types
(character data)
(character data)
5¥7 dots, 16 types
24 (display digit) ¥4 bits (symbol data)
24 (display digit) ¥8 bits (register for character data display)
4 bits (static mode)
: 9 to 24 digits
- Display duty (contrast adjustment)
- All lights ON/OFF
: 8 stages
• 3 interfaces with microcontroller
• 1-byte instruction execution (excluding data write to RAM)
: DA, CS, CP (4 interfaces if RESET is added)
• Built-in oscillation circuit (external C and R)
• Package options:
80-pin plastic QFP (QFP80-P-1414-0.65-K) (Product name: MSM9201-01GS-K)
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM9201-01GS-BK)
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BLOCK DIAGRAM
VDISP
VDD
GND
VFL
SEG1
DCRAM
CGROM
24w¥8b
240w¥35b
Segment
Driver
CGRAM
RESET
16w¥35b
SEG35
AD1
DA
CP
CS
8-bit
ADRAM
24w¥8b
Shift
AD
Driver
Register
DCRAM
Address
Counter
AD4
Address
Selector
Command
Decoder
Write
Address
Counter
Read
Address
Counter
P1
Port
Driver
Control
Circuit
P4
COM1
Digit
Control
Grid
Driver
Duty
Control
COM24
Timing
Timing
Generator 1
Generator 2
OSC0
OSC1
Oscillator
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INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits
Input pin
VDD
VDD
INPUT
GND
GND
Output pin
VDD
VDD
OUTPUT
GND
GND
Schematic Diagram of Driver Output Circuit
VDISP
VDISP
OUTPUT
VFL
VFL
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PIN CONFIGURATION (TOP VIEW)
60 COM22
AD3
AD4
1
2
3
4
5
6
7
8
9
59 COM21
58 COM20
57 COM19
56 COM18
55 COM17
54 COM16
53 COM15
52 COM14
51 COM13
50 COM12
49 COM11
48 COM10
47 COM9
46 COM8
45 COM7
44 COM6
43 COM5
42 COM4
41 COM3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8 10
SEG9 11
SEG10 12
SEG11 13
SEG12 14
SEG13 15
SEG14 16
SEG15 17
SEG16 18
SEG17 19
SEG18 20
NC: No connection
80-Pin Plastic QFP
(QFP80-P-1414-0.65-K)
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64
63
62
61
1
AD1
AD2
AD3
COM24
2
COM23
COM22
COM21
3
4
AD4
5
60 COM20
59
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
6
COM19
7
58 COM18
57
8
COM17
9
56 COM16
55
COM15
54 COM14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
53
COM13
52
COM12
51 COM11
50
49
48
47
COM10
COM9
COM8
COM7
46 COM6
45
COM5
44
COM4
43
COM3
42
COM2
41
COM1
NC: No connection
80-Pin Plastic QFP
(QFP80-P-1420-0.80-BK)
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PIN DESCRIPTIONS
Pin
Symbol Type Connects to:
Description
QFP-1* QFP-2*
Fluorescent Fluorescent display tube anode electrode drive output.
tube anode Directly connected to fluorescent display tube. No pull-down
electrode resistor is required. IOH>–5.0 mA
3-27
5-39 SEG1-35
O
O
O
O
Fluorescent Fluorescent display tube grid electrode drive output.
tube grid
Directly connected to fluorescent display tube. No pull-down
39-62
41-64 COM1-24
electrode resistor is required. IOH>–20.0 mA
Fluorescent Fluorescent display tube anode electrode drive output.
tube anode Directly connected to fluorescent display tube. No pull-down
electrode resistor is required. IOH>–10.0 mA
1, 2, 79, 80 1-4
AD1-4
LED drive General port output.
72-75
74-77
73
P1-4
VDD
control
Output of these pins in static operation, so these pins can drive
terminals the LED. IOH>–2.0 mA
71
—
—
—
—
Power
supply
VDD-GND are power supplies for internal logic.
VDISP-VFL are power supplies for driving fluorescent tubes.
38, 78
64
40, 80 VDISP1-2
Use the same power supply for VDD and VDISP
.
66
GND
63, 76
65, 78
VFL1-2
Micro-
Serial data input (positive logic).
70
69
68
72
71
70
DA
CP
CS
I
I
I
controller Input from LSB.
Micro- Shift clock input.
controller Serial data is shifted on the rising edge of CP.
Micro- Chip select input.
controller Setting this pin to "H" disables serial data transfer.
*
QFP-1 : QFP80-P-1414-0.65-K
QFP-2 : QFP80-P-1420-0.80-BK
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Pin
Symbol Type Connects to:
Description
QFP-1* QFP-2*
Reset input.
Setting this pin to "Low" initializes all the functions.
The initial status is as follows.
• Address of each RAM
• Data of each RAM
• Number of display digits
• Contrast adjusment
• All lights ON or OFF
• All outputs
address "00"H
Content is undefined
24 digits
Micro-
controller
or
8/16
67
69
RESET
I
OFF mode
C2, R2
"Low" level
RESET
(Circuit when R and C are
connected externally)
See Application Circuit.
C2
R2
External RC pin for RC oscillation.
Connect R and C externally. The RC time constant depends on the
VDD voltage used. Set the target oscillation frequency to 2 MHz.
65
66
67
68
OSC0
OSC1
I
C1, R1
OSC0
OSC1
(RC oscillation circuit)
See Application Circuit.
R1
O
C1
*
QFP-1 : QFP80-P-1414-0.65-K
QFP-2 : QFP80-P-1420-0.80-BK
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ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage 1
Symbol
VDD
Condition
Rating
Unit
(*1)
–0.3 to +6.5
–0.3 to +6.5
–80 to VDISP+0.3
–80 to VDD+0.3
565
V
V
V
V
VDISP
VFL
(*1)
Supply Voltage 2
Input Voltage
—
VIN
—
QFP80-P-1414-0.65-K
QFP80-P-1420-0.80-BK
—
Power Dissipation
PD
Ta£25°C
mW
°C
643
Storage Temperature
TSTG
IO1
–55 to +150
–30 to 0.0
–20 to 0.0
–10 to 0.0
–4.0 to +4.0
COM1-COM24
AD1-AD4
IO2
Output Current
mA
IO3
SEG1-SEG35
P1-P4
IO4
*1 Use the same power supply for V and V
.
DISP
DD
RECOMMENDED OPERATING CONDITIONS (1)
When the power supply voltage is 5V (typ)
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
VFL
Condition
Min.
4.5
Typ.
Max.
Unit
—
—
5.0
5.5
V
Supply Voltage 2
–60
—
—
–20
—
V
V
High Level Input Voltage
Low Level Input Voltage
CP Frequency
VIH
All input pins excluding OSC0 pin 0.7VDD
VIL
All input pins excluding OSC0 pin
—
—
—
0.3VDD
1.0
V
fC
—
R=3.3kW, C=47pF
DIGIT=1-24, R=3.3kW, C=47pF
—
—
MHz
MHz
Hz
Oscillation Frequency
Frame Frequency
fOSC
fFR
1.5
122
–40
2.0
163
—
2.5
204
85
Operating Temperature
Top
°C
RECOMMENDED OPERATING CONDITIONS (2)
When the power supply voltage is 3.3V (typ)
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
VFL
Condition
Min.
3.0
Typ.
Max.
Unit
—
—
3.3
3.6
V
Supply Voltage 2
–60
—
—
–20
—
V
V
High Level Input Voltage
Low Level Input Voltage
CP Frequency
VIH
All input pins excluding OSC0 pin 0.8VDD
VIL
All input pins excluding OSC0 pin
—
—
—
0.2VDD
1.0
V
fC
—
R=3.3kW, C=39pF
DIGIT=1–24, R=3.3kW, C=39pF
—
—
MHz
MHz
Hz
Oscillation Frequency
Frame Frequency
fOSC
fFR
1.5
122
–40
2.0
163
—
2.5
204
85
Operating Temperature
Top
°C
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¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD=VDISP=5.0V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
CS, CP,
Condition
Min.
Max.
Unit
High Level Input Voltage
—
0.7VDD
—
V
VIH
DA, RESET
CS, CP,
Low Level Input Voltage
High Level Input Current
Low Level Input Current
—
—
0.3VDD
1.0
V
VIL
IIH
IIL
DA, RESET
CS, CP,
VIH=VDD
VIL=0.0V
–1.0
–1.0
µA
µA
DA, RESET
CS, CP,
1.0
DA, RESET
COM1-24
AD1-4
VOH1
VOH2
VOH3
VOH4
IOH1=–20.0mA
IOH2=–10.0mA
IOH3=–5.0mA
IOH4=–2.0mA
VDISP–1.5
VDISP–1.5
VDISP–1.5
VDD–1.0
—
—
—
—
V
V
V
V
High Level Output
Voltage
SEG1-35
P1-4
COM1-24
AD1-4
Low Level Output
Voltage
VOL1
VOL2
IDD1
—
—
—
—
VFL+1.0
V
V
SEG1-35
P1-4
I
OL1=2mA
1.0
4
Duty=15/16
Digit=1–24
mA
fOSC
=
All outputs go ON
Duty=8/16
2MHz,
VDD, VDISP
Supply Current
no load
Digit=1–9
IDD2
—
3
mA
All outputs go OFF
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¡ Semiconductor
DC Characteristics (2)
(VDD=VDISP=3.3V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
CS, CP,
Condition
Min.
Max.
Unit
High Level Input Voltage
—
0.8VDD
—
V
VIH
VIL
IIH
IIL
DA, RESET
CS, CP,
Low Level Input Voltage
High Level Input Current
Low Level Input Current
—
—
0.2VDD
1.0
V
DA, RESET
CS, CP,
VIH=VDD
VIL=0.0V
–1.0
–1.0
µA
µA
DA, RESET
CS, CP,
1.0
DA, RESET
COM1-24
AD1-4
VOH1
VOH2
VOH3
VOH4
IOH1=–20.0mA
IOH2=–10.0mA
IOH3=–5.0mA
IOH4=–1.0mA
VDISP–1.5
VDISP–1.5
VDISP–1.5
VDD–1.0
—
—
—
—
V
V
V
V
High Level Output
Voltage
SEG1-35
P1-4
COM1-24
AD1-4
Low Level Output
Voltage
VOL1
VOL2
IDD1
—
—
—
—
VFL+1.0
V
V
SEG1-35
P1-4
I
OL1=2mA
1.0
3
Duty=15/16
Digit=1–24
mA
fOSC
=
All outputs go ON
Duty=8/16
2MHz,
VDD, VDISP
Supply Current
no load
Digit=1–9
IDD2
—
2
mA
All outputs go OFF
10/35
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¡ Semiconductor
AC Characteristics (1)
(VDD, VDISP=5.0V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
CP Pulse Width
DA Setup Time
DA Hold Time
tCW
—
300
300
300
300
16
tDS
—
—
ns
tDH
—
—
ns
CS Setup Time
CS Hold Time
tCSS
tCSH
tCSW
tDOFF
tWRES
tRSOFF
tR
—
—
ns
R1=3.3kW, C1=47pF
—
ms
ns
CS Wait Time
—
R1=3.3kW, C1=47pF
When RESET signal is input externally
—
300
8
—
Data Processing Time
RESET Pulse Width
DA Wait Time
—
ms
ns
300
300
—
—
—
ms
ms
ms
ms
ms
4.0
4.0
100
—
tR=20ꢀ to 80ꢀ
Cl=100pF
Slew Rate (All Drivers)
tF
—
tF=80ꢀ to 20ꢀ
VDD Rise Time
VDD Off Time
tPRZ
tPOF
When mounted on the unit
—
When mounted on the unit, VDD=0.0V
5.0
AC Characteristics (2)
(VDD, VDISP=3.3V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
CP Pulse Width
DA Setup Time
DA Hold Time
tCW
—
300
300
300
300
16
tDS
—
—
ns
tDH
—
—
ns
CS Setup Time
CS Hold Time
tCSS
tCSH
tCSW
tDOFF
tWRES
tRSOFF
tR
—
—
ns
R1=3.3kW, C1=39pF
—
ms
ns
CS Wait Time
—
R1=3.3kW, C1=39pF
When RESET signal is input externally
—
300
8
—
Data Processing Time
RESET Pulse Width
DA Wait Time
—
ms
ns
300
300
—
—
—
ms
ms
ms
ms
ms
4.0
4.0
100
—
tR=20ꢀ to 80ꢀ
Cl=100pF
Slew Rate (All Drivers)
tF
—
tF=80ꢀ to 20ꢀ
VDD Rise Time
VDD Off Time
tPRZ
tPOF
When mounted on the unit
—
When mounted on the unit, VDD=0.0V
5.0
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¡ Semiconductor
TIMING DIAGRAM
Symbol
VDD=3.3V 1ꢀ0
0.8 VDD
VDD=5.ꢀV 1ꢀ0
0.7 VDD
VIH
VIL
0.2 VDD
0.3 VDD
• Data Timing
tCSS
tCSW
0.7 VDD
0.3 VDD
CS
CP
DA
tCSH
fC
VIH
VIL
tCW tCW
tDOFF
tDH
tDS
VIH
VIL
VALID VALID
VALID VALID
• Reset Timing
0.8 VDD
0.0 V
tPRZ
VDD
tRSON
When input externally
tWRES
VIH
VIL
RESET
DA
tRSOFF
When external
VIH
VIL
R and C are
connected.
• Output Timing
tR
tF
0.8 VDISP
0.2 VFL
All outputs
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¡ Semiconductor
Digit Output Timing (for 24-digit display, at a duty of 15/16)
T=8/ fOSC
Frame cycle
Display timing
Blank timing
t1=1536T (t1=6.144 ms when fosc=2.0 MHz)
t2=60T (t2=240 ms when fosc=2.0 MHz)
VDISP
VFL
t3=4T
(t3=16 ms when fosc=2.0 MHz)
COM1
COM2
COM3
COM4
COM5
COM6
COM19
COM20
COM21
COM22
COM23
COM24
AD1-4
SEG1-35
VDISP
VFL
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FUNCTIONAL DESCRIPTION
Command List
1st byte
2nd byte
LSB
MSB LSB
MSB
Command
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
1
2
DCRAM data write
X0 X1 X2 X3 X4
1
0
0
C0 C1 C2 C3 C4 C5 C6 C7
C0 C5 C10 C15 C20 C25 C30
2nd byte
3rd byte
4th byte
5th byte
6th byte
*
*
*
*
*
*
C1 C6 C11 C16 C21 C26 C31
CGRAM data write 1
X0 X1 X2 X3
0
1
0
C2 C7 C12 C17 C22 C27 C32
*
C3 C8 C13 C18 C23 C28 C33
C4 C9 C14 C19 C24 C29 C34
3
4
5
6
7
ADRAM data write
General output port set
Display duty set
X0 X1 X2 X3 X4
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
C1 C2 C3
C0
*
*
*
P1 P2 P3 P4
*
: Don't care
Xn : Address specification for each RAM
*
D0 D1 D2
*
*
*
*
Number of display digits set
All lights ON/OFF
Test mode
K0 K1 K2 K3
Cn : Character code specification for each RAM
Pn : General output port status specification
Dn : Display duty specification
L
H
*
*
Kn : Number of display digits specification
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously,
addresses are internally incremented automatically.
H
L
: All lights ON instruction
: All lights OFF instruction
Therefore it is not necessary to specify the 1st byte when RAM data
for the 2nd and later bytes is written.
Note: The test mode is used for inspection before shipment.
It is not a user function.
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Positional Relationship Between SEGn and ADn (one digit)
C0 AD1
C1 AD2
C2 AD3
C3 AD4
ADRAM written data.
Corresponds to 2nd byte
C0
C1
C2
C3
C4
SEG1 SEG2 SEG3 SEG4 SEG5
C5 C6 C7 C8 C9
SEG6 SEG7 SEG8 SEG9 SEG10
C10
C11
C12
C13
C14
SEG11 SEG12
SEG13
SEG14
SEG15
C15
C16
C17
C18
C19
SEG16
SEG17
SEG18
SEG19
SEG20
C20
C21
C22
C23
C24
SEG21 SEG22 SEG23 SEG24 SEG25
C25
C26
C27
C28
C29
SEG26
SEG27
SEG28
SEG29
SEG30
C30
C31
C32
C33
C34
SEG31 SEG32 SEG33 SEG34 SEG35
CGRAM data write mode. Corresponds to 2nd byte
CGRAM data write mode. Corresponds to 3rd byte
CGRAM data write mode. Corresponds to 4th byte
CGRAM data write mode. Corresponds to 6th byte
CGRAM data write mode. Corresponds to 5th byte
15/35
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¡ Semiconductor
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rise of the shift clock, which
is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated
and data is written to each register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin
changes from "High" to "Low" is recognized in 8-bit units.
tDOFF
tCSH
CS
CP
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
DA
1st byte
2nd byte
2nd byte
Character code data of the
next address
When data is written to DCRAM* Command and address data
Character code data
*
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later
bytes.
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) which
initializes all functions.
The initial status is as follows.
• Address of each RAM .................. address "00"H
• Data of each RAM ........................ All contents are undefined
• General output port ..................... All general output ports go "Low"
• Number of display digits ............ 24 digits
• Contrast adjustment..................... 8/16
• All display lights ON or OFF ..... OFF mode
• Segment output ............................ All segment outputs go "Low"
• AD output ..................................... All AD outputs go "Low"
After reset is executed, perform settings again according to "Initial Setting Flowchart" shown
later.
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Description of Commands and Functions
1. DCRAM data write
(Specifies the address (00H to 1FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
DCRAM (Data Control RAM) has 5-bit addresses to store character code of CGROM and
CGRAM.
The character code specified in DCRAM is converted to a 5¥7 dot matrix character pattern via
CGROM or CGRAM.
The DCRAM can store 24 characters.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3 X4
1
0
0
: selects DCRAM data write mode and specifies DCRAM
address.
(Ex: Specifies DCRAM address 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(2nd)
: specifies character code of CGROM and CGRAM.
(written into DCRAM address 00H)
To specify the character code of CGROM and CGRAM continuously to the next address, specify
only character codes as follows.
Since the addresses of DCRAM are automatically incremented, they do not need to be specified.
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM.
(written into DCRAM address 01H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(4th)
: specifies character code of CGROM and CGRAM.
(written into DCRAM address 02H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(25th)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM.
(written into DCRAM address 17H)
Setting of CGROM and CGRAM character codes for up to 24 digits is now complete.
To further specify character codes continuously from DCRAM address 00H, dummy character
codes must be specified for DCRAM address 18H to 1FH (so that DCRAM address will be
incremented automatically and will be reset to 00H).
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(26th)
: specifies dummy character code of CGROM and CGRAM.
(not written into DCRAM address)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(33th)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies dummy character code of CGROM and CGRAM.
(not written into DCRAM address)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(34th)
: specifies character code of CGROM and CGRAM.
(rewritten into DCRAM address 00H)
X0 (LSB) to X4 (MSB): DCRAM address (5 bits: 24 characters)
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters)
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[COM positions and set DCRAM address]
HEX Xꢀ X1 X2 X3 X4
HEX Xꢀ X1 X2 X3 X4
COM position
COM1
COM position
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
—
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
—
—
—
—
—
—
—
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2. CGRAM data write
(Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has 4-bit addresses to store 5¥7 dot matrix character
patterns.
A character pattern stored in CGRAM can be displayed by specifying the character code
(address) in DCRAM.
The addresses of CGRAM are assigned to 00H to 0FH. (All the other addresses are the
CGROM addresses.)
(The CGRAM can store 16 types of character patterns.)
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
: selects CGRAM data write mode and specifies
CGRAM address.
X0 X1 X2 X3
0
1
0
*
(Ex: specifies CGRAM address 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
: specifies 1st column data.
(written into CGRAM address 00H)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
: specifies 2nd column data.
(written into CGRAM address 00H)
C1 C6 C11 C16 C21 C26 C31
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte
(4th)
: specifies 3rd column data.
(written into CGRAM address 00H)
C2 C7 C12 C17 C22 C27 C32
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
5th byte
(5th)
: specifies 4th column data.
(written into CGRAM address 00H)
C3 C8 C13 C18 C23 C28 C33
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
: specifies 5th column data.
(written into CGRAM address 00H)
C4 C9 C14 C19 C24 C29 C34
*
Tospecifycharacterpatterndatacontinuouslytothenextaddress, specifyonlycharacterpattern
data as follows.
Since the addresses of CGRAM are automatically incremented, they do not need to be specified.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient
for t
time between bytes.
DOFF
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
:
specifies 1st column data.
(written into CGRAM address 01H)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
:
:
specifies 5th column data.
(written into CGRAM address 01H)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
specifies 1st column data.
(written into CGRAM address 02H)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
:
:
specifies 5th column data.
(written into CGRAM address 02H)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
specifies 1st column data.
(written into CGRAM address 0FH)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81th)
:
:
specifies 5th column data.
(written into CGRAM address 0FH)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82th)
specifies 1st column data.
(rewritten into CGRAM address 00H.)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
:
specifies 5th column data.
(rewritten into CGRAM address 00H.)
C4 C9 C14 C19 C24 C29 C34
*
X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters)
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)
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[CGROM addresses and set CGRAM addresses]
Refer to ROM CODE
HEX Xꢀ X1 X2 X3
CGROM address
RAM00(00000000B)
RAM01(00000001B)
RAM02(00000010B)
RAM03(00000011B)
RAM04(00000100B)
RAM05(00000101B)
RAM06(00000110B)
RAM07(00000111B)
HEX Xꢀ X1 X2 X3
CGROM address
00
01
02
03
04
05
06
07
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
08
09
0A
0B
0C
0D
0E
0F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
RAM08(00001000B)
RAM09(00001001B)
RAM0A(00001010B)
RAM0B(00001011B)
RAM0C(00001100B)
RAM0D(00001101B)
RAM0E(00001110B)
RAM0F(00001111B)
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Positional relationship between the output area of CGROM and that of CGRAM
C0
C5
C1
C6
C2
C7
C3
C8
C4
C9
C10 C11 C12 C13 C14
C15 C16 C17 C18 C19
C20 C21 C22 C23 C24
C25 C26 C27 C28 C29
C30 C31 C32 C33 C34
Corresponds to 2nd byte (1st column)
Corresponds to 3rd byte (2nd column)
Corresponds to 6th byte (5th column)
Corresponds to 5th byte (4th column)
Corresponds to 4th byte (3rd column)
Note: CGROM (Character Generator ROM) has 8-bit addresses to generate 5¥7 dot matrix
character patterns.
CGRAM can store 240 types opf character patterns.
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3. ADRAM data write
(specifies address of ADRAM and writes symbol data)
ADRAM (Additional Data RAM) has 4-bit addresses to store symbol data.
Symbol data specified in ADRAM is directly output without CGROM and CGRAM.
(The DRAM can store 4 types of symbol patterns for each digit.)
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
: selects ADRAM data write mode and specifies ADRAM
address.
X0 X1 X2 X3 X4
1
1
0
(Ex: specifies ADRAM address 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3
2nd byte
(2nd)
: specifies symbol data.
(written into ADRAM address 00H)
*
*
*
*
To specify symbol data continuously to the next address, specify only symbol data as follows.
The addresses of ADRAM are automatically incremented. Specification of ADRAM addresses
is therefore unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
: specifies symbol data.
(written into ADRAM address 01H)
C0 C1 C2 C3
*
*
*
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
: specifies symbol data.
(written into ADRAM address 02H)
C0 C1 C2 C3
*
*
*
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3
2nd byte
(17th)
: specifies symbol data.
(written into ADRAM address 17FH)
*
*
*
*
Setting of symbol data for up to 24 digits is now complete.
To further specify symbol data continuously from DCRAM address 00H, dummy symbol data
must be specified for ADRAM addresses 18H to 1FH (so that the ADRAM address will be
incremented automatically and will be reset to 00H).
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(18th)
: specifies dummy symbol data.
(not written into ADRAM address)
C0 C1 C2 C3
*
*
*
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(65th)
: specifies dummy symbol data.
(not written into ADRAM address)
C0 C1 C2 C3
*
*
*
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(66th)
: specifies symbol data.
(rewritten into ADRAM address 00H.)
X0 (LSB) to X4 (MSB): ADRAM addresses (5 bits: 24 characters)
C0 (LSB) to C3 (MSB): Symbol data (4 bits: 4-symbol data per digit)
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[COM positions and ADRAM addresses]
HEX Xꢀ X1 X2 X3 X4 COM position HEX Xꢀ X1 X2 X3 X4 COM position
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
—
—
—
—
—
—
—
—
4. General output port set
(specifies the general output port status)
The general output port is an output for 4-bit static operation.
It is used to control other I/O devices and turn on LED. (Static operation.)
Thefluorescentdisplaytubecannotbedrivenbythisoutputport,becausewhenatthe"High"
level this output becomes the VDD voltage and when at the "Low" level it becomes the ground
potential.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
P1 P2 P3 P4
1st byte
: selects general output port and specifies
the output status.
*
0
0
1
P1-P4 : general output ports
* : don't care
[Set data and set state of general output port]
Pn
0
Display state of general output port
Sets P1-P4 to Low
(The state when power is applied or when RESET is input)
1
Sets P1-P4 to High
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5. Display duty set
(writes display duty value to duty cycle register)
Display duty adjusts contrast in 8 stages using 3-bit data.
At the time power is turned on or the RESET signal is input, the duty cycle register value is
"0". Always execute this instruction before turning the display on, then set a desired duty
value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
D0 D1 D2
1st byte
: selects display duty set mode and sets duty value.
*
*
1
0
1
D0 (LSB) to D2 (MSB) : display duty data (3 bits: 8 stages)
* : don't care
[Relation between setup data and controlled COM duty]
HEX
0
D2 D1 D0
COM duty
8/16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(The state at the time power is turned on or RESET
signal is input)
1
9/16
2
10/16
11/16
12/16
13/16
14/16
15/16
3
4
5
6
7
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6. Number of display digits set
(writes the number of display digits to the display digit register)
The number of display digits set can display 9 to 24 digits using 4-bit data.
At the time power is turned on or a RESET signal is input, the display digit register value is
"0". Alwaysexecutethisinstructiontochangethenumberofdigitsbeforeturningthedispaly
on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
K0 K1 K2 K3
1st byte
: selects the number of display digits set mode and specifies
the number of digits value.
*
0
1
1
K0 (LSB) to K3 (MSB): number of display digits data (4 bits: 16 digits)
[Relation between setup data and controlled COM]
Number of digits
Number of digits
of COM
HEX Kꢀ K1 K2 K3
HEX Kꢀ K1 K2 K3
of COM
COM1-24
COM1-9
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
COM1-16
COM1-17
COM1-10
COM1-11
COM1-12
COM1-13
COM1-14
COM1-15
COM1-18
COM1-19
COM1-20
COM1-21
COM1-22
COM1-23
The state at the time power is turned on or RESET signal is input
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7. All display lights ON/OFF set
(Turns all display lights ON or OFF)
The all display lights ON mode is used primarily for display testing.
The all display lights OFF mode is primarily used to prevent malfunction on power-up.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
: selects all display lights ON or OFF mode.
L
H
1
1
1
* * *
[Set data and display state of SEG and AD]
L
0
1
0
1
H
0
0
1
1
Display state of SEG and AD
All outputs maintain current states
Sets all outputs to Low
(The state at the time power is applied or RESET is input)
Sets all outputs to High
Sets all outputs to High
(All lights ON mode has priority.)
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Initial Setting Flowchart
Start
Apply VDD
Power is applied or RESET is input
Apply VFL
All display lights OFF
Status of all outputs by RESET
signal input
Specify number of
display digits
Specify display duty
Select a RAM to be used
DCRAM
CGRAM
ADRAM
Data write mode
(with address set)
Data write mode
(with address set)
Data write mode
(with address set)
Address is automatically
incremented
Address is automatically
incremented
Address is automatically
incremented
DCRAM
CGRAM
ADRAM
Character code
Character code
Character code
DCRAM
Is character code
write ended?
CGRAM
Is character code
write ended?
ADRAM
Is character code
write ended?
NO
NO
NO
YES
YES
YES
YES
Another RAM to
be set?
NO
Specify general output
port status
Release all display lights
OFF mode
Normal operation status (display ON)
End
29/35
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¡ Semiconductor
APPLICATION CIRCUIT
Heater transformer
5¥7-dot matrix fluorescent display tube
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (DIGIT)
VDD
VDD
4
35
24
R2
C2
VDD
VDD
VDISP1-2
,
AD1-4
SEG1-35 COM1-24
RESET
R4
LED
VDD
C3
Micro-
controller
Output Port
MSM9201-01
CS
CP
DA
4
P1-2
NPN Tr
GND
GND
GND VFL1-2
OSC0 OSC1
R1
GND
C1
R3
GND
VFL
C4
ZD
Notes: 1. The V value depends on the power supply voltage of the microcontroller used.
DD
Adjust the values of the constants R , R , R , C , and C to the power supply voltage
1
2
4
1
2
used.
2. The V value depends on the fluorescent display tube used. Adjust the values of the
FL
constants R and ZD to the power supply voltage used.
3
30/35
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¡ Semiconductor
Reference data
The figure below shows the relationship between the V voltage and the output current of each
FL
driver.
Take care that the total power consumption to be used does not exceed the power dissipation.
VFL Voltage vs. Output Current of Each Driver
–30
–25
–20
–15
–10
–5
COM1 to COM24
(Condition: VOH=VDISP–1.5 V)
AD1 to AD4
(Condition: VOH=VDISP–1.5 V)
SEG1 to SEG35
(Condition: VOH=VDISP–1.5 V)
0
–10
–20
–30
–40
–50
–60 (V)
VFL Voltage (VDD-n
)
31/35
PEDL9201-03
MSM9201-01
¡ Semiconductor
MSM9201-01 ROM CODE
00000000B (00H) to 00001111B (0FH) are the CGRAM addresses.
MSB
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LSB
0000 RAM0
0001 RAM1
0010 RAM2
0011 RAM3
0100 RAM4
0101 RAM5
0110 RAM6
0111 RAM7
1000 RAM8
1001 RAM9
1010 RAMA
1011 RAMB
1100 RAMC
1101 RAMD
1110 RAME
1111 RAMF
32/35
PEDL9201-03
MSM9201-01
¡ Semiconductor
PACKAGE DIMENSIONS
QFP80-P-1414-0.65-K
(Unit : mm)
.
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.85 TYP.
3/Nov. 28, 1996
Oki Electric Industry Co., Ltd.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
33/35
PEDL9201-03
MSM9201-01
¡ Semiconductor
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.27 TYP.
4/Nov. 28, 1996
Oki Electric Industry Co., Ltd.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
34/35
PEDL9201-03
MSM9201-01
¡ Semiconductor
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
35/35
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