MSM9200-XX [OKI]
5 X 7 Dot Character X 16-Digit Display Controller/Driver with Character RAM; 5× 7点阵字符x 16位数字显示控制器/驱动器，带有字符RAM
| 型号： | MSM9200-XX |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 5 X 7 Dot Character X 16-Digit Display Controller/Driver with Character RAM |
| 文件： | 总34页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2C0035-27-Y4
This version: Nov. 1997
Previous version: Jul. 1996
¡ Semiconductor
MSM9200-xx
5 ¥ 7 Dot Character ¥ 16-Digit Display Controller/Driver with Character RAM
GENERAL DESCRIPTION
The MSM9200-xx is a dot matrix vacuum fluorescent display tube controller driver IC which
displays characters, numerics and symbols.
Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from
a microcontroller. A display system is easily realized by internal ROM and RAM for character
display.
The MSM9200-xx has low power consumption because it is munufactured in CMOS process
technology.
-01 and -02 are available as general codes.
Custom codes are provided if necessary.
FEATURES
• Logic power supply (V
)
: 3.3 V±10%/5.0 V±10%
: 3.3 V±10%/5.0 V±10%
: –20 to –60 V
DD
• Fluorescent display tube drive power supply (V
• Fluorescent display tube drive power supply (V
• VFD driver output current
)
DISP
)
FL
(VFD driver output can directly be connected to the fluorescent display tube. No pull-down
resistor is required.)
- Segment driver (SEG1 to SEG35)
- Segment driver (AD1 to AD8)
- Grid driver (COM1 to COM16)
• General output port output current
- Output driver (P1-4)
: –5 mA
: –10 mA
: –30 mA
(V =–60V)
FL
(V =–60V)
FL
(V =–60V)
FL
: ±1 mA (V =3.3V±10%)
DD
±2 mA (V =5.0V±10%)
DD
• Content of display
- CGROM
- CGRAM
- ADRAM
- DCRAM
- General output port
• Display control function
- Display digit
5¥7 dots, 224 types
(character data)
(character data)
5¥7 dots, 32 types
16 (display digit) ¥8 bits (symbol data)
64 (stored digit) ¥8 bits (register for character data display)
4 bits (static mode)
: 1 to 16 digits
- Display duty (contrast adjustment)
: 16 stages
- Display blink position specification : Blinking time is input externally
- Display shift (left and right)
- All lights ON/OFF
: Can be set only for SEG output
• 4 interfaces with microcontroller
: DA, CS, CP, and BLINK (5 interfaces when RESET is
added)
• 1 byte instruction execution (excluding data write to RAM and display blink position
specification)
• Oscillation circuit included (external C and R)
• Package:
80-pin plastic QFP (QFP80-P-1414-0.65-K)
(Product name: MSM9200-xxGS-K)
xx indicated the code number.
1/34
¡ Semiconductor
MSM9200-xx
BLOCK DIAGRAM
VDISP
VDD
GND
VFL
BLINK
SEG1
DCRAM
CGROM
64w¥8b
224w¥35b
Segment
Driver
CGRAM
RESET
32w¥35b
SEG35
AD1
DA
CP
CS
8-bit
ADRAM
16w¥8b
Shift
AD
Driver
Register
DCRAM
Address
Counter
AD8
Address
Selector
Command
Decoder
Write
Address
Counter
Read
Address
Counter
P1
Port
Driver
Control
Circuit
P4
COM1
Digit
Control
Grid
Driver
Duty
Control
COM16
Timing
Timing
Generator 1
Generator 2
OSC0
OSC1
Oscillator
2/34
¡ Semiconductor
MSM9200-xx
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits
Input Pin
VDD
VDD
INPUT
GND
GND
Output Pin
VDD
VDD
OUTPUT
GND
GND
Schematic Diagram of Driver Output Circuit
VDISP
VDISP
OUTPUT
VFL
VFL
3/34
¡ Semiconductor
MSM9200-xx
PIN CONFIGURATION (TOP VIEW)
60 COM16
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
VDISP1
SEG1 10
SEG2 11
SEG3 12
SEG4 13
SEG5 14
SEG6 15
SEG7 16
SEG8 17
SEG9 18
SEG10 19
SEG11 20
1
2
3
4
5
6
7
8
9
59 COM15
58 COM14
57 COM13
56 COM12
55 COM11
54 COM10
53 COM9
52 COM8
51 COM7
50 COM6
49 COM5
48 COM4
47 COM3
46 COM2
45 COM1
44 SEG35
43 SEG34
42 SEG33
41 SEG32
NC: No connection
80-Pin Plastic QFP
4/34
¡ Semiconductor
MSM9200-xx
PIN DESCRIPTION
Pin
Symbol Type Connects to:
Fluorescent Fluorescent display tube anode electrode drive output.
tube grid Directly connected to fluorescent display tube and a pull-down
Description
10 to 44
SEG1-35
COM1-16
AD1-8
O
O
O
O
electrode resistor is not necessary. IOH>–5 mA
Fluorescent Fluorescent display tube grid electrode drive output.
tube grid
Directly connected to fluorescent display tube and a pull-down
45 to 60
1 to 8
electrode resistor is not necessary. IOH>–30 mA
Fluorescent Fluorescent display tube grid electrode drive output.
tube grid
Directly connected to fluorescent display tube and a pull-down
electrode resistor is not necessary. IOH>–10 mA
LED drive General port output.
control
Output of these pins in static mode, so control for LED driving is
73 to 76
P1-4
terminals performed through these pins.
64
9, 63, 78
72
VDD
VDISP1-3
GND
—
—
—
—
Power
supply
VDD-GND are power supplies for internal logic.
VDISP-VFL are power supplies for driving fluorescent tubes.
Use the same power supply for VDD and VDISP
Apply VFL after VDD and VDISP are applied.
Serial data input (positive logic).
.
61, 80
VFL1-2
Micro-
67
66
65
DA
CP
CS
I
I
I
controller Input from LSB.
Micro- Shift clock input.
controller Serial data is shifted on the rising edge of CP.
Micro- Chip select input.
controller "H" disables serial data transfer.
Display blink frequency input (square wave).
Only the position specified by the display blink position set command
is validated.
Micro-
68
BLINK
I
The time of "High" (light ON) and "Low" (light OFF) level of the signal
frequency to be input to BLINK is the blink time.
Fix BLINK pin to the VDD or GND pin when the display blink control
is not used.
controller
5/34
¡ Semiconductor
MSM9200-xx
Pin
Symbol Type Connects to:
Description
Reset input (pull-up resistor included).
"Low" initializes all the functions.
Initial status is as follows.
• Address of each RAM
• Data of each RAM
• Display digit
address "00"H
Content is undefined
Micro-
controller
or
16 digits
• Contrast adjusment
• Display blink
0/16
69
RESET
I
Blinking is disabled for all outputs
OFF mode
C2, R2
• All lights ON or OFF
• All outputs
"Low" level
RESET
(Circuit when R and C are
connected externally)
See Application Circuit.
C2
R2
External RC pin for RC oscillation.
Connect R and C externally. The RC time constant depends on the
VDD voltage used. Set the target oscillation frequency to 2 MHz.
71
70
OSC0
OSC1
I
C1, R1
OSC0
OSC1
(RC oscillation circuit)
See Application Circuit.
R1
O
C1
6/34
¡ Semiconductor
MSM9200-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
VFL
Condition
(*1)
Rating
–0.3 to 6.5
–0.3 to 6.5
–80 to VDISP+0.3
–80 to VDD+0.3
565
Unit
V
(*1)
V
Supply Voltage 2
Input Voltage
—
V
VIN
—
V
Power Dissipation
Storage Temperature
PD
Ta£25°C
—
mW
°C
TSTG
IO1
–55 to 150
–40 to 0.0
–20 to 0.0
–10 to 0.0
–4.0 to 4.0
COM1-COM16
AD1-AD8
SEG1-SEG35
P1-P4
IO2
Output Current
mA
IO3
IO4
*1 Use the same power supply for V and V
.
DISP
DD
RECOMMENDED OPERATING CONDITIONS-1
When the power supply voltage is 5V (typ).
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
VFL
Condition
Min.
4.5
Typ.
Max.
Unit
—
—
5.0
5.5
V
Supply Voltage 2
–60
—
—
–20
—
V
V
High Level Input Voltage
Low Level Input Voltage
CP Frequency
VIH
All input pins excluding OSC0 pin 0.7VDD
VIL
All input pins excluding OSC0 pin
—
—
—
—
0.3VDD
1.0
V
fC
—
MHz
MHz
Hz
µs
Oscillation Frequency
Frame Frequency
fOSC
fFR
tRSON
TOP
R1=3.3kW, C1=47pF
1.5
183
0
2.0
244
—
2.5
DIGIT=1–16, R =3.3kW, C =47pF
305
200
85
1
1
RESET Input Time
Operating Temperature
R2=1.0kW, C2=0.1PF
—
–40
—
°C
7/34
¡ Semiconductor
MSM9200-xx
RECOMMENDED OPERATING CONDITIONS-2
When the power supply voltage is 3.3V (typ).
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
VFL
Condition
Min.
3.0
Typ.
Max.
Unit
—
—
3.3
3.6
V
Supply Voltage 2
–60
—
—
–20
—
V
V
High Level Input Voltage
Low Level Input Voltage
CP Frequency
VIH
All input pins excluding OSC0 pin 0.8VDD
VIL
All input pins excluding OSC0 pin
—
—
—
—
0.2VDD
1.0
V
fC
—
MHz
MHz
Hz
µs
Oscillation Frequency
Frame Frequency
fOSC
fFR
tRSON
TOP
R1=3.3kW, C1=39pF
DIGIT=1–16, R1=3.3kW, C1=39pF
R2=1.0kW, C2=0.1µF
—
1.5
183
0
2.0
244
—
2.5
305
200
85
RESET Input Time
Operating Temperature
–40
—
°C
8/34
¡ Semiconductor
MSM9200-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD=VDISP=5.0V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
COM1-16
AD1-8
Condition
Min.
Max.
Unit
High Level Input Voltage
—
0.7VDD
—
V
VIH
Low Level Input Voltage
High Level Input Current
Low Level Input Current
—
—
0.3VDD
1.0
V
VIL
IIH
IIL
VIH=VDD
VIL=0.0V
–1.0
–1.0
µA
µA
1.0
VOH1
VOH2
VOH3
VOH4
IOH1=–30mA
IOH2=–10mA
IOH3=–5mA
IOH4=–2mA
VDISP–1.5
VDISP–1.5
VDISP–1.5
VDD–1.0
—
—
—
—
V
V
V
V
High Level Output
Voltage
SEG1-35
P1-4
COM1-16
AD1-8
Low Level Output
Voltage
VOL1
VOL2
IDD1
—
—
—
—
VFL+1.0
V
V
SEG1-35
P1-4
IOL1=2mA
1.0
4
Duty=15/16
Digit=1–16
mA
fOSC
=
All output lights ON
Duty=8/16
2MHz
VDD, VDISP
Current Consumption
no load
Digit=1–9
IDD2
—
3
mA
All output lights OFF
9/34
¡ Semiconductor
MSM9200-xx
DC Characteristics-2
(VDD=VDISP=3.3V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
COM1-16
AD1-8
Condition
Min.
Max.
Unit
High Level Input Voltage
—
0.8VDD
—
V
VIH
VIL
IIH
IIL
Low Level Input Voltage
High Level Input Current
Low Level Input Current
—
0.0
0.2VDD
1.0
V
VIH=VDD
VIL=0.0V
–1.0
–1.0
µA
µA
1.0
VOH1
VOH2
VOH3
VOH4
IOH1=–30mA
IOH2=–10mA
IOH3=–5mA
IOH4=–1mA
VDISP–1.5
VDISP–1.5
VDISP–1.5
VDD–1.0
—
—
—
—
V
V
V
V
High Level Output
Voltage
SEG1-35
P1-4
COM1-16
AD1-8
Low Level Output
Voltage
VOL1
VOL2
IDD1
—
—
—
—
VFL+1.0
V
V
SEG1-35
P1-4
IOL1=1mA
1.0
3
Duty=15/16
Digit=1–16
mA
fOSC
=
All output lights ON
Duty=8/16
2MHz
VDD, VDISP
Current Consumption
no load
Digit=1–9
IDD2
—
2
mA
All output lights OFF
10/34
¡ Semiconductor
MSM9200-xx
AC Characteristics-1
(VDD, VDISP=5.0V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
CP Pulse Width
DA Setup Time
DA Hold Time
tCW
—
300
300
300
300
16
tDS
—
—
ns
tDH
—
—
ns
CS Setup Time
CS Hold Time
tCSS
tCSH
tCSW
tDOFF
tRSON
tRSOFF
tR
—
—
ns
R1=3.3kW, C1=47PF
—
ms
ns
CS Wait Time
—
R1=3.3kW, C1=47PF
When RESET signal is input externally
—
300
8
—
Data Processing Time
RESET Pulse Width
Waite DA Time
—
ms
ns
300
300
—
—
—
ms
ms
ms
ms
ms
4.0
4.0
100
—
tR=20ꢀ to 80ꢀ
Cl=100pF
All Output Slow Rate
tF
—
tF=80ꢀ to 20ꢀ
VDD Rise Time
VDD Off Time
tPRZ
tPOF
When mounted in the unit
—
When mounted in the unit, VDD=0.0V
5.0
AC Characteristics-2
(VDD, VDISP=3.3V 10ꢀ, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
CP Pulse Width
DA Setup Time
DA Hold Time
tCW
—
300
300
300
300
16
tDS
—
—
ns
tDH
—
—
ns
CS Setup Time
CS Hold Time
tCSS
tCSH
tCSW
tDOFF
tWRES
tRSOFF
tR
—
—
ns
R1=3.3kW, C1=39PF
—
ms
ns
CS Wait Time
—
R1=3.3kW, C1=39PF
When RESET signal is input externally
—
300
8
—
Data Processing Time
RESET Pulse Width
DA Wait Time
—
ms
ns
300
300
—
—
—
ms
ms
ms
ms
ms
4.0
4.0
100
—
tR=20ꢀ to 80ꢀ
Cl=100pF
All Output Slew Rate
tF
—
tF=80ꢀ to 20ꢀ
VDD Rise Time
VDD Off Time
tPRZ
tPOF
When mounted in the unit
—
When mounted in the unit, VDD=0.0V
5.0
11/34
¡ Semiconductor
MSM9200-xx
TIMING DIAGRAM
• Data Timing
tCSS
tCSW
VIH
VIL
CS
CP
DA
tCSH
tC
fC
VIH
VIL
tCW tCW
tDOFF
tDH
tDS
VIH
VIL
VALID VALID
VALID VALID
• Reset Timing
0.8 VDD
0.0 V
tPRZ
tRSON
tRSOFF
VDD
When input externally
tWRES
tOF
VIH
0.5 VDD
VIL
RESET
DA
When external
R and C are
connected.
tRSOFF
VIH
VIL
• Output Timing
tR
tF
0.8 VDISP
0.2 VFL
All outputs
Symbol
VIH
VDD=3.3V±±10
0.8 VDD
VDD=5.1V±±10
0.7 VDD
VIL
0.2 VDD
0.3 VDD
12/34
¡ Semiconductor
MSM9200-xx
FUNCTIONAL DESCRIPTION
Command List
1st byte
2nd byte
LSB
MSB LSB
MSB
Command
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
1
2
3
4
DCRAM data write 1
DCRAM data write 2
DCRAM data write 3
DCRAM data write 4
X0 X1 X2 X3
X0 X1 X2 X3
X0 X1 X2 X3
X0 X1 X2 X3
1
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
C0 C1 C2 C3 C4 C5 C6 C7
C0 C1 C2 C3 C4 C5 C6 C7
C0 C1 C2 C3 C4 C5 C6 C7
C0 C1 C2 C3 C4 C5 C6 C7
C0 C5 C10 C15 C20 C25 C30
2nd byte
3rd byte
4th byte
5th byte
6th byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
*
*
*
*
*
*
*
*
C1 C6 C11 C16 C21 C26 C31
5
6
CGRAM data write 1
CGRAM data write 2
X0 X1 X2 X3
1
0
0
1
1
1
0
0
C2 C7 C12 C17 C22 C27 C32
C3 C8 C13 C18 C23 C28 C33
C4 C9 C14 C19 C24 C29 C34
C0 C5 C10 C15 C20 C25 C30
C1 C6 C11 C16 C21 C26 C31
X0 X1 X2 X3
C2 C7 C12 C17 C22 C27 C32
C3 C8 C13 C18 C23 C28 C33
*
*
C4 C9 C14 C19 C24 C29 C34
7
8
ADRAM data write
Display blink position
set
X0 X1 X2 X3
SG AD
1
0
1
0
1
0
0
1
C0 C1 C2 C3 C4 C5 C6 C7
G1 G2 G3 G4 G5 G6 G7 G8 2nd byte
G9 G10 G11 G12 G13 G14 G15 G16 3rd byte
*
*
9
A
B
C
D
E
DCRAM address shift
DCRAM address reset
General output port set
Display duty set
Number of digits set
All lights ON/OFF
Test mode
S
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
*
*
*
*
*
*
: Don't care
*
*
Xn : Address specification for each RAM
Cn : Character code specification for each RAM
SG : SEG display area specification
AD : AD display area specification
Gn : Display blink position specification
: Left and right display shift specification
Pn : General output port status specification
Dn : Display duty specification
P1 P2 P3 P4
D0 D1 D2 D3
K0 K1 K2 K3
L
H
*
*
S
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously,
addresses are internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data
for the 2nd and later bytes.
Kn : Number of digits specification
H
L
: All lights ON instruction
: All lights OFF instruction
Note: The test mode is used for inspection before shipment.
It is not a user function.
13/34
¡ Semiconductor
MSM9200-xx
Positional Relationship Between SEGn and ADn (one digit)
C0
C1
C2
C3
AD1
AD2
AD3
AD4
Area for the ADRAM data to
be output
C4
C5
C6
C7
AD5
AD6
AD7
AD8
C0
C1
C2
C3
C4
SEG1 SEG2 SEG3 SEG4 SEG5
C5
C6
C7
C8
C9
SEG6 SEG7 SEG8 SEG9 SEG10
C10
C11
C12
C13
C14
SEG11 SEG12
SEG13
SEG14
SEG15
C15
C16
C17
C18
C19
SEG16
SEG17
SEG18
SEG19
SEG20
C20
C21
C22
C23
C24
SEG21 SEG22 SEG23 SEG24 SEG25
C25
C26
C27
C28
C29
SEG26
SEG27
SEG28
SEG29
SEG30
C30
C31
C32
C33
C34
SEG31 SEG32 SEG33 SEG34 SEG35
CGRAM written data. Corresponds to 2nd byte
CGRAM written data. Corresponds to 3rd byte
CGRAM written data. Corresponds to 4th byte
CGRAM written data. Corresponds to 6th byte
CGRAM written data. Corresponds to 5th byte
14/34
¡ Semiconductor
MSM9200-xx
Data Transfer System and Command Write System
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock,
which is input into the CP pin. If 8-bit data is input, internal load signals are automatically
generated and data is written to each register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin
changes from "High" to "Low" is recognized in 8-bit units.
tDOFF
tCSH
CS
CP
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7
LSB MSB
DA
1st byte
2nd byte
2nd byte
Character code data of the
next address
When data is written to DCRAM* Command and address data
Character code data
*
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later
bytes.
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) and
initializes all functions.
Initial status is as follows.
• Address of each RAM .................. address "00"H
• Data of each RAM ........................ All contents are undefined
• Display blink ................................. Blinking is disabled for all outputs
• General output port ..................... All general output ports go "Low"
• Display digit.................................. 16 digits
• Contrast adjustment..................... 0/16
• All display lights ON or OFF ..... OFF mode
• Segment output ............................ All segment outputs go "Low"
• AD output ..................................... All AD outputs go "Low"
Reset again according to "Initial Setting Flowchart" after reset.
15/34
¡ Semiconductor
MSM9200-xx
Description of Commands and Functions
1. DCRAM data write 1
(Specifies the address (00H to 0FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
2. DCRAM data write 2
(Specifies the address (10H to 1FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
3. DCRAM data write 3
(Specifies the address (20H to 2FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
4. DCRAM data write 4
(Specifies the address (30H to 3FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
DCRAM (Data Control RAM) has a 6-bit address to store character code of CGROM and
CGRAM. (4 bits can be set by the user and the 2 bits on the MSB side are automatically set.)
The character code specified by DCRAM is converted to a 5¥7 dot matrix character pattern via
CGROM or CGRAM.
The capacity is 64¥8 bits, which can store 64 characters.
Note: The addresses 00H to 3FH of DCRAM are automatically incremented.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3
1
0
0
0
: selects DCRAM data write mode and specifies DCRAM
address
(Ex: Specifies DCRAM address 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(2nd)
: specifies character code of CGROM and CGRAM
: written into DCRAM address 00H
To specify the character code of CGROM and CGRAM continuously to the next address, specify
only character code as follows.
The addresses of DCRAM are automatically incremented. Specification of an address is
unnecessary.
16/34
¡ Semiconductor
MSM9200-xx
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM
: written into DCRAM address 01H
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(4th)
: specifies character code of CGROM and CGRAM
: written into DCRAM address 02H
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(17th)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM
: written into DCRAM address 0FH
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(18th)
: specifies character code of CGROM and CGRAM
: written into DCRAM address 10H
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(65th)
C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM
: written into DCRAM address 3FH
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(66th)
: specifies character code of CGROM and CGRAM
: DCRAM address 00H is rewritten
X0 (LSB) to X3 (MSB): DCRAM addresses (4 bits: 16 characters)
Note: A total of 64 characters for the four specifications
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 character)
[COM positions and set DCRAM addresses]
The states when RESET is input and DCRAM address reset commands are executed
Command
No.
COM
position
COM1
Command
No.
COM
HEX K1 K± K2 K3
HEX K1 K± K2 K3
position
00
01
0
1
0
0
0
0
0
0
20
21
0
1
0
0
0
0
0
0
COM2
1
3
0E
0F
10
11
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
COM15
COM16
2E
2F
30
31
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
2
4
1E
1F
0
1
1
1
1
1
1
1
3E
3F
0
1
1
1
1
1
1
1
17/34
¡ Semiconductor
MSM9200-xx
5. CGRAM data write 1
(Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.)
6. CGRAM data write 2
(Specifies the addresses 10H to 1FH of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has a 5-bit address to store 5¥7 dot matrix character
patterns. (4 bits can be set by the user and the 1 bit on the MSB is automatically set.)
A character pattern stored in CGRAM can be displayed by specifying the character code
(address) by DCRAM.
The address of CGRAM is assigned to 00H to 1FH. (All the other addresses are the CGROM
addresses.)
Capacity is (16¥2)¥35¥8 bits, which can store 32 types of character patterns.
Note: The addresses 00H to 1FH of CGRAM are automatically incremented.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
: selects CGRAM data write mode and specifies
CGRAM address.
X0 X1 X2 X3
1
0
1
0
(Ex: specifies CGRAM address 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
: specifies 1st column data
: rewritten into CGRAM address 00H
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
: specifies 2nd column data
: rewritten into CGRAM address 00H
C1 C6 C11 C16 C21 C26 C31
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte
(4th)
: specifies 3rd column data
: rewritten into CGRAM address 00H
C2 C7 C12 C17 C22 C27 C32
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
5th byte
(5th)
: specifies 4th column data
: rewritten into CGRAM address 00H
C3 C8 C13 C18 C23 C28 C33
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
: specifies 5th column data
: rewritten into CGRAM address 00H
C4 C9 C14 C19 C24 C29 C34
*
Tospecifycharacterpatterndatacontinuouslytothenextaddress, specifyonlycharacterpattern
data as follows.
The addresses of CGRAM are automatically incremented. Specification of an address is
therefore unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient
for t
time between bytes.
DOFF
18/34
¡ Semiconductor
MSM9200-xx
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
:
specifies 1st column data
: rewritten into CGRAM address 01H
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
:
:
specifies 5th column data
: rewritten into CGRAM address 01H
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
specifies 1st column data
: rewritten into CGRAM address 02H
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
:
:
specifies 5th column data
: rewritten into CGRAM address 02H
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
specifies 1st column data
: rewritten into CGRAM address 0FH
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81th)
:
:
specifies 5th column data
: rewritten into CGRAM address 0FH
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82th)
specifies 1st column data
: rewritten into CGRAM address 10H
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
:
:
specifies 5th column data
: rewritten into CGRAM address 10H
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(157th)
specifies 1st column data
: rewritten into CGRAM address 1FH
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(161th)
:
:
specifies 5th column data
: rewritten into CGRAM address 1FH
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(162th)
specifies 1st column data
(CGRAM address 00H is rewritten)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(167th)
:
specifies 5th column data
(CGRAM address 00H is rewritten)
C4 C9 C14 C19 C24 C29 C34
*
X0 (LSB) to X3 (MSB): CGRAM addresses (4 bits: 16 characters)
Note: A total of 32 characters for the two specifications.
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)
19/34
¡ Semiconductor
MSM9200-xx
Positional relationship between the output area of CGROM and that of CGRAM
C0
C5
C1
C6
C2
C7
C3
C8
C4
C9
C10 C11 C12 C13 C14
C15 C16 C17 C18 C19
C20 C21 C22 C23 C24
C25 C26 C27 C28 C29
C30 C31 C32 C33 C34
area that corresponds to 2nd byte (1st column)
area that corresponds to 3rd byte (2nd column)
area that corresponds to 6th byte (5th column)
area that corresponds to 5th byte (4th column)
area that corresponds to 4th byte (3rd column)
Note: CGROM (Character Generator ROM) has an 8-bit address to generate 5¥7 dot matrix
character patterns.
The capacity is 224¥35¥8 bits, which can store 224 types of character patterns.
2 types of general-purpose code are availble (see ROM CODE list) and custom codes are
provided on customer's request.
[CGROM addresses and set CGRAM addresses]
Refer to ROMCODE table
Command
No.
CGROM
Command
No.
CGROM
HEX K1 K± K2 K3
HEX K1 K± K2 K3
address
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RAM00(00000000B)
RAM01(00000001B)
RAM02(00000010B)
RAM03(00000011B)
RAM04(00000100B)
RAM05(00000101B)
RAM06(00000110B)
RAM07(00000111B)
RAM08(00001000B)
RAM09(00001001B)
RAM0A(00001010B)
RAM0B(00001011B)
RAM0C(00001100B)
RAM0D(00001101B)
RAM0E(00001110B)
RAM0F(00001111B)
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RAM10(00010000B)
RAM11(00010001B)
RAM12(00010010B)
RAM13(00010011B)
RAM14(00010100B)
RAM15(00010101B)
RAM16(00010110B)
RAM17(00010011B)
RAM18(00011000B)
RAM19(00011001B)
RAM1A(00011010B)
RAM1B(00011011B)
RAM1C(00011100B)
RAM1D(00011101B)
RAM1E(00011110B)
RAM1F(00011111B)
2
4
20/34
¡ Semiconductor
MSM9200-xx
7. ADRAM data write
(specifies address of ADRAM and writes symbol data)
ADRAM (Additional Data RAM) has a 4-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
The capacity is 8¥16 bits, which can store 8 types of symbol patterns for each digit.
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
: selects ADRAM data write mode and specifies ADRAM
address
X0 X1 X2 X3
1
1
1
0
(Ex: specifies ADRAM address 0H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(2nd)
: sets symbol data
(written into ADRAM address 0H)
To specify symbol data continuously to the next address, specify only symbol data as follows.
The address of ADRAM is automatically incremented. Specification of addresses is therefore
unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(3rd)
: sets symbol data
(written into ADRAM address 1H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(4th)
: sets symbol data
(written into ADRAM address 2H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(17th)
: sets symbol data
(written into ADRAM address FH)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
2nd byte
(18th)
: sets symbol data
(ADRAM address 00H is rewritten.)
X0 (LSB) to X3 (MSB): ADRAM addresses (4 bits: 16 characters)
C0 (LSB) to C7 (MSB): Symbol data (8-symbol data per digit)
21/34
¡ Semiconductor
MSM9200-xx
[COM positions and ADRAM addresses]
HEX D1 D± D2 D3
COM position
HEX D1 D± D2 D3
COM position
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
8. Display blink position set
(sets the blink position for the SEG area or AD area in COMn.
Display blink position can be set separately for the SEG area and AD area. In this case, select
by command in which COMn the SEG area or AD area is made blink.
The blink disabled state is entered for this setting when power is turned on or when a RESET
signal is input. The display blink cycle is determined by the frequency to be input to the
BLINK pin.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
: selects either the AD output area or the segment
output area and specifies digit
SG AD
0
0
0
1
* *
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
G1 G2 G3 G4 G5 G6 G7 G8
2nd byte
(2nd)
: specifies blink position to COM1 to COM8
: specifies blink position to COM9 to COM16
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
G9 G10 G11 G12 G13 G14 G15 G16
3rd byte
(3rd)
The 2nd and 3rd bytes (COM1 to COM16 position specification) are regarded as one data item,
so 300 ns is sufficient for t time between bytes.
DOFF
SG: Specifies SEG area
AD: Specifies AD area
Gn: Specifies blinks
22/34
¡ Semiconductor
MSM9200-xx
[SEG and AD display and set data]
SG/AD
Gn
0
SEG and AD display
Does not blink (current state)
Does not bilnk (current state)
Specified positions do not blink
Specified positions blink
0
0
1
1
(The state when power is applied or when RESET is input)
1
0
1
Note: If both SG and AD are set to "1" by command, both the SEG area and the AD area are
specified.
9. DCRAM address shift
(Shifts SEG output left or right.)
DCRAM address shift shifts SEG output 1 digit to the left or right using 1 bit data. AD output
cannot be shifted.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
SG
1st byte
: selects DCRAM address shift and sets shift
value (left, right)
1
0
0
1
* * *
S: Specifies the direction of shift
[Set data and shift direction of display]
S
0
1
Shift direction of display
Shift to left
Shift to right
23/34
¡ Semiconductor
MSM9200-xx
[DCRAM address shift and COM positions]
When S=0 (shift to left) is performed from the initial state.
Command
No.
COM
position
COM2
Command
No.
COM
HEX K1 K± K2 K3
HEX K1 K± K2 K3
position
00
01
0
1
0
0
0
0
0
0
20
21
0
1
0
0
0
0
0
0
COM3
1
3
0E
0F
10
11
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
COM16
2E
2F
30
31
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
2
4
1E
1F
0
1
1
1
1
1
1
1
3E
3F
0
1
1
1
1
1
1
1
COM1
When S=1 (shift to right) is performed from the initial state.
Command
No.
COM
Command
No.
COM
HEX K1 K± K2 K3
HEX K1 K± K2 K3
position
position
00
01
0
1
0
0
0
0
0
0
20
21
0
1
0
0
0
0
0
0
COM1
1
3
0E
0F
10
11
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
COM14
COM15
COM16
2E
2F
30
31
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
2
4
1E
1F
0
1
1
1
1
1
1
1
3E
3F
0
1
1
1
1
1
1
1
24/34
¡ Semiconductor
MSM9200-xx
A. DCRAM address reset
(returns display status to initial setting status)
The DCRAM address reset returns the status where a DCRAM address shift is executed to
initial status.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
: selects DCRAM address reset
0
1
0
1
* * * *
Relation between the DCRAM address shifts and the COM outputs
Initial status or the status where display address reset executed (DCRAM address is 00H)
COM output
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DCRAM address (HEX)
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
When left shift is executed in the initial status
COM output
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DCRAM address (HEX)
3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
When right shift is executed in the initial status
COM output
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DCRAM address (HEX)
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
B. General output port set
(specifies the general output port status)
The general output port is an output for 4-bit static operation.
It is used to control other I/O devices and turn on LED.
When at the "High" level, this output becomes the V voltage, and when at the "Low" level,
DD
it becomes the ground potential. Therefore, the fluorescent display tube cannot be driven.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
P1 P2 P3 P4
1st byte
: selects a general output port and specifies
the output status
1
1
0
1
P1-P4: general output port
[Set data and set state of general output port]
Pn
0
Display state of general output port
Sets to the output to Low
(The state when power is applied or when RESET is input.)
1
Sets to the output to High
25/34
¡ Semiconductor
MSM9200-xx
C. Display duty set
(writes display duty value to duty cycle register)
Display duty adjusts contrast in 16 stages using 4-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is
"0". Always execute this instruction before turning the display on, then set a desired duty
value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
D0 D1 D2 D3
1st byte
: selects display duty set mode and sets duty value
0
0
1
1
D0 (LSB) to D3 (MSB): display duty data (4 bits: 16 stages)
[Relation between setup data and controlled COM duty]
HEX
D3 D2 D1 D0
COM duty
0/16
HEX
8
D3 D2 D1 D0
COM duty
8/16
* 0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/16
9
9/16
2
2/16
A
10/16
11/16
12/16
13/16
14/16
15/16
3
3/16
B
4
4/16
C
5
5/16
D
E
6
6/16
7
7/16
F
*
The state when powered on or when RESET signal inputs.
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¡ Semiconductor
MSM9200-xx
D. Number of digits set
(writes the number of display digits to the display digit register)
The number of digits set can display a maximum of 16 digits using 4-bit data.
When power is turned on or when a RESET signal is input, the number of digit register value
is "0". Always execute this instruction to change the number of digits before turning the
dispaly on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
K0 K1 K2 K3
1st byte
: selects the number of digit set mode and specifies
the number of digit value
1
0
1
1
K0 (LSB) to K3 (MSB): number of digit data (4 bits: 16 digits)
[Relation between setup data and controlled COM]
Number of digits
Number of digits
of COM
HEX K3 K2 K± K1
HEX K3 K2 K± K1
of COM
COM1-16
COM1-1
COM1-2
COM1-3
COM1-4
COM1-5
COM1-6
COM1-7
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
9
A
B
C
D
E
F
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM1-8
COM1-9
COM1-10
COM1-11
COM1-12
COM1-13
COM1-14
COM1-15
E. All display lights ON/OFF set
(turns all dispaly lights ON or OFF)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used to prevent malfunction when power is turned on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
: selects all display lights ON or OFF mode and
sets all lights ON or OFF value
L
H
0
1
1
1
* *
[Set data and display state of SEG and AD]
L
0
1
0
1
H
0
0
1
1
Display state of SEG and AD
All outputs maintain current states
Sets all outputs to Low
(The state when power is applied or when RESET is input.)
Sets all outputs to High
Sets all outputs to High
(All lights ON mode has priority.)
27/34
¡ Semiconductor
MSM9200-xx
Initial Setting Flowchart
Apply VFL
All display lights OFF
General output port set
Number of digits set
Display duty set
Status of all outputs by RESET
signal input
Select a RAM to be used
DCRAM
CGRAM
ADRAM
Data write mode
(with address set)
Data write mode
Data write mode
(with address set)
(with address set)
Address is automatically
incremented
Address is automatically
incremented
Address is automatically
incremented
DCRAM
CGRAM
ADRAM
Character code
Character code
Character code
DCRAM
Is character code
write ended?
CGRAM
Is character code
write ended?
ADRAM
Is character code
write ended?
NO
NO
NO
YES
YES
YES
YES
Another RAM to
be set?
Releases all display lights
OFF mode
Display operation mode
End
28/34
¡ Semiconductor
MSM9200-xx
APPLICATION CIRCUIT
Heater transformer
5¥7-dot matrix fluorescent display tube
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (DIGIT)
VDD
8
35
16
R2
C2
VDD
VDD
VDISP1-3
,
AD1-8
SEG1-35 COM1-16
RESET
R4
LED
VDD
C3
MCU
MSM9200-xx
CS
4
CP
Output port
GND
P1-4
NPN Tr
DA
BLINK
GND VFL1-2
OSC0 OSC1
R1
GND
C1
R3
VFL
C4
ZD
Notes: 1. The V value depends on the power supply voltage of the microcontroller used.
DD
Adjust the values of the constants R , R , R , C , and C to the power supply voltage
1
2
4
1
2
used.
2. The V value depends on the fluorescent display tube used. Adjust the values of the
FL
constants R and ZD to the power supply voltage used.
3
29/34
¡ Semiconductor
MSM9200-xx
Reference data
The figure below shows the relationship between the V voltage and the output current of each
FL
driver.
Take care that the total power consumtion to be used does not exceed the power dissipation.
[VFL Voltage-Output Current of Each Driver]
(mA)
–30
COM1 to COM16
(Condition: VOH=VDISP–1.5 V)
–25
–20
–15
–10
–5
AD1 to AD8
(Condition: VOH=VDISP–1.5 V)
SEG1 to SEG35
(Condition: VOH=VDISP–1.5 V)
0
–10
–20
–30
–40
–50
–60 (V)
[VFL Voltage (VDD-n) ]
30/34
¡ Semiconductor
MSM9200-xx
MSM9200-01 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LSB
0000 RAM00 RAM10
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010
1011
1100
1101
1101
1111
RAM0A RAM1A
RAM0B RAM1B
RAM0C RAM1C
RAM0D RAM1D
RAM0E RAM1E
RAM0F RAM1F
31/34
¡ Semiconductor
MSM9200-xx
MSM9200-02 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LSB
0000 RAM00 RAM10
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010 RAM0A RAM1A
1011
1100
1101
1101
1111
RAM0B RAM1B
RAM0C RAM1C
RAM0D RAM1D
RAM0E RAM1E
RAM0F RAM1F
32/34
¡ Semiconductor
MSM9200-xx
Digit Output Timing (for 16-digit display, at a duty of 15/16)
T=8/ fOSC
Frame cycle
Display timing
Blank timing
t1=1024T (t1=4.096 ms when fosc=2.0 MHz)
t2=60T (t2=240 ms when fosc=2.0 MHz)
VDISP
VFL
t3=4T
(t3=16 ms when fosc=2.0 MHz)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
VDISP
VFL
AD1-8
SEG1-35
33/34
¡ Semiconductor
PACKAGE DIMENSIONS
QFP80-P-1414-0.65-K
MSM9200-xx
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.85 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
34/34
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