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TDA9983BHW/15/C1;5 [NXP]

IC SPECIALTY CONSUMER CIRCUIT, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT841-4, HTQFP-80, Consumer IC:Other;
TDA9983BHW/15/C1;5
型号： TDA9983BHW/15/C1;5
厂家： NXP    NXP
描述：

IC SPECIALTY CONSUMER CIRCUIT, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT841-4, HTQFP-80, Consumer IC:Other

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TDA9983B  
HDMI transmitter up to 150 MHz pixel rate with 3 × 8-bit video  
inputs and 4 × I2S-bus with S/PDIF  
Rev. 01 — 20 May 2008  
Product data sheet  
1. General description  
The TDA9983B is an HDMI transmitter (which also supports DVI) that enables a 3 × 8-bit  
RGB or YCBCR video stream (with a pixel rate up to 150 MHz for the TDA9983BHW/15  
version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and  
the additional information required by all the HDMI 1.2a standards.  
A programmable upscaling block enables a 720p/1080i output from a standard definition  
input. An intrafield deinterlacer is included in the scaler.  
In order to be compatible with most applications, the TDA9983B integrates a full  
programmable input formatter and color space conversion block. The video input formats  
accepted are YCBCR 4 : 4 : 4 (up to 3 × 8-bit), YCBCR 4 : 2 : 2 semi-planar (up to  
2 × 12-bit), YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit).  
For ITU656-like formats, double edges are supported so that data can be sampled on  
rising and falling edges.  
The device can be controlled via an I2C-bus interface.  
2. Features  
I 3 × 8-bit video data input bus, CMOS and LV-TTL compatible  
I Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or  
VREF, HREF and FREF could be used for input data synchronization  
I Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus)  
I The TDA9983B has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio  
sampling rate up to 192 kHz  
I 250 MHz to 1.50 GHz HDMI transmitter operation  
I Programmable input formatter and upsampler/interpolator allows input of any of the  
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats  
I Programmable color space converter:  
N RGB to YCBCR  
N YCBCR to RGB  
I The upscaler enables a 720p/1080i output from a standard definition input using  
intelligent edge interpolation  
I Controllable via I2C-bus  
I Low power dissipation  
I 1.8 V and 3.3 V power supplies  
I Power-down mode  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
I Hard reset  
3. Applications  
I DVD players and recorders  
I Set-Top Box (STB)  
I AV receivers and amplifiers (repeater)  
I Camcorders  
I Digital still cameras  
I Media players  
I PVRs  
I Media centers PCs, graphics add-in boards, notebook PCs  
I Switches  
4. Quick reference data  
Table 1.  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V;  
DDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V;  
DDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 °C; unless otherwise specified.  
Quick reference data  
V
V
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
TDA9983BHW/8 and TDA9983BHW/15  
VDDA(FRO_3V3) free running oscillator 3.3 V  
analog supply voltage  
3.0  
3.0  
3.3  
3.3  
3.6  
3.6  
V
V
VDDA(PLL_3V3) PLL 3.3 V analog supply  
voltage  
[1]  
[1]  
VDDD(3V3)  
VDDH(3V3)  
VDDC(1V8)  
Tamb  
digital supply voltage (3.3 V)  
HDMI supply voltage (3.3 V)  
core supply voltage (1.8 V)  
ambient temperature  
3.0  
3.0  
3.3  
3.3  
3.6  
3.6  
1.95  
70  
V
V
1.65 1.8  
V
0
-
°C  
TDA9983BHW/8; up to 81 MHz  
fclk(max) maximum clock frequency  
Pcons  
[2]  
[2]  
[3]  
[2]  
[3]  
81  
-
-
-
MHz  
mW  
mW  
mW  
mW  
power consumption  
322  
338  
458  
472  
-
worst case  
worst case  
-
503  
-
Ptot  
Ppd  
total power dissipation  
-
-
651  
power dissipation in  
power-down mode  
-
13.5 38.4 mW  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
2 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 1.  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V;  
DDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V;  
DDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 °C; unless otherwise specified.  
Quick reference data …continued  
V
V
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
TDA9983BHW/15; up to 150 MHz  
[4]  
[4]  
[4]  
fclk(max)  
Pcons  
Ptot  
maximum clock frequency  
150  
-
-
MHz  
mW  
mW  
power consumption  
-
-
-
361  
495  
583  
732  
total power dissipation  
Ppd  
power dissipation in  
power-down mode  
13.5 38.4 mW  
[1] The VDDD(3V3) and VDDC(1V8) power supplies must always follow the sequence shown in Figure 14 to ensure  
proper power-up conditions.  
[2] Video format:  
a) Input 480p (ITU656 embedded sync, rising edge)  
b) Output 1080i (YCBCR 4 : 2 : 2)  
[3] Worst case video format:  
a) Input 480p (YCBCR 4 : 2 : 2 semi-planar)  
b) Output 720p (YCBCR 4 : 2 : 2)  
[4] Video format:  
a) Input 1080p (RGB 4 : 4 : 4 external sync, rising edge)  
b) Output 1080p (RGB 4 : 4 : 4)  
5. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
TDA9983BHW HTQFP80 plastic thermal enhanced thin quad flat package;  
SOT841-4  
80 leads; body 12 × 12 × 1 mm; exposed die pad  
5.1 Ordering options  
Table 3.  
Survey of type numbers  
Extended type number  
Sampling frequency  
(Msample/s)  
Application  
TDA9983BHW/8/C1  
TDA9983BHW/15/C1  
81  
customer specific version  
customer specific version  
150  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
3 of 119  
 
 
 
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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x  
V
PP  
V
V
DDC(1V8)  
DDH(3V3)  
V
DDA(PLL_3V3)  
V
V
I2C_SCL I2C_SDA  
43 44  
A0 A1  
41 40  
RST_N  
42  
DDD(3V3)  
DDA(FRO_3V3)  
3
13, 48,  
71  
16, 45, 23  
59, 74  
38  
28, 34  
20  
19  
DDC_SCL  
DDC_SDA  
2
I C-BUS  
HPD  
MANAGEMENT  
18  
DDC-BUS  
HARD  
RESET  
HPD  
SLAVE  
4 to 11  
12  
AP7 to AP0  
ACLK  
17  
AUDIO  
PROCESSING  
IRQ  
GENERATION  
INT  
DATA  
ISLAND  
PACKET  
INFORMATION  
FRAMES AND  
PACKETS  
27  
26  
TXC+  
TXC−  
68 to 70,  
75 to 79  
30  
29  
TX0+  
VIDEO PROCESSING  
RGB  
VPA[7:0]  
TX0−  
57 and 58,  
61 to 65,  
67  
HDMI  
SERIALIZER  
YC  
C
R
4 : 4 : 4  
33  
32  
B
TX1+  
VPB[7:0]  
VPC[7:0]  
COLOR  
SPACE  
3 × 8-bit  
DOWNSAMPLING  
TX1−  
49 to 56  
FROM  
4 : 4 : 4  
TO  
VIDEO  
INPUT  
PROCESSOR  
CONVERTER  
RGB TO YUV  
YUV TO RGB  
2
(1)  
36  
35  
VSYNC/VREF  
HSYNC/HREF  
DE/FREF  
UPSCALER  
UPSAMPLING  
FROM  
TX2+  
1
(1)  
4 : 2 : 2  
(1)  
TX2−  
4 : 2 : 2  
TO  
4 : 4 : 4  
(4 : 4 : 4)  
80  
66  
DEINTERLACER  
(1)  
(1)  
INTRAFIELD  
VCLK  
TDA9983B  
YC  
B
C
4 : 2 : 2  
2 × 12-bit  
R
ITU656 or ITU656-like  
or 1 × 12-bit  
14, 47,  
15, 60,  
25, 31,  
72  
73  
37  
22  
39  
46  
21  
TM  
24  
001aag248  
V
V
V
V
V
V
EXT_SWING  
SSD  
SSC  
SSA(FRO_3V3)  
SSA(PLL_3V3)  
SSH  
SSA(PLL_1V8)  
(1) Block can be bypassed.  
Fig 1. Block diagram  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
7. Pinning information  
7.1 Pinning  
1
2
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
HSYNC/HREF  
VSYNC/VREF  
V
V
SSC  
DDC(1V8)  
3
V
VPB[6]  
VPB[7]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
PP  
4
AP7  
AP6  
AP5  
AP4  
AP3  
AP2  
AP1  
AP0  
ACLK  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
TDA9983B  
V
V
V
V
V
V
DDD(3V3)  
DDD(3V3)  
SSD  
V
V
SSD  
SSC  
SSA(PLL_1V8)  
DDC(1V8)  
DDC(1V8)  
INT  
I2C_SDA  
I2C_SCL  
RST_N  
A0  
HPD  
DDC_SDA  
DDC_SCL  
001aag249  
Fig 2. Pin configuration  
7.2 Pin description  
Table 4.  
Symbol  
Pin description  
Pin  
Type[1] Description  
HSYNC/HREF  
VSYNC/VREF  
VPP  
1
2
3
I
horizontal synchronization or reference input  
vertical synchronization or reference input  
I
P
programming voltage (must be connected to the ground of  
the digital core in normal operation)  
AP7  
AP6  
AP5  
4
5
6
I
I
I
audio port 7 input; auxiliary (AUX)  
audio port 6 input; S/PDIF stream  
audio port 5 input; optional master clock MCLK for S/PDIF  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
5 of 119  
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 4.  
Pin description …continued  
Symbol  
AP4  
Pin  
7
Type[1] Description  
I
audio port 4 input; I2S-bus 3  
AP3  
8
I
audio port 3 input; I2S-bus 2  
AP2  
9
I
audio port 2 input; I2S-bus 1  
AP1  
10  
11  
12  
13  
14  
15  
16  
17  
I
audio port 1 input; I2S-bus 0  
AP0  
I
audio port 0 input; word select WS for I2S-bus  
audio clock input; clock SCK for I2S-bus  
supply voltage for input ports (3.3 V)  
ground for input ports  
ACLK  
VDDD(3V3)  
VSSD  
I
P
G
G
P
O
VSSC  
ground for digital core  
VDDC(1V8)  
INT  
supply voltage for digital core (1.8 V)  
interrupt output (open drain); warns the external  
microprocessor that a special event has occurred; must be  
connected to a pull-up resistor; 5 V tolerant  
HPD  
18  
19  
I
hot plug detect input; 5 V tolerant  
DDC_SDA  
I/O  
DDC-bus data input/output (open drain); must be connected  
to a pull-up resistor; 5 V tolerant  
DDC_SCL  
TM  
20  
21  
O
I
DDC-bus clock output (open drain); must be connected to a  
pull-up resistor; 5 V tolerant  
internal test mode input (must be connected to the ground of  
the digital core in normal operation)  
VSSA(FRO_3V3)  
VDDA(FRO_3V3)  
EXT_SWING  
22  
23  
24  
G
P
I
analog ground for free running oscillator  
analog supply voltage for free running oscillator (3.3 V)  
external swing adjust input; a fixed resistor must be  
connected between this pin and VDDH(3V3) to set the HDMI  
output swing (see Section 8.14.1)  
VSSH  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
G
O
O
P
O
O
G
O
O
P
O
O
G
P
G
I
ground for HDMI transmitter  
TXC−  
negative clock channel for HDMI output  
positive clock channel for HDMI output  
supply voltage for HDMI transmitter (3.3 V)  
negative data channel 0 for HDMI output  
positive data channel 0 for HDMI output  
ground for HDMI transmitter  
TXC+  
VDDH(3V3)  
TX0−  
TX0+  
VSSH  
TX1−  
negative data channel 1 for HDMI output  
positive data channel 1 for HDMI output  
supply voltage for HDMI transmitter (3.3 V)  
negative data channel 2 for HDMI output  
positive data channel 2 for HDMI output  
ground for HDMI transmitter  
TX1+  
VDDH(3V3)  
TX2−  
TX2+  
VSSH  
VDDA(PLL_3V3)  
VSSA(PLL_3V3)  
A1  
analog supply voltage for PLL (3.3 V)  
analog ground reference for PLL  
I2C-bus slave address input 1; bit 1  
I2C-bus slave address input 0; bit 0  
hard reset input; active LOW  
A0  
I
RST_N  
I
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
6 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 4.  
Pin description …continued  
Symbol  
Pin  
Type[1] Description  
I2C_SCL  
43  
I
I2C-bus clock input of device (open drain); must be connected  
to a pull-up resistor; 5 V tolerant  
I2C_SDA  
44  
I/O  
I2C-bus data input/output of device; open drain; must be  
connected to a pull-up resistor; 5 V tolerant  
VDDC(1V8)  
VSSA(PLL_1V8)  
VSSD  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
P
G
G
P
I
supply voltage for digital core (1.8 V)  
analog ground reference for PLL  
ground for input ports  
VDDD(3V3)  
VPC[7]  
VPC[6]  
VPC[5]  
VPC[4]  
VPC[3]  
VPC[2]  
VPC[1]  
VPC[0]  
VPB[7]  
VPB[6]  
VDDC(1V8)  
VSSC  
supply voltage for input ports (3.3 V)  
video port C input bit 7  
I
video port C input bit 6  
I
video port C input bit 5  
I
video port C input bit 4  
I
video port C input bit 3  
I
video port C input bit 2  
I
video port C input bit 1  
I
video port C input bit 0  
I
video port B input bit 7  
I
video port B input bit 6  
P
G
I
supply voltage for digital core (1.8 V)  
ground for digital core  
VPB[5]  
VPB[4]  
VPB[3]  
VPB[2]  
VPB[1]  
VCLK  
video port B input bit 5  
I
video port B input bit 4  
I
video port B input bit 3  
I
video port B input bit 2  
I
video port B input bit 1  
I
video pixel clock input  
VPB[0]  
VPA[7]  
VPA[6]  
VPA[5]  
VDDD(3V3)  
VSSD  
I
video port B input bit 0  
I
video port A input bit 7  
I
video port A input bit 6  
I
video port A input bit 5  
P
G
G
P
I
supply voltage for input ports (3.3 V)  
ground for input ports  
VSSC  
ground for digital core  
VDDC(1V8)  
VPA[4]  
VPA[3]  
VPA[2]  
VPA[1]  
VPA[0]  
DE/FREF  
supply voltage for digital core (1.8 V)  
video port A input bit 4  
I
video port A input bit 3  
I
video port A input bit 2  
I
video port A input bit 1  
I
video port A input bit 0  
I
video data enable input or field reference input  
Exposed die pad central  
G
exposed die pad; must be connected to the ground of the  
HDMI transmitter (VSSH  
)
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
7 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
[1] P = power supply; G = ground; I = input; O = output.  
8. Functional description  
The TDA9983B is designed to convert digital data (video and audio) into an HDMI or a  
DVI stream. This HDMI stream can handle RGB, YCBCR 4 : 4 : 4 and YCBCR 4 : 2 : 2. The  
TDA9983B can accept at its inputs any of the following video modes:  
• RGB  
• YCBCR 4 : 4 : 4  
• YCBCR 4 : 2 : 2 semi-planar  
• YCBCR 4 : 2 : 2 ITU656 and ITU656-like  
It can also handle audio. The TDA9983B can accept at its inputs any of the following audio  
buses:  
• I2S-bus (4 lines): up to 8 audio channels  
• S/PDIF (1 channel): L-PCM (IEC 60958) or compressed audio (IEC 61937)  
8.1 System clock  
The clock management is based on a set of 3 PLLs that generate the different clocks  
required inside the chip. This includes:  
• PLL double edge can generate a clock at twice the VCLK input frequency to capture  
the data at the video input formatter  
• PLL scaling can create a new video processing scaled clock taking into account the  
scaling ratio programmed in the scaler  
• PLL serializer is a system clock generator, which enables the stream produced by the  
encoder to be transmitted on the HDMI data channel at ten times the sampling rate or  
more; see Section 8.14.2  
8.2 Video input processor  
The TDA9983B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0]. The  
TDA9983B can reallocate and swap each of the 3 ports input channels by inverting the  
bus and swapping each port.  
The TDA9983B can be set to latch data at either the rising or falling edge or both.  
The video input formats accept (see Table 5):  
• RGB  
• YCBCR 4 : 4 : 4 (up to 3 × 8-bit)  
• YCBCR 4 : 2 : 2 semi-planar (up to 2 × 12-bit)  
• YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
8 of 119  
 
 
 
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 5.  
Inputs of video input formatter  
Color  
space  
Format  
Channels  
Sync  
Rising  
edge  
Falling  
edge  
Double  
edge[1]  
Transmission  
input format  
Max. pixel clock  
on pin VCLK  
(MHz)  
Max. input Reference  
format  
RGB  
4 : 4 : 4  
3 × 8-bit  
external  
X
X
X
X
X
150  
Table 6  
Table 7  
external  
X
X
X
X
X
150  
embedded  
embedded  
external  
150  
150  
YCBCR  
4 : 4 : 4  
3 × 8-bit  
150  
external  
150  
embedded  
embedded  
150  
150  
YCBCR  
4 : 2 : 2  
up to 1 × 12-bit external  
ITU656-like  
ITU656-like  
ITU656-like  
ITU656-like  
ITU656-like  
ITU656-like  
ITU656-like  
54.054  
54.054  
27.027  
54.054  
54.054  
27.027  
148.5  
148.5  
148.5  
148.5  
480p/576p  
480p/576p  
480p/576p  
480p/576p  
480p/576p  
480p/576p  
1080p  
Table 8  
external  
external  
embedded  
X
X
Table 9  
X
Table 10  
embedded  
X
embedded  
Table 11  
Table 12  
up to 2 × 12-bit external  
semi-planar  
X
X
external  
X
X
1080p  
embedded  
embedded  
SMPTE293M  
SMPTE293M  
1080p  
Table 13  
1080p  
[1] Double edge means both rising and falling edges.  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 6.  
RGB 4 : 4 : 4 mappings  
RGB 4 : 4 : 4 (3 × 8-bit) external synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
Video port A  
Pin  
Video port B  
RGB 4 : 4 : 4 Pin  
Video port C  
RGB 4 : 4 : 4 Pin  
Control  
RGB 4 : 4 : 4 Pin  
RGB 4 : 4 : 4  
HSYNC/HREF used  
VSYNC/VREF used  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
B[0]  
B[1]  
B[2]  
B[3]  
B[4]  
B[5]  
B[6]  
B[7]  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
VPB[6]  
VPB[7]  
G[0]  
G[1]  
G[2]  
G[3]  
G[4]  
G[5]  
G[6]  
G[7]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
R[0]  
R[1]  
R[2]  
R[3]  
R[4]  
R[5]  
R[6]  
R[7]  
DE/FREF  
used  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
B0  
G0  
R0  
B1  
G1  
R1  
B2  
G2  
R2  
B3  
G3  
R3  
...  
...  
...  
Bxxx  
Gxxx  
Rxxx  
Bxxx  
Gxxx  
Rxxx  
001aag380  
DE could also be generated from HSYNC/HREF and VSYNC/VREF  
Fig 3. Pixel encoding in RGB 4 : 4 : 4 (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
10 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 7.  
YCBCR 4 : 4 : 4 mappings  
YCBCR 4 : 4 : 4 (3 × 8-bit) external synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
Video port A  
Video port B  
Video port C  
Control  
Pin  
YCBCR 4 : 4 : 4 Pin  
YCBCR 4 : 4 : 4 Pin  
YCBCR 4 : 4 : 4 Pin  
YCBCR 4 : 4 : 4  
used  
VPA[0] CB[0]  
VPA[1] CB[1]  
VPA[2] CB[2]  
VPA[3] CB[3]  
VPA[4] CB[4]  
VPA[5] CB[5]  
VPA[6] CB[6]  
VPA[7] CB[7]  
VPB[0] Y[0]  
VPB[1] Y[1]  
VPB[2] Y[2]  
VPB[3] Y[3]  
VPB[4] Y[4]  
VPB[5] Y[5]  
VPB[6] Y[6]  
VPB[7] Y[7]  
VPC[0] CR[0]  
VPC[1] CR[1]  
VPC[2] CR[2]  
VPC[3] CR[3]  
VPC[4] CR[4]  
VPC[5] CR[5]  
VPC[6] CR[6]  
VPC[7] CR[7]  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
used  
used  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
C 0  
B
C 1  
B
C 2  
B
C 3  
B
...  
...  
...  
C xxx  
B
C xxx  
B
Y0  
Y1  
Y2  
Y3  
Yxxx  
Yxxx  
C 0  
R
C 1  
R
C 2  
R
C 3  
R
C xxx  
R
C xxx  
R
001aag381  
DE could also be generated from HSYNC/HREF and VSYNC/VREF  
Fig 4. Pixel encoding in YCBCR 4 : 4 : 4 (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
11 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 8.  
YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge mappings  
YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2  
VPA[0] CB[0]  
VPA[1] CB[1]  
VPA[2] CB[2]  
VPA[3] CB[3]  
VPA[4] -  
Y0[0] CR[0]  
Y0[1] CR[1]  
Y0[2] CR[2]  
Y0[3] CR[3]  
Y1[0] VPB[0] CB[4]  
Y1[1] VPB[1] CB[5]  
Y1[2] VPB[2] CB[6]  
Y1[3] VPB[3] CB[7]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF used  
VSYNC/VREF used  
DE/FREF  
used  
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]  
VPB[5] CB[9]  
VPA[5] -  
VPA[6] -  
VPB[6] CB[10] Y0[10] CR[10] Y1[10]  
VPB[7] CB[11] Y0[11] CR[11] Y1[11]  
VPA[7] -  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
R
Y1  
...  
C xxx  
R
Yxxx  
001aag383  
Fig 5. Pixel encoding YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
12 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 9.  
YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge mappings  
YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2  
VPA[0] CB[0]  
VPA[1] CB[1]  
VPA[2] CB[2]  
VPA[3] CB[3]  
VPA[4] -  
Y0[0] CR[0]  
Y0[1] CR[1]  
Y0[2] CR[2]  
Y0[3] CR[3]  
Y1[0] VPB[0] CB[4]  
Y1[1] VPB[1] CB[5]  
Y1[2] VPB[2] CB[6]  
Y1[3] VPB[3] CB[7]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF used  
VSYNC/VREF used  
DE/FREF  
used  
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]  
VPB[5] CB[9]  
VPA[5] -  
VPA[6] -  
VPB[6] CB[10] Y0[10] CR[10] Y1[10]  
VPB[7] CB[11] Y0[11] CR[11] Y1[11]  
VPA[7] -  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
R
Y1  
...  
C xxx  
R
Yxxx  
001aag382  
Fig 6. Pixel encoding YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge (rising and falling) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
13 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 10. YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge mappings  
YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
YCBCR 4 : 2 : 2  
VPA[0] CB[0]  
VPA[1] CB[1]  
VPA[2] CB[2]  
VPA[3] CB[3]  
VPA[4] -  
Y0[0] CR[0]  
Y0[1] CR[1]  
Y0[2] CR[2]  
Y0[3] CR[3]  
Y1[0] VPB[0] CB[4]  
Y1[1] VPB[1] CB[5]  
Y1[2] VPB[2] CB[6]  
Y1[3] VPB[3] CB[7]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF not used  
VSYNC/VREF not used  
DE/FREF  
not used  
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]  
VPB[5] CB[9]  
VPA[5] -  
VPA[6] -  
VPB[6] CB[10] Y0[10] CR[10] Y1[10]  
VPB[7] CB[11] Y0[11] CR[11] Y1[11]  
VPA[7] -  
VCLK  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
R
Y1  
...  
C xxx  
R
Yxxx  
001aag385  
Fig 7. Pixel encoding YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
14 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 11. YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge mappings  
YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
Pin  
YCBCR 4 : 2 : 2 (ITU656-like)  
YCBCR 4 : 2 : 2  
VPA[0] CB[0]  
VPA[1] CB[1]  
VPA[2] CB[2]  
VPA[3] CB[3]  
VPA[4] -  
Y0[0] CR[0]  
Y0[1] CR[1]  
Y0[2] CR[2]  
Y0[3] CR[3]  
Y1[0] VPB[0] CB[4]  
Y1[1] VPB[1] CB[5]  
Y1[2] VPB[2] CB[6]  
Y1[3] VPB[3] CB[7]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF not used  
VSYNC/VREF not used  
DE/FREF  
not used  
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]  
VPB[5] CB[9]  
VPA[5] -  
VPA[6] -  
VPB[6] CB[10] Y0[10] CR[10] Y1[10]  
VPB[7] CB[11] Y0[11] CR[11] Y1[11]  
VPA[7] -  
VCLK  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
R
Y1  
...  
C xxx  
R
Yxxx  
001aag384  
Fig 8. Pixel encoding YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge (rising and falling)  
input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
15 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 12. YCBCR 4 : 2 : 2 semi-planar external synchronization mappings  
YCBCR 4 : 2 : 2 semi-planar external synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.  
Video port A  
Video port B  
Pin YCBCR 4 : 2 : 2  
semi-planar  
Video port C  
Control  
Pin  
YCBCR 4 : 2 : 2  
semi-planar  
Pin  
YCBCR 4 : 2 : 2  
semi-planar  
Pin  
YCBCR  
4 : 2 : 2  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
Y0[0]  
Y0[1]  
Y0[2]  
Y0[3]  
CB[0]  
CB[1]  
CB[2]  
CB[3]  
Y1[0]  
VPB[0] Y0[4]  
VPB[1] Y0[5]  
VPB[2] Y0[6]  
VPB[3] Y0[7]  
VPB[4] Y0[8]  
VPB[5] Y0[9]  
VPB[6] Y0[10]  
VPB[7] Y0[11]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Y1[10]  
Y1[11]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
CB[4]  
CB[5]  
CB[6]  
CB[7]  
CB[8]  
CB[9]  
CB[10]  
CB[11]  
CR[4]  
HSYNC/HREF used  
VSYNC/VREF used  
Y1[1]  
Y1[2]  
Y1[3]  
CR[0]  
CR[1]  
CR[2]  
CR[3]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
CR[10]  
CR[11]  
DE/FREF  
used  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
VPC[7:0]; VPA[7:4]  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
...  
...  
C 0  
B
C 0  
R
C 2  
B
C 2  
R
C 4  
B
C 4  
R
001aag386  
Fig 9. Pixel encoding YCBCR 4 : 2 : 2 semi-planar external synchronization (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
16 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 13. YCBCR 4 : 2 : 2 semi-planar embedded synchronization mappings  
YCBCR 4 : 2 : 2 semi-planar embedded synchronization single edge.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.  
Video port A  
Video port B  
Pin YCBCR 4 : 2 : 2  
semi-planar  
Video port C  
Control  
Pin  
YCBCR 4 : 2 : 2  
semi-planar  
Pin  
YCBCR 4 : 2 : 2  
semi-planar  
Pin  
YCBCR  
4 : 2 : 2  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
Y0[0]  
Y0[1]  
Y0[2]  
Y0[3]  
CB[0]  
CB[1]  
CB[2]  
CB[3]  
Y1[0]  
VPB[0] Y0[4]  
VPB[1] Y0[5]  
VPB[2] Y0[6]  
VPB[3] Y0[7]  
VPB[4] Y0[8]  
VPB[5] Y0[9]  
VPB[6] Y0[10]  
VPB[7] Y0[11]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Y1[10]  
Y1[11]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
CB[4]  
CB[5]  
CB[6]  
CB[7]  
CB[8]  
CB[9]  
CB[10]  
CB[11]  
CR[4]  
HSYNC/HREF not used  
VSYNC/VREF not used  
Y1[1]  
Y1[2]  
Y1[3]  
CR[0]  
CR[1]  
CR[2]  
CR[3]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
CR[10]  
CR[11]  
DE/FREF  
not used  
VCLK  
VPB[7:0]; VPA[3:0]  
VPC[7:0]; VPA[7:4]  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
...  
...  
C 0  
B
C 0  
R
C 2  
B
C 2  
R
C 4  
B
C 4  
R
001aag387  
Fig 10. Pixel encoding YCBCR 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
17 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
8.3 Synchronization  
The TDA9983B can be synchronized with Hsync/Vsync external inputs or with extraction  
of the sync information from embedded sync (SAV/EAV) codes inside the video stream.  
8.3.1 Timing extraction generator  
This block can extract the synchronization signals Href, Vref and Fref from Start Active  
Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data  
stream. Synchronization signals can be embedded in RGB, YCBCR 4 : 4 : 4, YCBCR  
4 : 2 : 2 semi-planar (up to 2 × 12-bit), YCBCR 4 : 2 : 2 ITU656 and ITU656-like (up to  
1 × 12-bit).  
8.3.2 Data enable generator  
The TDA9983B contains a Data Enable (DE) generator; this can generate an internal DE  
signal for a system which does not provide one.  
8.4 Input and output video format  
Due to the flexible video input formatter, the TDA9983B can accept a large range of input  
formats. This flexibility allows the TDA9983B to be compatible with the maximum possible  
number of MPEG decoders. Moreover, these input formats may be changed in many ways  
(color space converter, upsampler, downsampler and scaler) to be transmitted across the  
HDMI link. Table 14 gives the possible inputs and outputs.  
Table 14. Use of color space converter, upsampler, downsampler and scaler  
Input  
Scaler  
Output  
Color space  
RGB  
Color space Format Channels  
Format Channels  
4 : 4 : 4 3 × 8-bit  
4 : 2 : 2 2 × 12-bit  
4 : 4 : 4 3 × 8-bit  
4 : 4 : 4 3 × 8-bit  
4 : 2 : 2 2 × 12-bit  
4 : 4 : 4 3 × 8-bit  
4 : 2 : 2 2 × 12-bit  
4 : 4 : 4 3 × 8-bit  
4 : 4 : 4 3 × 8-bit  
4 : 2 : 2 2 × 12-bit  
4 : 4 : 4 3 × 8-bit  
4 : 4 : 4 3 × 8-bit  
RGB  
4 : 4 : 4 3 × 8-bit  
4 : 4 : 4 3 × 8-bit  
4 : 2 : 2 up to 1 × 12-bit  
up to 2 × 12-bit  
no scaling  
no scaling  
no scaling  
no scaling  
no scaling  
no scaling  
scalable  
YCBCR  
YCBCR  
RGB  
YCBCR  
YCBCR  
YCBCR  
YCBCR  
YCBCR  
YCBCR  
RGB  
scalable  
scalable  
scalable  
YCBCR  
YCBCR  
RGB  
scalable  
scalable  
8.5 Upsampler  
The incoming YCBCR 4 : 2 : 2 (2 × 12-bit) data stream format could be upsampled into a  
12-bit YCBCR 4 : 4 : 4 (3 × 12-bit) data stream by repeating or linearly interpolating the  
chrominance pixels.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
18 of 119  
 
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
8.6 Color space converter  
The color space converter is used to convert input video data from one type to another  
color space (RGB to YCBCR and YCBCR to RGB). This block can be bypassed and each  
coefficient is programmable via the I2C-bus register.  
OinG\Y  
OinR\C  
OoutY \G  
C11 C12 C13  
C21 C22 C23  
C31 C32 C33  
Y\G  
G\Y  
OoutC \R  
CB\R =  
×
R\CB  
+
+
B
B
CR\B  
B\CR  
OinB\C  
OoutC \B  
R
R
8.7 Downsampler  
This block works only with YCBCR input format; these filters downsample the CB and CR  
signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the  
pipeline delay of the filters, to put the Y channel in phase with the CB-CR channels.  
8.8 Audio input format  
The TDA9983B is compatible with HDMI 1.2a (DVD support). The TDA9983B can carry  
audio in I2S-bus format (one stereo up to four stereo channels) or in S/PDIF format.  
S/PDIF or I2S-bus format can be selected via the I2C-bus. Only one audio format can be  
used at a time: either S/PDIF or I2S-bus. Table 15 shows the audio port allocation.  
Table 15. Audio port configuration  
All audio ports are LV-TTL compatible.  
Audio port  
AP0  
I2S-bus and S/PDIF input configuration  
WS (word select)  
AP1  
I2S-bus audio port 0  
AP2  
I2S-bus audio port 1  
AP3  
I2S-bus audio port 2  
AP4  
I2S-bus audio port 3  
AP5  
MCLK (master clock for S/PDIF)  
S/PDIF input  
AP6  
AP7  
AUX (internal test)  
ACLK  
SCK (I2S-bus clock)  
8.9 S/PDIF  
The audio port AP6 is used for the S/PDIF feature. In this format the TDA9983B supports  
2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream up to  
8 multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9983B is able to  
recover the original clock from the S/PDIF signal (no need for an external clock). In  
addition it can also use an external clock (MCLK) to decode the S/PDIF signal.  
8.10 I2S-bus  
The TDA9983B supports the NXP I2S-bus format. There are four I2S-bus stereo input  
channels (AP1 to AP4), which enable 8 uncompressed audio channels to be carried. The  
I2S-bus input interface receives an I2S-bus signal including serial data, word select and  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
19 of 119  
 
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
serial clock. Various I2S-bus formats are supported and can be selected by setting the  
appropriate bits of the register. The I2S-bus input interface can receive up to 24-bit wide  
audio samples via the serial data input with a clock frequency of at least 32 times the input  
sample frequency fs. Since the I2S-bus format is MSB aligned, audio data with an arbitrary  
precision can be received automatically. Audio samples with a precision better than 24  
bits are truncated to 24 bits. If the input clock has a frequency of 32 × fs, only 16-bit audio  
samples can be received. In this case, the 8 LSBs will be set to logic 0. The serial data  
signal carries the serial baseband audio data, sample by sample left/right interleaved. The  
word select signal WS indicates whether left or right channel information is transferred  
over the serial data line. The formats for 16-bit and 32-bit modes are shown in Figure 11.  
AP0/WS  
ACLK  
left channel  
right channel  
0
R
B23  
B0  
L
0
L
0
L
0
L
B23  
B0  
R
0
R
0
R
0
R
B23  
L
APx  
L
R
x = 1, 2, 3, 4  
001aag915  
a. 32-bit mode  
AP0/WS  
left channel  
right channel  
ACLK  
B0  
R
B15  
B14  
B13  
B2  
L
B1  
L
B0  
L
B15  
B14  
B13  
B2  
R
B1  
R
B0  
R
B15  
L
APx  
L
L
L
R
R
R
x = 1, 2, 3, 4  
001aag916  
b. 16-bit mode  
Fig 11. NXP I2S-bus formats  
8.11 Power management  
The TDA9983B can be powered down via the I2C-bus register.  
8.12 Interrupt controller  
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has  
occurred (hot plug detect). This interrupt is maskable.  
Hot plug or unplug detect: pin HPD is the hot plug detection pin; it is 5 V input tolerant.  
8.13 Initialization  
Hard reset: after power-up, the TDA9983B is activated by a hard reset via pin RST_N.  
However, the TDA9983B has a power-on reset.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
20 of 119  
 
 
 
 
TDA9983B  
NXP Semiconductors  
8.14 HDMI  
150 MHz pixel rate HDMI transmitter  
8.14.1 Output HDMI buffers  
An external resistor must be used to set the HDMI output amplitude. It has to be  
connected between pin EXT_SWING and VDDH(3V3)  
.
8.14.2 Pixel repetition  
To transmit video formats with pixel rates below 25 Msample/s or to increase the number  
of audio sample packets in each frame, the TDA9983B uses pixel repetition to increase  
the transmitted pixel clock.  
Table 16. Pixel repetition  
SRL_PR[3]  
SRL_PR[2]  
SRL_PR[1]  
SRL_PR[0]  
Pixel repeated  
no repetition  
once  
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
x
0
1
0
1
0
1
0
1
0
1
x
x
twice  
3 times  
4 times  
5 times  
6 times  
7 times  
8 times  
9 times  
undefined  
undefined  
8.14.3 HDMI and DVI receiver discrimination  
This information is located in the E-EDID receiver part, in the ‘Vendor-Specific Data block’  
within the first CEA EDID timing extension. If the 24-bit IEEE registration identifier  
contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device  
will be treated as a DVI device. However, the TDA9983B does not have direct access to  
that information since E-EDID is read by an external microprocessor through the  
TDA9983B I2C-bus gate.  
8.14.4 DDC channel  
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard  
mode (100 kHz).  
8.14.4.1 E-EDID reading  
In order to get receiver capabilities, the TDA9983B must read the E-EDID of the receiver.  
This is made possible by temporarily connecting the I2C-bus to the DDC lines, so that the  
microprocessor is able to read full EDID.  
8.15 Scaler unit  
The scaler unit has the following features:  
• Upscaling only: to expand input image horizontally and vertically  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
21 of 119  
 
 
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
• Embedded deinterlacer (no need for output memory)  
• Maximum output operating frequency: 74.5 MHz (HDTV supported 1080i, 720p)  
• Input video standards (YCBCR 4 : 2 : 2 semi-planar, ITU656 and ITU656-like YCBCR,  
no RGB and no YCBCR 4 : 4 : 4)  
8.16 Input and output video scaler  
The scaler converts the standard definition video signals (480i/576i, 480p/576p) into  
720p, 1080i as illustrated in Figure 12.  
VIDEO STANDARD OUTPUT  
FORMAT  
861B  
FORMAT  
861B  
(1) (2) (3)  
2, 3  
720  
1280  
1920  
720  
×
×
×
×
480p  
720p  
1080i  
480i  
(1)  
4
(1)  
5
6, 7 (NTSC)  
16  
(4) (5) (6) (1)  
(1)  
1920 × 1080p  
(1) (2) (3)  
17, 18  
19  
720  
1280  
1920  
×
×
×
×
576p  
720p  
1080i  
576i  
(1)  
(1)  
20  
(4) (5) (6) (1)  
21, 22 (PAL) 720  
31  
(1)  
001aag258  
1920 × 1080p  
All upscaling modes are available only for YCBCR 4 : 2 : 2 input format.  
(1) Pass through  
(2) Upscaling  
(3) Upscaling and interlacing  
(4) Deinterlacing  
(5) Deinterlacing and upscaling  
(6) Deinterlacing, upscaling and interlacing  
Fig 12. Input and output video scaler  
8.17 I2C-bus interface  
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode  
(400 kHz).  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
22 of 119  
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9. I2C-bus register definitions  
9.1 I2C-bus protocol  
The registers of the TDA9983B can be accessed via the I2C-bus. The TDA9983B is used  
as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are  
supported.  
Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1.  
The I2C-bus device address is given in Table 17.  
Table 17. Device address  
Device address  
R/W  
-
A6  
1
A5  
1
A4  
1
A3  
0
A2  
0
A1  
A1  
A0  
A0  
1/0  
The I2C-bus access format is shown in Figure 13.  
For read access, the master writes the address of the TDA9983B, the subaddress to  
access the specific register and then the data.  
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9  
SCL  
SDA  
SLAVE ADDRESS  
SUBADDRESS  
DATA  
STOP  
001aaf292  
Fig 13. I2C-bus access  
9.2 Memory page management  
The I2C-bus memory is split into several pages and the selection between pages is made  
with common register CURPAGE_ADR. It is only necessary to write in this register once  
to change the current page. So multiple read or write operations in the same page need a  
write register CURPAGE_ADR once at the beginning.  
Table 18. Memory pages  
Page address Memory page description  
Reference  
00h  
01h  
02h  
10h  
11h  
12h  
General control  
see Section 9.3 on page 23  
see Section 9.4 on page 43  
see Section 9.5 on page 55  
see Section 9.6 on page 63  
see Section 9.7 on page 81  
see Section 9.8 on page 98  
Scaler  
PLL settings  
Information frames and packets  
Audio settings and content info packets  
HDMI and DVI  
9.3 General control page register definitions  
The current page address for the general control page is 00h.  
The configuration of the registers for this page is given in Table 19.  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
23 of 119  
 
 
 
 
 
 
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 19. I2C-bus registers of memory page 00h[1]  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
0
6
1
x
5
1
x
4
0
3
0
2
0
1
1
0 (LSB)  
VERSION  
00h  
01h  
02h  
:
R
W
-
0
0110 0010  
0000 0000  
0000 0000  
:
MAIN_CNTRL0  
Not used  
SCALER  
CEHS  
CECS  
DEHS  
DECS  
SR  
-
:
:
:
Not used  
0Eh  
-
-
0000 0000  
0000 0000  
INT_FLAGS_0  
INT_FLAGS_1  
Not used  
0Fh R/W  
10h R/W  
x
x
x
x
x
x
x
HPD  
x
x
HPD_IN  
SC_DEIL  
SC_VID  
SC_OUT  
SC_IN  
VS_RPT 0000 0000  
0000 0000  
:
11h  
:
-
-
:
:
:
Not used  
1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
:
-
-
0000 0000  
0000 0001  
0010 0100  
0101 0110  
VIP_CNTRL_0  
VIP_CNTRL_1  
VIP_CNTRL_2  
VIP_CNTRL_3  
VIP_CNTRL_4  
VIP_CNTRL_5  
Not used  
W
W
W
W
W
W
-
MIRR_A  
MIRR_C  
MIRR_E  
EDGE  
SWAP_A[2:0]  
SWAP_C[2:0]  
SWAP_E[2:0]  
MIRR_B  
MIRR_D  
MIRR_F  
EMB  
SWAP_B[2:0]  
SWAP_D[2:0]  
SWAP_F[2:0]  
H_TGL  
x
TST_656  
x
SP_SYNC[1:0]  
V_TGL  
X_TGL  
0001 0110  
0000 0001  
TST_PAT  
x
x
x
CCIR656  
x
BLANKIT[1:0]  
BLC[1:0]  
x
SP_CNT[1:0]  
CKCASE 0000 0000  
-
:
0000 0000  
:
:
:
Not used  
7Fh  
80h  
81h  
82h  
83h  
84h  
85h  
86h  
87h  
88h  
89h  
8Ah  
8Bh  
8Ch  
-
-
0000 0000  
MAT_CONTRL  
MAT_OI1_MSB  
MAT_OI1_LSB  
MAT_OI2_MSB  
MAT_OI2_LSB  
MAT_OI3_MSB  
MAT_OI3_LSB  
MAT_P11_MSB  
MAT_P11_LSB  
MAT_P12_MSB  
MAT_P12_LSB  
MAT_P13_MSB  
MAT_P13_LSB  
W
W
W
W
W
W
W
W
W
W
W
W
W
x
x
x
x
x
x
x
x
x
x
MAT_BP  
MAT_SC[1:0]  
0000 0101  
0000 0000  
0000 0000  
0000 0110  
0000 0000  
0000 0110  
0000 0000  
0000 0010  
0000 0000  
0000 0110  
1001 0010  
0000 0111  
0101 0000  
OFFSET_IN1[10:8]  
OFFSET_IN2[10:8]  
OFFSET_IN3[10:8]  
P11[10:8]  
OFFSET_IN1[7:0]  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
OFFSET_IN2[7:0]  
x
x
OFFSET_IN3[7:0]  
x
x
x
x
x
x
P11[7:0]  
P12[7:0]  
P13[7:0]  
P12[10:8]  
P13[10:8]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 19. I2C-bus registers of memory page 00h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
MAT_P21_MSB  
MAT_P21_LSB  
MAT_P22_MSB  
MAT_P22_LSB  
MAT_P23_MSB  
MAT_P23_LSB  
MAT_P31_MSB  
MAT_P31_LSB  
MAT_P32_MSB  
MAT_P32_LSB  
MAT_P33_MSB  
MAT_P33_LSB  
MAT_OO1_MSB  
MAT_OO1_LSB  
MAT_OO2_MSB  
MAT_OO2_LSB  
MAT_OO3_MSB  
MAT_OO3_LSB  
Not used  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
A0h  
A1h  
A2h  
A3h  
A4h  
A5h  
A6h  
A7h  
A8h  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-
x
x
x
x
x
P21[10:8]  
0000 0010  
0000 0000  
0000 0010  
1100 1110  
0000 0000  
0000 0000  
0000 0010  
0000 0000  
0000 0000  
0000 0000  
0000 0011  
1000 1100  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0001  
0000 0000  
0000 0001  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
P21[7:0]  
P22[7:0]  
P23[7:0]  
P31[7:0]  
P32[7:0]  
P33[7:0]  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
P22[10:8]  
P23[10:8]  
P31[10:8]  
P32[10:8]  
P33[10:8]  
OFFSET_OUT1[10:8]  
OFFSET_OUT2[10:8]  
OFFSET_OUT3[10:8]  
-
OFFSET_OUT1[7:0]  
x
x
OFFSET_OUT2[7:0]  
x
x
OFFSET_OUT3[7:0]  
-
-
-
-
-
-
-
VIDFORMAT  
W
W
W
W
W
W
W
W
W
W
W
W
W
x
x
x
x
x
x
VIDFORMAT[4:0]  
REFPIX_MSB  
REFPIX_LSB  
REFLINE_MSB  
REFLINE_LSB  
NPIX_MSB  
PRESET_PIX[12:8]  
PRESET_PIX[7:0]  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PRESET_LINE[10:8]  
NPIX[12:8]  
PRESET_LINE[7:0]  
NPIX_LSB  
NPIX[7:0]  
NLINE_MSB  
x
x
x
x
NLINE[10:8]  
VS_LINE_START_1[10:8]  
NLINE_LSB  
NLINE[7:0]  
VS_LINE_STRT_1_MSB A9h  
VS_LINE_STRT_1_LSB AAh  
VS_LINE_START_1[7:0]  
VS_PIX_START_1[12:8]  
VS_PIX_START_1[7:0]  
VS_PIX_STRT_1_MSB  
VS_PIX_STRT_1_LSB  
ABh  
ACh  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 19. I2C-bus registers of memory page 00h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
VS_LINE_END_1_MSB  
VS_LINE_END_1_LSB  
VS_PIX_END_1_MSB  
VS_PIX_END_1_LSB  
ADh  
AEh  
AFh  
B0h  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
x
x
x
x
x
VS_LINE_END_1[10:8]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
VS_LINE_END_1[7:0]  
VS_PIX_END_1[12:8]  
VS_PIX_END_1[7:0]  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
VS_LINE_STRT_2_MSB B1h  
VS_LINE_STRT_2_LSB B2h  
x
x
VS_LINE_START_2[10:8]  
VS_LINE_START_2[7:0]  
VS_PIX_STRT_2_MSB  
VS_PIX_STRT_2_LSB  
VS_LINE_END_2_MSB  
VS_LINE_END_2_LSB  
VS_PIX_END_2_MSB  
VS_PIX_END_2_LSB  
HS_PIX_START_MSB  
HS_PIX_START_LSB  
HS_PIX_STOP_MSB  
HS_PIX_STOP_LSB  
VWIN_START_1_MSB  
VWIN_START_1_LSB  
VWIN_END_1_MSB  
VWIN_END_1_LSB  
VWIN_START_2_MSB  
VWIN_START_2_LSB  
VWIN_END_2_MSB  
VWIN_END_2_LSB  
DE_START_MSB  
B3h  
B4h  
B5h  
B6h  
B7h  
B8h  
B9h  
BAh  
BBh  
BCh  
BDh  
BEh  
BFh  
C0h  
C1h  
C2h  
C3h  
C4h  
C5h  
C6h  
C7h  
C8h  
C9h  
CAh  
VS_PIX_START_2[12:8]  
VS_PIX_START_2[7:0]  
x
x
VS_LINE_END_2[10:8]  
VS_LINE_END_2[7:0]  
VS_PIX_END_2[12:8]  
VS_PIX_END_2[7:0]  
HS_PIX_START[7:0]  
HS_PIX_END[7:0]  
HS_PIX_START[12:8]  
HS_PIX_END[12:8]  
x VWIN_START_1[10:8]  
x
VWIN_START_1[7:0]  
x
x
VWIN_END_1[10:8]  
VWIN_START_2[10:8]  
VWIN_END_2[10:8]  
VWIN_END_1[7:0]  
x
x
VWIN_START_2[7:0]  
x
x
VWIN_END_2[7:0]  
DE_START[12:8]  
DE_START_LSB  
DE_START[7:0]  
DE_STOP_MSB  
DE_END[12:8]  
DE_STOP_LSB  
DE_END[7:0]  
CBW[7:0]  
COLBAR_WIDTH  
TBG_CNTRL_0  
SYNC_  
ONCE  
SYNC_  
MTHD  
FRAME_  
DIS  
x
x
x
x
x
TBG_CNTRL_1  
CBh  
W
x
DWIN_DIS  
VHX_EXT[2:0]  
VH_TGL[2:0]  
0000 0000  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 19. I2C-bus registers of memory page 00h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
VBL_OFFSET_START  
VBL_OFFSET_END  
HBL_OFFSET_START  
HBL_OFFSET_END  
DWIN_RE_DE  
DWIN_FE_DE  
Not used  
CCh  
CDh  
CEh  
CFh  
D0h  
D1h  
D2h  
:
W
W
W
W
W
W
-
VBLOFF_START[7:0]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0001 0001  
0111 1010  
0000 0000  
:
VBLOFF_END[7:0]  
HBLOFF_START[7:0]  
HBLOFF_END[7:0]  
DWIN_RE_DE[7:0]  
DWIN_FE_DE[7:0]  
-
:
:
:
Not used  
E3h  
E4h  
E5h  
-
-
0000 0000  
0000 0000  
0x00 0000  
HVF_CNTRL_0  
HVF_CNTRL_1  
W
W
SM  
x
RWB  
x
x
x
x
PREFIL[1:0]  
VQR[1:0]  
INTPOL[1:0]  
SEMI_  
PLANAR  
PAD[1:0]  
YUVBLK  
FOR  
Not used  
Not used  
TIMER_H  
E6h  
E7h  
E8h  
-
-
-
-
0000 0000  
0000 0000  
xx00 0001  
W
IM_  
WD_  
x
x
TIM_H[1:0]  
CLKSEL  
CLKSEL  
TIMER_M  
TIMER_L  
Not used  
:
E9h  
EAh  
EBh  
:
W
W
-
TIM_M[7:0]  
1100 0010  
0100 0000  
0000 0000  
:
TIM_L[7:0]  
-
:
:
Not used  
NDIV_IM  
NDIV_PF  
RPT_CNTRL  
LEAD_OFF  
TRAIL_OFF  
Not used  
:
EDh  
EEh  
EFh  
F0h  
F1h  
F2h  
F3h  
:
-
-
0000 0000  
0000 0011  
0001 1011  
0000 0000  
0000 0010  
0000 0010  
0000 0000  
:
W
W
W
W
W
-
x
x
x
x
NDIV_IM[3:0]  
REPEAT[3:0]  
NDIF_PF[7:0]  
x
x
x
x
x
x
x
x
x
x
x
x
-
LEAD_OFFSET[3:0]  
TRAIL_OFFSET[3:0]  
:
:
Not used  
For test  
F7h  
F8h  
F9h  
FAh  
FBh  
-
-
0000 0000  
0000 0000  
W
W
-
x
x
x
x
x
x
x
x
GHOST_XADDR  
Not used  
Not used  
GHOST_XADDR[6:0]  
A0_ZERO 0110 0000  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0000 0000  
0000 0000  
-
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 19. I2C-bus registers of memory page 00h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
-
5
-
4
3
2
1
0 (LSB)  
Not used  
FCh  
FDh  
-
-
-
-
-
-
-
0000 0000  
0000 0000  
AIP_CLKSEL  
W
x
x
x
SEL_AIP[1:0]  
GHOST_ADDR[6:0]  
CURPAGE_ADR[7:0]  
SEL_POL_  
CLK  
SEL_FS[1:0]  
GHOST_ADDR  
CURPAGE_ADR  
FEh  
FFh  
W
W
GHOST_ 1010 0001  
DIS  
0000 0000  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.3.1 Main control register  
Table 20. VERSION register (address 00h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 4  
3 to 0  
-
-
R
R
0110  
0010  
TDA9983B device version  
die version  
Table 21. MAIN_CNTRL0 register (address 01h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
scaler  
7
SCALER  
W
0*  
HDMI video formatter uses vip-output (scaler is  
bypassed)  
1
HDMI video formatter uses scaler-output  
undefined  
6 to 5  
4
x
W
W
00*  
I2C-bus enable high speed  
CEHS  
0*  
1
I2C_SDA and I2C_SCL set to Standard or Fast  
mode  
I2C_SDA and I2C_SCL set to High-speed mode  
I2C-bus enable current source  
3
2
CECS  
DEHS  
W
W
0*  
1
I2C_SCL pull-up current source disabled  
I2C_SCL pull-up current source enabled  
DDC-bus enable high speed  
0*  
1
DDC_SDA and DDC_SCL set to Standard or  
Fast mode  
DDC_SDA and DDC_SCL set to High-speed  
mode  
1
0
DECS  
SR  
W
W
DDC-bus enable current source  
DDC_SCL pull-up current source disabled  
DDC_SCL pull-up current source enabled  
soft reset  
0*  
1
0*  
1
no specific action  
soft reset for all modules which do not use the  
cclk clock domain  
9.3.2 Interrupt flags/masks registers  
Table 22. INT_FLAGS_0 register (address 0Fh) bit description  
Legend: * = default value  
Bit  
7 to 2  
1
Symbol  
x
Access Value  
Description  
0000 00* undefined  
HPD: transition on HPD input  
R/W  
R/W  
HPD  
0*  
1
FALSE/INT_disabled  
TRUE/INT_enabled  
undefined  
0
x
R/W  
0*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
29 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 23. INT_FLAGS_1 register (address 10h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7
HPD_IN  
R/W  
0*  
HPD input: transition on HPD input  
HPD is LOW  
1
HPD is HIGH  
6
5
x
R/W  
R/W  
0*  
undefined  
SC_DEIL  
scaler deinterlace: scaler deinterlaced video  
buffer failure  
0*  
1
FALSE/INT_disabled  
TRUE/INT_enabled  
4
3
2
SC_VID  
SC_OUT  
SC_IN  
R/W  
R/W  
R/W  
scaler video: scaler primary video buffer full failure  
FALSE/INT_disabled  
0*  
1
TRUE/INT_enabled  
scaler output: scaler output failure  
FALSE/INT_disabled  
0*  
1
TRUE/INT_enabled  
scaler input: scaler input failure  
FALSE/INT_disabled  
0*  
1
TRUE/INT_enabled  
1
0
x
R/W  
R/W  
0*  
undefined  
VS_RPT  
rising edge on VS_RPT detected  
FALSE/INT_disabled  
0*  
1
TRUE/INT_enabled  
9.3.3 Video input processing control registers  
Table 24. VIP_CNTRL_0 register (address 20h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7
MIRR_A  
W
W
mirror A  
no specific action  
0*  
1
mirror nibble; m[23:20] = s[20:23]  
swap A selector  
6 to 4  
SWAP_A[2:0]  
000*  
001  
010  
011  
100  
other  
pin VPC[7:4] = vp[23:20]  
pin VPC[3:0] = vp[23:20]  
pin VPB[7:4] = vp[23:20]  
pin VPB[3:0] = vp[23:20]  
pin VPA[7:4] = vp[23:20]  
pin VPA[3:0] = vp[23:20]  
mirror B  
3
MIRR_B  
W
0*  
1
no specific action  
mirror nibble; m[19:16] = s[16:19]  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
30 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 24. VIP_CNTRL_0 register (address 20h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
swap B selector  
2 to 0  
SWAP_B[2:0]  
W
000  
001*  
010  
011  
100  
other  
pin VPC[7:4] = vp[19:16]  
pin VPC[3:0] = vp[19:16]  
pin VPB[7:4] = vp[19:16]  
pin VPB[3:0] = vp[19:16]  
pin VPA[7:4] = vp[19:16]  
pin VPA[3:0] = vp[19:16]  
Table 25. VIP_CNTRL_1 register (address 21h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7
MIRR_C  
W
W
mirror C  
no specific action  
0*  
1
mirror nibble; m[15:12] = s[12:15]  
swap C selector  
6 to 4  
SWAP_C[2:0]  
000  
001  
010*  
011  
100  
other  
pin VPC[7:4] = vp[15:12]  
pin VPC[3:0] = vp[15:12]  
pin VPB[7:4] = vp[15:12]  
pin VPB[3:0] = vp[15:12]  
pin VPA[7:4] = vp[15:12]  
pin VPA[3:0] = vp[15:12]  
mirror D  
3
MIRR_D  
W
W
0*  
1
no specific action  
mirror nibble; m[11:8] = s[8:11]  
swap D selector  
2 to 0  
SWAP_D[2:0]  
000  
001  
010  
011  
100*  
other  
pin VPC[7:4] = vp[11:8]  
pin VPC[3:0] = vp[11:8]  
pin VPB[7:4] = vp[11:8]  
pin VPB[3:0] = vp[11:8]  
pin VPA[7:4] = vp[11:8]  
pin VPA[3:0] = vp[11:8]  
Table 26. VIP_CNTRL_2 register (address 22h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7
MIRR_E  
W
0*  
1
mirror E  
no specific action  
mirror nibble; m[7:4] = s[4:7]  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
31 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 26. VIP_CNTRL_2 register (address 22h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
6 to 4  
SWAP_E[2:0]  
W
swap E selector  
000  
001  
010  
011  
100  
101*  
other  
W
pin VPC[7:4] = vp[7:4]  
pin VPC[3:0] = vp[7:4]  
pin VPB[7:4] = vp[7:4]  
pin VPB[3:0] = vp[7:4]  
pin VPA[7:4] = vp[7:4]  
pin VPA[3:0] = vp[7:4]  
pin VPA[3:0] = vp[7:4]  
mirror F  
3
MIRR_F  
0*  
no specific action  
1
mirror nibble; m[3:0] = s[0:3]  
swap F selector  
2 to 0  
SWAP_F[2:0]  
W
000  
001  
010  
011  
100  
110*  
other  
pin VPC[7:4] = vp[3:0]  
pin VPC[3:0] = vp[3:0]  
pin VPB[7:4] = vp[3:0]  
pin VPB[3:0] = vp[3:0]  
pin VPA[7:4] = vp[3:0]  
pin VPA[3:0] = vp[3:0]  
pin VPA[3:0] = vp[3:0]  
Table 27. VIP_CNTRL_3 register (address 23h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
edge  
7
EDGE  
W
0*  
vp-bus synchronized on positive edge of  
vip_clk_m  
1
vp-bus synchronized on negative edge of  
vip_clk_m  
6
x
W
W
0*  
undefined  
5 to 4  
SP_SYNC[1:0]  
sp synchronization  
00  
01*  
10  
11  
sp_cnt synchronized by hemb  
sp_cnt synchronized by rising edge de  
sp_cnt synchronized by rising edge of hs  
sp_cnt fixed at i2c_sp_cnt  
embedded  
3
2
EMB  
W
W
0*  
1
no specific action  
use embedded synchronization codes  
v_toggle  
V_TGL  
0
no specific action  
1*  
toggle vs/vref  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
32 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 27. VIP_CNTRL_3 register (address 23h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
h_toggle  
1
H_TGL  
W
0
no specific action  
toggle hs/href  
x_toggle  
1*  
W
0*  
1
0
X_TGL  
no specific action  
toggle de/fref  
Table 28. VIP_CNTRL_4 register (address 24h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7
TST_PAT  
W
W
test pattern  
0*  
1
no specific action  
insert test pattern with high data activity  
test 656: test mode (ITU656 via audio port AP)  
no specific action  
6
TST_656  
0*  
1
inject ITU656 video via audio port  
undefined  
5
4
x
W
W
0*  
CCIR656  
CCIR 656: ITU656 or ITU656-like at the input  
no specific action  
0*  
1
activate ITU data demultiplexing (from ITU656 or  
ITU656-like to 4 : 2 : 2 semi-planar)  
3 to 2  
BLANKIT[1:0]  
W
W
blankit: select source for blankit control  
not de  
00*  
01  
10  
11  
hs AND vs  
(not hs) AND vs  
hemb AND vemb  
1 to 0  
BLC[1:0]  
blanking codes  
00  
01*  
10  
11  
no insertion of blanking codes or test pattern  
blanking codes set to RGB 4 : 4 : 4 levels  
blanking codes set to YUV 4 : 4 : 4 levels  
blanking codes set to YUV 4 : 2 : 2 levels  
Table 29. VIP_CNTRL_5 register (address 25h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 3  
2 to 1  
x
W
W
0000 0* undefined  
SP_CNT[1:0]  
sp counter  
00*  
01  
10  
11  
sp_cnt preset to ’00’  
sp_cnt preset to ’01’  
sp_cnt preset to ’10’  
sp_cnt preset to ’11’  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
33 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 29. VIP_CNTRL_5 register (address 25h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
ckcase  
0
CKCASE  
W
0*  
1
no specific action  
toggle clk1case (phase clk1 with respect to  
clk2)  
9.3.4 Color space conversion registers  
Table 30. MAT_CONTRL register (address 80h) bit description  
Legend: * = default value  
Bit  
7 to 3  
2
Symbol  
x
Access Value  
Description  
0000 0* undefined  
matrix bypassed: bypasses or not the matrix and  
offsets  
uses color space conversion  
W
W
MAT_BP  
0
1*  
bypasses  
1 and 0 MAT_SC[1:0]  
W
matrix scale factor selection: sets the scale  
factor to convert the floating matrix [Cxy] into an  
integer matrix [Pxy]:  
C11 C12 C13  
P11 P12 P13  
C21 C22 C23  
C31 C32 C33  
= INT(S ×  
)
P21 P22 P23  
P31 P32 P33  
The choice depends on the biggest coefficient in  
absolute value |Cxy|  
00  
01*  
10  
11  
when 2 ≤ |Cxy| < 4; S = 256  
when 1 ≤ |Cxy| < 2; S = 512  
when |Cxy| < 1; S = 1024  
undefined  
Table 31. Offset input registers (address 81h to 86h) bit description  
Legend: * = default value  
Address Register  
Bit  
MAT_OI1_MSB 7 to 3 x  
2 to 0 OFFSET_IN1[10:8]  
Symbol  
Access Value  
Description  
81h  
W
W
W
W
W
W
W
W
W
0000 0* undefined  
000*  
00h*  
offset input 1: compensates the  
brightness value for the G/Y channel[1]  
82h  
83h  
MAT_OI1_LSB 7 to 0 OFFSET_IN1[7:0]  
MAT_OI2_MSB 7 to 3 x  
0000 0* undefined  
2 to 0 OFFSET_IN2[10:8]  
110*  
00h*  
offset input 2: compensates the  
brightness value for the R/CR channel[1]  
84h  
85h  
MAT_OI2_LSB 7 to 0 OFFSET_IN2[7:0]  
MAT_OI3_MSB 7 to 3 x  
0000 0* undefined  
2 to 0 OFFSET_IN3[10:8]  
110*  
00h*  
offset input 3: compensates the  
brightness value for the B/CB channel[1]  
86h  
MAT_OI3_LSB 7 to 0 OFFSET_IN3[7:0]  
[1] The value is a signed 11-bit two’s complement integer.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
34 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 32. Coefficient registers (address 87h to 98h) bit description  
Legend: * = default value  
Address Register  
Bit  
MAT_P11_MSB 7 to 3 x  
2 to 0 P11[10:8]  
7 to 0 P11[7:0]  
MAT_P12_MSB 7 to 3 x  
2 to 0 P12[10:8]  
7 to 0 P12[7:0]  
MAT_P13_MSB 7 to 3 x  
2 to 0 P13[10:8]  
7 to 0 P13[7:0]  
MAT_P21_MSB 7 to 3 x  
2 to 0 P21[10:8]  
7 to 0 P21[7:0]  
MAT_P22_MSB 7 to 3 x  
2 to 0 P22[10:8]  
7 to 0 P22[7:0]  
MAT_P23_MSB 7 to 3 x  
2 to 0 P23[10:8]  
7 to 0 P23[7:0]  
MAT_P31_MSB 7 to 3 x  
2 to 0 P31[10:8]  
7 to 0 P31[7:0]  
MAT_P32_MSB 7 to 3 x  
2 to 0 P32[10:8]  
7 to 0 P32[7:0]  
MAT_P33_MSB 7 to 3 x  
2 to 0 P33[10:8]  
7 to 0 P33[7:0]  
Symbol  
Access Value  
Description  
87h  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0000 0* undefined  
010*  
00h*  
coefficient (1, 1): coefficient from the  
G/Y channel to the G/Y channel[1]  
88h  
89h  
MAT_P11_LSB  
0000 0* undefined  
110*  
92h*  
coefficient (1, 2): coefficient from the  
R/CR channel to the G/Y channel[1]  
8Ah  
8Bh  
MAT_P12_LSB  
0000 0* undefined  
111*  
50h*  
coefficient (1, 3): coefficient from the  
B/CB channel to the G/Y channel[1]  
8Ch  
8Dh  
MAT_P13_LSB  
0000 0* undefined  
010*  
00h*  
coefficient (2, 1): coefficient from the  
G/Y channel to the R/CR channel[1]  
8Eh  
8Fh  
MAT_P21_LSB  
0000 0* undefined  
010*  
coefficient (2, 2): coefficient from the  
R/CR channel to the R/CR channel[1]  
90h  
91h  
MAT_P22_LSB  
CEh*  
0000 0* undefined  
000*  
00h*  
coefficient (2, 3): coefficient from the  
B/CB channel to the R/CR channel[1]  
92h  
93h  
MAT_P23_LSB  
0000 0* undefined  
010*  
00h*  
coefficient (3, 1): coefficient from the  
G/Y channel to the B/CB channel[1]  
94h  
95h  
MAT_P31_LSB  
0000 0* undefined  
000*  
00h*  
coefficient (3, 2): coefficient from the  
R/CR channel to the B/CB channel[1]  
96h  
97h  
MAT_P32_LSB  
0000 0* undefined  
011*  
8Ch*  
coefficient (3, 3): coefficient from the  
B/CB channel to the B/CB channel[1]  
98h  
MAT_P33_LSB  
[1] The value is a signed 11-bit two’s complement integer.  
Table 33. Offset output registers (address 99h to 9Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
MAT_OO1_MSB 7 to 3 x  
2 to 0 OFFSET_OUT1[10:8]  
7 to 0 OFFSET_OUT1[7:0]  
MAT_OO2_MSB 7 to 3 x  
2 to 0 OFFSET_OUT2[10:8]  
MAT_OO2_LSB 7 to 0 OFFSET_OUT2[7:0]  
Symbol  
Access Value  
Description  
99h  
W
W
W
W
W
W
0000 0* undefined  
000*  
00h*  
offset output 1: new clamp level for the  
G/Y channel[1]  
9Ah  
9Bh  
MAT_OO1_LSB  
0000 0* undefined  
000*  
00h*  
offset output 2: new clamp level for the  
R/CR channel[1]  
9Ch  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
35 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 33. Offset output registers (address 99h to 9Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
MAT_OO3_MSB 7 to 3 x  
2 to 0 OFFSET_OUT3[10:8]  
7 to 0 OFFSET_OUT3[7:0]  
Symbol  
Access Value  
Description  
9Dh  
W
W
W
0000 0* undefined  
000*  
00h*  
offset output 3: new clamp level for the  
B/CB channel[1]  
9Eh  
MAT_OO3_LSB  
[1] The value is a signed 11-bit two’s complement integer.  
9.3.5 Video format registers  
Table 34. VIDFORMAT register (address A0h) bit description  
Legend: * = default value  
Bit  
7 to 5 x  
4 to 0 VIDFORMAT[4:0] W  
Symbol  
Access Value  
Description  
W
000*  
undefined  
video format: see EIA/CEA-861B specification  
640 × 480p at 60 Hz (format 1 (VGA))  
720 × 480p at 60 Hz (format 2/3)  
1280 × 720p at 60 Hz (format 4)  
1920 × 1080i at 60 Hz (format 5)  
720 × 480i at 60 Hz (format 6/7)  
720 × 240p at 60 Hz (format 8/9)  
1920 × 1080p at 60 Hz (format 16)  
720 × 576p at 50 Hz (format 17/18)  
1280 × 720p at 50 Hz (format 19)  
1920 × 1080i at 50 Hz (format 20)  
720 × 576i at 50 Hz (format 21/22)  
720 × 288p at 50 Hz (format 23/24)  
1920 × 1080p at 50 Hz (format 31)  
0 0000*  
0 0001  
0 0010  
0 0011  
0 0100  
0 0101  
0 0110  
0 0111  
0 1000  
0 1001  
0 1010  
0 1011  
others  
Table 35. REFPIX_xxx, REFLINE_xxx, NPIX_xxx and NLINE_xxx registers (address A1h to A8h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
A1h  
REFPIX_MSB  
7 to 5 x  
W
W
W
W
W
W
W
W
W
W
W
W
000*  
undefined  
4 to 0 PRESET_PIX[12:8]  
7 to 0 PRESET_PIX[7:0]  
7 to 3 x  
0 0000* preset pixel: reference pixel  
preset  
A2h  
A3h  
REFPIX_LSB  
01h*  
REFLINE_MSB  
0000 0* undefined  
2 to 0 PRESET_LINE[10:8]  
7 to 0 PRESET_LINE[7:0]  
7 to 5 x  
000*  
01h*  
000*  
preset line: reference line  
preset  
A4h  
A5h  
REFLINE_LSB  
NPIX_MSB  
undefined  
4 to 0 NPIX[12:8]  
7 to 0 NPIX[7:0]  
7 to 3 x  
0 0000* number pixel: number of pixels  
per line  
A6h  
A7h  
NPIX_LSB  
00h*  
NLINE_MSB  
0000 0* undefined  
2 to 0 NLINE[10:8]  
7 to 0 NLINE[7:0]  
000*  
00h*  
number line: number of lines  
per frame  
A8h  
NLINE_LSB  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
36 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 36. VS_LINE_STRT_xx, VS_PIX_STRT_xx, VS_LINE_END_xx, VS_PIX_END_xx registers (address A9h to  
B8h) bit description  
Legend: * = default value  
Address Register  
Bit  
VS_LINE_STRT_1_MSB 7 to 3 x  
2 to 0 VS_LINE_START_1[10:8] W  
Symbol  
Access Value  
Description  
A9h  
W
0000 0* undefined  
000*  
00h*  
vertical synchronization line  
start 1: vertical synchronization  
line number for start pulse in  
field 1  
AAh  
VS_LINE_STRT_1_LSB 7 to 0 VS_LINE_START_1[7:0]  
W
ABh  
ACh  
VS_PIX_STRT_1_MSB 7 to 5 x  
4 to 0 VS_PIX_START_1[12:8]  
W
W
W
000*  
undefined  
0 0000* vertical synchronization pixel  
start 1: vertical synchronization  
pixel number for start pulse in  
field 1  
VS_PIX_STRT_1_LSB  
7 to 0 VS_PIX_START_1[7:0]  
00h*  
ADh  
AEh  
VS_LINE_END_1_MSB 7 to 3 x  
2 to 0 VS_LINE_END_1[10:8]  
VS_LINE_END_1_LSB 7 to 0 VS_LINE_END_1[7:0]  
W
W
W
0000 0* undefined  
000*  
00h*  
vertical synchronization line  
end 1: vertical synchronization  
line number for end pulse in  
field 1  
AFh  
B0h  
VS_PIX_END_1_MSB  
VS_PIX_END_1_LSB  
7 to 5 x  
W
W
W
000*  
undefined  
4 to 0 VS_PIX_END_1[12:8]  
7 to 0 VS_PIX_END_1[7:0]  
0 0000* vertical synchronization pixel  
end 1: vertical synchronization  
pixel number for end pulse in  
field 1  
00h*  
B1h  
B2h  
VS_LINE_STRT_2_MSB 7 to 3 x  
W
0000 0* undefined  
2 to 0 VS_LINE_START_2[10:8] W  
000*  
00h*  
vertical synchronization line  
start 2: vertical synchronization  
line number for start pulse in  
field 2  
VS_LINE_STRT_2_LSB 7 to 0 VS_LINE_START_2[7:0]  
W
B3h  
B4h  
VS_PIX_STRT_2_MSB 7 to 5 x  
4 to 0 VS_PIX_START_2[12:8]  
W
W
W
000*  
undefined  
0 0000* vertical synchronization pixel  
start 2: vertical synchronization  
pixel number for start pulse in  
field 2  
VS_PIX_STRT_2_LSB  
7 to 0 VS_PIX_START_2[7:0]  
00h*  
B5h  
B6h  
VS_LINE_END_2_MSB 7 to 3 x  
2 to 0 VS_LINE_END_2[10:8]  
VS_LINE_END_2_LSB 7 to 0 VS_LINE_END_2[7:0]  
W
W
W
0000 0* undefined  
000*  
00h*  
vertical synchronization line  
end 2: vertical synchronization  
line number for end pulse in  
field 2  
B7h  
B8h  
VS_PIX_END_2_MSB  
VS_PIX_END_2_LSB  
7 to 5 x  
W
W
W
000*  
undefined  
4 to 0 VS_PIX_END_2[12:8]  
7 to 0 VS_PIX_END_2[7:0]  
0 0000* vertical synchronization pixel  
end 2: vertical synchronization  
pixel number for end pulse in  
field 2  
00h*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
37 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 37. HS_PIX_xx registers (address B9h to BCh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
B9h  
HS_PIX_START_MSB  
7 to 5 x  
W
W
W
W
W
W
000*  
undefined  
4 to 0 HS_PIX_START[12:8]  
7 to 0 HS_PIX_START[7:0]  
7 to 5 x  
0 0000* horizontal synchronization pixel  
number for start pulse in field 1  
BAh  
BBh  
HS_PIX_START_LSB  
HS_PIX_STOP_MSB  
00h*  
000*  
undefined  
4 to 0 HS_PIX_END[12:8]  
7 to 0 HS_PIX_END[7:0]  
0 0000* horizontal synchronization pixel  
number for end pulse in field 2  
BCh  
HS_PIX_STOP_LSB  
00h*  
Table 38. VWIN_START_xx and VWIN_END_xx registers (address BDh and C4h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
BDh  
VWIN_START_1_MSB 7 to 3  
x
W
W
W
0000 0* undefined  
2 to 0 VWIN_START_1[10:8]  
000*  
00h*  
vertical window start 1:  
vertical window line number for  
start pulse in field 1  
BEh  
BFh  
VWIN_START_1_LSB 7 to 0 VWIN_START_1[7:0]  
VWIN_END_1_MSB  
VWIN_END_1_LSB  
7 to 3  
x
W
W
W
0000 0* undefined  
2 to 0 VWIN_END_1[10:8]  
7 to 0 VWIN_END_1[7:0]  
000*  
00h*  
vertical window end 1: vertical  
window line number for end  
pulse in field 1  
C0h  
C1h  
VWIN_START_2_MSB 7 to 3  
x
W
W
W
0000 0* undefined  
2 to 0 VWIN_START_2[10:8]  
000*  
00h*  
vertical window start 2:  
vertical window line number for  
start pulse in field 2  
C2h  
C3h  
VWIN_START_2_LSB 7 to 0 VWIN_START_2[7:0]  
VWIN_END_2_MSB  
VWIN_END_2_LSB  
7 to 3  
x
W
W
W
0000 0* undefined  
2 to 0 VWIN_END_2[10:8]  
7 to 0 VWIN_END_2[7:0]  
000*  
00h*  
vertical window end 2: vertical  
window line number for end  
pulse in field 2  
C4h  
Table 39. DE_xxx registers (address C5h to C8h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
C5h  
DE_START_MSB  
7 to 5 x  
W
W
W
000*  
undefined  
4 to 0 DE_START[12:8]  
7 to 0 DE_START[7:0]  
0 0000* data enable start: data enable  
pixel number for start pulse in  
field 1  
C6h  
C7h  
DE_START_LSB  
DE_STOP_MSB  
00h*  
7 to 5 x  
W
W
W
000*  
undefined  
4 to 0 DE_END[12:8]  
7 to 0 DE_END[7:0]  
0 0000* data enable end: data enable  
pixel number for end pulse in  
field 2  
C8h  
DE_STOP_LSB  
00h*  
Table 40. COLBAR_WIDTH register (address C9h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
00h* color bar width  
7 to 0  
CBW[7:0]  
W
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
38 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 41. TBG_CNTRL_0 register (address CAh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
sync once  
7
SYNC_ONCE  
W
0*  
line/pixel counters are synchronized each  
frame  
1
line/pixel counters are synchronized only  
once  
6
SYNC_MTHD  
W
sync method  
0*  
synchronization is based on combination  
of v and h  
1
synchronization is based on combination  
of v and x (de)  
5
FRAME_DIS  
W
frame disable: synchronized by linecnt = 1  
AND pixelcnt = 1  
0*  
1
enable video frames  
disable video frames  
4 to 0  
x
W
0 0000* undefined  
Table 42. TBG_CNTRL_1 register (address CBh) bit description  
Legend: * = default value  
Bit  
7
Symbol  
x
Access Value  
Description  
W
W
0*  
undefined  
6
DWIN_DIS  
data island window disable  
data island window active  
data island window disabled  
vhx_ext 2: bit 2  
0*  
1
5
4
3
2
VHX_EXT[2]  
VHX_EXT[1]  
VHX_EXT[0]  
VH_TGL[2]  
W
W
W
W
0*  
1
vs = vs_tbg (internal)  
vs = v_vip (external)  
vhx_ext 1: bit 1  
0*  
1
hs = hs_tbg (internal)  
hs = h_vip (external)  
vhx_ext 0: bit 0  
0*  
1
de = de_tbg (internal)  
de = x_vip (external)  
vh_tgl 2: bit 2  
0*  
1
vs/hs-polarity is determined by  
vidformat_table  
vs/hs-polarity depends on VH_TGL[1:0]  
vh_tgl 1: bit 1  
1
0
VH_TGL[1]  
VH_TGL[0]  
W
W
0*  
1
no specific action  
toggle vs (only when VH_TGL[2] = 1)  
vh_tgl 0: bit 0  
0*  
1
no specific action  
toggle hs (only when VH_TGL[2] = 1)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
39 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 43. OFFSET registers (address CCh to CFh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
CCh  
CDh  
CEh  
CFh  
VBL_OFFSET_START 7 to 0 VBLOFF_START[7:0]  
W
W
W
W
00h* vertical blanking offset start:  
vertical blanking offset at start  
active window  
VBL_OFFSET_END  
7 to 0 VBLOFF_END[7:0]  
00h* vertical blanking offset end:  
vertical blanking offset at end  
active window  
HBL_OFFSET_START 7 to 0 HBLOFF_START[7:0]  
00h* horizontal blanking offset start:  
horizontal blanking offset at start  
active window  
HBL_OFFSET_END  
7 to 0 HBLOFF_END[7:0]  
00h* horizontal blanking offset end:  
horizontal blanking offset at end  
active window  
Table 44. DWIN_xx_DE registers (address D0h and D1h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
D0h  
DWIN_RE_DE  
7 to 0 DWIN_RE_DE[7:0]  
W
11h* data window rising edge data  
enable: data island window rising  
edge offset with respect to data  
enable  
D1h  
DWIN_FE_DE  
7 to 0 DWIN_FE_DE[7:0]  
W
7Ah* data window falling edge data  
enable: data island window falling  
edge offset with respect to data  
enable  
9.3.6 HDMI video formatter control registers  
Table 45. HVF_CNTRL_0 register (address E4h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7
SM  
W
W
service mode  
0*  
1
no specific action  
service mode (color bar inserted in video path)  
red, white, blue  
6
RWB  
0*  
1
4-bar color bar (Red - White - Blue - Black)  
8-bar color bar (White - Yellow - Magenta -  
Red - Cyan - Green - Blue - Black)  
5 to 4  
3 to 2  
x
W
W
00*  
undefined  
PREFIL[1:0]  
prefilter  
00*  
01  
10  
11  
no prefilter  
[1 2 1]  
[−1 0 9 16 9 0 −1]  
27 taps ITU601-compliant halfband filter  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
40 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 45. HVF_CNTRL_0 register (address E4h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
1 to 0  
INTPOL[1:0]  
W
interpolation  
00*  
01  
bypass (from 4 : 4 : 4 to 4 : 4 : 4)  
intpol_by_2 (from 4 : 2 : 2 to 4 : 4 : 4); copy  
sample  
10  
11  
intpol_by_2 (from 4 : 2 : 2 to 4 : 4 : 4); linear  
interpolation ([1 2 1] / 2 filter)  
undefined  
Table 46. HVF_CNTRL_1 register (address E5h) bit description  
Legend: * = default value  
Bit  
7
Symbol  
Access Value Description  
x
W
W
0*  
undefined  
6
SEMI_PLANAR  
semi-planar  
0
1
4 : 4 : 4 at the input of the vrf-module  
4 : 2 : 2 at the input of the vrf-module  
pad  
5 to 4  
PAD[1:0]  
VQR[1:0]  
W
W
00*  
01  
10  
11  
12-bit data path  
8-bit data path; 4 LSBs set to 0000  
10-bit data path; 2 LSBs set to 00  
10-bit data path; 2 LSBs set to 00  
video quantization range  
full-scale  
3 to 2  
00*  
01  
RGB/YUV (max. 235 to min. 16)  
10  
Y (max. 235 to min. 16);  
U (max. 240 to min. 16);  
V (max. 240 to min. 16)  
11  
Y (max. 235 to min. 16);  
U (max. 240 to min. 16);  
V (max. 240 to min. 16)  
1
0
YUVBLK  
FOR  
W
W
YUV blank  
0*  
1
UV blank level = 16  
UV blank level = 0  
formatter  
0*  
1
transparent formatter (4 : 4 : 4 or 4 : 2 : 2  
unprocessed)  
4 : 2 : 2 output format (4 : 4 : 4 to 4 : 2 : 2  
conversion active)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
41 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.3.7 Timer control registers  
Table 47. Timer control registers (address E8h to EAh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
E8h  
TIMER_H  
7
IM_CLKSEL  
W
im timer clock select  
0
1
ddc_master clocked by  
hdmi_clk / (NDIV_IM[3:0] + 1)  
ddc_master clocked by  
cclk / 3 (typically 10 MHz)  
6
WD_CLKSEL  
W
watchdog timer clock select  
0
1
wd_timer clocked by  
hdmi_clk / (NDIV_PF[7:0] + 1)  
wd_timer clocked by cclk / 32  
5 to 2  
1 to 0  
x
W
W
0000* undefined  
timer control register height  
TIM_H[1:0]  
00  
01*  
10  
00  
tim[17:16] = ’00’  
tim[17:16] = ’01’  
tim[17:16] = ’10’  
tim[17:16] = ’11’  
E9h  
EAh  
TIMER_M  
TIMER_L  
7 to 0  
7 to 0  
TIM_M[7:0]  
TIM_L[7:0]  
W
W
timer control register medium  
tim[15:8] = TIM_M[7:0]  
timer control register low  
tim[7:0] = TIM_L[7:0]  
C2h*  
40h*  
9.3.8 NDIV register  
Table 48. NDIV_xxx registers (address EEh and EFh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
EEh  
NDIV_IM  
NDIV_PF  
7 to 4  
x
W
W
0000* undefined  
N divisor DDC-bus master  
3 to 0 NDIV_IM[3:0]  
0011*  
N divisor to set clock period for  
DDC-bus master  
EFh  
7 to 0 NDIV_PF[7:0]  
W
N divisor pixel frequency  
1Bh*  
N divisor to set clock period for timers  
(equals pixel frequency)  
9.3.9 Control registers  
Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
F0h  
F1h  
RPT_CNTRL  
7 to 4  
x
W
W
W
W
0000*  
0000*  
0000*  
0010*  
undefined  
3 to 0 REPEAT[3:0]  
7 to 4  
3 to 0 LEAD_OFFSET[3:0]  
repeat: repeater control  
undefined  
LEAD_OFF  
x
leading offset: leading offset for dwin  
(in case rpt > 1)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
42 of 119  
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
F2h  
F9h  
FDh  
TRAIL_OFF  
7 to 4  
x
W
W
0000*  
0010*  
undefined  
3 to 0 TRAIL_OFFSET[3:0]  
trailing offset: trailing offset for dwin (in  
case rpt > 1)  
GHOST_XADDR 7 to 1 GHOST_XADDR[6:0] W  
0110  
000*  
ghost extended address  
0
A0_ZERO  
x
W
W
W
0*  
-
AIP_CLKSEL  
7 to 5  
000*  
undefined  
4 to 3 SEL_AIP[1:0]  
selection audio input  
00*  
01  
1X  
0*  
S/PDIF  
I2S-bus  
for internal use  
select polarity clock: for internal use  
select fs: CTS reference  
aclk  
2
SEL_POL_CLK  
W
W
1 to 0 SEL_FS[1:0]  
00*  
01  
mclk  
1X  
fs_64 (S/PDIF)  
FEh  
GHOST_ADDR  
7 to 1 GHOST_ADDR[6:0]  
W
W
1010  
000*  
ghost address  
0
GHOST_DIS  
1*  
-
9.3.10 Current page address register  
Table 50. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
00h*  
Description  
7 to 0  
CURPAGE_ADR[7:0]  
W
current page address: selects the  
current memory page  
9.4 Scaler page register definitions  
The current page address for the Scaler page is 01h.  
The configuration of the registers for this page is given in Table 51.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
43 of 119  
 
 
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 51. I2C-bus registers of memory page 01h[1]  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
SC_VIDFORMAT  
SC_CNTRL  
00h  
01h  
W
W
LUT_SEL[1:0]  
VID_FORMAT_O[2:0]  
VID_FORMAT_I[2:0]  
0000 0000  
0000 0000  
x
x
x
x
IL_OUT_  
ON  
PHASES_  
V
VS_ON  
DEIL_ON  
SC_DELTA_PHASE_V  
SC_DELTA_PHASE_H  
SC_START_PHASE_H  
SC_NPIX_IN_LSB  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
W
W
W
W
W
W
W
W
W
W
W
W
R
x
x
x
DELTA_PHASE_V[6:0]  
DELTA_PHASE_H[4:0]  
START_PHASE_H[3:0]  
0001 1110  
0001 0000  
x
x
x
x
x
0000 0000  
NPIX_IN[7:0]  
1101 0000  
SC_NPIX_IN_MSB  
x
x
x
x
x
x
x
x
x
x
x
x
NPIX_IN[9:8]  
NPIX_OUT[10:8]  
NLINE_IN[9:8]  
0000 0010  
SC_NPIX_OUT_LSB  
SC_NPIX_OUT_MSB  
SC_NLINE_IN_LSB  
SC_NLINE_IN_MSB  
SC_NLINE_OUT_LSB  
SC_NLINE_OUT_MSB  
SC_NLINE_SKIP  
NPIX_OUT[7:0]  
1101 0000  
x
x
0000 0010  
NLINE_IN[7:0]  
0100 0000  
x
x
x
x
0000 0010  
NLINE_OUT[7:0]  
0100 0000  
x
x
x
x
x
x
x
x
x
x
NLINE_OUT[9:8]  
NLINE_SKIP[2:0]  
0000 0010  
0000 0000  
SC_SAMPLE_BUFFILL  
SAMPLE_BUFFILL_COMMAND[7:0]  
MAX_BUFFILL_P[7:0]  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
SC_MAX_BUFFILL_P_0 0Fh  
SC_MAX_BUFFILL_P_1 10h  
SC_MAX_BUFFILL_D_0 11h  
SC_MAX_BUFFILL_D_1 12h  
SC_SAMPLE_FIFOFILL 13h  
R
R
x
x
x
x
x
x
x
MAX_BUFFILL_P[11:8]  
R
MAX_BUFFILL_D[7:0]  
x
R
MAX_BUFFILL_D[11:8]  
R
SAMPLE_FIFOFILL_COMMAND[7:0]  
MAX_FIFOFILL_PI[4:0]  
SC_MAX_FIFOFILL_PI  
14h  
R
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SC_MIN_FIFOFILL_PO1 15h  
SC_MIN_FIFOFILL_PO2 16h  
SC_MIN_FIFOFILL_PO3 17h  
SC_MIN_FIFOFILL_PO4 18h  
R
MIN_FIFOFILL_PO1[4:0]  
MIN_FIFOFILL_PO2[4:0]  
MIN_FIFOFILL_PO3[4:0]  
MIN_FIFOFILL_PO4[4:0]  
MAX_FIFOFILL_DI[4:0]  
MAX_FIFOFILL_DO[4:0]  
R
R
R
SC_MAX_FIFOFILL_DI  
19h  
R
SC_MAX_FIFOFILL_DO 1Ah  
R
SC_VS_LUT_0  
SC_VS_LUT_1  
SC_VS_LUT_2  
SC_VS_LUT_3  
1Bh  
1Ch  
1Dh  
1Eh  
W
W
W
W
VS_LUT0[7:0]  
VS_LUT1[7:0]  
VS_LUT2[7:0]  
VS_LUT3[7:0]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 51. I2C-bus registers of memory page 01h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
SC_VS_LUT_4  
SC_VS_LUT_5  
SC_VS_LUT_6  
SC_VS_LUT_7  
SC_VS_LUT_8  
SC_VS_LUT_9  
SC_VS_LUT_10  
SC_VS_LUT_11  
SC_VS_LUT_12  
SC_VS_LUT_13  
SC_VS_LUT_14  
SC_VS_LUT_15  
SC_VS_LUT_16  
SC_VS_LUT_17  
SC_VS_LUT_18  
SC_VS_LUT_19  
SC_VS_LUT_20  
SC_VS_LUT_21  
SC_VS_LUT_22  
SC_VS_LUT_23  
SC_VS_LUT_24  
SC_VS_LUT_25  
SC_VS_LUT_26  
SC_VS_LUT_27  
SC_VS_LUT_28  
SC_VS_LUT_29  
SC_VS_LUT_30  
SC_VS_LUT_31  
SC_VS_LUT_32  
SC_VS_LUT_33  
SC_VS_LUT_34  
SC_VS_LUT_35  
1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
33h  
34h  
35h  
36h  
37h  
38h  
39h  
3Ah  
3Bh  
3Ch  
3Dh  
3Eh  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
VS_LUT4[7:0]  
VS_LUT5[7:0]  
VS_LUT6[7:0]  
VS_LUT7[7:0]  
VS_LUT8[7:0]  
VS_LUT9[7:0]  
VS_LUT10[7:0]  
VS_LUT11[7:0]  
VS_LUT12[7:0]  
VS_LUT13[7:0]  
VS_LUT14[7:0]  
VS_LUT15[7:0]  
VS_LUT16[7:0]  
VS_LUT17[7:0]  
VS_LUT18[7:0]  
VS_LUT19[7:0]  
VS_LUT20[7:0]  
VS_LUT21[7:0]  
VS_LUT22[7:0]  
VS_LUT23[7:0]  
VS_LUT24[7:0]  
VS_LUT25[7:0]  
VS_LUT26[7:0]  
VS_LUT27[7:0]  
VS_LUT28[7:0]  
VS_LUT29[7:0]  
VS_LUT30[7:0]  
VS_LUT31[7:0]  
VS_LUT32[7:0]  
VS_LUT33[7:0]  
VS_LUT34[7:0]  
VS_LUT35[7:0]  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 51. I2C-bus registers of memory page 01h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
SC_VS_LUT_36  
SC_VS_LUT_37  
SC_VS_LUT_38  
SC_VS_LUT_39  
SC_VS_LUT_40  
SC_VS_LUT_41  
SC_VS_LUT_42  
SC_VS_LUT_43  
SC_VS_LUT_44  
Not used  
3Fh  
40h  
41h  
42h  
43h  
44h  
45h  
46h  
47h  
48h  
:
W
W
W
W
W
W
W
W
W
-
VS_LUT36[7:0]  
VS_LUT37[7:0]  
VS_LUT38[7:0]  
VS_LUT39[7:0]  
VS_LUT40[7:0]  
VS_LUT41[7:0]  
VS_LUT42[7:0]  
VS_LUT43[7:0]  
VS_LUT44[7:0]  
-
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
XXXX XXXX  
0000 0000  
:
:
:
:
Not used  
9Fh  
A0h  
A1h  
A2h  
A3h  
A4h  
A5h  
A6h  
A7h  
A8h  
A9h  
:
-
-
0000 0000  
0000 0000  
0000 0000  
0000 0001  
0000 0000  
0000 0001  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
:
VIDFORMAT  
W
W
W
W
W
W
W
W
W
-
x
x
x
x
x
x
x
x
x
x
VIDFORMAT[2:0]  
REFPIX_MSB  
REFPIX_LSB  
REFLINE_MSB  
REFLINE_LSB  
NPIX_MSB  
x
x
x
x
PRESET_PIX[9:8]  
PRESET_LINE[9:8]  
NPIX[9:8]  
PRESET_PIX[7:0]  
x
x
x
x
x
x
x
x
x
x
x
PRESET_LINE[7:0]  
x
x
NPIX_LSB  
NPIX[7:0]  
NLINE_MSB  
x
x
NLINE[9:8]  
NLINE_LSB  
NLINE[7:0]  
Not used  
-
:
:
:
Not used  
BCh  
BDh  
BEh  
BFh  
C0h  
C1h  
C2h  
C3h  
C4h  
-
-
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
VWIN_START_1_MSB  
VWIN_START_1_LSB  
VWIN_END_1_MSB  
VWIN_END_1_LSB  
VWIN_START_2_MSB  
VWIN_START_2_LSB  
VWIN_END_2_MSB  
VWIN_END_2_LSB  
W
W
W
W
W
W
W
W
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
VWIN_START_1[9:8]  
VWIN_END_1[9:8]  
VWIN_START_2[9:8]  
VWIN_END_2[9:8]  
VWIN_START_1[7:0]  
x
x
VWIN_END_1[7:0]  
x
x
VWIN_START_2[7:0]  
x
x
VWIN_END_2[7:0]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 51. I2C-bus registers of memory page 01h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
DE_START_MSB  
DE_START_LSB  
DE_STOP_MSB  
DE_STOP_LSB  
Not used  
C5h  
C6h  
C7h  
C8h  
C9h  
CAh  
W
W
W
W
-
x
x
x
x
x
x
DE_START[9:8]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
DE_START[7:0]  
x
-
x
-
x
-
x
x
x
DE_END[9:8]  
DE_END[7:0]  
-
-
-
-
-
TBG_CNTRL_0  
W
SYNC_  
ONCE  
SYNC_  
MTHD  
FRAME_  
DIS  
x
TOP_EXT  
DE_EXT  
TOP_SEL TOP_TGL  
Not used  
:
CBh  
:
-
:
-
:
0000 0000  
:
Not used  
CURPAGE_ADR  
FEh  
FFh  
-
-
0000 0000  
0000 0000  
W
CURPAGE_ADR[7:0]  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.4.1 Scaler control registers  
Table 52. SC_VIDFORMAT register (address 00h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
look-up table select  
7 and 6 LUT_SEL[1:0]  
W
00*  
01  
default coefficient set #1 (video)  
default coefficient set #2 (enhanced sharpness)  
coefficient set as programmed via I2C-bus  
video format output  
480p 60 Hz  
1X  
5 to 3  
VID_FORMAT_O[2:0] W  
000*  
001  
010  
011  
1XX  
576p 50 Hz  
720p 50 Hz/60 Hz  
1080i 50 Hz/60 Hz  
customized format  
video format input  
480i 60 Hz  
2 to 0  
VID_FORMAT_I[2:0]  
W
000*  
001  
010  
011  
1XX  
576i 50 Hz  
480p 60 Hz  
576p 50 Hz  
customized format  
Table 53. SC_CNTRL register (address 01h) bit description  
Legend: * = default value  
Bit  
7 to 4  
3
Symbol  
x
Access Value Description  
W
W
0000* undefined  
interlaced output on  
IL_OUT_ON  
0*  
1
internal line phase toggle is ignored  
interlaced output; output lines depend on  
internal line phase toggle  
2
1
0
PHASES_V  
VS_ON  
W
W
W
vertical phases  
90 vertical phases  
54 vertical phases  
vertical scaler on  
vertical scaler off  
vertical scaler on  
deinterlacer on  
deinterlacer off  
0*  
1
0*  
1
DEIL_ON  
0*  
1
deinterlacer on  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
48 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 54. SC_x_PHASE_x registers (address 02h to 04h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
02h  
03h  
04h  
SC_DELTA_PHASE_V  
7
x
W
W
W
W
W
W
0*  
undefined  
6 to 0  
7 to 5  
4 to 0  
DELTA_PHASE_V[6:0]  
001 1110* delta phase vertical  
SC_DELTA_PHASE_H  
x
000*  
undefined  
DELTA_PHASE_H[4:0]  
1 0000*  
0000*  
0000*  
delta phase horizontal  
undefined  
SC_START_PHASE_H 7 to 4  
3 to 0  
x
START_PHASE_H[3:0]  
start phase horizontal  
Table 55. SC_NPIX_xx registers (address 05h to 08h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
06h  
SC_NPIX_IN_MSB  
7 to 2  
1 to 0  
7 to 0  
7 to 3  
2 to 0  
7 to 0  
x
W
W
W
W
W
W
0000 00*  
undefined  
NPIX_IN[9:8]  
NPIX_IN[7:0]  
x
10*  
number of input pixels  
05h  
08h  
SC_NPIX_IN_LSB  
D0h*  
0000 0*  
010*  
SC_NPIX_OUT_MSB  
undefined  
NPIX_OUT[10:8]  
NPIX_OUT[7:0]  
number of output pixels  
07h  
SC_NPIX_OUT_LSB  
D0h*  
Table 56. SC_NLINE_xx registers (address 09h to 0Dh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
0Ah  
SC_NLINE_IN_MSB  
7 to 2  
1 to 0  
7 to 0  
x
W
W
W
W
W
W
W
W
0000 00*  
undefined  
NLINE_IN[9:8]  
NLINE_IN[7:0]  
x
10*  
number of input lines  
09h  
0Ch  
SC_NLINE_IN_LSB  
40h*  
SC_NLINE_OUT_MSB 7 to 2  
1 to 0  
0000 00*  
10*  
undefined  
NLINE_OUT[9:8]  
NLINE_OUT[7:0]  
x
number of output lines  
0Bh  
0Dh  
SC_NLINE_OUT_LSB  
SC_NLINE_SKIP  
7 to 0  
7 to 3  
2 to 0  
40h*  
0000 0*  
000*  
undefined  
NLINE_SKIP[2:0]  
number of output lines  
skipped: by vertical  
scaler  
Table 57. SC_x_BUFFILL_xx registers (address 0Eh to 12h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
0Eh  
SC_SAMPLE_BUFFILL  
7 to 0 SAMPLE_BUFFILL_  
COMMAND[7:0]  
R
-
sample buffer filling  
command: when this address  
is read the BUFFILL values are  
sampled  
10h  
0Fh  
SC_MAX_BUFFILL_P_1 7 to 4  
x
R
R
R
-
-
-
undefined  
3 to 0 MAX_BUFFILL_P[11:8]  
max buffer filling primary:  
filling primary video buffer  
SC_MAX_BUFFILL_P_0 7 to 0 MAX_BUFFILL_P[7:0]  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
49 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 57. SC_x_BUFFILL_xx registers (address 0Eh to 12h) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
12h  
SC_MAX_BUFFILL_D_1 7 to 4  
x
R
R
R
-
-
-
undefined  
3 to 0 MAX_BUFFILL_D[11:8]  
max buffer filling  
deinterlaced: filling video  
deinterlaced buffer  
11h  
SC_MAX_BUFFILL_D_0 7 to 0 MAX_BUFFILL_D[7:0]  
Table 58. SC_xx_FIFOFILL_xx registers (address 13h to 1Ah) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
13h  
SC_SAMPLE_FIFOFILL 7 to 0 SAMPLE_FIFOFILL_  
COMMAND[7:0]  
R
-
sample FIFO filling command:  
when this address is read the  
FIFOFILL values are sampled  
14h  
SC_MAX_FIFOFILL_PI 7 to 5 x  
4 to 0 MAX_FIFOFILL_PI[4:0]  
R
R
-
-
undefined  
max FIFO filling primary input:  
filling primary video input FIFO  
15h  
16h  
17h  
18h  
19h  
1Ah  
SC_MIN_FIFOFILL_PO1 7 to 5 x  
R
-
-
undefined  
4 to 0 MIN_FIFOFILL_PO1[4:0] R  
min FIFO filling primary  
output 1: filling primary video  
output FIFO#1  
SC_MIN_FIFOFILL_PO2 7 to 5 x  
R
-
-
undefined  
4 to 0 MIN_FIFOFILL_PO2[4:0] R  
min FIFO filling primary  
output 2: filling primary video  
output FIFO#2  
SC_MIN_FIFOFILL_PO3 7 to 5 x  
R
-
-
undefined  
4 to 0 MIN_FIFOFILL_PO3[4:0] R  
min FIFO filling primary  
output 3: filling primary video  
output FIFO#3  
SC_MIN_FIFOFILL_PO4 7 to 5 x  
R
-
-
undefined  
4 to 0 MIN_FIFOFILL_PO4[4:0] R  
min FIFO filling primary  
output 4: filling primary video  
output FIFO#4  
SC_MAX_FIFOFILL_DI 7 to 5 x  
4 to 0 MAX_FIFOFILL_DI[4:0]  
R
R
-
-
undefined  
max FIFO filling deinterlaced  
input: filling deinterlaced video  
input FIFO  
SC_MAX_FIFOFILL_DO 7 to 5 x  
4 to 0 MAX_FIFOFILL_DO[4:0]  
R
R
-
-
undefined  
max FIFO filling deinterlaced  
output: filling deinterlaced video  
output FIFO  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
50 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description  
Legend: * = default value  
Address Register  
SC_VS_LUT_0  
Bit  
Symbol  
Access Value Description  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
7 to 0 VS_LUT0[7:0]  
7 to 0 VS_LUT1[7:0]  
7 to 0 VS_LUT2[7:0]  
7 to 0 VS_LUT3[7:0]  
7 to 0 VS_LUT4[7:0]  
7 to 0 VS_LUT5[7:0]  
7 to 0 VS_LUT6[7:0]  
7 to 0 VS_LUT7[7:0]  
7 to 0 VS_LUT8[7:0]  
7 to 0 VS_LUT9[7:0]  
7 to 0 VS_LUT10[7:0]  
7 to 0 VS_LUT11[7:0]  
7 to 0 VS_LUT12[7:0]  
7 to 0 VS_LUT13[7:0]  
7 to 0 VS_LUT14[7:0]  
7 to 0 VS_LUT15[7:0]  
7 to 0 VS_LUT16[7:0]  
7 to 0 VS_LUT17[7:0]  
7 to 0 VS_LUT18[7:0]  
7 to 0 VS_LUT19[7:0]  
7 to 0 VS_LUT20[7:0]  
7 to 0 VS_LUT21[7:0]  
7 to 0 VS_LUT22[7:0]  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vertical scaler LUT 0: external LUT  
coefficient[0] for vertical scaler  
SC_VS_LUT_1  
SC_VS_LUT_2  
SC_VS_LUT_3  
SC_VS_LUT_4  
SC_VS_LUT_5  
SC_VS_LUT_6  
SC_VS_LUT_7  
SC_VS_LUT_8  
SC_VS_LUT_9  
SC_VS_LUT_10  
SC_VS_LUT_11  
SC_VS_LUT_12  
SC_VS_LUT_13  
SC_VS_LUT_14  
SC_VS_LUT_15  
SC_VS_LUT_16  
SC_VS_LUT_17  
SC_VS_LUT_18  
SC_VS_LUT_19  
SC_VS_LUT_20  
SC_VS_LUT_21  
SC_VS_LUT_22  
vertical scaler LUT 1: external LUT  
coefficient[1] for vertical scaler  
vertical scaler LUT 2: external LUT  
coefficient[2] for vertical scaler  
vertical scaler LUT 3: external LUT  
coefficient[3] for vertical scaler  
vertical scaler LUT 4: external LUT  
coefficient[4] for vertical scaler  
vertical scaler LUT 5: external LUT  
coefficient[5] for vertical scaler  
vertical scaler LUT 6: external LUT  
coefficient[6] for vertical scaler  
vertical scaler LUT 7: external LUT  
coefficient[7] for vertical scaler  
vertical scaler LUT 8: external LUT  
coefficient[8] for vertical scaler  
vertical scaler LUT 9: external LUT  
coefficient[9] for vertical scaler  
vertical scaler LUT 10: external LUT  
coefficient[10] for vertical scaler  
vertical scaler LUT 11: external LUT  
coefficient[11] for vertical scaler  
vertical scaler LUT 12: external LUT  
coefficient[12] for vertical scaler  
vertical scaler LUT 13: external LUT  
coefficient[13] for vertical scaler  
vertical scaler LUT 14: external LUT  
coefficient[14] for vertical scaler  
vertical scaler LUT 15: external LUT  
coefficient[15] for vertical scaler  
vertical scaler LUT 16: external LUT  
coefficient[16] for vertical scaler  
vertical scaler LUT 17: external LUT  
coefficient[17] for vertical scaler  
vertical scaler LUT 18: external LUT  
coefficient[18] for vertical scaler  
vertical scaler LUT 19: external LUT  
coefficient[19] for vertical scaler  
vertical scaler LUT 20: external LUT  
coefficient[20] for vertical scaler  
vertical scaler LUT 21: external LUT  
coefficient[21] for vertical scaler  
vertical scaler LUT 22: external LUT  
coefficient[22] for vertical scaler  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
51 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description …continued  
Legend: * = default value  
Address Register  
SC_VS_LUT_23  
Bit  
Symbol  
Access Value Description  
32h  
33h  
34h  
35h  
36h  
37h  
38h  
39h  
3Ah  
3Bh  
3Ch  
3Dh  
3Eh  
3Fh  
40h  
41h  
42h  
43h  
44h  
45h  
46h  
47h  
7 to 0 VS_LUT23[7:0]  
7 to 0 VS_LUT24[7:0]  
7 to 0 VS_LUT25[7:0]  
7 to 0 VS_LUT26[7:0]  
7 to 0 VS_LUT27[7:0]  
7 to 0 VS_LUT28[7:0]  
7 to 0 VS_LUT29[7:0]  
7 to 0 VS_LUT30[7:0]  
7 to 0 VS_LUT31[7:0]  
7 to 0 VS_LUT32[7:0]  
7 to 0 VS_LUT33[7:0]  
7 to 0 VS_LUT34[7:0]  
7 to 0 VS_LUT35[7:0]  
7 to 0 VS_LUT36[7:0]  
7 to 0 VS_LUT37[7:0]  
7 to 0 VS_LUT38[7:0]  
7 to 0 VS_LUT39[7:0]  
7 to 0 VS_LUT40[7:0]  
7 to 0 VS_LUT41[7:0]  
7 to 0 VS_LUT42[7:0]  
7 to 0 VS_LUT43[7:0]  
7 to 0 VS_LUT44[7:0]  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vertical scaler LUT 23: external LUT  
coefficient[23] for vertical scaler  
SC_VS_LUT_24  
SC_VS_LUT_25  
SC_VS_LUT_26  
SC_VS_LUT_27  
SC_VS_LUT_28  
SC_VS_LUT_29  
SC_VS_LUT_30  
SC_VS_LUT_31  
SC_VS_LUT_32  
SC_VS_LUT_33  
SC_VS_LUT_34  
SC_VS_LUT_35  
SC_VS_LUT_36  
SC_VS_LUT_37  
SC_VS_LUT_38  
SC_VS_LUT_39  
SC_VS_LUT_40  
SC_VS_LUT_41  
SC_VS_LUT_42  
SC_VS_LUT_43  
SC_VS_LUT_44  
vertical scaler LUT 24: external LUT  
coefficient[24] for vertical scaler  
vertical scaler LUT 25: external LUT  
coefficient[25] for vertical scaler  
vertical scaler LUT 26: external LUT  
coefficient[26] for vertical scaler  
vertical scaler LUT 27: external LUT  
coefficient[27] for vertical scaler  
vertical scaler LUT 28: external LUT  
coefficient[28] for vertical scaler  
vertical scaler LUT 29: external LUT  
coefficient[29] for vertical scaler  
vertical scaler LUT 30: external LUT  
coefficient[30] for vertical scaler  
vertical scaler LUT 31: external LUT  
coefficient[31] for vertical scaler  
vertical scaler LUT 32: external LUT  
coefficient[32] for vertical scaler  
vertical scaler LUT 33: external LUT  
coefficient[33] for vertical scaler  
vertical scaler LUT 34: external LUT  
coefficient[34] for vertical scaler  
vertical scaler LUT 35: external LUT  
coefficient[35] for vertical scaler  
vertical scaler LUT 36: external LUT  
coefficient[36] for vertical scaler  
vertical scaler LUT 37: external LUT  
coefficient[37] for vertical scaler  
vertical scaler LUT 38: external LUT  
coefficient[38] for vertical scaler  
vertical scaler LUT 39: external LUT  
coefficient[39] for vertical scaler  
vertical scaler LUT 40: external LUT  
coefficient[40] for vertical scaler  
vertical scaler LUT 41: external LUT  
coefficient[41] for vertical scaler  
vertical scaler LUT 42: external LUT  
coefficient[42] for vertical scaler  
vertical scaler LUT 43: external LUT  
coefficient[43] for vertical scaler  
vertical scaler LUT 44: external LUT  
coefficient[44] for vertical scaler  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
52 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.4.2 Scaling input time base generator control registers  
Table 60. VIDFORMAT register (address A0h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
0000 0* undefined  
video format: time base generator for scaler  
7 to 3  
2 to 0  
x
W
W
VIDFORMAT[2:0]  
input formats  
000*  
001  
010  
011  
1XX  
480i 60 Hz  
576i 50 Hz  
480p 60 Hz  
576p 50 Hz  
reserved for future use  
Table 61. REFPIX_xx, REFLINE_xx, NPIX_xx and NLINE_xx registers (address A1h to A8h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
A1h  
REFPIX_MSB  
7 to 2 x  
W
W
W
W
W
W
W
W
W
W
W
W
0000 00* undefined  
1 to 0 PRESET_PIX[9:8]  
7 to 0 PRESET_PIX[7:0]  
7 to 2 x  
00*  
preset pixel: reference pixel  
preset  
A2h  
A3h  
REFPIX_LSB  
01h*  
REFLINE_MSB  
0000 00* undefined  
1 to 0 PRESET_LINE[9:8]  
7 to 0 PRESET_LINE[7:0]  
7 to 2 x  
00*  
preset line: reference line preset  
A4h  
A5h  
REFLINE_LSB  
NPIX_MSB  
01h*  
0000 00* undefined  
1 to 0 NPIX[9:8]  
7 to 0 NPIX[7:0]  
7 to 2 x  
00*  
number pixel: number of pixels  
per line  
A6h  
A7h  
NPIX_LSB  
00h*  
NLINE_MSB  
0000 00* undefined  
1 to 0 NLINE[9:8]  
7 to 0 NLINE[7:0]  
00*  
number line: number of lines per  
frame  
A8h  
NLINE_LSB  
00h*  
Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description  
Legend: * = default value  
Address Register  
Bit  
VWIN_START_1_MSB 7 to 2 x  
1 to 0 VWIN_START_1[9:8]  
Symbol  
Access Value  
Description  
BDh  
W
W
W
0000 00* undefined  
00*  
vertical window start 1: vertical  
window line number for start  
pulse in field 1  
BEh  
BFh  
VWIN_START_1_LSB  
7 to 0 VWIN_START_1[7:0]  
00h*  
VWIN_END_1_MSB  
7 to 2 x  
W
W
W
0000 00* undefined  
1 to 0 VWIN_END_1[9:8]  
7 to 0 VWIN_END_1[7:0]  
00*  
vertical window end 1: vertical  
window line number for end pulse  
in field 1  
C0h  
C1h  
VWIN_END_1_LSB  
00h*  
VWIN_START_2_MSB 7 to 2 x  
1 to 0 VWIN_START_2[9:8]  
7 to 0 VWIN_START_2[7:0]  
W
W
W
0000 00* undefined  
00*  
vertical window start 2: vertical  
window line number for start  
pulse in field 2  
C2h  
VWIN_START_2_LSB  
00h*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
53 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
C3h  
VWIN_END_2_MSB  
7 to 2 x  
W
W
W
0000 00* undefined  
1 to 0 VWIN_END_2[9:8]  
7 to 0 VWIN_END_2[7:0]  
00*  
vertical window end 2: vertical  
window line number for end pulse  
in field 2  
C4h  
VWIN_END_2_LSB  
00h*  
Table 63. DE_START_x and DE_STOP_x registers (address C5h to C8h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
C5h  
DE_START_MSB  
7 to 2 x  
W
W
W
0000 00* undefined  
1 to 0 DE_START[9:8]  
7 to 0 DE_START[7:0]  
00*  
data enable start: data enable  
pixel number for start pulse in  
field 1  
C6h  
C7h  
DE_START_LSB  
DE_STOP_MSB  
00h*  
7 to 2 x  
W
W
W
0000 00* undefined  
1 to 0 DE_END[9:8]  
7 to 0 DE_END[7:0]  
00*  
data enable end: data enable  
pixel number for end pulse in  
field 2  
C8h  
DE_STOP_LSB  
00h*  
Table 64. TBG_CNTRL_0 register (address CAh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
sync once  
7
SYNC_ONCE  
W
0*  
line/pixel counters are synchronized each  
frame  
1
line/pixel counters are synchronized only  
once  
6
5
SYNC_MTHD  
FRAME_DIS  
W
sync method  
0*  
synchronization is based on combination of  
v and h  
1
synchronization is based on combination of  
v and x (de)  
W
frame disable: synchronized by linecnt = 1  
AND pixelcnt = 1  
0*  
1
enable video frames  
disable video frames  
undefined  
4
3
x
W
W
0*  
TOP_EXT  
top external  
0*  
1
top = top_tbg_sci  
top = x_vip (external; fref)  
data enable external  
de = de_tbg_sci (internal)  
de = x_vip (external; de)  
2
DE_EXT  
W
0*  
1
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
54 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 64. TBG_CNTRL_0 register (address CAh) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
top select  
1
TOP_SEL  
W
0*  
top_tbg_sci = top_tbg_sci (internal;  
programmed via I2C-bus)  
1
top_tbg_sci = top_tbg_vrf  
top toggle  
0
TOP_TGL  
W
0*  
1
no specific action  
toggle top_tbg_sci  
9.4.3 Current page address register  
Table 65. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
00h*  
Description  
7 to 0  
CURPAGE_ADR[7:0]  
W
current page address: selects the current  
memory page  
9.5 PLL settings page register definitions  
The current page address for the PLL settings page is 02h.  
The configuration of the registers for this page is given in Table 66.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
55 of 119  
 
 
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 66. I2C-bus registers of memory page 02h[1]  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
PLL_SERIAL_1  
PLL_SERIAL_2  
PLL_SERIAL_3  
00h R/W  
01h R/W  
02h R/W  
x
SRL_MAN_IP  
SRL_REG_IP[2:0]  
SRL_IZ[1:0]  
SRL_FDN  
0000 0000  
0000 0000  
SRL_PR[3:0]  
x
x
x
x
SRL_NOSC[1:0]  
x
x
x
SRL_PXIN_  
SEL  
SRL_DE  
SRL_CCIR 0000 0000  
SERIALIZER  
BUFFER_OUT  
PLL_SCG1  
03h R/W  
04h R/W  
05h R/W  
SRL_PHASE3[3:0]  
SRL_PHASE2[3:0]  
SRL_FORCE[1:0]  
0000 0000  
x
x
x
x
x
x
x
x
x
x
SRL_CLK[1:0]  
0000 0000  
x
x
x
x
x
SCG_FDN 0000 0001  
PLL_SCG2  
06h R/W BYPASS_  
SCG  
SELPLLCL  
KIN  
SCG_NOSC[1:0]  
1001 0000  
PLL_SCGN1  
PLL_SCGN2  
PLL_SCGR1  
PLL_SCGR2  
07h R/W  
SCG_NDIV[7:0]  
1111 1010  
0000 0000  
0101 1011  
0000 0000  
08h R/W  
09h R/W  
0Ah R/W  
x
x
x
x
x
x
x
SCG_NDIV[10:8]  
SCG_RDIV[7:0]  
x
x
x
x
x
x
SCG_  
RDIV[8]  
PLL_DE  
0Bh R/W BYPASS_  
PLLDE  
PLLDE_NOSC[1:0]  
x
PLLDE_IZ[1:0]  
PLLDE_  
FDN  
1000 0001  
CCIR_DIV  
VAI_PLL  
0Ch R/W  
0Dh  
x
x
x
x
x
x
x
x
x
REFDIV2  
0000 0001  
0000 0000  
R
PLLDE_HVP  
PLLSCG_  
HVP  
PLLSRL_  
HVP  
PLLDE_  
LOCK  
PLLSCG_  
LOCK  
PLLSRL_  
LOCK  
AUDIO_DIV  
TEST1  
0Eh R/W  
0Fh R/W  
x
x
x
x
x
x
x
x
x
AUDIO_DIV[2:0]  
TST_NOSC  
0000 0011  
0000 0000  
TSTSER  
PHOE  
x
x
TST_HVP  
TEST2  
10h R/W  
11h R/W  
x
x
x
x
x
x
x
x
x
PWD1V8  
DIVTESTOE 0000 0000  
SEL_CLK1 0000 0000  
SEL_CLK  
ENA_SC_  
CLK  
SEL_VRF_CLK[1:0]  
Not used  
:
12h  
:
-
:
-
:
0000 0000  
:
Not used  
FEh  
-
-
0000 0000  
0000 0000  
CURPAGE_ADR FFh  
W
CURPAGE_ADR[7:0]  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.5.1 PLL serial registers  
Table 67. PLL_SERIAL_1 register (address 00h) bit description  
Legend: * = default value  
Bit  
7
Symbol  
Access Value  
Description  
x
R/W  
R/W  
0*  
undefined  
6
SRL_MAN_IP  
serializer manual current pole  
0*  
1
automatic setting of output current pole  
charge pump (ip_auto)  
manual setting of output current pole charge  
pump (ip_manual)  
5 to 3  
SRL_REG_IP[2:0]  
R/W  
serializer current pole: PLL pole charge  
pump output current (ip_manual)  
000*  
001  
010  
011  
100  
101  
110  
111  
400 nA  
200 nA  
133 nA  
100 nA  
80 nA  
66 nA  
57 nA  
50 nA  
2 to 1  
SRL_IZ[1:0]  
R/W  
R/W  
serializer zero current: PLL zero charge  
pump output current  
00*  
01  
10  
11  
Iz / 5  
Iz / 10  
Iz / 15  
Iz / 20  
0
SRL_FDN  
serializer fdn  
normal (PLL loop active)  
standby (PLL loop open)  
0*  
1
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
57 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 68. PLL_SERIAL_2 register (address 01h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 4  
SRL_PR[3:0]  
R/W  
serializer pixel repetition: pixel repetition  
factor (ip_auto)  
0000*  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
other  
pr = 1 (ip_auto = 400 nA)  
pr = 2 (ip_auto = 200 nA)  
pr = 3 (ip_auto = 133 nA)  
pr = 4 (ip_auto = 100 nA)  
pr = 5 (ip_auto = 80 nA)  
pr = 6 (ip_auto = 66 nA)  
pr = 7 (ip_auto = 57 nA)  
pr = 8 (ip_auto = 50 nA)  
pr = 9 (ip_auto = 50 nA)  
pr = 10 (ip_auto = 50 nA)  
undefined  
3 to 2  
1 to 0  
x
R/W  
R/W  
00*  
undefined  
SRL_NOSC[1:0]  
serializer N oscillator: predivider division  
factor  
00*  
01  
10  
11  
div_by_1; PLL output frequency range =  
(800 to 1500) Msample/s (Iz = 1.0+)  
div_by_2; PLL output frequency range =  
(400 to 800) Msample/s (Iz = 1.5+)  
div_by_4; PLL output frequency range =  
(200 to 400) Msample/s (Iz = 2.0+)  
div_by_4; PLL output frequency range =  
(200 to 400) Msample/s (Iz = 2.0+)  
Table 69. PLL_SERIAL_3 register (address 02h) bit description  
Legend: * = default value  
Bit  
7 to 5  
4
Symbol  
Access Value  
Description  
x
R/W  
R/W  
000*  
undefined  
SRL_PXIN_SEL  
serializer pixel input select  
PXINclko = SCAclko  
PXINclko = SCAclko / 2  
undefined  
0*  
1
3 to 2  
1
x
R/W  
R/W  
00*  
SRL_DE  
serializer double edge: double edge divider  
in feedback loop  
0*  
1
no division  
divide by 2  
0
SRL_CCIR  
R/W  
serializer CCIR  
pllsrl_in = pllsrl_refin  
pllsrl_in = pllsrl_refin / 2  
0*  
1
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
58 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 70. SERIALIZER register (address 03h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 4  
SRL_PHASE3[3:0]  
R/W  
0000* serializer phase 3: phase selection of third  
storage level of the serializer input  
3 to 0  
SRL_PHASE2[3:0]  
R/W  
0000* serializer phase 2: phase selection of second  
storage level of the serializer input  
Table 71. BUFFER_OUT register (address 04h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
0000* undefined  
serializer force  
7 to 4  
3 to 2  
x
R/W  
R/W  
SRL_FORCE[1:0]  
00*  
01  
10  
11  
TMDS outputs active (normal operation)  
TMDS outputs active (normal operation)  
TMDS outputs forced '0'  
TMDS outputs forced '1'  
1 to 0  
SRL_CLK[1:0]  
R/W  
serializer clock  
00*  
01  
10  
11  
TMDS TXC = TMDSclk (normal operation)  
TMDS TXC = SERclk / 2  
TMDS TXC = undefined  
TMDS TXC = SERclk  
Table 72. PLL_SCG1 register (address 05h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 1  
x
R/W  
0000  
000*  
undefined  
0
SCG_FDN  
R/W  
scg fnd  
0
normal (PLL loop active)  
standby (PLL loop open)  
1*  
Table 73. PLL_SCG2 register (address 06h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7
BYPASS_SCG  
R/W  
0
bypass scg  
SCAclko = scg_nosc predivider output  
SCAclko = pllscg_inref  
undefined  
1*  
6 to 5  
4
x
R/W  
R/W  
00*  
SELPLLCLKIN  
select PLL clock input  
pllscg_in = pllsca_inref  
pllscg_in = pllclkin  
undefined  
0
1*  
00*  
3 to 2  
x
R/W  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
59 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 73. PLL_SCG2 register (address 06h) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
1 to 0  
SCG_NOSC[1:0]  
R/W  
00*  
scg N oscillator  
div_by_1; PLL output frequency range =  
(80 to 150) Msample/s  
01  
10  
11  
div_by_2; PLL output frequency range =  
(40 to 80) Msample/s  
div_by_4; PLL output frequency range =  
(20 to 40) Msample/s  
div_by_8; PLL output frequency range =  
(10 to 20) Msample/s  
Table 74. PLL_SCGNx registers (address 07h to 08h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
08h  
PLL_SCGN2  
7 to 3 x  
R/W  
R/W  
R/W  
0000 0*  
undefined  
2 to 0 SCG_NDIV[10:8]  
7 to 0 SCG_NDIV[7:0]  
000*  
FAh*  
scg N divider: PLL feedback oscillator  
divider  
07h  
PLL_SCGN1  
Table 75. PLL_SCGRx registers (address 09h to 0Ah) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
0Ah  
PLL_SCGR2  
7 to 1 x  
R/W  
R/W  
R/W  
0000 000* undefined  
0
SCG_RDIV[8]  
0*  
scg R divider: divider value of the PLL  
reference input clock  
09h  
PLL_SCGR1  
7 to 0 SCG_RDIV[7:0]  
5Bh*  
Table 76. PLL_DE register (address 0Bh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7
BYPASS_PLLDE  
R/W  
0
bypass PLL double edge  
pllde0 = de_nosc predivider output  
pllde0 = pllde_inref  
1*  
6
x
R/W  
0*  
undefined  
5 to 4  
PLLDE_NOSC[1:0] R/W  
PLL double edge N oscillator  
00*  
01  
10  
11  
0*  
div_by_1; PLL output frequency range =  
(80 to 150) Msample/s  
div_by_2; PLL output frequency range =  
(40 to 80) Msample/s  
div_by_4; PLL output frequency range =  
(20 to 40) Msample/s  
div_by_8; PLL output frequency range =  
(10 to 20) Msample/s  
3
x
R/W  
undefined  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
60 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 76. PLL_DE register (address 0Bh) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
2 to 1  
PLLDE_IZ[1:0]  
R/W  
00*  
01  
PLL double edge zero current  
Iz / 5  
Iz / 10  
10  
Iz / 15  
11  
Iz / 20  
0
PLLDE_FDN  
R/W  
0
PLL double edge fdn  
normal (PLL loop active)  
standby (PLL loop open)  
1*  
Table 77. CCIR_DIV register (address 0Ch) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
7 to 1  
x
R/W  
0000  
000*  
undefined  
0
REFDIV2  
R/W  
reference divider 2  
pllde_inref = pllclkin  
pllde_inref = pllclkin / 2  
0
1*  
Table 78. VAI_PLL register (address 0Dh) bit description  
Legend: * = default value  
Bit  
7
Symbol  
Access Value Description  
x
R
R
0*  
undefined  
6
PLLDE_HVP  
PLL DE high voltage protection  
PLLDE high voltage protection cell output is ’0’  
PLLDE high voltage protection cell output is ’1’  
PLL SCG high voltage protection  
PLLSCG high voltage protection cell output is ’0’  
PLLSCG high voltage protection cell output is ’1’  
PLL SRL high voltage protection  
PLLSRL high voltage protection cell output is ’0’  
PLLSRL high voltage protection cell output is ’1’  
undefined  
0*  
1
5
4
PLLSCG_HVP  
PLLSRL_HVP  
R
R
0*  
1
0*  
1
3
2
x
R
R
0*  
PLLDE_LOCK  
PLL DE locked  
0*  
1
PLLDE not locked  
PLLDE in lock  
1
0
PLLSCG_LOCK  
PLLSRL_LOCK  
R
R
PLL SCG locked  
0*  
1
PLLSCG not locked  
PLLSCG in lock  
PLL SRL locked  
0*  
1
PLLSRL not locked  
PLLSRL in lock  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
61 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 79. AUDIO_DIV register (address 0Eh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
Description  
0000 0* undefined  
audio divider: not guaranteed; under  
7 to 3  
2 to 0  
x
R/W  
R/W  
AUDIO_DIV[2:0]  
reservation (ip_manual)  
Audio_Clk_Out = SERclk / 1  
Audio_Clk_Out = SERclk / 2  
Audio_Clk_Out = SERclk / 4  
Audio_Clk_Out = SERclk / 8  
Audio_Clk_Out = SERclk / 16  
Audio_Clk_Out = SERclk / 32  
do not use  
000  
001  
010  
011*  
100  
101  
11X  
Table 80. TESTx registers (address 0Fh and 10h) bit description  
Legend: * = default value  
Address Register  
0Fh TEST1  
Bit  
Symbol  
Access Value  
Description  
7 to 5 x  
R/W  
R/W  
000*  
undefined  
4
TSTSERPHOE  
test serializer phoe  
0*  
1
srl_tst_ph2_o = '0'; srl_tst_ph3_o = '0'  
srl_tst_ph2_o = 'active'; srl_tst_ph3_o = 'active'  
undefined  
3 to 2 x  
R/W  
R/W  
00*  
1
TST_NOSC  
test N oscillator: test mode nosc predividers  
0*  
1
normal mode; input nosc predivider = PLL  
oscillator output  
test mode; input nosc predivider = PLL  
reference input  
0
TST_HVP  
R/W  
test high voltage protection: test high voltage  
protection cells  
0*  
1
normal PLL mode  
test mode; HVP input forced to VDDA(PLL_3V3)  
10h  
TEST2  
7 to 2 x  
R/W  
R/W  
0000 00* undefined  
power-down 1.8 V  
1
PWD1V8  
0*  
1
normal operation  
sleep mode PLLs  
0
DIVTESTOE  
R/W  
divider tests output enable: enable activity of  
scaler PLL dividers test outputs  
0*  
1
test outputs = '0'  
test outputs = active  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
62 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 81. SEL_CLK register (address 11h) bit description  
Legend: * = default value  
Bit  
7 to 4  
3
Symbol  
Access Value Description  
x
R/W  
R/W  
0000* undefined  
enable scaler clocks  
ENA_SC_CLK  
0*  
1
disable scaler clocks (sc_clk_m, clk1_m)  
enable scaler clocks (sc_clk_m, clk1_m)  
select video reformatter clock  
2 to 1  
SEL_VRF_CLK[1:0] R/W  
00*  
01  
10  
11  
vrf_clk_m = not tmdsclkpo;  
sc_clk_m = tmdsclkpo  
vrf_clk_m = scaclko_pllscgon;  
sc_clk_m = not scaclko_pllscgon  
vrf_clk_m = scaclko_tmdsclkn;  
sc_clk_m = not scaclko_tmdsclkn  
vrf_clk_m = scaclko_tmdsclkn;  
sc_clk_m = not scaclko_tmdsclkn  
0
SEL_CLK1  
R/W  
select clock 1  
0*  
1
clk1_m = not (plldeo)  
clk1_m = plldeo_div2  
9.5.2 Current page address register  
Table 82. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7 to 0  
CURPAGE_ADR[7:0]  
W
00h*  
current page address: selects the current  
memory page  
9.6 Information frames and packets page register definitions  
The current page address for the Information frames and packets page is 10h.  
The configuration of the registers for this page is given in Table 83.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
63 of 119  
 
 
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1]  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
Not used  
00h  
:
-
:
-
:
0000 0000  
:
:
Not used  
1Fh  
-
-
0000 0000  
1000 0001  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
VSP_IF_TYPE  
VSP_IF_VERSION  
VSP_IF_LENGTH  
20h R/W  
21h R/W  
22h R/W  
VSP_IF_TYPE[7:0]  
VSP_IF_VERSION[7:0]  
x
x
x
VSP_IF_LENGTH[4:0]  
VSP_IF_CHECKSUM[7:0]  
VSP_IF_CHECKSUM 23h R/W  
VSP_IF_IEEE_LSB  
VSP_IF_IEEE_ISB  
VSP_IF_IEEE_MSB  
VSP_IF_BYTE4  
VSP_IF_BYTE5  
VSP_IF_BYTE6  
VSP_IF_BYTE7  
VSP_IF_BYTE8  
VSP_IF_BYTE9  
VSP_IF_BYTE10  
VSP_IF_BYTE11  
VSP_IF_BYTE12  
VSP_IF_BYTE13  
VSP_IF_BYTE14  
VSP_IF_BYTE15  
VSP_IF_BYTE16  
VSP_IF_BYTE17  
VSP_IF_BYTE18  
VSP_IF_BYTE19  
VSP_IF_BYTE20  
VSP_IF_BYTE21  
VSP_IF_BYTE22  
VSP_IF_BYTE23  
VSP_IF_BYTE24  
VSP_IF_BYTE25  
24h R/W  
25h R/W  
26h R/W  
27h R/W  
28h R/W  
29h R/W  
2Ah R/W  
2Bh R/W  
2Ch R/W  
2Dh R/W  
2Eh R/W  
2Fh R/W  
30h R/W  
31h R/W  
32h R/W  
33h R/W  
34h R/W  
35h R/W  
36h R/W  
37h R/W  
38h R/W  
39h R/W  
3Ah R/W  
3Bh R/W  
3Ch R/W  
VSP_IF_IEEE[7:0]  
VSP_IF_IEEE[15:8]  
VSP_IF_IEEE[23:16]  
VSP_IF_PB4[7:0]  
VSP_IF_PB5[7:0]  
VSP_IF_PB6[7:0]  
VSP_IF_PB7[7:0]  
VSP_IF_PB8[7:0]  
VSP_IF_PB9[7:0]  
VSP_IF_PB10[7:0]  
VSP_IF_PB11[7:0]  
VSP_IF_PB12[7:0]  
VSP_IF_PB13[7:0]  
VSP_IF_PB14[7:0]  
VSP_IF_PB15[7:0]  
VSP_IF_PB16[7:0]  
VSP_IF_PB17[7:0]  
VSP_IF_PB18[7:0]  
VSP_IF_PB19[7:0]  
VSP_IF_PB20[7:0]  
VSP_IF_PB21[7:0]  
VSP_IF_PB22[7:0]  
VSP_IF_PB23[7:0]  
VSP_IF_PB24[7:0]  
VSP_IF_PB25[7:0]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
VSP_IF_BYTE26  
VSP_IF_BYTE27  
Not used  
3Dh R/W  
3Eh R/W  
VSP_IF_PB26[7:0]  
VSP_IF_PB27[7:0]  
-
0000 0000  
0000 0000  
0000 0000  
1000 0010  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
3Fh  
-
AVI_IF_TYPE  
40h R/W  
41h R/W  
42h R/W  
43h R/W  
44h R/W  
45h R/W  
46h R/W  
47h R/W  
48h R/W  
49h R/W  
4Ah R/W  
4Bh R/W  
4Ch R/W  
4Dh R/W  
4Eh R/W  
4Fh R/W  
50h R/W  
51h R/W  
52h R/W  
53h R/W  
54h R/W  
55h R/W  
56h R/W  
57h R/W  
58h R/W  
59h R/W  
5Ah R/W  
5Bh R/W  
5Ch R/W  
AVI_IF_TYPE[7:0]  
AVI_IF_VERSION[7:0]  
AVI_IF_VERSION  
AVI_IF_LENGTH  
AVI_IF_CHECKSUM  
AVI_IF_BYTE1  
AVI_IF_BYTE2  
AVI_IF_BYTE3  
AVI_IF_BYTE4  
AVI_IF_BYTE5  
AVI_IF_BYTE6  
AVI_IF_BYTE7  
AVI_IF_BYTE8  
AVI_IF_BYTE9  
AVI_IF_BYTE10  
AVI_IF_BYTE11  
AVI_IF_BYTE12  
AVI_IF_BYTE13  
AVI_IF_BYTE14  
AVI_IF_BYTE15  
AVI_IF_BYTE16  
AVI_IF_BYTE17  
AVI_IF_BYTE18  
AVI_IF_BYTE19  
AVI_IF_BYTE20  
AVI_IF_BYTE21  
AVI_IF_BYTE22  
AVI_IF_BYTE23  
AVI_IF_BYTE24  
AVI_IF_BYTE25  
x
x
x
AVI_IF_LENGTH[4:0]  
AVI_IF_CHECKSUM[7:0]  
AVI_IF_A AVI_IF_B[1:0]  
AVI_IF_R[3:0]  
AVI_IF_SC[1:0]  
reserved  
AVI_IF_Y[1:0]  
AVI_IF_S[1:0]  
AVI_IF_C[1:0]  
AVI_IF_M[1:0]  
reserved  
reserved  
AVI_IF_VIC[6:0]  
reserved  
AVI_IF_PR[3:0]  
LINE_E_TP_BAR[7:0]  
LINE_E_TP_BAR[15:8]  
LINE_S_BT_BAR[7:0]  
LINE_S_BT_BAR[15:8]  
PIX_E_LF_BAR[7:0]  
PIX_E_LF_BAR[15:8]  
PIX_S_RG_BAR[7:0]  
PIX_S_RG_BAR[15:8]  
AVI_IF_RB14[7:0]  
AVI_IF_RB15[7:0]  
AVI_IF_RB16[7:0]  
AVI_IF_RB17[7:0]  
AVI_IF_RB18[7:0]  
AVI_IF_RB19[7:0]  
AVI_IF_RB20[7:0]  
AVI_IF_RB21[7:0]  
AVI_IF_RB22[7:0]  
AVI_IF_RB23[7:0]  
AVI_IF_RB24[7:0]  
AVI_IF_RB25[7:0]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
AVI_IF_BYTE26  
AVI_IF_BYTE27  
Not used  
5Dh R/W  
5Eh R/W  
AVI_IF_RB26[7:0]  
AVI_IF_RB27[7:0]  
-
0000 0000  
0000 0000  
0000 0000  
1000 0011  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
5Fh  
-
SPD_IF_TYPE  
SPD_IF_VERSION  
SPD_IF_LENGTH  
60h R/W  
61h R/W  
62h R/W  
SPD_IF_TYPE[7:0]  
SPD_IF_VERSION[7:0]  
x
x
x
SPD_IF_LENGTH[4:0]  
SPD_IF_CHECKSUM[7:0]  
SPD_IF_CHECKSUM 63h R/W  
SPD_IF_BYTE1  
SPD_IF_BYTE2  
SPD_IF_BYTE3  
SPD_IF_BYTE4  
SPD_IF_BYTE5  
SPD_IF_BYTE6  
SPD_IF_BYTE7  
SPD_IF_BYTE8  
SPD_IF_BYTE9  
SPD_IF_BYTE10  
SPD_IF_BYTE11  
SPD_IF_BYTE12  
SPD_IF_BYTE13  
SPD_IF_BYTE14  
SPD_IF_BYTE15  
SPD_IF_BYTE16  
SPD_IF_BYTE17  
SPD_IF_BYTE18  
SPD_IF_BYTE19  
SPD_IF_BYTE20  
SPD_IF_BYTE21  
SPD_IF_BYTE22  
SPD_IF_BYTE23  
SPD_IF_BYTE24  
SPD_IF_BYTE25  
64h R/W  
65h R/W  
66h R/W  
67h R/W  
68h R/W  
69h R/W  
6Ah R/W  
6Bh R/W  
6Ch R/W  
6Dh R/W  
6Eh R/W  
6Fh R/W  
70h R/W  
71h R/W  
72h R/W  
73h R/W  
74h R/W  
75h R/W  
76h R/W  
77h R/W  
78h R/W  
79h R/W  
7Ah R/W  
7Bh R/W  
7Ch R/W  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SPD_IF_VN1[6:0]  
SPD_IF_VN2[6:0]  
SPD_IF_VN3[6:0]  
SPD_IF_VN4[6:0]  
SPD_IF_VN5[6:0]  
SPD_IF_VN6[6:0]  
SPD_IF_VN7[6:0]  
SPD_IF_VN8[6:0]  
SPD_IF_PD1[6:0]  
SPD_IF_PD2[6:0]  
SPD_IF_PD3[6:0]  
SPD_IF_PD4[6:0]  
SPD_IF_PD5[6:0]  
SPD_IF_PD6[6:0]  
SPD_IF_PD7[6:0]  
SPD_IF_PD8[6:0]  
SPD_IF_PD9[6:0]  
SPD_IF_PD10[6:0]  
SPD_IF_PD11[6:0]  
SPD_IF_PD12[6:0]  
SPD_IF_PD13[6:0]  
SPD_IF_PD14[6:0]  
SPD_IF_PD15[6:0]  
SPD_IF_PD16[6:0]  
SPD_IF_SDI[7:0]  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
SPD_IF_BYTE26  
SPD_IF_BYTE27  
Not used  
7Dh R/W  
7Eh R/W  
SPD_IF_BYTE26[7:0]  
SPD_IF_BYTE27[7:0]  
-
0000 0000  
0000 0000  
0000 0000  
1000 0100  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
7Fh  
-
AUD_IF_TYPE  
AUD_IF_VERSION  
AUD_IF_LENGTH  
80h R/W  
81h R/W  
82h R/W  
AUD_IF_TYPE[7:0]  
AUD_IF_VERSION[7:0]  
x
x
x
AUD_IF_LENGTH[4:0]  
AUD_IF_CHECKSUM 83h R/W  
AUD_IF_CHECKSUM[7:0]  
reserved  
AUD_IF_BYTE1  
AUD_IF_BYTE2  
AUD_IF_BYTE3  
AUD_IF_BYTE4  
AUD_IF_BYTE5  
84h R/W  
85h R/W  
86h R/W  
87h R/W  
88h R/W  
AUD_IF_CT[3:0]  
reserved  
AUD_IF_CC[2:0]  
AUD_IF_SS[1:0]  
AUD_IF_SF[2:0]  
AUD_IF_BYTE3[7:0]  
AUD_IF_CA[7:0]  
AUD_IF_  
DM_INH  
AUD_IF_LSV[3:0]  
reserved  
AUD_IF_BYTE6  
AUD_IF_BYTE7  
AUD_IF_BYTE8  
AUD_IF_BYTE9  
AUD_IF_BYTE10  
AUD_IF_BYTE11  
AUD_IF_BYTE12  
AUD_IF_BYTE13  
AUD_IF_BYTE14  
AUD_IF_BYTE15  
AUD_IF_BYTE16  
AUD_IF_BYTE17  
AUD_IF_BYTE18  
AUD_IF_BYTE19  
AUD_IF_BYTE20  
AUD_IF_BYTE21  
AUD_IF_BYTE22  
AUD_IF_BYTE23  
AUD_IF_BYTE24  
89h R/W  
8Ah R/W  
8Bh R/W  
8Ch R/W  
8Dh R/W  
8Eh R/W  
8Fh R/W  
90h R/W  
91h R/W  
92h R/W  
93h R/W  
94h R/W  
95h R/W  
96h R/W  
97h R/W  
98h R/W  
99h R/W  
9Ah R/W  
9Bh R/W  
AUD_IF_BYTE6[7:0]  
AUD_IF_BYTE7[7:0]  
AUD_IF_BYTE8[7:0]  
AUD_IF_BYTE9[7:0]  
AUD_IF_BYTE10[7:0]  
AUD_IF_BYTE11[7:0]  
AUD_IF_BYTE12[7:0]  
AUD_IF_BYTE13[7:0]  
AUD_IF_BYTE14[7:0]  
AUD_IF_BYTE15[7:0]  
AUD_IF_BYTE16[7:0]  
AUD_IF_BYTE17[7:0]  
AUD_IF_BYTE18[7:0]  
AUD_IF_BYTE19[7:0]  
AUD_IF_BYTE20[7:0]  
AUD_IF_BYTE21[7:0]  
AUD_IF_BYTE22[7:0]  
AUD_IF_BYTE23[7:0]  
AUD_IF_BYTE24[7:0]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
AUD_IF_BYTE25  
AUD_IF_BYTE26  
AUD_IF_BYTE27  
Not used  
9Ch R/W  
9Dh R/W  
9Eh R/W  
AUD_IF_BYTE25[7:0]  
AUD_IF_BYTE26[7:0]  
AUD_IF_BYTE27[7:0]  
-
0000 0000  
0000 0000  
0000 0000  
0000 0000  
1000 0101  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
9Fh  
-
MPS_IF_TYPE  
MPS_IF_VERSION  
MPS_IF_LENGTH  
A0h R/W  
A1h R/W  
A2h R/W  
MPS_IF_TYPE[7:0]  
MPS_IF_VERSION[7:0]  
x
x
x
MPS_IF_LENGTH[4:0]  
MPS_IF_CHECKSUM[7:0]  
MPS_IF_CHECKSUM A3h R/W  
MPS_IF_BYTE1  
MPS_IF_BYTE2  
MPS_IF_BYTE3  
MPS_IF_BYTE4  
MPS_IF_BYTE5  
A4h R/W  
A5h R/W  
A6h R/W  
A7h R/W  
A8h R/W  
MPS_IF_MB0[7:0]  
MPS_IF_MB1[7:0]  
MPS_IF_MB2[7:0]  
MPS_IF_MB3[7:0]  
reserved  
MPS_IF_  
FR0  
reserved  
MPS_IF_MF[1:0]  
MPS_IF_BYTE6  
MPS_IF_BYTE7  
MPS_IF_BYTE8  
MPS_IF_BYTE9  
MPS_IF_BYTE10  
MPS_IF_BYTE11  
MPS_IF_BYTE12  
MPS_IF_BYTE13  
MPS_IF_BYTE14  
MPS_IF_BYTE15  
MPS_IF_BYTE16  
MPS_IF_BYTE17  
MPS_IF_BYTE18  
MPS_IF_BYTE19  
MPS_IF_BYTE20  
MPS_IF_BYTE21  
MPS_IF_BYTE22  
MPS_IF_BYTE23  
A9h R/W  
AAh R/W  
ABh R/W  
ACh R/W  
ADh R/W  
AEh R/W  
AFh R/W  
B0h R/W  
B1h R/W  
B2h R/W  
B3h R/W  
B4h R/W  
B5h R/W  
B6h R/W  
B7h R/W  
B8h R/W  
B9h R/W  
BAh R/W  
MPS_IF_BYTE6[7:0]  
MPS_IF_BYTE7[7:0]  
MPS_IF_BYTE8[7:0]  
MPS_IF_BYTE9[7:0]  
MPS_IF_BYTE10[7:0]  
MPS_IF_BYTE11[7:0]  
MPS_IF_BYTE12[7:0]  
MPS_IF_BYTE13[7:0]  
MPS_IF_BYTE14[7:0]  
MPS_IF_BYTE15[7:0]  
MPS_IF_BYTE16[7:0]  
MPS_IF_BYTE17[7:0]  
MPS_IF_BYTE18[7:0]  
MPS_IF_BYTE19[7:0]  
MPS_IF_BYTE20[7:0]  
MPS_IF_BYTE21[7:0]  
MPS_IF_BYTE22[7:0]  
MPS_IF_BYTE23[7:0]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 83. I2C-bus registers of memory page 10h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
MPS_IF_BYTE24  
MPS_IF_BYTE25  
MPS_IF_BYTE26  
MPS_IF_BYTE27  
Not used  
BBh R/W  
BCh R/W  
BDh R/W  
BEh R/W  
MPS_IF_BYTE24[7:0]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
:
MPS_IF_BYTE25[7:0]  
MPS_IF_BYTE26[7:0]  
MPS_IF_BYTE27[7:0]  
BFh  
:
-
:
-
:
:
Not used  
FEh  
FFh  
-
-
0000 0000  
0000 0000  
CURPAGE_ADR  
W
CURPAGE_ADR[7:0]  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.6.1 Vendor-specific InfoFrame registers  
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a  
specification for the correct definition of data bytes.  
Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
20h  
VSP_IF_TYPE  
7 to 0 VSP_IF_TYPE[7:0]  
R/W  
R/W  
81h* vendor-specific InfoFrame packet  
type: gives the packet type of the  
vendor-specific InfoFrame packet (80h +  
InfoFrame type code as per  
EIA/CEA-861B)  
21h  
22h  
VSP_IF_VERSION 7 to 0 VSP_IF_  
VERSION[7:0]  
00h* vendor-specific InfoFrame version:  
gives the version number of the  
vendor-specific InfoFrame  
VSP_IF_LENGTH  
7 to 5 x  
4 to 0 VSP_IF_  
LENGTH[4:0]  
R/W  
R/W  
000* reserved (shall be 000)  
0
vendor-specific InfoFrame length:  
0000* gives the number of data bytes for the  
vendor-specific InfoFrame; this length  
does not include the checksum  
23h  
VSP_IF_  
CHECKSUM  
7 to 0 VSP_IF_  
CHECKSUM[7:0]  
R/W  
00h* vendor-specific InfoFrame checksum:  
shall be calculated such that a byte-wide  
sum of all three bytes of the packet  
header and all valid bytes of the  
vendor-specific InfoFrame packet  
contents (determined by InfoFrame  
length) plus the checksum itself equals 0  
24h  
25h  
26h  
VSP_IF_IEEE_LSB 7 to 0 VSP_IF_IEEE[7:0]  
VSP_IF_IEEE_ISB 7 to 0 VSP_IF_IEEE[15:8]  
R/W  
R/W  
00h* vendor-specific InfoFrame IEEE: 24-bit  
IEEE registration identifier  
00h*  
VSP_IF_IEEE_MSB 7 to 0 VSP_IF_IEEE[23:16] R/W  
00h*  
vendor-specific InfoFrame payload  
byte x: x = 4 to 27  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
33h  
34h  
35h  
36h  
VSP_IF_BYTE4  
VSP_IF_BYTE5  
VSP_IF_BYTE6  
VSP_IF_BYTE7  
VSP_IF_BYTE8  
VSP_IF_BYTE9  
VSP_IF_BYTE10  
VSP_IF_BYTE11  
VSP_IF_BYTE12  
VSP_IF_BYTE13  
VSP_IF_BYTE14  
VSP_IF_BYTE15  
VSP_IF_BYTE16  
VSP_IF_BYTE17  
VSP_IF_BYTE18  
VSP_IF_BYTE19  
7 to 0 VSP_IF_PB4[7:0]  
7 to 0 VSP_IF_PB5[7:0]  
7 to 0 VSP_IF_PB6[7:0]  
7 to 0 VSP_IF_PB7[7:0]  
7 to 0 VSP_IF_PB8[7:0]  
7 to 0 VSP_IF_PB9[7:0]  
7 to 0 VSP_IF_PB10[7:0]  
7 to 0 VSP_IF_PB11[7:0]  
7 to 0 VSP_IF_PB12[7:0]  
7 to 0 VSP_IF_PB13[7:0]  
7 to 0 VSP_IF_PB14[7:0]  
7 to 0 VSP_IF_PB15[7:0]  
7 to 0 VSP_IF_PB16[7:0]  
7 to 0 VSP_IF_PB17[7:0]  
7 to 0 VSP_IF_PB18[7:0]  
7 to 0 VSP_IF_PB19[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
byte 4  
byte 5  
byte 6  
byte 7  
byte 8  
byte 9  
byte 10  
byte 11  
byte 12  
byte 13  
byte 14  
byte 15  
byte 16  
byte 17  
byte 18  
byte 19  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
70 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
37h  
38h  
39h  
3Ah  
3Bh  
3Ch  
3Dh  
3Eh  
VSP_IF_BYTE20  
7 to 0 VSP_IF_PB20[7:0]  
7 to 0 VSP_IF_PB21[7:0]  
7 to 0 VSP_IF_PB22[7:0]  
7 to 0 VSP_IF_PB23[7:0]  
7 to 0 VSP_IF_PB24[7:0]  
7 to 0 VSP_IF_PB25[7:0]  
7 to 0 VSP_IF_PB26[7:0]  
7 to 0 VSP_IF_PB27[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
byte 20  
byte 21  
byte 22  
byte 23  
byte 24  
byte 25  
byte 26  
byte 27  
VSP_IF_BYTE21  
VSP_IF_BYTE22  
VSP_IF_BYTE23  
VSP_IF_BYTE24  
VSP_IF_BYTE25  
VSP_IF_BYTE26  
VSP_IF_BYTE27  
9.6.2 Auxiliary video information InfoFrame registers  
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a  
specification for the correct definition of data bytes.  
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
R/W 82h* auxiliary video information InfoFrame  
40h  
AVI_IF_TYPE  
7 to 0 AVI_IF_TYPE[7:0]  
packet type: gives the packet type of the  
auxiliary video information InfoFrame  
packet (80h + InfoFrame type code as  
per EIA/CEA-861B)  
41h  
42h  
AVI_IF_VERSION 7 to 0 AVI_IF_VERSION[7:0] R/W  
00h* auxiliary video information InfoFrame  
version: gives the version number of the  
auxiliary video information InfoFrame  
AVI_IF_LENGTH  
7 to 5 x  
R/W  
R/W  
000* reserved (shall be 000)  
4 to 0 AVI_IF_LENGTH[4:0]  
0
auxiliary video information InfoFrame  
0000* length: gives the number of data bytes  
for the auxiliary video information  
InfoFrame; this length does not include  
the checksum  
43h  
AVI_IF_  
CHECKSUM  
7 to 0 AVI_IF_  
R/W  
00h* auxiliary video information InfoFrame  
checksum: shall be calculated such that  
a byte-wide sum of all three bytes of the  
packet header and all valid bytes of the  
auxiliary video information InfoFrame  
packet contents (determined by  
CHECKSUM[7:0]  
InfoFrame length) plus the checksum  
itself equals 0  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
71 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
44h  
AVI_IF_BYTE1  
7
reserved  
R/W  
R/W  
0*  
reserved (shall be zero)  
6 to 5 AVI_IF_Y[1:0]  
auxiliary video information InfoFrame  
Y: RGB or YCBCR indicator  
00*  
01  
10  
11  
RGB  
YCBCR 4 : 2 : 2  
YCBCR 4 : 4 : 4  
future  
4
AVI_IF_A  
R/W  
R/W  
auxiliary video information InfoFrame  
A: active format information present  
0*  
1
no data  
active format information valid  
3 to 2 AVI_IF_B[1:0]  
1 to 0 AVI_IF_S[1:0]  
7 to 6 AVI_IF_C[1:0]  
5 to 4 AVI_IF_M[1:0]  
3 to 0 AVI_IF_R[3:0]  
auxiliary video information InfoFrame  
bar: bar information  
00*  
01  
10  
11  
bar data not valid  
vertical bar info valid  
horizontal bar info valid  
vertical and horizontal bar info valid  
R/W  
R/W  
R/W  
R/W  
auxiliary video information InfoFrame  
scan: scan information  
00*  
01  
10  
11  
no data  
overscanned (television)  
underscanned (computer)  
future  
45h  
AVI_IF_BYTE2  
auxiliary video information InfoFrame  
colorimetry: colorimetry  
00*  
01  
10  
11  
no data  
ITU601  
ITU709  
future  
auxiliary video information InfoFrame  
M: picture aspect ratio  
00*  
01  
10  
11  
no data  
4 : 3  
16 : 9  
future  
auxiliary video information InfoFrame  
ratio: active format aspect ratio  
1000  
1001  
1010  
1011  
other  
same as picture aspect ratio  
4 : 3 (center)  
16 : 9 (center)  
14 : 9 (center)  
per DVB AFD active_format field  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
72 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
46h  
AVI_IF_BYTE3  
7 to 2 reserved  
R/W  
0000 reserved (shall be zero)  
00*  
1 to 0 AVI_IF_SC[1:0]  
R/W  
auxiliary video information InfoFrame  
scaling: non-uniform picture scaling  
00*  
01  
10  
11  
no known non-uniform scaling  
picture has been scaled horizontally  
picture has been scaled vertically  
picture has been scaled horizontally  
and vertically  
47h  
48h  
AVI_IF_BYTE4  
AVI_IF_BYTE5  
7
reserved  
R/W  
R/W  
0*  
reserved (shall be zero)  
6 to 0 AVI_IF_VIC[6:0]  
000  
auxiliary video information InfoFrame  
0000* video identification code: video  
identification code  
7 to 4 reserved  
R/W  
R/W  
0000* reserved (shall be zero)  
3 to 0 AVI_IF_PR[3:0]  
0000* auxiliary video information InfoFrame  
pixel repetition: pixel repetition  
49h  
4Ah  
4Bh  
4Ch  
4Dh  
4Eh  
4Fh  
50h  
AVI_IF_BYTE6  
AVI_IF_BYTE7  
AVI_IF_BYTE8  
AVI_IF_BYTE9  
AVI_IF_BYTE10  
AVI_IF_BYTE11  
AVI_IF_BYTE12  
AVI_IF_BYTE13  
7 to 0 LINE_E_TP_BAR[7:0] R/W  
7 to 0 LINE_E_TP_BAR[15:8] R/W  
7 to 0 LINE_S_BT_BAR[7:0] R/W  
7 to 0 LINE_S_BT_BAR[15:8] R/W  
00h* line number of end of top bar  
00h*  
00h* line number of start of bottom bar  
00h*  
7 to 0 PIX_E_LF_BAR[7:0]  
7 to 0 PIX_E_LF_BAR[15:8] R/W  
7 to 0 PIX_S_RG_BAR[7:0] R/W  
7 to 0 PIX_S_RG_BAR[15:8] R/W  
R/W  
00h* pixel number of end of left bar  
00h*  
00h* pixel number of start of right bar  
00h*  
auxiliary video information InfoFrame  
reserved byte x: x = 14 to 27  
51h  
52h  
53h  
54h  
55h  
56h  
57h  
58h  
59h  
5Ah  
5Bh  
5Ch  
5Dh  
5Eh  
AVI_IF_BYTE14  
AVI_IF_BYTE15  
AVI_IF_BYTE16  
AVI_IF_BYTE17  
AVI_IF_BYTE18  
AVI_IF_BYTE19  
AVI_IF_BYTE20  
AVI_IF_BYTE21  
AVI_IF_BYTE22  
AVI_IF_BYTE23  
AVI_IF_BYTE24  
AVI_IF_BYTE25  
AVI_IF_BYTE26  
AVI_IF_BYTE27  
7 to 0 AVI_IF_RB14[7:0]  
7 to 0 AVI_IF_RB15[7:0]  
7 to 0 AVI_IF_RB16[7:0]  
7 to 0 AVI_IF_RB17[7:0]  
7 to 0 AVI_IF_RB18[7:0]  
7 to 0 AVI_IF_RB19[7:0]  
7 to 0 AVI_IF_RB20[7:0]  
7 to 0 AVI_IF_RB21[7:0]  
7 to 0 AVI_IF_RB22[7:0]  
7 to 0 AVI_IF_RB23[7:0]  
7 to 0 AVI_IF_RB24[7:0]  
7 to 0 AVI_IF_RB25[7:0]  
7 to 0 AVI_IF_RB26[7:0]  
7 to 0 AVI_IF_RB27[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
byte 14; reserved (shall be zero)  
byte 15; reserved (shall be zero)  
byte 16; reserved (shall be zero)  
byte 17; reserved (shall be zero)  
byte 18; reserved (shall be zero)  
byte 19; reserved (shall be zero)  
byte 20; reserved (shall be zero)  
byte 21; reserved (shall be zero)  
byte 22; reserved (shall be zero)  
byte 23; reserved (shall be zero)  
byte 24; reserved (shall be zero)  
byte 25; reserved (shall be zero)  
byte 26; reserved (shall be zero)  
byte 27; reserved (shall be zero)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
73 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.6.3 Source product description InfoFrame registers  
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a  
specification for the correct definition of data bytes.  
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
60h  
SPD_IF_TYPE  
7 to 0 SPD_IF_TYPE[7:0]  
R/W  
83h*  
source product description  
InfoFrame packet type: gives the  
packet type of the source product  
description InfoFrame packet (80h  
+ InfoFrame type code as per  
EIA/CEA-861B)  
61h  
62h  
SPD_IF_VERSION  
SPD_IF_LENGTH  
7 to 0 SPD_IF_  
VERSION[7:0]  
R/W  
R/W  
00h*  
source product description  
InfoFrame version: gives the  
version number of the source  
product description InfoFrame  
7 to 5 x  
000*  
reserved (shall be 000)  
4 to 0 SPD_IF_LENGTH[4:0] R/W  
0 0000*  
source product description  
InfoFrame length: gives the  
number of data bytes for the  
source product description  
InfoFrame; this length does not  
include the checksum  
63h  
SPD_IF_CHECKSUM 7 to 0 SPD_IF_  
CHECKSUM[7:0]  
R/W  
00h*  
source product description  
InfoFrame checksum: shall be  
calculated such that a byte-wide  
sum of all three bytes of the packet  
header and all valid bytes of the  
source product description  
InfoFrame packet contents  
(determined by InfoFrame length)  
plus the checksum itself equals 0  
source product description  
InfoFrame vendor name: 7-bit  
ASCII code  
64h  
65h  
66h  
67h  
68h  
69h  
6Ah  
SPD_IF_BYTE1  
SPD_IF_BYTE2  
SPD_IF_BYTE3  
SPD_IF_BYTE4  
SPD_IF_BYTE5  
SPD_IF_BYTE6  
SPD_IF_BYTE7  
7
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0*  
reserved (shall be zero)  
character 1  
6 to 0 SPD_IF_VN1[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 2  
6 to 0 SPD_IF_VN2[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 3  
6 to 0 SPD_IF_VN3[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 4  
6 to 0 SPD_IF_VN4[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 5  
6 to 0 SPD_IF_VN5[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 6  
6 to 0 SPD_IF_VN6[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 7  
6 to 0 SPD_IF_VN7[6:0]  
000 0000*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
74 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
6Bh  
SPD_IF_BYTE8  
7
x
R/W  
R/W  
0*  
reserved (shall be zero)  
character 8  
6 to 0 SPD_IF_VN8[6:0]  
000 0000*  
source product description  
InfoFrame product description:  
7-bit ASCII code  
6Ch  
6Dh  
6Eh  
6Fh  
70h  
71h  
72h  
73h  
74h  
75h  
76h  
77h  
78h  
79h  
7Ah  
7Bh  
SPD_IF_BYTE9  
SPD_IF_BYTE10  
SPD_IF_BYTE11  
SPD_IF_BYTE12  
SPD_IF_BYTE13  
SPD_IF_BYTE14  
SPD_IF_BYTE15  
SPD_IF_BYTE16  
SPD_IF_BYTE17  
SPD_IF_BYTE18  
SPD_IF_BYTE19  
SPD_IF_BYTE20  
SPD_IF_BYTE21  
SPD_IF_BYTE22  
SPD_IF_BYTE23  
SPD_IF_BYTE24  
7
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0*  
reserved (shall be zero)  
character 1  
6 to 0 SPD_IF_PD1[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 2  
6 to 0 SPD_IF_PD2[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 3  
6 to 0 SPD_IF_PD3[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 4  
6 to 0 SPD_IF_PD4[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 5  
6 to 0 SPD_IF_PD5[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 6  
6 to 0 SPD_IF_PD6[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 7  
6 to 0 SPD_IF_PD7[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 8  
6 to 0 SPD_IF_PD8[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 9  
6 to 0 SPD_IF_PD9[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 10  
6 to 0 SPD_IF_PD10[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 11  
6 to 0 SPD_IF_PD11[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 12  
6 to 0 SPD_IF_PD12[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 13  
6 to 0 SPD_IF_PD13[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 14  
6 to 0 SPD_IF_PD14[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 15  
6 to 0 SPD_IF_PD15[6:0]  
000 0000*  
0*  
7
x
reserved (shall be zero)  
character 16  
6 to 0 SPD_IF_PD16[6:0]  
000 0000*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
75 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
7Ch  
SPD_IF_BYTE25  
7 to 0 SPD_IF_SDI[7:0]  
R/W  
source product description  
InfoFrame source device  
information: source device  
information  
00h*  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
unknown  
digital STB  
DVD  
D-VHS  
HDD video  
DVC  
DSC  
video CD  
game  
PC general  
source product description  
InfoFrame data byte  
7Dh  
7Eh  
SPD_IF_BYTE26  
SPD_IF_BYTE27  
7 to 0 SPD_IF_BYTE26[7:0] R/W  
7 to 0 SPD_IF_BYTE27[7:0] R/W  
00h*  
00h*  
data byte 26  
data byte 27  
9.6.4 Audio InfoFrame registers  
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a  
specification for the correct definition of data bytes.  
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
80h  
AUD_IF_TYPE  
7 to 0 AUD_IF_TYPE[7:0]  
R/W  
84h*  
00h*  
audio InfoFrame packet type:  
gives the packet type of the audio  
InfoFrame packet (80h +  
InfoFrame type code as per  
EIA/CEA-861B)  
81h  
82h  
AUD_IF_VERSION  
AUD_IF_LENGTH  
7 to 0 AUD_IF_  
VERSION[7:0]  
R/W  
R/W  
audio InfoFrame version: gives  
the version number of the audio  
InfoFrame  
7 to 5 x  
000*  
reserved (shall be zero)  
4 to 0 AUD_IF_LENGTH[4:0] R/W  
0 0000*  
audio InfoFrame length: gives  
the number of data bytes for the  
audio InfoFrame; this length does  
not include the checksum  
83h  
AUD_IF_CHECKSUM 7 to 0 AUD_IF_  
CHECKSUM[7:0]  
R/W  
00h*  
audio InfoFrame checksum:  
shall be calculated such that a  
byte-wide sum of all three bytes of  
the packet header and all valid  
bytes of the audio InfoFrame  
packet contents (determined by  
InfoFrame length) plus the  
checksum itself equals 0  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
76 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
84h  
AUD_IF_BYTE1  
7 to 4 AUD_IF_CT[3:0]  
R/W  
audio InfoFrame coding type:  
audio coding type  
0000*  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
other  
refer to stream header  
IEC 60958 PCM  
AC-3  
MPEG1  
MP3  
MPEG2  
AAC  
DTS  
ATRAC  
undefined  
reserved bit  
3
reserved  
R/W  
R/W  
0*  
2 to 0 AUD_IF_CC[2:0]  
audio InfoFrame channel count:  
audio channel count  
000*  
001  
010  
011  
100  
101  
110  
111  
000*  
refer to stream header  
2 channels  
3 channels  
4 channels  
5 channels  
6 channels  
7 channels  
8 channels  
85h  
AUD_IF_BYTE2  
7 to 5 reserved  
R/W  
R/W  
reserved (shall be zero)  
4 to 2 AUD_IF_SF[2:0]  
audio InfoFrame sampling  
frequency: sampling frequency  
000*  
001  
010  
011  
100  
101  
110  
111  
refer to stream header  
32 kHz  
44.1 kHz (CD)  
48 kHz  
88.2 kHz  
96 kHz  
176.4 kHz  
192 kHz  
1 to 0 AUD_IF_SS[1:0]  
R/W  
audio InfoFrame sample size:  
sample size  
00*  
01  
10  
11  
refer to stream header  
16 bits  
20 bits  
24 bits  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
77 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
86h  
AUD_IF_BYTE3  
7 to 0 AUD_IF_BYTE3[7:0]  
R/W  
00h*  
audio InfoFrame data byte 3:  
value × 8 kHz = maximum bit rate  
of audio stream (compressed  
audio format)  
87h  
88h  
AUD_IF_BYTE4  
AUD_IF_BYTE5  
7 to 0 AUD_IF_CA[7:0]  
R/W  
R/W  
00h*  
audio InfoFrame channel  
allocation: channel allocation  
(LPCM)  
7
AUD_IF_DM_INH  
audio InfoFrame down-mix  
inhibit flag: down-mix inhibit flag  
0*  
1
permitted or no information  
about any assertion of this  
prohibited  
6 to 3 AUD_IF_LSV[3:0]  
R/W  
audio InfoFrame level shift  
value: level shift value  
0000*  
0001  
0010  
0011  
1000  
:
0 dB  
1 dB  
2 dB  
3 dB  
4 dB  
:
1111  
000*  
15 dB  
2 to 0 reserved  
R/W  
reserved (shall be 000h)  
audio InfoFrame data byte x:  
x = 6 to 27  
89h  
8Ah  
8Bh  
8Ch  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
AUD_IF_BYTE6  
AUD_IF_BYTE7  
AUD_IF_BYTE8  
AUD_IF_BYTE9  
AUD_IF_BYTE10  
AUD_IF_BYTE11  
AUD_IF_BYTE12  
AUD_IF_BYTE13  
AUD_IF_BYTE14  
AUD_IF_BYTE15  
AUD_IF_BYTE16  
AUD_IF_BYTE17  
AUD_IF_BYTE18  
AUD_IF_BYTE19  
AUD_IF_BYTE20  
AUD_IF_BYTE21  
AUD_IF_BYTE22  
AUD_IF_BYTE23  
7 to 0 AUD_IF_BYTE6[7:0]  
6 to 0 AUD_IF_BYTE7[7:0]  
6 to 0 AUD_IF_BYTE8[7:0]  
6 to 0 AUD_IF_BYTE9[7:0]  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
byte 6: reserved (shall be zero)  
byte 7: reserved (shall be zero)  
byte 8: reserved (shall be zero)  
byte 9: reserved (shall be zero)  
byte 10: reserved (shall be zero)  
byte 11: reserved (shall be zero)  
byte 12: reserved (shall be zero)  
byte 13: reserved (shall be zero)  
byte 14: reserved (shall be zero)  
byte 15: reserved (shall be zero)  
byte 16: reserved (shall be zero)  
byte 17: reserved (shall be zero)  
byte 18: reserved (shall be zero)  
byte 19: reserved (shall be zero)  
byte 20: reserved (shall be zero)  
byte 21: reserved (shall be zero)  
byte 22: reserved (shall be zero)  
byte 23: reserved (shall be zero)  
7 to 0 AUD_IF_BYTE10[7:0] R/W  
7 to 0 AUD_IF_BYTE11[7:0] R/W  
7 to 0 AUD_IF_BYTE12[7:0] R/W  
7 to 0 AUD_IF_BYTE13[7:0] R/W  
7 to 0 AUD_IF_BYTE14[7:0] R/W  
7 to 0 AUD_IF_BYTE15[7:0] R/W  
7 to 0 AUD_IF_BYTE16[7:0] R/W  
7 to 0 AUD_IF_BYTE17[7:0] R/W  
7 to 0 AUD_IF_BYTE18[7:0] R/W  
7 to 0 AUD_IF_BYTE19[7:0] R/W  
7 to 0 AUD_IF_BYTE20[7:0] R/W  
7 to 0 AUD_IF_BYTE21[7:0] R/W  
7 to 0 AUD_IF_BYTE22[7:0] R/W  
7 to 0 AUD_IF_BYTE23[7:0] R/W  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
78 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
9Bh  
9Ch  
9Dh  
9Eh  
AUD_IF_BYTE24  
7 to 0 AUD_IF_BYTE24[7:0] R/W  
7 to 0 AUD_IF_BYTE25[7:0] R/W  
7 to 0 AUD_IF_BYTE26[7:0] R/W  
7 to 0 AUD_IF_BYTE27[7:0] R/W  
00h*  
00h*  
00h*  
00h*  
byte 24: reserved (shall be zero)  
byte 25: reserved (shall be zero)  
byte 26: reserved (shall be zero)  
byte 27: reserved (shall be zero)  
AUD_IF_BYTE25  
AUD_IF_BYTE26  
AUD_IF_BYTE27  
9.6.5 MPEG source InfoFrame registers  
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a  
specification for the correct definition of data bytes.  
Table 88. MPS_IF_xx registers (address A0h to BEh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
A0h  
MPS_IF_TYPE  
7 to 0 MPS_IF_TYPE[7:0]  
R/W  
85h*  
00h*  
MPEG source InfoFrame packet  
type: gives the packet type of the  
MPEG source InfoFrame packet  
(80h + InfoFrame type code as per  
EIA/CEA-861B)  
A1h  
A2h  
MPS_IF_VERSION 7 to 0 MPS_IF_VERSION[7:0] R/W  
MPEG source InfoFrame  
version: gives the version number  
of the MPEG source InfoFrame  
MPS_IF_LENGTH  
7 to 5 x  
R/W  
000*  
reserved (shall be zero)  
4 to 0 MPS_IF_LENGTH[4:0] R/W  
0 0000*  
MPEG source InfoFrame length:  
gives the number of data bytes for  
the MPEG source InfoFrame; this  
length does not include the  
checksum  
A3h  
MPS_IF_  
CHECKSUM  
7 to 0 MPS_IF_  
CHECKSUM[7:0]  
R/W  
00h*  
MPEG source InfoFrame  
checksum: shall be calculated  
such that a byte-wide sum of all  
three bytes of the packet header  
and all valid bytes of the MPEG  
source InfoFrame packet contents  
(determined by InfoFrame length)  
plus the checksum itself equals 0  
MPEG source InfoFrame MPEG  
bit rate (Hz)  
A4h  
A5h  
A6h  
A7h  
MPS_IF_BYTE1  
MPS_IF_BYTE2  
MPS_IF_BYTE3  
MPS_IF_BYTE4  
7 to 0 MPS_IF_MB0[7:0]  
7 to 0 MPS_IF_MB1[7:0]  
7 to 0 MPS_IF_MB2[7:0]  
7 to 0 MPS_IF_MB3[7:0]  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
MB#0 (lower byte)  
MB#1 (medium byte)  
MB#2 (medium byte)  
MB#3 (upper byte)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
79 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 88. MPS_IF_xx registers (address A0h to BEh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
A8h  
MPS_IF_BYTE5  
7 to 5 reserved  
R/W  
R/W  
000*  
reserved  
4
MPS_IF_FR0  
MPEG source InfoFrame field  
repeat 0: for 3 : 2 pull-down  
0*  
1
new field (picture)  
repeated field  
reserved  
3 to 2 reserved  
R/W  
R/W  
00*  
1 to 0 MPS_IF_MF[1:0]  
MPEG source InfoFrame MPEG  
frame: MPEG frame  
00*  
01  
10  
11  
unknown (no data)  
I picture  
B picture  
P picture  
MPEG source InfoFrame byte x:  
x = 6 to 27  
A9h  
AAh  
ABh  
ACh  
ADh  
AEh  
AFh  
B0h  
B1h  
B2h  
B3h  
B4h  
B5h  
B6h  
B7h  
B8h  
B9h  
BAh  
BBh  
BCh  
BDh  
BEh  
MPS_IF_BYTE6  
MPS_IF_BYTE7  
MPS_IF_BYTE8  
MPS_IF_BYTE9  
MPS_IF_BYTE10  
MPS_IF_BYTE11  
MPS_IF_BYTE12  
MPS_IF_BYTE13  
MPS_IF_BYTE14  
MPS_IF_BYTE15  
MPS_IF_BYTE16  
MPS_IF_BYTE17  
MPS_IF_BYTE18  
MPS_IF_BYTE19  
MPS_IF_BYTE20  
MPS_IF_BYTE21  
MPS_IF_BYTE22  
MPS_IF_BYTE23  
MPS_IF_BYTE24  
MPS_IF_BYTE25  
MPS_IF_BYTE26  
MPS_IF_BYTE27  
7 to 0 MPS_IF_BYTE6[7:0]  
6 to 0 MPS_IF_BYTE7[7:0]  
6 to 0 MPS_IF_BYTE8[7:0]  
6 to 0 MPS_IF_BYTE9[7:0]  
7 to 0 MPS_IF_BYTE10[7:0]  
7 to 0 MPS_IF_BYTE11[7:0]  
7 to 0 MPS_IF_BYTE12[7:0]  
7 to 0 MPS_IF_BYTE13[7:0]  
7 to 0 MPS_IF_BYTE14[7:0]  
7 to 0 MPS_IF_BYTE15[7:0]  
7 to 0 MPS_IF_BYTE16[7:0]  
7 to 0 MPS_IF_BYTE17[7:0]  
7 to 0 MPS_IF_BYTE18[7:0]  
7 to 0 MPS_IF_BYTE19[7:0]  
7 to 0 MPS_IF_BYTE20[7:0]  
7 to 0 MPS_IF_BYTE21[7:0]  
7 to 0 MPS_IF_BYTE22[7:0]  
7 to 0 MPS_IF_BYTE23[7:0]  
7 to 0 MPS_IF_BYTE24[7:0]  
7 to 0 MPS_IF_BYTE25[7:0]  
7 to 0 MPS_IF_BYTE26[7:0]  
7 to 0 MPS_IF_BYTE27[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
byte 6: reserved (shall be zero)  
byte 7: reserved (shall be zero)  
byte 8: reserved (shall be zero)  
byte 9: reserved (shall be zero)  
byte 10: reserved (shall be zero)  
byte 11: reserved  
000 0000*  
000 0000*  
000 0000*  
00h*  
00h*  
00h*  
byte 12: reserved  
00h*  
byte 13: reserved  
00h*  
byte 14: reserved  
00h*  
byte 15: reserved  
00h*  
byte 16: reserved  
00h*  
byte 17: reserved  
00h*  
byte 18: reserved  
00h*  
byte 19: reserved  
00h*  
byte 20: reserved  
00h*  
byte 21: reserved  
00h*  
byte 22: reserved  
00h*  
byte 23: reserved  
00h*  
byte 24: reserved  
00h*  
byte 25: reserved  
00h*  
byte 26: reserved  
00h*  
byte 27: reserved  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
80 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.6.6 Current page address register  
Table 89. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
00h* current page address: selects the current  
memory page  
7 to 0  
CURPAGE_ADR[7:0] W  
9.7 Audio settings and content info packets page register definitions  
The current page address for the audio settings and content info packets page is 11h.  
The configuration of the registers for this page is given in Table 90.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
81 of 119  
 
 
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Table 90. I2C-bus registers of memory page 11h[1]  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
AIP_CNTRL_0  
CA_I2S  
00h R/W  
01h R/W  
02h R/W  
03h R/W  
04h R/W  
05h R/W  
06h R/W  
07h R/W  
08h R/W  
09h R/W  
0Ah R/W  
0Bh R/W  
x
x
x
x
RST_CTS ACR_MAN  
x
x
LAYOUT  
SWAP  
RST_FIFO  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0100  
0111 1000  
0110 1001  
0000 0000  
0000 0000  
0110 0000  
0000 0000  
0000 0000  
x
x
x
x
x
x
CA_I2S[4:0]  
For test  
x
x
x
x
x
x
x
x
x
x
For test  
LATENCY_RD  
ACR_CTS_0  
ACR_CTS_1  
ACR_CTS_2  
ACR_N_0  
LATENCY_RD[7:0]  
CTS[7:0]  
CTS[15:8]  
x
x
x
x
CTS[19:16]  
N[7:0]  
ACR_N_1  
N[15:8]  
x
ACR_N_2  
x
x
x
x
x
x
N[19:16]  
SET_  
GC_AVMUTE  
x
x
x
x
CLR_MUTE  
MUTE  
CTS_N  
0Ch R/W  
0Dh R/W  
x
x
x
x
M_SEL[1:0]  
K_SEL[2:0]  
0000 0000  
0000 0100  
0000 0000  
ENC_CNTRL  
DIP_FLAGS  
x
-
x
CTL_CODE[1:0]  
DC_CTL[1:0]  
0Eh R/W FORCE_  
NULL  
NULL  
ACP  
IF4  
ISRC2  
ISRC1  
GC  
IF1  
ACR  
DIP_IF_FLAGS  
Not used  
0Fh R/W  
x
x
IF5  
IF3  
IF2  
x
0000 0000  
0000 0000  
:
10h  
:
-
:
-
:
:
Not used  
13h  
-
-
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
CH_STAT_B_0  
CH_STAT_B_1  
CH_STAT_B_3  
CH_STAT_B_4  
14h R/W  
15h R/W  
16h R/W  
17h R/W  
CH_STAT_BYTE_0[7:0]  
CH_STAT_BYTE_1[7:0]  
CH_STAT_BYTE_3[7:0]  
CH_STAT_BYTE_4[7:0]  
CH_STAT_B_2_AP0_L 18h R/W  
CH_STAT_B_2_AP0_R 19h R/W  
CH_STAT_B_2_AP1_L 1Ah R/W  
CH_STAT_B_2_AP1_R 1Bh R/W  
CH_STAT_B_2_AP2_L 1Ch R/W  
CH_STAT_B_2_AP2_R 1Dh R/W  
CH_STAT_B_2_AP3_L 1Eh R/W  
CH_STAT_BYTE_2_AP0_L[7:0]  
CH_STAT_BYTE_2_AP0_R[7:0]  
CH_STAT_BYTE_2_AP1_L[7:0]  
CH_STAT_BYTE_2_AP1_R[7:0]  
CH_STAT_BYTE_2_AP2_L[7:0]  
CH_STAT_BYTE_2_AP2_R[7:0]  
CH_STAT_BYTE_2_AP3_L[7:0]  
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Table 90. I2C-bus registers of memory page 11h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
CH_STAT_B_2_AP3_R 1Fh R/W  
ISRC1_PACKET_TYPE 20h R/W  
CH_STAT_BYTE_2_AP3_R[7:0]  
ISRC1_PACKET_TYPE[7:0]  
ISRC1_RSVD[5:3]  
0000 0000  
0000 0101  
0000 0000  
ISRC1_CTRL  
21h R/W  
ISRC_  
CONT  
ISRC_  
VALID  
ISRC_STATUS[2:0]  
ISRC1_RSVD  
22h R/W  
23h R/W  
24h R/W  
25h R/W  
26h R/W  
27h R/W  
28h R/W  
29h R/W  
2Ah R/W  
2Bh R/W  
2Ch R/W  
2Dh R/W  
2Eh R/W  
2Fh R/W  
30h R/W  
31h R/W  
32h R/W  
33h R/W  
34h R/W  
35h R/W  
36h R/W  
37h R/W  
38h R/W  
39h R/W  
3Ah R/W  
3Bh R/W  
3Ch R/W  
3Dh R/W  
ISRC1_RSVD[7:0]  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
UPC_EAN_ISRC_0  
UPC_EAN_ISRC_1  
UPC_EAN_ISRC_2  
UPC_EAN_ISRC_3  
UPC_EAN_ISRC_4  
UPC_EAN_ISRC_5  
UPC_EAN_ISRC_6  
UPC_EAN_ISRC_7  
UPC_EAN_ISRC_8  
UPC_EAN_ISRC_9  
UPC_EAN_ISRC_10  
UPC_EAN_ISRC_11  
UPC_EAN_ISRC_12  
UPC_EAN_ISRC_13  
UPC_EAN_ISRC_14  
UPC_EAN_ISRC_15  
ISRC1_PB16  
UPC_EAN_ISRC_0[7:0]  
UPC_EAN_ISRC_1[7:0]  
UPC_EAN_ISRC_2[7:0]  
UPC_EAN_ISRC_3[7:0]  
UPC_EAN_ISRC_4[7:0]  
UPC_EAN_ISRC_5[7:0]  
UPC_EAN_ISRC_6[7:0]  
UPC_EAN_ISRC_7[7:0]  
UPC_EAN_ISRC_8[7:0]  
UPC_EAN_ISRC_9[7:0]  
UPC_EAN_ISRC_10[7:0]  
UPC_EAN_ISRC_11[7:0]  
UPC_EAN_ISRC_12[7:0]  
UPC_EAN_ISRC_13[7:0]  
UPC_EAN_ISRC_14[7:0]  
UPC_EAN_ISRC_15[7:0]  
ISRC1_PB_BYTE_16[7:0]  
ISRC1_PB_BYTE_17[7:0]  
ISRC1_PB_BYTE_18[7:0]  
ISRC1_PB_BYTE_19[7:0]  
ISRC1_PB_BYTE_20[7:0]  
ISRC1_PB_BYTE_21[7:0]  
ISRC1_PB_BYTE_22[7:0]  
ISRC1_PB_BYTE_23[7:0]  
ISRC1_PB_BYTE_24[7:0]  
ISRC1_PB_BYTE_25[7:0]  
ISRC1_PB_BYTE_26[7:0]  
ISRC1_PB17  
ISRC1_PB18  
ISRC1_PB19  
ISRC1_PB20  
ISRC1_PB21  
ISRC1_PB22  
ISRC1_PB23  
ISRC1_PB24  
ISRC1_PB25  
ISRC1_PB26  
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Table 90. I2C-bus registers of memory page 11h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
ISRC1_PB27  
Not used  
3Eh R/W  
ISRC1_PB_BYTE_27[7:0]  
-
0000 0000  
0000 0000  
0000 0110  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
3Fh  
-
ISRC2_PACKET_TYPE 40h R/W  
ISRC2_PACKET_TYPE[7:0]  
ISRC2_RSVD1[7:0]  
ISRC2_RSVD1  
41h R/W  
42h R/W  
43h R/W  
44h R/W  
45h R/W  
46h R/W  
47h R/W  
48h R/W  
49h R/W  
4Ah R/W  
4Bh R/W  
4Ch R/W  
4Dh R/W  
4Eh R/W  
4Fh R/W  
50h R/W  
51h R/W  
52h R/W  
53h R/W  
54h R/W  
55h R/W  
56h R/W  
57h R/W  
58h R/W  
59h R/W  
5Ah R/W  
5Bh R/W  
5Ch R/W  
5Dh R/W  
ISRC2_RSVD2  
ISRC2_RSVD2[7:0]  
UPC_EAN_ISRC_16  
UPC_EAN_ISRC_17  
UPC_EAN_ISRC_18  
UPC_EAN_ISRC_19  
UPC_EAN_ISRC_20  
UPC_EAN_ISRC_21  
UPC_EAN_ISRC_22  
UPC_EAN_ISRC_23  
UPC_EAN_ISRC_24  
UPC_EAN_ISRC_25  
UPC_EAN_ISRC_26  
UPC_EAN_ISRC_27  
UPC_EAN_ISRC_28  
UPC_EAN_ISRC_29  
UPC_EAN_ISRC_30  
UPC_EAN_ISRC_31  
ISRC2_PB16  
UPC_EAN_ISRC_16[7:0]  
UPC_EAN_ISRC_17[7:0]  
UPC_EAN_ISRC_18[7:0]  
UPC_EAN_ISRC_19[7:0]  
UPC_EAN_ISRC_20[7:0]  
UPC_EAN_ISRC_21[7:0]  
UPC_EAN_ISRC_22[7:0]  
UPC_EAN_ISRC_23[7:0]  
UPC_EAN_ISRC_24[7:0]  
UPC_EAN_ISRC_25[7:0]  
UPC_EAN_ISRC_26[7:0]  
UPC_EAN_ISRC_27[7:0]  
UPC_EAN_ISRC_28[7:0]  
UPC_EAN_ISRC_29[7:0]  
UPC_EAN_ISRC_30[7:0]  
UPC_EAN_ISRC_31[7:0]  
ISRC2_PB_BYTE_16[7:0]  
ISRC2_PB_BYTE_17[7:0]  
ISRC2_PB_BYTE_18[7:0]  
ISRC2_PB_BYTE_19[7:0]  
ISRC2_PB_BYTE_20[7:0]  
ISRC2_PB_BYTE_21[7:0]  
ISRC2_PB_BYTE_22[7:0]  
ISRC2_PB_BYTE_23[7:0]  
ISRC2_PB_BYTE_24[7:0]  
ISRC2_PB_BYTE_25[7:0]  
ISRC2_PB_BYTE_26[7:0]  
ISRC2_PB17  
ISRC2_PB18  
ISRC2_PB19  
ISRC2_PB20  
ISRC2_PB21  
ISRC2_PB22  
ISRC2_PB23  
ISRC2_PB24  
ISRC2_PB25  
ISRC2_PB26  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
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Table 90. I2C-bus registers of memory page 11h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
ISRC2_PB27  
Not used  
5Eh R/W  
ISRC2_PB_BYTE_27[7:0]  
-
0000 0000  
0000 0000  
0000 0100  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
5Fh  
-
ACP_PACKET_TYPE  
ACP_TYPE  
ACP_RSVD  
ACP_PB0  
60h R/W  
61h R/W  
62h R/W  
63h R/W  
64h R/W  
65h R/W  
66h R/W  
67h R/W  
68h R/W  
69h R/W  
6Ah R/W  
6Bh R/W  
6Ch R/W  
6Dh R/W  
6Eh R/W  
6Fh R/W  
70h R/W  
71h R/W  
72h R/W  
73h R/W  
74h R/W  
75h R/W  
76h R/W  
77h R/W  
78h R/W  
79h R/W  
7Ah R/W  
7Bh R/W  
7Ch R/W  
7Dh R/W  
ACP_PACKET_TYPE[7:0]  
ACP_TYPE[7:0]  
ACP_RSVD[7:0]  
ACP_PB_BYTE_0[7:0]  
ACP_PB_BYTE_1[7:0]  
ACP_PB_BYTE_2[7:0]  
ACP_PB_BYTE_3[7:0]  
ACP_PB_BYTE_4[7:0]  
ACP_PB_BYTE_5[7:0]  
ACP_PB_BYTE_6[7:0]  
ACP_PB_BYTE_7[7:0]  
ACP_PB_BYTE_8[7:0]  
ACP_PB_BYTE_9[7:0]  
ACP_PB_BYTE_10[7:0]  
ACP_PB_BYTE_11[7:0]  
ACP_PB_BYTE_12[7:0]  
ACP_PB_BYTE_13[7:0]  
ACP_PB_BYTE_14[7:0]  
ACP_PB_BYTE_15[7:0]  
ACP_PB_BYTE_16[7:0]  
ACP_PB_BYTE_17[7:0]  
ACP_PB_BYTE_18[7:0]  
ACP_PB_BYTE_19[7:0]  
ACP_PB_BYTE_20[7:0]  
ACP_PB_BYTE_21[7:0]  
ACP_PB_BYTE_22[7:0]  
ACP_PB_BYTE_23[7:0]  
ACP_PB_BYTE_24[7:0]  
ACP_PB_BYTE_25[7:0]  
ACP_PB_BYTE_26[7:0]  
ACP_PB1  
ACP_PB2  
ACP_PB3  
ACP_PB4  
ACP_PB5  
ACP_PB6  
ACP_PB7  
ACP_PB8  
ACP_PB9  
ACP_PB10  
ACP_PB11  
ACP_PB12  
ACP_PB13  
ACP_PB14  
ACP_PB15  
ACP_PB16  
ACP_PB17  
ACP_PB18  
ACP_PB19  
ACP_PB20  
ACP_PB21  
ACP_PB22  
ACP_PB23  
ACP_PB24  
ACP_PB25  
ACP_PB26  
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 90. I2C-bus registers of memory page 11h[1] …continued  
Register  
Sub R/W  
addr  
Bit  
Default value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
ACP_PB27  
Not used  
:
7Eh R/W  
ACP_PB_BYTE_27[7:0]  
0000 0000  
0000 0000  
:
7Fh  
:
-
:
-
:
Not used  
CURPAGE_ADR  
FEh  
FFh  
-
-
0000 0000  
0000 0000  
W
CURPAGE_ADR[7:0]  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.7.1 Audio input processor control registers  
Table 91. AIP_CNTRL_0 register (address 00h) bit description  
Legend: * = default value  
Bit  
7
Symbol  
x
Access Value  
Description  
R/W  
R/W  
0*  
undefined  
6
RST_CTS  
reset CTS  
0*  
1
no specific action  
reset CTS generation (soft reset)  
audio clock regeneration manual  
5
ACR_MAN  
R/W  
0*  
1
automatic audio clock regeneration time  
stamp generation  
manual audio clock regeneration time stamp  
generation  
4 to 3  
2
x
R/W  
R/W  
00*  
undefined  
LAYOUT  
layout  
0*  
1
set layout 0  
set layout 1  
1
0
SWAP  
R/W  
R/W  
0*  
swap: for internal use  
reset FIFO  
RST_FIFO  
0*  
1
no specific action  
reset audio FIFO  
Table 92. CA_I2S register (address 01h) bit description  
Legend: * = default value  
Bit  
Symbol  
x
Access Value  
Description  
7 to 5  
4 to 0  
R/W  
R/W  
000*  
undefined  
channel allocation I2S-bus port: layout 1  
CA_I2S[4:0]  
0 0000*  
Table 93. LATENCY_RD register (address 04h) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
R/W 04h*  
Description  
7 to 0  
LATENCY_RD[7:0]  
latency read: latency value in audio FIFO  
Table 94. ACR_CTS_x registers (address 05h to 07h) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
07h  
ACR_CTS_2  
7 to 4  
x
R/W  
R/W  
R/W  
R/W  
0000* undefined  
3 to 0 CTS[19:16]  
7 to 0 CTS[15:8]  
7 to 0 CTS[7:0]  
0000* CTS: audio clock recovery CTS value for  
manual CTS settings  
06h  
05h  
ACR_CTS_1  
ACR_CTS_0  
69h*  
78h*  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
87 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 95. ACR_N_x registers (address 08h to 0Ah) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value  
Description  
0Ah  
ACR_N_2  
7 to 4 x  
R/W  
R/W  
R/W  
R/W  
0000*  
0000*  
60h*  
undefined  
3 to 0 N[19:16]  
7 to 0 N[15:8]  
7 to 0 N[7:0]  
N: audio clock recovery N value for  
manual N-settings  
09h  
08h  
ACR_N_1  
ACR_N_0  
00h*  
Table 96. GC_AVMUTE register (address 0Bh) bit description  
Legend: * = default value  
Bit  
7 to 2  
1
Symbol  
x
Access Value  
Description  
0000 00* undefined  
set mute: GCP.SB0 (bit 0)  
R/W  
R/W  
SET_MUTE  
0*  
1
no specific action  
set AVMUTE flag  
0
CLR_MUTE  
R/W  
clear mute: GCP.SB0 (bit 4)  
no specific action  
0*  
1
clear AVMUTE flag  
Table 97. CTS_N register (address 0Ch) bit description  
Legend: * = default value  
Bit  
Symbol  
x
Access Value  
Description  
7 to 6  
5 to 4  
R/W  
R/W  
00*  
undefined  
M_SEL[1:0]  
M select: postdivider mts (measured time  
stamp)  
00*  
01  
10  
11  
0*  
CTS = mts  
CTS = mts / 2  
CTS = mts / 4  
CTS = mts / 8  
3
x
R/W  
R/W  
undefined  
2 to 0  
K_SEL[2:0]  
K select: predivider (scales n)  
000*  
001  
010  
011  
1XX  
k = 1  
k = 2  
k = 3  
k = 4  
k = 8  
Table 98. ENC_CNTRL register (address 0Dh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
R/W 0000* undefined  
7 to 4  
x
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
88 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 98. ENC_CNTRL register (address 0Dh) bit description …continued  
Legend: * = default value  
Bit Symbol  
3 to 2 CTL_CODE[1:0]  
Access Value Description  
R/W  
control code: force CTL[1:0]  
00  
CTL[1:0] = 00 (DVI mode)  
01*  
CTL[1:0] = 01 (advised to use in case of  
HDMI mode)  
10  
11  
CTL[1:0] = 10 (only for debugging purposes)  
CTL[1:0] = 11 (only for debugging purposes)  
disparity counter control  
1 to 0 DC_CTL[1:0]  
R/W  
00*  
01  
10  
11  
video guard band initializes disparity_cnt  
video_data_enable enables disparity_cnt  
free-running disparity_cnt  
undefined  
Table 99. DIP_FLAGS register (address 0Eh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
7
FORCE_NULL  
R/W  
R/W  
force null  
0*  
1
no specific action  
insert null-packets continuously  
null  
6
5
NULL  
0*  
1
no specific action  
insert one null-packet (this bit is reset by  
internal control)  
-
R/W  
R/W  
-: data packet header/contents as specified by  
registers 80h to 9Eh  
0*  
1
no specific action  
insert InfoFrame in first free slot after the  
keepout window  
4
3
ACP  
audio content protection: data packet  
header/contents as specified by registers 60h  
to 7Eh (see Table 105)  
0*  
1
no specific action  
insert ’acp’ in first free slot after the keepout  
window  
ISRC2  
R/W  
international standard recording code 2:  
data packet header/contents as specified by  
registers 40h to 5Eh (see Table 104)  
0*  
1
no specific action  
insert ’isrc2’ in first free slot after the keepout  
window  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
89 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 99. DIP_FLAGS register (address 0Eh) bit description …continued  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
2
ISRC1  
R/W  
international standard recording code 1:  
data packet header/contents as specified by  
registers 20h to 3Eh (see Table 103)  
0*  
1
no specific action  
insert ’isrc1’ in first free slot after the keepout  
window  
1
0
GC  
R/W  
R/W  
general control  
0*  
1
no specific action  
insert general control packet (just after  
v-pulse)  
ACR  
audio clock regeneration  
no specific action  
0*  
1
insert audio clock regeneration packets  
Table 100. DIP_IF_FLAGS register (address 0Fh) bit description  
Legend: * = default value  
Bit  
7 to 6  
5
Symbol  
Access Value Description  
x
R/W  
R/W  
00*  
undefined  
IF5  
if5: data packet header/contents as specified  
by registers A0h to BEh (page 10h)  
0*  
1
no specific action  
insert ’if5’ in first free slot after the keepout  
window  
4
3
2
1
0
IF4  
IF3  
IF2  
IF1  
x
R/W  
R/W  
R/W  
R/W  
R/W  
if4: data packet header/contents as specified  
by registers 80h to 9Eh (page 10h)  
0*  
1
no specific action  
insert ’if4’ in first free slot after the keepout  
window  
if3: data packet header/contents as specified  
by registers 60h to 7Eh (page 10h)  
0*  
1
no specific action  
insert ’if3’ in first free slot after the keepout  
window  
if2: data packet header/contents as specified  
by registers 40h to 5Eh (page 10h)  
0*  
1
no specific action  
insert ’if2’ in first free slot after the keepout  
window  
if1: data packet header/contents as specified  
by registers 20h to 3Eh (page 10h)  
0*  
1
no specific action  
insert ’if1’ in first free slot after the keepout  
window  
0*  
undefined  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
90 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 101. CH_STAT_B_x channel status bytes 0, 1, 3 and 4 registers (address 14h to 17h) bit description  
Legend: * = default value  
Address  
Register  
Bit  
Symbol  
Access Value Description  
channel status byte x:  
x = 0 to 4  
14h  
15h  
16h  
17h  
CH_STAT_B_0  
CH_STAT_B_1  
CH_STAT_B_3  
CH_STAT_B_4  
7 to 0  
7 to 0  
7 to 0  
7 to 0  
CH_STAT_BYTE_0[7:0]  
CH_STAT_BYTE_1[7:0]  
CH_STAT_BYTE_3[7:0]  
CH_STAT_BYTE_4[7:0]  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
byte 0  
byte 1  
byte 3  
byte 4  
Table 102. CH_STAT_B_2_APx_n channel status byte 2 registers (address 18h to 1Fh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
channel status byte 2  
of audio port x:  
x = 0 to 3  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
CH_STAT_B_2_AP0_L 7 to 0 CH_STAT_BYTE_2_AP0_L[7:0] R/W  
CH_STAT_B_2_AP0_R 7 to 0 CH_STAT_BYTE_2_AP0_R[7:0] R/W  
CH_STAT_B_2_AP1_L 7 to 0 CH_STAT_BYTE_2_AP1_L[7:0] R/W  
CH_STAT_B_2_AP1_R 7 to 0 CH_STAT_BYTE_2_AP1_R[7:0] R/W  
CH_STAT_B_2_AP2_L 7 to 0 CH_STAT_BYTE_2_AP2_L[7:0] R/W  
CH_STAT_B_2_AP2_R 7 to 0 CH_STAT_BYTE_2_AP2_R[7:0] R/W  
CH_STAT_B_2_AP3_L 7 to 0 CH_STAT_BYTE_2_AP3_L[7:0] R/W  
CH_STAT_B_2_AP3_R 7 to 0 CH_STAT_BYTE_2_AP3_R[7:0] R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
audio port 0 left  
audio port 0 right  
audio port 1 left  
audio port 1 right  
audio port 2 left  
audio port 2 right  
audio port 3 left  
audio port 3 right  
9.7.2 ISRC packets registers  
Below is an example of use. Please refer to HDMI 1.2a specification for the correct  
definition of data bytes.  
See HDMI 1.2a specification, section 8.8 for rules regarding the use of the ISRC packets.  
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
20h  
ISRC1_PACKET_  
7 to 0 ISRC1_PACKET_TYPE[7:0] R/W  
05h* ISRC1 packet type: packet type  
TYPE  
of the ISRC1 packet  
21h  
ISRC1_CTRL  
7
6
ISRC_CONT  
ISRC_VALID  
R/W  
R/W  
R/W  
R/W  
0*  
0*  
ISRC continued: ISRC continued  
in next packet  
ISRC valid: ISRC status and data  
are valid  
5 to 3 ISRC1_RSVD[5:3]  
2 to 0 ISRC_STATUS[2:0]  
000* ISRC1 reserved: reserved (shall  
be zero)  
000* ISRC status  
001  
010  
100  
starting position  
intermediate position  
ending position  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
91 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
22h  
ISRC1_RSVD  
7 to 0 ISRC1_RSVD[7:0]  
R/W  
00h* ISRC1 reserved: reserved (shall  
be zero)  
ISRC1 data byte x: x = 0 to 15  
UPC/EAN or ISRC byte 0  
UPC/EAN or ISRC byte 1  
UPC/EAN or ISRC byte 2  
UPC/EAN or ISRC byte 3  
UPC/EAN or ISRC byte 4  
UPC/EAN or ISRC byte 5  
UPC/EAN or ISRC byte 6  
UPC/EAN or ISRC byte 7  
UPC/EAN or ISRC byte 8  
UPC/EAN or ISRC byte 9  
UPC/EAN or ISRC byte 10  
UPC/EAN or ISRC byte 11  
UPC/EAN or ISRC byte 12  
UPC/EAN or ISRC byte 13  
UPC/EAN or ISRC byte 14  
UPC/EAN or ISRC byte 15  
ISRC1 data byte x: x = 16 to 27  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
UPC_EAN_ISRC_0  
UPC_EAN_ISRC_1  
UPC_EAN_ISRC_2  
UPC_EAN_ISRC_3  
UPC_EAN_ISRC_4  
UPC_EAN_ISRC_5  
UPC_EAN_ISRC_6  
UPC_EAN_ISRC_7  
UPC_EAN_ISRC_8  
UPC_EAN_ISRC_9  
7 to 0 UPC_EAN_ISRC_0[7:0]  
7 to 0 UPC_EAN_ISRC_1[7:0]  
7 to 0 UPC_EAN_ISRC_2[7:0]  
7 to 0 UPC_EAN_ISRC_3[7:0]  
7 to 0 UPC_EAN_ISRC_4[7:0]  
7 to 0 UPC_EAN_ISRC_5[7:0]  
7 to 0 UPC_EAN_ISRC_6[7:0]  
7 to 0 UPC_EAN_ISRC_7[7:0]  
7 to 0 UPC_EAN_ISRC_8[7:0]  
7 to 0 UPC_EAN_ISRC_9[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
UPC_EAN_ISRC_10 7 to 0 UPC_EAN_ISRC_10[7:0]  
UPC_EAN_ISRC_11 7 to 0 UPC_EAN_ISRC_11[7:0]  
UPC_EAN_ISRC_12 7 to 0 UPC_EAN_ISRC_12[7:0]  
UPC_EAN_ISRC_13 7 to 0 UPC_EAN_ISRC_13[7:0]  
UPC_EAN_ISRC_14 7 to 0 UPC_EAN_ISRC_14[7:0]  
UPC_EAN_ISRC_15 7 to 0 UPC_EAN_ISRC_15[7:0]  
33h  
34h  
ISRC1_PB16  
ISRC1_PB17  
ISRC1_PB18  
ISRC1_PB19  
ISRC1_PB20  
ISRC1_PB21  
ISRC1_PB22  
ISRC1_PB23  
ISRC1_PB24  
ISRC1_PB25  
ISRC1_PB26  
ISRC1_PB27  
7 to 0 ISRC1_PB_BYTE_16[7:0]  
7 to 0 ISRC1_PB_BYTE_17[7:0]  
7 to 0 ISRC1_PB_BYTE_18[7:0]  
7 to 0 ISRC1_PB_BYTE_19[7:0]  
7 to 0 ISRC1_PB_BYTE_20[7:0]  
7 to 0 ISRC1_PB_BYTE_21[7:0]  
7 to 0 ISRC1_PB_BYTE_22[7:0]  
7 to 0 ISRC1_PB_BYTE_23[7:0]  
7 to 0 ISRC1_PB_BYTE_24[7:0]  
7 to 0 ISRC1_PB_BYTE_25[7:0]  
7 to 0 ISRC1_PB_BYTE_26[7:0]  
7 to 0 ISRC1_PB_BYTE_27[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
reserved byte 16 (shall be set to  
a value of 0)  
reserved byte 17 (shall be set to  
a value of 0)  
35h  
reserved byte 18 (shall be set to  
a value of 0)  
36h  
reserved byte 19 (shall be set to  
a value of 0)  
37h  
reserved byte 20 (shall be set to  
a value of 0)  
38h  
reserved byte 21 (shall be set to  
a value of 0)  
39h  
reserved byte 22 (shall be set to  
a value of 0)  
3Ah  
3Bh  
3Ch  
3Dh  
3Eh  
TDA9983B_1  
reserved byte 23 (shall be set to  
a value of 0)  
reserved byte 24 (shall be set to  
a value of 0)  
reserved byte 25 (shall be set to  
a value of 0)  
reserved byte 26 (shall be set to  
a value of 0)  
reserved byte 27 (shall be set to  
a value of 0)  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
92 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
40h  
41h  
42h  
ISRC2_PACKET_  
TYPE  
7 to 0 ISRC2_PACKET_TYPE[7:0] R/W  
06h* ISRC2 packet type: packet type  
of the ISRC2 packet  
ISRC2_RSVD1  
7 to 0 ISRC2_RSVD1[7:0]  
7 to 0 ISRC2_RSVD2[7:0]  
R/W  
R/W  
00h* ISRC2 reserved 1: reserved  
(shall be zero)  
ISRC2_RSVD2  
00h* ISRC2 reserved 2: reserved  
(shall be zero)  
ISRC2 data byte x: x = 0 to 15  
43h  
44h  
45h  
46h  
47h  
48h  
49h  
4Ah  
4Bh  
4Ch  
4Dh  
4Eh  
4Fh  
50h  
51h  
52h  
UPC_EAN_ISRC_16 7 to 0 UPC_EAN_ISRC_16[7:0]  
UPC_EAN_ISRC_17 7 to 0 UPC_EAN_ISRC_17[7:0]  
UPC_EAN_ISRC_18 7 to 0 UPC_EAN_ISRC_18[7:0]  
UPC_EAN_ISRC_19 7 to 0 UPC_EAN_ISRC_19[7:0]  
UPC_EAN_ISRC_20 7 to 0 UPC_EAN_ISRC_20[7:0]  
UPC_EAN_ISRC_21 7 to 0 UPC_EAN_ISRC_21[7:0]  
UPC_EAN_ISRC_22 7 to 0 UPC_EAN_ISRC_22[7:0]  
UPC_EAN_ISRC_23 7 to 0 UPC_EAN_ISRC_23[7:0]  
UPC_EAN_ISRC_24 7 to 0 UPC_EAN_ISRC_24[7:0]  
UPC_EAN_ISRC_25 7 to 0 UPC_EAN_ISRC_25[7:0]  
UPC_EAN_ISRC_26 7 to 0 UPC_EAN_ISRC_26[7:0]  
UPC_EAN_ISRC_27 7 to 0 UPC_EAN_ISRC_27[7:0]  
UPC_EAN_ISRC_28 7 to 0 UPC_EAN_ISRC_28[7:0]  
UPC_EAN_ISRC_29 7 to 0 UPC_EAN_ISRC_29[7:0]  
UPC_EAN_ISRC_30 7 to 0 UPC_EAN_ISRC_30[7:0]  
UPC_EAN_ISRC_31 7 to 0 UPC_EAN_ISRC_31[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
UPC/EAN or ISRC byte 16  
UPC/EAN or ISRC byte 17  
UPC/EAN or ISRC byte 18  
UPC/EAN or ISRC byte 19  
UPC/EAN or ISRC byte 20  
UPC/EAN or ISRC byte 21  
UPC/EAN or ISRC byte 22  
UPC/EAN or ISRC byte 23  
UPC/EAN or ISRC byte 24  
UPC/EAN or ISRC byte 25  
UPC/EAN or ISRC byte 26  
UPC/EAN or ISRC byte 27  
UPC/EAN or ISRC byte 28  
UPC/EAN or ISRC byte 29  
UPC/EAN or ISRC byte 30  
UPC/EAN or ISRC byte 31  
ISRC2 data byte x: x = 16 to 27  
53h  
54h  
55h  
56h  
57h  
58h  
59h  
5Ah  
5Bh  
ISRC2_PB16  
ISRC2_PB17  
ISRC2_PB18  
ISRC2_PB19  
ISRC2_PB20  
ISRC2_PB21  
ISRC2_PB22  
ISRC2_PB23  
ISRC2_PB24  
7 to 0 ISRC2_PB_BYTE_16[7:0]  
7 to 0 ISRC2_PB_BYTE_17[7:0]  
7 to 0 ISRC2_PB_BYTE_18[7:0]  
7 to 0 ISRC2_PB_BYTE_19[7:0]  
7 to 0 ISRC2_PB_BYTE_20[7:0]  
7 to 0 ISRC2_PB_BYTE_21[7:0]  
7 to 0 ISRC2_PB_BYTE_22[7:0]  
7 to 0 ISRC2_PB_BYTE_23[7:0]  
7 to 0 ISRC2_PB_BYTE_24[7:0]  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
reserved byte 16 (shall be set to  
a value of 0)  
reserved byte 17 (shall be set to  
a value of 0)  
reserved byte 18 (shall be set to  
a value of 0)  
reserved byte 19 (shall be set to  
a value of 0)  
reserved byte 20 (shall be set to  
a value of 0)  
reserved byte 21 (shall be set to  
a value of 0)  
reserved byte 22 (shall be set to  
a value of 0)  
reserved byte 23 (shall be set to  
a value of 0)  
reserved byte 24 (shall be set to  
a value of 0)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
93 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
5Ch  
5Dh  
5Eh  
ISRC2_PB25  
7 to 0 ISRC2_PB_BYTE_25[7:0]  
7 to 0 ISRC2_PB_BYTE_26[7:0]  
7 to 0 ISRC2_PB_BYTE_27[7:0]  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
reserved byte 25 (shall be set to  
a value of 0)  
ISRC2_PB26  
ISRC2_PB27  
reserved byte 26 (shall be set to  
a value of 0)  
reserved byte 27 (shall be set to  
a value of 0)  
9.7.3 Audio content protection packet registers  
Below is an example of use. Please refer to HDMI 1.2a specification for the correct  
definition of data bytes.  
See HDMI 1.2a specification, section 9.3 for rules regarding the use of ACP packets.  
Table 105. ACP packet registers (address 60h to 7Eh) bit description  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
60h  
ACP_  
PACKET_  
TYPE  
7 to 0 ACP_PACKET_  
TYPE[7:0]  
R/W  
04h*  
audio content protection packet type:  
packet type of the audio content protection  
packet  
61h  
62h  
63h  
ACP_TYPE  
ACP_RSVD  
ACP_PB0  
7 to 0 ACP_TYPE[7:0]  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
audio content protection type: content  
protection type  
7 to 0 ACP_RSVD[7:0]  
7 to 0 ACP_PB_BYTE_0[7:0]  
audio content protection reserved:  
reserved (shall be zero)  
audio content protection data byte 0  
ACP_TYPE = 2: DVD-audio  
DVD-Audio_Type_Dependent_  
Generation [8 bits] identifies the  
generation of the DVD-Audio-specific  
ACP_Type_ Dependent fields. Shall be  
set to logic 1.  
ACP_TYPE = 3: super audio CD  
CCI_1_b0[7:0]  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
94 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 105. ACP packet registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
audio content protection data byte 1  
64h  
ACP_PB1  
7 to 6 ACP_PB_BYTE_1[7:6]  
5 to 3 ACP_PB_BYTE_1[5:3]  
2 to 1 ACP_PB_BYTE_1[2:1]  
R/W  
00*  
ACP_TYPE = 2: DVD audio  
Copy_Permission[1:0] =  
audio_copy_permission parameter  
ACP_TYPE = 3: super audio CD  
CCI_1_b1[7:6]  
R/W  
000*  
ACP_TYPE = 2: DVD audio  
Copy_Number[2:0] =  
audio_copy_number parameter  
ACP_TYPE = 3: super audio CD  
CCI_1_b1[5:3]  
R/W  
R/W  
00*  
0*  
ACP_TYPE = 2: DVD audio  
Quality[1:0] = audio_quality parameter  
ACP_TYPE = 3: super audio CD  
CCI_1_b1[2:1]  
0
ACP_PB_BYTE_1[0]  
ACP_TYPE = 2: DVD audio  
Transaction = audio_transaction  
parameter  
ACP_TYPE = 3: super audio CD  
CCI_1_b1[0]  
65h  
66h  
67h  
68h  
ACP_PB2  
ACP_PB3  
ACP_PB4  
ACP_PB5  
7 to 0 ACP_PB_BYTE_2[7:0]  
7 to 0 ACP_PB_BYTE_3[7:0]  
7 to 0 ACP_PB_BYTE_4[7:0]  
7 to 0 ACP_PB_BYTE_5[7:0]  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
audio content protection data byte 2  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b2[7:0]  
audio content protection data byte 3  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b3[7:0]  
audio content protection data byte 4  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b4[7:0]  
audio content protection data byte 5  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b5[7:0]  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
95 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 105. ACP packet registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
69h  
6Ah  
6Bh  
6Ch  
6Dh  
6Eh  
6Fh  
70h  
ACP_PB6  
ACP_PB7  
ACP_PB8  
ACP_PB9  
ACP_PB10  
ACP_PB11  
ACP_PB12  
ACP_PB13  
7 to 0 ACP_PB_BYTE_6[7:0]  
7 to 0 ACP_PB_BYTE_7[7:0]  
7 to 0 ACP_PB_BYTE_8[7:0]  
7 to 0 ACP_PB_BYTE_9[7:0]  
R/W  
R/W  
R/W  
R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
audio content protection data byte 6  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b6[7:0]  
audio content protection data byte 7  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b7[7:0]  
audio content protection data byte 8  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b8[7:0]  
audio content protection data byte 9  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b9[7:0]  
7 to 0 ACP_PB_BYTE_10[7:0] R/W  
7 to 0 ACP_PB_BYTE_11[7:0] R/W  
7 to 0 ACP_PB_BYTE_12[7:0] R/W  
7 to 0 ACP_PB_BYTE_13[7:0] R/W  
audio content protection data byte 10  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b10[7:0]  
audio content protection data byte 11  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b11[7:0]  
audio content protection data byte 12  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b12[7:0]  
audio content protection data byte 13  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b13[7:0]  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
96 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 105. ACP packet registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
71h  
72h  
73h  
ACP_PB14  
ACP_PB15  
ACP_PB16  
7 to 0 ACP_PB_BYTE_14[7:0] R/W  
7 to 0 ACP_PB_BYTE_15[7:0] R/W  
7 to 0 ACP_PB_BYTE_16[7:0] R/W  
00h*  
00h*  
00h*  
audio content protection data byte 14  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b14[7:0]  
audio content protection data byte 15  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b15[7:0]  
audio content protection data byte 16  
ACP_TYPE = 2: DVD audio  
reserved (0)  
ACP_TYPE = 3: super audio CD  
CCI_1_b16[7:0]  
74h  
75h  
76h  
77h  
78h  
79h  
ACP_PB17  
ACP_PB18  
ACP_PB19  
ACP_PB20  
ACP_PB21  
ACP_PB22  
7 to 0 ACP_PB_BYTE_17[7:0] R/W  
7 to 0 ACP_PB_BYTE_18[7:0] R/W  
7 to 0 ACP_PB_BYTE_19[7:0] R/W  
7 to 0 ACP_PB_BYTE_20[7:0] R/W  
7 to 0 ACP_PB_BYTE_21[7:0] R/W  
7 to 0 ACP_PB_BYTE_22[7:0] R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
00h*  
audio content protection data byte 17  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 18  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 19  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 20  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 21  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 22  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
97 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 105. ACP packet registers (address 60h to 7Eh) bit description …continued  
Legend: * = default value  
Address Register  
Bit  
Symbol  
Access Value Description  
7Ah  
7Bh  
7Ch  
7Dh  
7Eh  
ACP_PB23  
ACP_PB24  
ACP_PB25  
ACP_PB26  
ACP_PB27  
7 to 0 ACP_PB_BYTE_23[7:0] R/W  
7 to 0 ACP_PB_BYTE_24[7:0] R/W  
7 to 0 ACP_PB_BYTE_25[7:0] R/W  
7 to 0 ACP_PB_BYTE_26[7:0] R/W  
7 to 0 ACP_PB_BYTE_27[7:0] R/W  
00h*  
00h*  
00h*  
00h*  
00h*  
audio content protection data byte 23  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 24  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 25  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 26  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
audio content protection data byte 27  
ACP_TYPE = 2: DVD audio or  
ACP_TYPE = 3: super audio CD  
reserved (0)  
9.7.4 Current page address register  
Table 106. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value Description  
00h* current page address: selects the current  
memory page  
7 to 0  
CURPAGE_ADR[7:0] W  
9.8 HDMI and DVI page register definitions  
The current page address for the HDMI and DVI page is 12h.  
The configuration of the registers for this page is given in Table 107.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
98 of 119  
 
 
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Table 107. I2C-bus registers of memory page 12h[1]  
Register  
Sub R/W  
addr  
Bit  
Default  
value  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
Not used  
:
00h  
:
-
:
-
:
0000 0000  
:
Not used  
HDCP_TX33  
Not used  
:
B7h  
-
-
0000 0000  
0000 0000  
0000 0000  
:
B8h R/W  
x
x
x
x
x
x
HDMI  
x
B9h  
:
-
:
-
:
Not used  
CURPAGE_ADR  
FEh  
FFh  
-
-
0000 0000  
0000 0000  
W
CURPAGE_ADR[7:0]  
[1] R: reading register  
W: writing register  
x: bit must be set to default value for proper operation  
-: not used  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
9.8.1 HDMI control registers  
Table 108. HDCP_TX33 register (address B8h) bit description  
Legend: * = default value  
Bit  
7 to 6  
1
Symbol  
x
Access Value  
Description  
R/W  
R/W  
0000 00* undefined  
HDMI  
HDMI  
0*  
1
DVI mode  
HDMI mode  
undefined  
0
x
R/W  
0*  
9.8.2 Current page address register  
Table 109. CURPAGE_ADR register (address FFh) bit description  
Legend: * = default value  
Bit  
Symbol  
Access Value  
00h*  
Description  
7 to 0  
CURPAGE_ADR[7:0]  
W
current page address: selects the  
current memory page  
10. Limiting values  
Table 110. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDD(3V3)  
VDD(1V8)  
∆VDD  
Tstg  
Parameter  
Conditions  
Min  
−0.5  
−0.5  
−0.5  
−55  
0
Max  
+4.6  
+2.5  
+0.5  
+150  
70  
Unit  
V
supply voltage (3.3 V)  
supply voltage (1.8 V)  
supply voltage difference  
storage temperature  
ambient temperature  
junction temperature  
V
V
°C  
°C  
°C  
V
Tamb  
Tj  
-
125  
Vesd  
electrostatic discharge voltage HBM  
−1500  
+1500  
11. Thermal characteristics  
Table 111. Thermal characteristics  
Symbol  
Parameter  
Conditions  
Typ  
Unit  
Rth(j-a)  
thermal resistance from junction in free air; JEDEC 4L board  
to ambient  
26.5  
K/W  
Rth(j-c)  
thermal resistance from junction  
to case  
10.2  
K/W  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
100 of 119  
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
12. Static characteristics  
Table 112. Supplies  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;  
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V  
and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
TDA9983BHW/8 and TDA9983BHW/15  
VDDA(FRO_3V3) free running oscillator 3.3 V analog supply voltage  
VDDA(PLL_3V3) PLL 3.3 V analog supply voltage  
3.0  
3.0  
3.0  
3.0  
1.65  
3.3  
3.3  
3.3  
3.3  
1.8  
3.6  
3.6  
3.6  
3.6  
1.95  
V
V
V
V
V
VDDH(3V3)  
VDDD(3V3)  
VDDC(1V8)  
HDMI supply voltage (3.3 V)  
digital supply voltage (3.3 V)  
core supply voltage (1.8 V)  
[1]  
[1]  
TDA9983BHW/8; up to 81 MHz  
IDDA(FRO_3V3)  
IDDA(PLL_3V3)  
IDDD(3V3)  
IDDH(3V3)  
IDDC(1V8)  
fclk(max)  
free running oscillator 3.3 V analog supply current  
-
0
1
mA  
[2]  
PLL 3.3 V analog supply current  
digital supply current (3.3 V)  
HDMI supply current (3.3 V)  
core supply current (1.8 V)  
maximum clock frequency  
power consumption  
-
4.5  
-
6
mA  
-
5
mA  
-
14  
16.5  
mA  
[2]  
[3]  
[3]  
[2]  
[3]  
[2]  
-
154.5 200  
mA  
81  
-
-
-
MHz  
mW  
mW  
mW  
mW  
mW  
Pcons  
322  
338  
458  
472  
13.5  
-
worst case  
worst case  
-
503  
-
Ptot  
Ppd  
total power dissipation  
-
-
651  
38.4  
power dissipation in power-down mode  
-
TDA9983BHW/15; up to 150 MHz  
IDDA(FRO_3V3)  
IDDA(PLL_3V3)  
IDDD(3V3)  
IDDH(3V3)  
IDDC(1V8)  
fclk(max)  
Pcons  
free running oscillator 3.3 V analog supply current  
-
0
1
mA  
[4]  
PLL 3.3 V analog supply current  
digital supply current (3.3 V)  
HDMI supply current (3.3 V)  
core supply current (1.8 V)  
maximum clock frequency  
power consumption  
-
4
5
mA  
-
-
5
mA  
-
14  
167  
-
16.5  
210  
-
mA  
[4]  
[4]  
[4]  
[4]  
-
mA  
150  
MHz  
mW  
mW  
mW  
-
-
-
361  
495  
13.5  
583  
732  
38.4  
Ptot  
total power dissipation  
Ppd  
power dissipation in power-down mode  
[1] The VDDD(3V3) and VDDC(1V8) power supplies must always follow the sequence shown in Figure 14 to ensure proper power-up conditions.  
[2] Worst case video format:  
a) Input 480p (YCBCR 4 : 2 : 2 semi-planar)  
b) Output 720p (YCBCR 4 : 2 : 2)  
[3] Video format:  
a) Input 480p (ITU656 embedded sync, rising edge)  
b) Output 1080i (YCBCR 4 : 2 : 2)  
[4] Video format:  
a) Input 1080p (RGB 4 : 4 : 4 external sync, rising edge)  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
101 of 119  
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
b) Output 1080p (RGB 4 : 4 : 4)  
Table 113. LV-TTL digital inputs and outputs  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;  
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V  
and Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE  
and RST_N  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input capacitance  
-
-
0.8  
-
V
2.0  
−1  
−1  
-
-
V
-
+1  
+1  
-
µA  
µA  
pF  
IIH  
Ci  
-
4.5  
5 V tolerant input: pin HPD  
VIL  
VIH  
Ci  
LOW-level input voltage  
-
-
0.8  
V
HIGH-level input voltage  
input capacitance  
2.0  
-
-
-
-
V
4.5  
pF  
Output: pin INT  
VOL  
LOW-level output voltage  
CL = 10 pF; IOL = 2 mA  
-
-
0.4  
V
Table 114. TMDS outputs  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;  
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V  
and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+  
Vo(p-p)  
VOH  
peak-to-peak output voltage single output; Rext = 610 Ω (1 % tolerance)  
400  
525  
600  
mV  
V
with test load and operating condition as in  
HIGH-level output voltage  
3.125 3.3  
2.535 2.8  
3.475  
3.065  
HDMI 1.2a specification  
LOW-level output voltage  
VOL  
V
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
102 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
13. Dynamic characteristics  
Table 115. Timing characteristics  
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;  
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.  
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V  
and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Supplies: pins VDDC(1V8), VDDD(3V3); see Figure 14  
td delay time  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
1
-
-
ms  
Clock inputs: pins VCLK, VPA[7:0], VPB[7:0], VPC[7:0]; see Figure 15, 16, 17, 18 and 19  
fclk(max)  
maximum clock frequency  
TDA9983BHW/8  
TDA9983BHW/15  
81  
-
-
-
-
-
-
MHz  
MHz  
ns  
150  
−1.3  
3.6  
40  
-
tsu(D)  
th(D)  
δclk  
data input set-up time  
data input hold time  
clock duty cycle  
-
-
ns  
60  
%
DDC I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL  
fSCL SCL clock frequency standard mode  
I2C-bus; 5 V tolerant; master bus: pins I2C_SDA and I2C_SCL  
-
-
100  
kHz  
fSCL  
SCL clock frequency  
standard mode  
fast mode  
-
-
-
-
100  
400  
kHz  
kHz  
TMDS output pins: TXC− and TXC+  
fclk(max) maximum clock frequency  
TDA9983BHW/8  
TDA9983BHW/15  
81  
-
-
-
-
MHz  
MHz  
150  
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2− and TX2+  
fclk(max)  
maximum clock frequency  
TDA9983BHW/8  
TDA9983BHW/15  
810  
1.5  
-
-
-
-
MHz  
GHz  
3.3 V  
1.8 V  
50 %  
27 %  
t
≥ 0 s  
d
001aag259  
Fig 14. Power supply sequencing  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
103 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
13.1 Input format  
In Table 116 the port VPA has been mapped to CB (YUV space)/B (RGB space), VPB has  
been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to CR (YUV  
space)/R (RGB space).  
Table 116. Input format  
Input pins  
Signal  
RGB  
YUV  
4 : 4 : 4[1]  
4 : 4 : 4[2]  
4 : 2 : 2 (semi-planar)[3]  
4 : 2 : 2: (ITU656-like)[4]  
Video port A  
VPA[0]  
CB[0]/B[0]  
CB[1]/B[1]  
CB[2]/B[2]  
CB[3]/B[3]  
CB[4]/B[4]  
CB[5]/B[5]  
CB[6]/B[6]  
CB[7]/B[7]  
B[0]  
B[1]  
B[2]  
B[3]  
B[4]  
B[5]  
B[6]  
B[7]  
CB[0]  
CB[1]  
CB[2]  
CB[3]  
CB[4]  
CB[5]  
CB[6]  
CB[7]  
Y0[0]  
Y0[1]  
Y0[2]  
Y0[3]  
CB[0]  
CB[1]  
CB[2]  
CB[3]  
Y1[0]  
Y1[1]  
Y1[2]  
Y1[3]  
CR[0]  
CR[1]  
CR[2]  
CR[3]  
CB[0]  
CB[1]  
CB[2]  
CB[3]  
L
Y0[0] CR[0] Y1[0]  
VPA[1]  
Y0[1] CR[1] Y1[1]  
Y0[2] CR[2] Y1[2]  
Y0[3] CR[3] Y1[3]  
VPA[2]  
VPA[3]  
VPA[4]  
L
L
L
L
L
L
L
L
L
L
L
L
VPA[5]  
L
VPA[6]  
L
VPA[7]  
L
Video port B  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
VPB[6]  
VPB[7]  
Video port C  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
Y[0]/G[0]  
Y[1]/G[1]  
Y[2]/G[2]  
Y[3]/G[3]  
Y[4]/G[4]  
Y[5]/G[5]  
Y[6]/G[6]  
Y[7]/G[7]  
G[0]  
G[1]  
G[2]  
G[3]  
G[4]  
G[5]  
G[6]  
G[7]  
Y[0]  
Y[1]  
Y[2]  
Y[3]  
Y[4]  
Y[5]  
Y[6]  
Y[7]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
Y0[10]  
Y0[11]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Y1[10]  
Y1[11]  
CB[4]  
CB[5]  
CB[6]  
CB[7]  
CB[8]  
CB[9]  
Y0[4] CR[4] Y1[4]  
Y0[5] CR[5] Y1[5]  
Y0[6] CR[6] Y1[6]  
Y0[7] CR[7] Y1[7]  
Y0[8] CR[8] Y1[8]  
Y0[9] CR[9] Y1[9]  
CB[10] Y0[10] CR[10] Y1[10]  
CB[11] Y0[11] CR[11] Y1[11]  
CR[0]/R[0]  
CR[1]/R[1]  
CR[2]/R[2]  
CR[3]/R[3]  
CR[4]/R[4]  
CR[5]/R[5]  
CR[6]/R[6]  
CR[7]/R[7]  
R[0]  
R[1]  
R[2]  
R[3]  
R[4]  
R[5]  
R[6]  
R[7]  
CR[0]  
CR[1]  
CR[2]  
CR[3]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CB[4]  
CB[5]  
CB[6]  
CB[7]  
CB[8]  
CB[9]  
CB[10]  
CB[11]  
CR[4]  
CR[5]  
CR[6]  
CR[7]  
CR[8]  
CR[9]  
CR[10]  
CR[11]  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[1] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
[2] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
[3] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.  
[4] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
104 of 119  
 
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
13.2 Example of supported video  
The TDA9983B supports all EIA/CEA-861B, ATSC video input formats.  
Table 117. Timing parameters for EIA/CEA-861B  
Format nr. Format V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler  
(Hz)  
(kHz)  
(MHz)  
59.94 Hz systems  
1 (VGA)  
640 × 480p  
59.9401  
59.9401  
59.9401  
800  
858  
1650  
2200  
858  
858  
858  
858  
525  
525  
750  
1125  
525  
262  
263  
525  
31.4685  
31.4685  
44.955  
25.174825  
27  
1
1
1
1
2
2
2
-
2, 3  
4
720 × 480p  
X
-
1280 × 720p  
74.175824  
74.175824  
13.5  
5
1920 × 1080i 59.9401  
33.7163  
15.7343  
15.7043  
15.7642  
15.7343  
-
6, 7 (NTSC) 720 × 480i  
59.9401  
59.9401  
59.9401  
59.9401  
X
-
8, 9  
720 × 240p  
720 × 240p  
720 × 480i  
13.474286  
13.525714  
13.5  
8, 9  
-
10, 11  
4, 5, 7[1], 8[1],  
10[1]  
-
12, 13  
12, 13  
720 × 240p  
720 × 240p  
1440 × 480p  
59.9401  
59.9401  
59.9401  
858  
858  
262  
263  
15.7043  
15.7642  
13.474286  
13.525714  
4, 5, 7[1], 8[1],  
10[1]  
4, 5, 7[1], 8[1],  
10[1]  
-
-
14, 15  
16[1]  
1716  
2200  
525  
31.4685  
67.4326  
54  
2
1
-
-
1920 × 1080p 59.9401  
1125  
148.35165[1]  
60 Hz systems  
1 (VGA)  
640 × 480p  
720 × 480p  
1280 × 720p  
60  
60  
60  
800  
858  
1650  
2200  
858  
858  
858  
858  
525  
525  
750  
1125  
525  
262  
263  
525  
31.5  
25.2  
1
1
1
1
2
2
2
-
2, 3  
4
31.5  
27.27  
X
-
45  
74.25  
5
1920 × 1080i 60  
33.75  
15.75  
15.72  
15.78  
15.75  
74.25  
-
6, 7 (NTSC) 720 × 480i  
60  
60  
60  
60  
13.5135  
13.48776  
13.53924  
13.5135  
X
-
8, 9  
720 × 240p  
720 × 240p  
720 × 480i  
8, 9  
-
10, 11  
4, 5, 7[1], 8[1],  
10[1]  
-
12, 13  
12, 13  
720 × 240p  
720 × 240p  
1440 × 480p  
60  
60  
60  
858  
858  
262  
263  
15.72  
15.78  
13.48776  
13.53924  
4, 5, 7[1], 8[1],  
10[1]  
4, 5, 7[1], 8[1],  
10[1]  
-
-
14, 15  
16[1]  
1716  
2200  
525  
31.5  
67.5  
54.054  
148.5[1]  
2
1
-
-
1920 × 1080p 60  
1125  
50 Hz systems  
17, 18  
19  
720 × 576p  
50  
50  
864  
625  
750  
1125  
625  
312  
313  
31.25  
37.5  
27  
1
1
1
1
2
2
X
-
1280 × 720p  
1980  
2640  
864  
74.25  
74.25  
13.5  
20  
1920 × 1080i 50  
28.125  
15.625  
15.6  
-
21, 22 (PAL) 720 × 576i  
50  
50  
50  
X
-
23, 24  
23, 24  
720 × 288p  
720 × 288p  
864  
13.4784  
13.5216  
864  
15.65  
-
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
105 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 117. Timing parameters for EIA/CEA-861B …continued  
Format nr.  
Format  
V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler  
(Hz)  
(kHz)  
(MHz)  
13.5648  
13.5  
23, 24  
25, 26  
720 × 288p  
720 × 576i  
50  
864  
864  
314  
625  
15.7  
2
-
-
50  
15.625  
4, 5, 7[1], 8[1],  
10[1]  
27, 28  
27, 28  
720 × 288p  
720 × 288p  
50  
50  
864  
864  
312  
313  
15.6  
13.4784  
13.5216  
4, 5, 7[1], 8[1],  
10[1]  
4, 5, 7[1], 8[1],  
10[1]  
-
-
15.65  
27, 28  
29, 30  
31[1]  
720 × 288p  
50  
50  
864  
314  
15.7  
13.5648  
54  
148.5[1]  
2
1
1
-
-
-
1440 × 576p  
1728  
2640  
625  
31.25  
56.25  
1920 × 1080p 50  
1125  
Various systems  
32  
32  
33  
34  
34  
1920 × 1080p 23.976  
2750  
2750  
2640  
2200  
2200  
1125  
1125  
1125  
1125  
1125  
26.973  
27  
74.175824  
74.25  
1
1
1
1
1
-
-
-
-
-
1920 × 1080p 24  
1920 × 1080p 25  
1920 × 1080p 29.97  
1920 × 1080p 30  
28.125  
33.716  
33.75  
74.25  
74.175824  
74.25  
[1] Only for TDA9983BHW/15.  
Table 118. Timing parameters for PC standards below 150 MHz  
Standard  
Format  
V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler  
(Hz)  
(kHz)  
(MHz)  
VGA  
640 × 350p  
640 × 400p  
720 × 400p  
640 × 480p  
640 × 480p  
640 × 480p  
640 × 480p  
800 × 600p  
800 × 600p  
800 × 600p  
800 × 600p  
800 × 600p  
85.08  
85.08  
85.039  
832  
832  
936  
445  
445  
446  
525  
520  
500  
509  
37.8606  
37.8606  
37.927394  
31.5000192  
31.5000192  
35.50004078  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
59.94005994 800  
31.46853147 25.17482517  
72.809  
75  
832  
840  
832  
37.86068  
37.5  
31.50008576  
31.5  
85.008  
56.250  
60.317  
72.188  
75.000  
85.061  
43.269072  
35.15625  
37.879076  
48.077208  
46.875  
35.9998679  
36  
SVGA  
1024 625  
1056 628  
40.00030426  
50.00029632  
49.5  
1040 666  
1056 625  
1048 631  
53.673491  
56.24981857  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
106 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 118. Timing parameters for PC standards below 150 MHz …continued  
Standard  
Format  
V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler  
(Hz)  
(kHz)  
(MHz)  
XGA  
1024 × 786p  
1024 × 786p  
1024 × 786p  
60.004  
70.069  
75.029  
1344 806  
1328 806  
1312 800  
1376 808  
1264 817  
1600 900  
1576 907  
48.363224  
56.475614  
60.0232  
65.00017306  
74.99961539  
78.7504384  
94.50034458  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1024 × 786p[1] 84.997  
68.677576  
1024 × 786i 86.957  
35.5219345 44.89972521  
1152 × 864p[1] 75.000  
1152 × 864p[1] 84.999  
1280 × 960p[1] 60  
1280 × 960p[1] 85.002  
1280 × 1024p[1] 60.020  
1280 × 1024p[1] 75.025  
67.5  
108  
77.094093  
121.5002906  
108  
1800 1000 60  
1728 1011 85.937022  
1688 1066 63.98132  
1688 1066 79.97665  
148.499174  
108.0004682  
135.0005852  
SXGA[1]  
[1] Only for TDA9983BHW/15.  
13.3 Timing diagrams  
VCLK  
t
t
clk(H) clk(L)  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
B0  
G0  
R0  
B1  
G1  
R1  
B2  
G2  
R2  
B3  
G3  
R3  
...  
...  
...  
Bxxx  
Bxxx  
Gxxx  
Rxxx  
Gxxx  
Rxxx  
t
h(D)  
t
su(D)  
001aag250  
Fig 15. Timing in RGB 4 : 4 : 4 (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
107 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
VCLK  
t
t
clk(H) clk(L)  
HSYNC/HREF  
CONTROL  
VSYNC/VREF  
INPUTS  
DE/FREF  
VPA[7:0]  
C 0  
B
C 1  
B
C 2  
B
C 3  
B
...  
...  
...  
C xxx  
B
C xxx  
B
VPB[7:0]  
VPC[7:0]  
Y0  
Y1  
Y2  
Y3  
Yxxx  
Yxxx  
C 0  
R
C 1  
R
C 2  
R
C 3  
R
C xxx  
R
C xxx  
R
t
h(D)  
t
su(D)  
001aag251  
001aag252  
001aag253  
Fig 16. Timing in YCBCR 4 : 4 : 4 (rising edge) input  
VCLK  
t
t
clk(L)  
clk(H)  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
Y1  
...  
C xxx  
Yxxx  
R
R
t
t
h(D)  
h(D)  
t
t
su(D)  
su(D)  
Fig 17. Timing YCBCR 4 : 2 : 2 ITU656-like double edge (rising and falling) input  
VCLK  
t
t
clk(H) clk(L)  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
C 0  
B
Y0  
C 0  
R
Y1  
...  
C xxx  
R
Yxxx  
t
h(D)  
t
su(D)  
Fig 18. Timing YCBCR 4 : 2 : 2 ITU656-like single edge external (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
108 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
VCLK  
t
t
t
clk(H) clk(L)  
h(D)  
HSYNC/HREF  
CONTROL  
VSYNC/VREF  
INPUTS  
DE/FREF  
VPB[7:0]; VPA[3:0]  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
...  
...  
VPC[7:0]; VPA[7:4]  
C 0  
B
C 0  
R
C 2  
B
C 2  
R
C 4  
B
C 4  
R
t
su(D)  
001aag256  
Fig 19. Timing YCBCR 4 : 2 : 2 semi-planar external synchronization (rising edge) input  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
109 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
14. Application information  
DAC  
DAC  
DAC  
CVBS/Y/(G)  
DENC  
G
ADC  
DSP  
C/P /(B)  
B
LO  
P /(R)  
R
audio  
I S-bus  
AUX  
data  
2
or S/PDIF  
8
HDMI  
data stream  
HDMI TX  
STEREO  
AUDIO DAC  
001aaf298  
Fig 20. Application diagram for Set-Top Box  
DAC  
DAC  
DAC  
CVBS/Y/(G)  
DENC  
DVD  
READ  
ENGINE  
DSP  
C/P /(B)  
B
P /(R)  
R
audio  
I S-bus  
or S/PDIF  
AUX  
data  
2
8
HDMI  
data stream  
SCALER HDMI TX  
STEREO  
AUDIO DAC  
001aaf299  
Fig 21. Application diagram for DVD player  
HDMI clock  
reset  
digital video  
(up to 24 bits)  
HDMI channel 0  
HDMI channel 1  
HDMI channel 2  
hot plug detect  
sync signals  
MICROPROCESSOR  
HDMI  
RECEIVER/  
REPEATER  
HDMI  
TDA9983B  
MASTER  
MPEG2  
DECODER  
2
audio, S/PDIF and I S-bus  
IRQ  
2
2
DDC (SCL and SDA)  
I C-bus  
I C-bus  
MASTER  
MASTER  
SLAVE  
SLAVE  
E-EDID  
HDMI SOURCE  
SLAVE ADDRESS A0  
CEC line  
001aag260  
Fig 22. Transmitter connection with external world  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
110 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
15. Package outline  
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad  
SOT841-4  
c
y
exposed die pad  
X
D
h
A
60  
41  
Z
61  
40  
E
e
(A )  
3
A
A
2
E
E
H
E
h
M
w
θ
b
p
A
1
L
p
L
detail X  
pin 1 index  
80  
21  
1
20  
M
v
v
A
M
w
Z
D
b
p
e
D
B
M
H
D
B
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
1
A
2
A
3
b
c
D
D
E
E
e
H
D
H
E
L
L
v
w
y
Z
Z
θ
p
h
h
p
D
E
max  
°
°
0.15 1.05  
0.05 0.95  
0.27 0.20 12.1 4.79 12.1 4.79  
0.17 0.09 11.9 4.69 11.9 4.69  
14.15 14.15  
13.85 13.85  
0.75  
0.45  
1.45 1.45  
1.05 1.05  
7
0
mm  
1.2  
0.25  
0.5  
1
0.2 0.08 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
06-04-25  
06-06-20  
SOT841-4  
MS-026  
Fig 23. Package outline SOT841-4 (HTQFP80)  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
111 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
16. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
16.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
16.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
• Through-hole components  
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
• Board specifications, including the board finish, solder masks and vias  
• Package footprints, including solder thieves and orientation  
• The moisture sensitivity level of the packages  
• Package placement  
• Inspection and repair  
• Lead-free soldering versus SnPb soldering  
16.3 Wave soldering  
Key characteristics in wave soldering are:  
• Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
• Solder bath specifications, including temperature and impurities  
TDA9983B_1  
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Product data sheet  
Rev. 01 — 20 May 2008  
112 of 119  
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
16.4 Reflow soldering  
Key characteristics in reflow soldering are:  
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus  
reducing the process window  
• Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 119 and 120  
Table 119. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
235  
≥ 350  
220  
< 2.5  
≥ 2.5  
220  
220  
Table 120. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 24.  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
113 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 24. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
17. Soldering: additional information  
The package of this device supports the reflow soldering process only.  
18. Abbreviations  
Table 121. Abbreviations  
Acronym  
AAC  
Description  
Advanced Audio Coding  
Active Coding-3  
AC-3  
ACP  
Audio Content Protection  
Analog-to-Digital Converter  
Active Format Descriptor  
Adaptive TRansform Acoustic Coding  
Audio Video  
ADC  
AFD  
ATRAC  
AV  
CEC  
Consumer Electronic Control  
Complimentary Metal-Oxide Semiconductor  
Cycle Time Stamp  
CMOS  
CTS  
DAC  
Digital-to-Analog Converter  
Display Data Channel  
DDC  
DENC  
DSC  
Digital video ENCoder  
Distributed Source Code  
Digital Signal Processor  
Digital Transmission System  
DSP  
DTS  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
114 of 119  
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
Table 121. Abbreviations …continued  
Acronym  
Description  
DVB  
Digital Video Broadcast  
Digital Video Camera  
Digital Versatile Disc  
Digital Visual Interface  
Data-VHS  
DVC  
DVD  
DVI  
D-VHS  
EAV  
End Active Video  
EDID ROM  
E-EDID  
FIFO  
HBM  
HDCP  
HDD  
HDMI  
HDTV  
HPD  
Extended Display Identification Data ROM  
Enhanced Extended Display Identification Data  
First In First Out  
Human Body Model  
High-bandwidth Digital Content Protection  
Hard-Disk Drive  
High-Definition Multimedia Interface  
High-Definition Television  
Hot Plug Detect  
ID  
Identifier  
IRQ  
Interrupt ReQuest  
ISRC  
KSV  
International Standard Recording Code  
Key Selection Vector  
LO  
Local Oscillator  
L-PCM  
LSB  
Linear Pulse Code Modulation  
Least Significant Bit  
LUT  
Look-Up Table  
LV-TTL  
MSB  
PAL  
Low Voltage Transistor-Transistor Logic  
Most Significant Bit  
Phase Alternating Line  
PCM  
PLL  
Pulse-Code Modulation  
Phase-Locked Loop  
PVR  
Personal Video Recorder  
Red Green Blue  
RGB  
Rx  
Receiver  
SAV  
Start Active Video  
STB  
Set-Top Box  
S/PDIF  
TMDS  
Tx  
Sony/Philips Digital Interface  
Transition Minimized Differential Signalling  
Transmitter  
UPC/EAN  
YUV  
Universal Product Code/European Assistance Network (GS1)  
Y = luminance, U = normalized blue, V = normalized red  
Y = luminance, CB = chroma component blue, CR = chroma component red  
YCBCR  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
115 of 119  
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
19. Revision history  
Table 122. Revision history  
Document ID  
Release date  
20080520  
Data sheet status  
Change notice  
Supersedes  
TDA9983B_1  
Product data sheet  
-
-
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
116 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
20. Legal information  
20.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
20.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
20.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
20.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
21. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
117 of 119  
 
 
 
 
 
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
22. Contents  
1
General description . . . . . . . . . . . . . . . . . . . . . . 1  
9.3.8  
9.3.9  
9.3.10  
9.4  
9.4.1  
9.4.2  
NDIV register . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Control registers. . . . . . . . . . . . . . . . . . . . . . . 42  
Current page address register . . . . . . . . . . . . 43  
Scaler page register definitions . . . . . . . . . . . 43  
Scaler control registers . . . . . . . . . . . . . . . . . 48  
Scaling input time base generator control  
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Current page address register . . . . . . . . . . . . 55  
PLL settings page register definitions . . . . . . 55  
PLL serial registers . . . . . . . . . . . . . . . . . . . . 57  
Current page address register . . . . . . . . . . . . 63  
Information frames and packets page register  
definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Vendor-specific InfoFrame registers. . . . . . . . 70  
Auxiliary video information InfoFrame  
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3
4
5
5.1  
6
9.4.3  
9.5  
9.5.1  
9.5.2  
9.6  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
8
8.1  
8.2  
8.3  
8.3.1  
8.3.2  
8.4  
8.5  
8.6  
Functional description . . . . . . . . . . . . . . . . . . . 8  
System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Video input processor. . . . . . . . . . . . . . . . . . . . 8  
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18  
Timing extraction generator . . . . . . . . . . . . . . 18  
Data enable generator . . . . . . . . . . . . . . . . . . 18  
Input and output video format. . . . . . . . . . . . . 18  
Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Color space converter. . . . . . . . . . . . . . . . . . . 19  
Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Audio input format. . . . . . . . . . . . . . . . . . . . . . 19  
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Power management . . . . . . . . . . . . . . . . . . . . 20  
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20  
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
HDMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Output HDMI buffers. . . . . . . . . . . . . . . . . . . . 21  
Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21  
HDMI and DVI receiver discrimination . . . . . . 21  
DDC channel . . . . . . . . . . . . . . . . . . . . . . . . . 21  
9.6.1  
9.6.2  
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
Source product description InfoFrame  
9.6.3  
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Audio InfoFrame registers . . . . . . . . . . . . . . . 76  
MPEG source InfoFrame registers. . . . . . . . . 79  
Current page address register . . . . . . . . . . . . 81  
Audio settings and content info packets page  
register definitions . . . . . . . . . . . . . . . . . . . . . 81  
Audio input processor control registers . . . . . 87  
ISRC packets registers. . . . . . . . . . . . . . . . . . 91  
Audio content protection packet registers . . . 94  
Current page address register . . . . . . . . . . . . 98  
HDMI and DVI page register definitions. . . . . 98  
HDMI control registers . . . . . . . . . . . . . . . . . 100  
Current page address register . . . . . . . . . . . 100  
9.6.4  
9.6.5  
9.6.6  
9.7  
8.7  
8.8  
8.9  
9.7.1  
9.7.2  
9.7.3  
9.7.4  
9.8  
8.10  
8.11  
8.12  
8.13  
8.14  
8.14.1  
8.14.2  
8.14.3  
8.14.4  
9.8.1  
9.8.2  
10  
11  
12  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . 100  
Thermal characteristics . . . . . . . . . . . . . . . . 100  
Static characteristics . . . . . . . . . . . . . . . . . . 101  
8.14.4.1 E-EDID reading. . . . . . . . . . . . . . . . . . . . . . . . 21  
8.15  
8.16  
8.17  
Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Input and output video scaler . . . . . . . . . . . . . 22  
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 22  
13  
Dynamic characteristics. . . . . . . . . . . . . . . . 103  
Input format . . . . . . . . . . . . . . . . . . . . . . . . . 104  
Example of supported video . . . . . . . . . . . . 105  
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . 107  
13.1  
13.2  
13.3  
9
9.1  
9.2  
9.3  
9.3.1  
9.3.2  
9.3.3  
9.3.4  
9.3.5  
9.3.6  
9.3.7  
I2C-bus register definitions. . . . . . . . . . . . . . . 23  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23  
Memory page management . . . . . . . . . . . . . . 23  
General control page register definitions . . . . 23  
Main control register . . . . . . . . . . . . . . . . . . . . 29  
Interrupt flags/masks registers . . . . . . . . . . . . 29  
Video input processing control registers. . . . . 30  
Color space conversion registers . . . . . . . . . . 34  
Video format registers. . . . . . . . . . . . . . . . . . . 36  
HDMI video formatter control registers. . . . . . 40  
Timer control registers . . . . . . . . . . . . . . . . . . 42  
14  
15  
Application information . . . . . . . . . . . . . . . . 110  
Package outline . . . . . . . . . . . . . . . . . . . . . . . 111  
16  
Soldering of SMD packages . . . . . . . . . . . . . 112  
Introduction to soldering. . . . . . . . . . . . . . . . 112  
Wave and reflow soldering . . . . . . . . . . . . . . 112  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . 112  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . 113  
16.1  
16.2  
16.3  
16.4  
17  
18  
Soldering: additional information . . . . . . . . 114  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 114  
continued >>  
TDA9983B_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 20 May 2008  
118 of 119  
 
TDA9983B  
NXP Semiconductors  
150 MHz pixel rate HDMI transmitter  
19  
Revision history. . . . . . . . . . . . . . . . . . . . . . . 116  
20  
Legal information. . . . . . . . . . . . . . . . . . . . . . 117  
Data sheet status . . . . . . . . . . . . . . . . . . . . . 117  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 117  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 117  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 117  
20.1  
20.2  
20.3  
20.4  
21  
22  
Contact information. . . . . . . . . . . . . . . . . . . . 117  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 20 May 2008  
Document identifier: TDA9983B_1  

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