TDA9991HL [NXP]

CCD Image Sensor, IMAGE SENSOR-CCD, 8-15V-1, SQUARE, SURFACE MOUNT, PLASTIC, QFP-48;
TDA9991HL
型号: TDA9991HL
厂家: NXP    NXP
描述:

CCD Image Sensor, IMAGE SENSOR-CCD, 8-15V-1, SQUARE, SURFACE MOUNT, PLASTIC, QFP-48

CD 传感器 换能器
文件: 总24页 (文件大小:116K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
TDA9991HL  
Vertical line driver and DC-DC  
converter for Full Frame and  
Frame Transfer CCD image  
sensors  
Preliminary specification  
2001 May 29  
Supersedes data of 2000 Dec 22  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
FEATURES  
The versatile programmable DC-DC converter generates  
two positive voltages (VCAPNS and VCAPH) and the non  
programmable DC-DC converter generates a negative  
voltage (VVL) which is used internally. Voltage regulators  
convert the DC-DC converter outputs into low-noise output  
voltages (VNS, VSFD, VHFB and VSH). The required  
voltages for the image sensor and the drivers can be  
programmed via the serial bus with sufficient accuracy to  
optimize the performance of the sensors. An on-board  
reference voltage ensures stable output voltages over the  
entire temperature range.  
Enables compact and cost effective camera design  
Eight two-level low-ohmic line drivers suitable for Philips  
Full Frame (FF) and Frame Transfer (FT) CCD image  
sensors  
Versatile programmable DC-DC converters and voltage  
regulators to create all required low-noise supply  
voltages for the Philips FT CCD sensor family and for  
the on-chip drivers  
DC-DC converter can be operated with an on-chip free  
running oscillator or with an external clock  
An internal DCOK signal enables the vertical line drivers  
when the DC-DC converter output voltages and the  
regulator output voltages are at their required  
Wide supply range also suitable for direct use on  
batteries  
(programmable) level. When either VHFB, VCAPNS or VNS  
drops below 80% of it’s programmed level, the DCOK  
signal will become LOW. A signal on pin START (inverse  
of DCOK signal) indicates that the device has started up  
and is externally available.  
Electronic shutter driver (charge reset)  
Fast start-up  
DC ready signal available indicating the TDA9991HL  
has started up  
3-wire serial bus  
The use of two external coils enables high efficiency of the  
DC-DC converters and fast starting up. The maximum  
current built-up in coil L2 can be set with an external  
resistor RLIM optimizing the efficiency of the DC-DC  
converter and making it independent of supply voltage  
variations.  
Separate digital supply voltage for optimal interfacing  
with DSP circuit and serial bus  
Low current consumption in Power-down mode.  
APPLICATIONS  
The DC-DC converter operates from an on-chip free  
running oscillator or from an external clock signal.  
Digital still camera  
Desktop video camera  
Security camera  
Camcorder  
The low impedance of the drivers enables fast transfer of  
the image of the sensor. The drivers can switch between  
0 V and VHFB (8 to 15 V). The eight vertical drivers (image  
gate drivers) can be put into 3-state via the serial bus.  
DSP applications.  
Charge reset of the CCD can be performed with a separate  
electronic shutter driver.  
GENERAL DESCRIPTION  
When the TDA9991 is in Power-on mode, a HIGH level at  
pin PWD will put the chip in Power-down mode. A LOW  
level at pin PWD will enable Power-on mode again.  
When pin PWD is left open-circuit, a pull-down resistor will  
keep this input LOW.  
The TDA9991HL forms the interface between the pulse  
pattern generator and the CCD image sensor in camera  
systems and minimizes the component count significantly  
by integration of various functions. The device contains  
eight vertical line drivers, a shutter driver for charge reset,  
a versatile programmable DC-DC converter,  
a non-programmable DC-DC converter and voltage  
regulators which create all required low noise supply  
voltages for FT and FF CCD sensors. A three wire serial  
bus, similar to the ones used in the Philips front-end ICs  
(TDA8786 and TDA8783) is used for programming the  
device.  
In the Power-down mode (set via the serial bus or through  
pin PWD) the current consumption becomes virtually zero.  
The serial bus is still available.  
2001 May 29  
2
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
QUICK REFERENCE DATA  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
VDDA1  
VDDA2  
VDDD  
analog supply voltage 1  
analog supply voltage 2  
digital supply voltage  
3.6  
7
V
V
V
3.6  
2.6  
7
3.6  
Vertical line drivers  
Ro(on)  
HIGH- and LOW-level output  
on-resistance  
IL(H) = 200 mA; IL(L) = 200 mA −  
0.66  
16.5  
Shutter driver  
Ro(on)  
HIGH- and LOW-level output  
on-resistance  
IL(H) = 3 mA; IL(L) = 3 mA  
Output voltage regulators  
VHFB  
VNS  
high output voltage  
Nwell substrate output voltage  
programmable  
programmable  
8
15  
31  
24  
10  
V
V
V
V
17  
18  
3
VSFD  
VSH  
source follower drain output voltage programmable  
shutter driver output voltage programmable  
Temperature range  
Toper  
operating temperature  
20  
+70  
°C  
ORDERING INFORMATION  
TYPE  
PACKAGE  
DESCRIPTION  
NUMBER  
NAME  
VERSION  
TDA9991HL  
LQFP48  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
SOT313-2  
2001 May 29  
3
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
BLOCK DIAGRAM  
+V  
+V  
DDA  
V
DDD  
V
DDA1  
DDD  
AGND1  
CAPBG  
43  
DGND  
48  
AGND3 HDA HDB AGND4  
7
8
4
28  
27  
33  
34  
V
SH  
BAND GAP  
REFERENCE  
VOLTAGE  
SHUTTER  
DRIVER  
11  
SHO  
10  
47  
46  
45  
44  
42  
41  
40  
39  
SHIN  
VA1  
VA2  
VA3  
VA4  
VB1  
VB2  
VB3  
VB4  
VERTICAL LINE DRIVERS  
30  
29  
26  
25  
31  
32  
35  
36  
A1  
A2  
A3  
A4  
B1  
B2  
B3  
B4  
LOGIC  
CONTROL  
AND  
INTERFACE  
1
3
SDATA  
SCLK  
SERIAL  
INTERFACE  
37  
38  
PWD  
2
6
SEN  
OSC  
START  
OSCILLATOR  
V
SH  
R
OSC  
TDA9991HL  
DCOK  
V
15  
DDA2  
+V  
23  
22  
20  
21  
DDA  
SFD  
NS  
+
L2  
L2  
L1  
17  
14  
DC-DC  
CONVERTERS  
VOLTAGE  
REGULATORS  
SH  
+
VBE  
L1  
24  
HFB  
AGND2  
16  
9
13  
VL  
18  
19  
5
12  
LIM  
CAPNS CAPH  
V5V  
CAP12  
MGT242  
R
LIM  
Fig.1 Block diagram.  
4
2001 May 29  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
PINNING  
SYMBOL PIN  
DESCRIPTION  
SYMBOL PIN  
DESCRIPTION  
serial bus data input  
NS  
22 Nwell substrate voltage output  
SDATA  
SEN  
1
2
3
4
5
SFD  
HFB  
A4  
23 source follower drain voltage output  
24 horizontal voltage feedback output  
25 A4 driver output  
serial bus enable input  
serial bus clock input  
digital supply voltage  
SCLK  
VDDD  
V5V  
A3  
26 A3 driver output  
filter capacitor of digital supply  
voltage  
HDA  
AGND3  
A2  
27 A drivers high voltage supply  
28 A drivers analog ground 3  
29 A2 driver output  
OSC  
6
external oscillator resistor or clock  
input  
A1  
30 A1 driver output  
AGND1  
VDDA1  
LIM  
7
8
9
analog ground 1  
B1  
31 B1 driver output  
analog supply voltage 1  
peak current limiting resistor  
B2  
32 B2 driver output  
HDB  
AGND4  
B3  
33 B drivers high voltage supply  
34 B drivers analog ground 4  
35 B3 driver output  
SHIN  
SHO  
CAP12  
VL  
10 electronic shutter driver input  
11 electronic shutter driver output  
12 filter capacitor of DC-DC converter  
B4  
36 B4 driver output  
13 DC-DC converter negative low  
voltage  
PWD  
START  
VB4  
VB3  
VB2  
VB1  
CAPBG  
VA4  
VA3  
VA2  
VA1  
DGND  
37 power-down input  
38 DC voltages ready output  
39 B4 driver digital input  
40 B3 driver digital input  
41 B2 driver digital input  
42 B1 driver digital input  
43 filter capacitor of band gap reference  
44 A4 driver digital input  
45 A3 driver digital input  
46 A2 driver digital input  
47 A1 driver digital input  
48 digital ground  
L1  
14 coil 1 connection  
VDDA2  
15 DC-DC converter analog supply  
voltage 2  
AGND2  
L2  
16 DC-DC converter analog ground 2  
17 coil 2 connection  
CAPNS  
18 filter capacitor of DC-DC converter  
CAPNS voltage  
CAPH  
19 filter capacitor of DC-DC converter  
CAPH voltage output  
SH  
20 shutter voltage output  
21 base voltage output  
VBE  
2001 May 29  
5
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
1
2
36 B4  
35  
SDATA  
SEN  
B3  
34 AGND4  
33  
SCLK  
3
V
4
HDB  
DDD  
V5V  
OSC  
5
32 B2  
31 B1  
6
TDA9991HL  
AGND1  
7
A1  
30  
V
29 A2  
8
DDA1  
LIM  
SHIN  
9
AGND3  
28  
27 HDA  
10  
11  
12  
26  
SHO  
A3  
CAP12  
25 A4  
MGT243  
Fig.2 Pin configuration.  
2001 May 29  
6
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
FUNCTIONAL DESCRIPTION  
The TDA9991HL can be separated into three main blocks  
(see Fig.1):  
handbook, halfpage  
V
DDA  
V
CAPNS  
L2  
DC-DC converters  
Voltage regulators  
Drivers.  
S2  
V
CAPH  
S1  
The functionality of the blocks is described below.  
DC-DC converters  
The principle of the DC-DC converter with positive output  
voltages VCAPNS and VCAPH is shown in Fig.3. The two  
voltages are generated by charging coil L2 (closing S1)  
and then discharging the charge built-up in coil L2 (by  
opening S1) into the capacitor at pin CAPNS or, when S2  
is closed, into the capacitor at pin CAPH. Since VCAPNS is  
always higher than VCAPH, closing S2 will not cause a  
discharge of the capacitor at pin CAPNS into the capacitor  
at pin CAPH.  
MGT244  
Fig.3 Principle of DC-DC converter with positive  
output voltage.  
The current through switch S1 is being monitored and will  
not exceed the maximum value set by an external resistor  
at pin LIM. Limiting the maximum current will make the  
charge built-up in coil L2 independent of the supply  
voltage therefore keeping the converter efficiency  
constant.  
handbook, halfpage  
V
DDA  
S3  
L1  
V
VL  
L1  
MGT245  
The principle of the DC-DC converter with the negative  
output voltage VVL is shown in Fig.4. The negative voltage  
is generated by charging coil L1 (closing S3) and then  
discharging the charge built-up in coil L1 (by opening S3)  
into the capacitor at pin VL. The capacitor at pin VL will be  
charged to approximately 3 V; there is no current limiting.  
Fig.4 Principle of DC-DC converter with negative  
output voltage.  
Voltage regulators  
For an optimal performance of the CCD, the sensor  
voltages VSH, VNS, VSFD and VHFB are being generated by  
programmable voltage regulators with a very high ripple  
rejection.  
CAPNS,  
CAPH  
AMP1,  
AMP2,  
AMP3  
The voltage regulators for VSH, VNS and VSFD all have the  
same principle shown in Fig.5.  
V
DAC  
Peak currents are being supplied by the capacitor at the  
output while the voltage regulator charges the capacitor  
more slowly. The value of the capacitor determines the  
output voltage drop when a peak current is being drawn.  
SH,  
NS,  
SFD  
V
V
V
=
= 1  
= 1  
SH  
NS  
SFD  
MGT246  
Fig.5 Principle of voltage regulators.  
2001 May 29  
7
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
The voltage regulator for the drivers supply (VHFB) can  
operate in two modes, depending on the application it is  
used in:  
handbook, halfpage  
CAPH  
Mode 1 at fast transport with high peak current  
Mode 2 at slow transport with constant current.  
AMP4  
V
DAC  
VBE  
C1  
MODE 1  
In applications where the transport of the image is done in  
a very short period large currents (up to 1.5 A) are being  
drawn which cannot be supplied by the voltage regulator  
itself. In that event an external transistor is used to supply  
the large peak currents (see Fig.6). Mode 1 is selected via  
the serial interface (Latch 1, bit D1 = 0; see Table 3).  
HFB  
C2  
V
= 8 to 15 V  
HFB  
R1  
MGT247  
Fig.6 Principle of voltage regulator of drivers  
supply in mode 1.  
In mode 1 the external transistor can supply large peak  
currents which are being drawn from the capacitor used at  
pin CAPH. Since VCAPH is chosen to be 2.6 or 5.15 V  
(programmable via the serial bus with bit VD2X) above  
VHFB the voltage at the capacitor at pin CAPH can drop  
approximately 1.8 or 4.5 V during the transport without  
affecting VHFB. This reduces the value (size) of the  
capacitor required at pin CAPH. During the transport the  
base-emitter voltage of the external transistor will increase  
causing a drop on VHFB. The drop depends on the static  
current set by R1 and the maximum peak current being  
drawn and can be calculated with the following formula:  
handbook, halfpage  
MGT249  
V
V
V
CAPH  
HFB  
Ipeak  
Vdrop = 25 mV × Ln  
-----------  
IR1  
t
transport  
transport  
The static current should be approximately 500 µA.  
Capacitor C2, connected to the emitter, filters out the  
spikes averaging the peak current. When the peak current  
stops, the increased base-emitter voltage will drop back to  
its normal level (see Fig.7).  
Fig.7 Output voltage at pin CAPH during transport.  
The base voltage VVBE might have been changed slightly  
(tens of millivolts) but will get back to its desired level fast.  
After transport the capacitor at pin CAPH will be charged  
again by the DC-DC converter.  
CAPH  
MODE 2  
AMP4  
V
DAC  
VBE  
HFB  
In applications where the transport of the image is slow, a  
constant current is required which can be supplied by the  
voltage regulator and no external transistor is needed.  
Mode 2 is selected via the serial interface (bit D1 = 1).  
V
= 8  
HFB  
C1  
In mode 2, pins VBE and HFB must be tied together (see  
Fig.8).  
MGT248  
In this mode the voltage regulator can supply currents up  
to 30 mA. Peak currents need to be filtered out by  
capacitor C1.  
Fig.8 Principle of voltage regulator of drivers  
supply in mode 2.  
2001 May 29  
8
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
START-UP CYCLE  
During the start-up (pin START = HIGH and the internal  
signal DCOK = LOW) the maximum output current of  
AMP4 (see Fig.8) will be increased from 0.5 mA minimum  
to 30 mA maximum. This is done to decrease the time  
required to fully charge capacitor C1 during starting up.  
MGT250  
handbook, halfpage  
V
START  
H
When pin START = LOW (all voltages are at their required  
level) or when VVBE is at its required level, the minimum  
output current of AMP4 will automatically drop back to  
0.5 mA. When mode 2 is selected the maximum output  
current of AMP4 will remain 30 mA after starting up.  
L
0%  
80 ± 5%  
100%  
An integrated start-up cycle ensures a fast and safe  
start-up of the TDA9991HL. The principle of the start-up  
cycle (hysteresis) is shown in Fig.9. When starting up the  
signal at pin START will be HIGH. When VCAPNS and  
regulator output voltage  
VCAPH are at 100% of their programmed level and VHFB  
and VNS are above 80% of their programmed level,  
pin START will become LOW. When VCAPNS, VHFB or VNS  
drops below approximately 80% of their programmed level  
the TDA9991HL will start again with the start-up cycle.  
Fig.9 Hysteresis of start-up cycle.  
When starting up, the capacitor at pin CAPNS will be  
charged prior to the capacitor at pin CAPH. The capacitor  
at pin VL is charged by a separate DC-DC converter  
independent of the start-up cycle.  
V
handbook, halfpage  
HFB  
HDA,  
HDB  
Vertical line drivers  
For frame transport the TDA9991HL has eight two-level  
low-ohmic drivers available. The principle of the driver  
outputs is shown in Fig.10.  
VA1 to VA4,  
VB1 to VB4  
A1 to A4,  
B1 to B4  
LOGIC  
INTERFACE  
A logic interface converts the digital input signal into the  
two control signals for the driver transistors. It also  
prevents both transistors to switch on at the same time.  
During start-up the drivers are kept in 3-state.  
3-STATE DCOK  
MGT251  
Table 1 A and B drivers; note 1  
Fig.10 Principle of driver output.  
LEVEL AT INPUT PINS  
LEVEL AT OUTPUT PINS  
LOW  
HIGH  
LOW  
Shutter driver  
HIGH  
Table 2 Shutter driver output  
Note  
1. The internal DCOK signal will keep the A and B  
outputs in 3-state until the output voltages of the  
DC-DC converter and voltage regulators are at their  
required level.  
INPUT LEVEL AT  
PIN SHIN  
OUTPUT LEVEL AT  
PIN SHO  
LOW  
HIGH  
LOW  
HIGH  
2001 May 29  
9
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
Serial interface  
SDATA  
SHIFT REGISTER  
D0 D1 D2 D3 D4 A0 A1 A2  
SCLK  
SEN  
LSB  
MSB  
5
LATCH  
SELECTION  
5
2
4
5
4
4
POWER ON/OFF,  
3-STATE ON/OFF,  
OSCILLATOR  
FREE/EXTERNAL  
(LATCH 0)  
VD2X,  
MODE  
(LATCH 1)  
V
V
V
V
HFB  
NS  
SFD  
SH  
(LATCH 2)  
(LATCH 3)  
(LATCH 4)  
(LATCH 5)  
on/off outputs oscillator  
3-state  
VD2X  
4-bit DAC  
5-bit DAC  
4-bit DAC  
4-bit DAC  
mode  
MGT252  
Fig.11 Serial interface block diagram.  
t
su(SDATA)  
t
h(SDATA)  
SDATA  
SCLK  
SEN  
A2  
A1  
A0  
D4  
D3  
D2  
D1  
D0  
MGT253  
t
t
h(SEN)  
su(SEN)  
Pin SEN must stay HIGH for at least two clock cycles after each word.  
Fig.12 Loading sequence of input data to control DACs via the serial interface.  
10  
2001 May 29  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
Table 3 Serial interface programming (see Fig.11)  
ADDRESS BITS  
DATA BITS(1)  
D2  
LATCH  
DESCRIPTION  
A2  
0
A1  
A0  
0
D4  
D3  
D1  
D0  
0
0
power-on, 3-state and clock selection  
power-down (note 2)  
power-on  
0
1
0
1
outputs in normal operation  
outputs in 3-state  
don’t care  
X
0
1
free running oscillator  
external clock signal  
fixed value  
0
1
0
0
1
voltage drop and mode selection  
2.7 V drop (bit VD2X = 0)  
5.4 V drop (bit VD2X = 1)  
mode 1  
0
1
0
1
mode 2  
2
3
4
5
0
0
1
1
1
1
0
0
0
1
0
1
4 bits of VHFB  
X
X
X
0
:
0
:
0
:
0
:
output is 8 V  
steps of approximately 467 mV  
output is 15 V  
1
1
1
1
5 bits of VNS  
0
:
0
:
0
:
0
:
0
:
output is 17 V  
steps of approximately 450 mV  
output is 31 V  
1
1
1
1
1
4 bits of VSFD  
X
X
X
0
:
0
:
0
:
0
:
output is 18 V  
steps of approximately 400 mV  
output is 24 V  
1
1
1
1
4 bits of VSH  
X
X
X
0
:
0
:
0
:
0
:
output is 3 V  
steps of approximately 467 mV  
output is 10 V  
1
1
1
1
Notes  
1. X is a don’t care.  
2. The Power-down mode also shuts down the DC-DC converter.  
2001 May 29  
11  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
PARAMETER  
analog supply voltage 1  
CONDITIONS  
MIN.  
0.3  
MAX.  
UNIT  
VDDA1  
VDDA2  
VDDD  
Vn  
+7  
+7  
V
analog supply voltage 2  
digital supply voltage  
voltage at pins  
0.3  
0.3  
V
V
+5.5  
VA1 to VA4, VB1 to VB4, V5V, PWD,  
SDATA, SEN, SCLK, SHIN and OSC  
0.3  
VDDD + 0.3(1)  
V
CAPBG  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
6  
V
V5V + 0.3  
V
V
V
V
V
V
V
V
CAP12  
+15  
+20  
+20  
+45  
+45  
VBE, SH, HFB, HDA and HDB  
CAPH  
coil not connected  
coil not connected  
CAPNS  
NS and SFD  
VL  
AGND1, AGND2, AGND3 and AGND4  
VDGND 0.3 VDGND + 0.3  
In  
current at pins  
A1 to A4 and B1 to B4  
static current  
100  
0
+100  
5
mA  
mA  
mA  
mA  
mA  
VL  
LIM  
3  
0
SHO  
START  
50  
3  
+50  
+0.2  
Note  
1. Maximum value of VDDD + 0.3 V but not higher than 5.5 V.  
QUALITY SPECIFICATION  
In accordance with “SNW-FQ-611E”.  
CHARACTERISTICS  
VDDA = 5 V; VDDD = 3.3 V; Tamb = 25 °C; inputs VA1 to VA4 and VB1 to VB4 are HIGH; VSHIN = 0 V; L1 = 47 µH;  
L2 = 4.7 µH; RLIM = 680 ; VHFB = 12 V; VNS = 24 V; VSFD = 20 V; VSH = 8 V; VSTART = LOW; no load for regulator  
output voltages; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supplies  
VDDA1  
analog supply voltage 1  
analog supply current 1  
3.6  
5
7
V
IDDA1  
VVA1 to VVA4 = VDDD  
;
3.5  
mA  
VVB1 to VVB4 = VDDD  
VSEN = 0  
;
Iq(DDA1)  
VDDA2  
quiescent analog supply  
current 1  
Power-down mode;  
latch 0 = 00X00; note 1  
300  
7
µA  
analog supply voltage 2  
3.6  
5
V
2001 May 29  
12  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
IDDA2  
analog supply current 2  
VVA1 to VVA4 = VDDD  
;
;
130  
mA  
VVB1 to VVB4 = VDDD  
SEN = 0; note 2  
Power-down mode;  
latch 0 = 00X00; note 1  
V
Iq(DDA2)  
quiescent analog supply  
current 2  
4
µA  
VDDD  
IDDD  
digital supply voltage  
digital supply current  
2.6  
3.3  
3.6  
V
VVA1 to VVA4 = VDDD  
;
460  
µA  
VVB1 to VVB4 = VDDD  
VSEN = 0  
;
Iq(DDD)  
quiescent digital supply  
current  
Power-down mode;  
latch 0 = 00X00; note 1  
100  
µA  
Vertical line drivers A and B  
Ro(on)  
HIGH- and LOW-level output IL(H) = 200 mA;  
0.6  
16  
18  
0.66  
20  
0.72  
29  
on-resistance  
IL(L) = 200 mA  
tr  
tf  
rise time of outputs  
V
NS VHFB > 7 V;  
CL = 6.8 nF  
NS VHFB > 7 V;  
ns  
ns  
fall time of outputs  
V
23  
29  
CL = 6.8 nF  
VOH  
VOL  
HIGH-level output voltage  
LOW-level output voltage  
VHFB  
V
0
V
ILO(Z)  
output leakage current in  
3-state  
3-state; VO < 6 V;  
latch 0 = 00X11  
1  
+1  
µA  
tPD  
propagation delay  
no load  
40  
ns  
ns  
tPD  
propagation delay difference  
between channels  
3
Shutter driver (pin SHO)  
Ro(on)  
HIGH- and LOW-level output IL(H) = 3 mA;  
16.5  
on-resistance  
IL(L) = 3 mA  
VOH  
VOL  
tr  
HIGH-level output voltage  
LOW-level output voltage  
rise time  
VSH  
0
V
V
V
NS VSH > 7 V;  
CL = 2 nF  
NS VSH > 7 V;  
50  
ns  
tf  
fall time  
V
50  
ns  
CL = 2 nF  
DC-DC converters  
VCAPNS output voltage at pin CAPNS  
VCAPH  
VNS + 6  
V
V
V
%
output voltage at pin CAPH bit VD2X = 0; note 3  
bit VD2X = 1; note 3  
VHFB + 2.45 VHFB + 2.6  
VHFB + 2.75  
VHFB + 4.9  
VHFB + 5.15 VHFB + 5.4  
IL2(max)  
variation of maximum  
note 4  
15  
+15  
current built-up in coil L2  
tstart  
start-up time of the DC-DC  
converter  
VSTART = HIGH;  
RLIM = 680 ;  
35  
60  
ms  
VHFB = 13.1 V; note 5  
2001 May 29  
13  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Output voltage regulators  
HIGH VOLTAGE FEEDBACK OUTPUT (PIN HFB)  
VHFB  
high voltage output  
programmable (4 bits)  
8
0
15  
+5  
0.5  
V
VHFB  
VHFB(T)  
output voltage variation  
5  
%
%
output voltage variation with Tamb = 20 to +70 °C  
temperature  
RR  
ripple rejection  
VSTART = LOW;  
60  
dB  
f = 0 to 1 MHz; note 6  
BASE VOLTAGE OUTPUT (PIN VBE)  
IVBE  
DC output current  
VSTART = LOW; note 7  
0.5  
30  
mA  
mA  
IVBE(start) output current during  
start-up  
VSTART = HIGH or in  
mode 2; note 7  
NWELL SUBSTRATE VOLTAGE OUTPUT (PIN NS)  
VNS  
output voltage  
programmable (5 bits); 17  
note 8  
31  
V
INS  
DC output current  
0
4
mA  
%
VNS  
VNS(T)  
output voltage variation  
5  
+5  
0.5  
output voltage variation with Tamb = 20 to +70 °C  
%
temperature  
RR  
ripple rejection  
VSTART = LOW;  
50  
dB  
f = 0 to 1 MHz; note 6  
SOURCE FOLLOWER DRAIN VOLTAGE OUTPUT (PIN SFD)  
VSFD  
output voltage  
programmable (4 bits); 18  
note 8  
24  
V
ISFD  
DC output current  
0
20  
+5  
0.5  
mA  
%
VSFD  
VSFD(T)  
output voltage variation  
5  
output voltage variation with Tamb = 20 to +70 °C  
%
temperature  
RR  
ripple rejection  
VSTART = LOW;  
50  
dB  
f = 0 to 1 MHz; note 6  
SHUTTER DRIVER VOLTAGE OUTPUT (PIN SH)  
VSH  
output voltage  
programmable (4 bits)  
3
0
10  
3
V
ISH  
DC output current  
output voltage variation  
mA  
%
VSH  
VSH(T)  
5  
+5  
0.5  
output voltage variation with Tamb = 20 to +70 °C  
%
temperature  
RR  
ripple rejection  
VSTART = LOW;  
60  
dB  
f = 0 to 1 MHz; note 6  
2001 May 29  
14  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Oscillator  
ffr  
free running oscillator  
frequency  
latch 0 = 00X01;  
ROSC = 47 k; note 9  
4
5.35  
6.75  
MHz  
MHz  
%
fclk  
external clock input  
frequency  
latch 0 = 01X01; note 9  
4
6.75  
60  
δ
duty factor external clock  
input frequency  
40  
Serial interface (see Fig.12)  
fSCLK(max) maximum clock frequency  
VDDD = 3.6V  
DDD = 3.3V  
VDDD = 3.0V  
DDD = 2.6V  
4.0  
3.3  
2.5  
1.8  
MHz  
MHz  
MHz  
MHz  
s
V
V
tsu(SEN)  
SEN set-up time  
compared to SCLK  
rising edge  
0.16  
------------------------  
fSCLK(max)  
tsu(SDATA) SDATA set-up time  
compared to SCLK  
rising edge  
s
s
s
0.16  
------------------------  
fSCLK(max)  
th(SEN)  
SEN hold time  
compared to SCLK  
rising edge  
0.08  
------------------------  
fSCLK(max)  
th(SDATA)  
SDATA hold time  
compared to SCLK  
rising edge  
0.16  
------------------------  
fSCLK(max)  
Control inputs  
VIL LOW-level input voltage at  
note 10  
note 11  
0.2  
0.3VDDD  
V
V
pins SEN, SDATA, SCLK,  
SHIN, PWD, VA1 to VA4,  
VB1 to VB4 and OSC  
VIH  
HIGH-level input voltage at  
pins SEN, SDATA, SCLK,  
SHIN, PWD, VA1 to VA4,  
VB1 to VB4 and OSC  
0.7VDDD  
5.5  
Digital output (pin START)  
VSTART(L) LOW-level output voltage  
Isink(max) = 20 µA;  
note 12  
0.4  
V
V
VSTART(H) HIGH-level output voltage  
Isource(max) = 20 µA;  
V
DDD 0.4  
note 13  
Temperature range  
Toper  
operating temperature  
20  
+70  
°C  
2001 May 29  
15  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
Notes  
1. A Power-on reset function puts the TDA9991HL in the Power-down mode when VDDD is supplied.  
2. The supply current is measured without load (CCD) using the following programmed voltages:  
VNS = 28 V; VSFD = 21 V; VHFB = 13 V; VSH = 8 V. The power consumption depends on the value of RLIM, the supply  
voltages, programmed voltages and the efficiency of the DC-DC convertor under load condition. Therefore, the value  
of IDDA2 in this table is a rough indication.  
3. During transport VCAPH may drop to VHFB + 0.7 V (over the entire temperature range):  
a) Bit VDX2 = 0: voltage drop is 1.8 V  
b) Bit VDX2 = 1: voltage drop is 4.5 V.  
1308  
RLIM  
4. IL2(max)  
=
-------------  
5. The charging time of the electrolytic capacitor at pin CAPNS is very small compared to the charging time of the  
electrolytic capacitor at pin CAPH. The start-up time depends on:  
a) Peak current IL2(max) chosen through coil L2; the maximum allowable peak current is 2.1 A  
b) Value of the electrolytic capacitor at pin CAPH (470 µF)  
c) Oscillator frequency  
d) Required voltage level at pin CAPH.  
6. Drivers not active.  
7. During start-up (VSTART = HIGH) the maximum output current at pin HFB is increased to allow fast starting up.  
8. VNS > VSFD  
9. Pin OSC can be connected to an external clock or to an external resistor (in case the internal oscillator is used).  
10. At VDDD = 2.6 V the maximum LOW-level voltage is 0.2VDDD  
.
.
11. At VDDD = 2.6 V the minimum HIGH-level voltage is 0.8VDDD  
12. VSTART will become LOW when:  
.
a) All output voltages at pins HFB, NS and CAPNS are at 100% of their required (programmable) level  
b) VCAPH = VHFB + 2.7 V (bit VD2X = 0) or VCAPH = VHFB + 5.4 V (bit VD2X = 1); VCAPH needs to have reached the  
programmed voltage only once for VSTART to go LOW.  
13. VSTART will become HIGH when either VHFB, VNS or VCAPNS drops below 80% (typical) of their programmed level.  
2001 May 29  
16  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
APPLICATION INFORMATION  
drivers  
control  
start  
100  
nF  
48 47 46 45 44 43 42 41 40 39 38 37  
SDATA  
SEN  
B4  
B4  
B3  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
B3  
serial  
bus  
2
SCLK  
AGND4  
HDB  
B2  
3
V
DDD  
V
4
DDD  
100 nF  
V5V  
OSC  
B2  
5
47 kΩ  
B1  
B1  
6
PHILIPS  
TDA9991HL  
AGND1  
A1  
CCD(FT)  
A1  
7
V
DDA1  
A2  
V
A2  
8
DDA  
R
LIM  
SHIN  
AGND3  
HDA  
A3  
9
LIM  
shutter  
control  
10  
11  
12  
SHO  
A3  
A4  
100 nF  
CAP12  
A4  
13 14 15 16 17 18 19 20 21 22 23 24  
L1  
L2  
47  
kΩ  
(1)  
BC868  
V
V
DDA  
DDA  
10 µF  
1 µF  
(1)  
27 kΩ  
10 470  
µF µF  
47  
µF  
22  
220  
nF  
100 220  
µF  
nF nF  
330  
nF  
MGT254  
L1 = 47 µH.  
L2 = 4.7 µH.  
RLIM = 680 .  
(1) The (emitter) current through the external resistor should be approximately 500 µA.  
The value of the resistor can be adjusted depending on the emitter voltage (VHFB).  
Fig.13 Application diagram.  
2001 May 29  
17  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
PACKAGE OUTLINE  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.60  
mm  
0.25  
0.5  
1.0  
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
99-12-27  
00-01-19  
SOT313-2  
136E05  
MS-026  
2001 May 29  
18  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
Introduction to soldering surface mount packages  
Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
Reflow soldering  
The footprint must incorporate solder thieves at the  
downstream end.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Manual soldering  
Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
2001 May 29  
19  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE  
WAVE  
not suitable  
REFLOW(1)  
BGA, HBGA, LFBGA, SQFP, TFBGA  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS  
PLCC(3), SO, SOJ  
suitable  
suitable  
suitable  
not suitable(2)  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2001 May 29  
20  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
DEFINITIONS  
STATUS(2)  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2001 May 29  
21  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
NOTES  
2001 May 29  
22  
Philips Semiconductors  
Preliminary specification  
Vertical line driver and DC-DC converter for Full Frame  
and Frame Transfer CCD image sensors  
TDA9991HL  
NOTES  
2001 May 29  
23  
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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 68 9211, Fax. +359 2 68 9102  
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,  
Tel. +48 22 5710 000, Fax. +48 22 5710 001  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Colombia: see South America  
Czech Republic: see Austria  
Tel. +65 350 2538, Fax. +65 251 6500  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,  
Tel. +45 33 29 3333, Fax. +45 33 29 3905  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,  
Tel. +27 11 471 5401, Fax. +27 11 471 5398  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615 800, Fax. +358 9 6158 0920  
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 4728 6600, Fax. +33 1 4728 6638  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 2353 60, Fax. +49 40 2353 6300  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,  
Tel: +36 1 382 1700, Fax: +36 1 382 1800  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,  
Tel. +66 2 361 7910, Fax. +66 2 398 3447  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
Tel. +39 039 203 6838, Fax +39 039 203 6800  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057  
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 3341 299, Fax.+381 11 3342 553  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 27 24825  
Internet: http://www.semiconductors.philips.com  
72  
SCA  
© Philips Electronics N.V. 2001  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
753504/03/pp24  
Date of release: 2001 May 29  
Document order number: 9397 750 08187  

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