TDA9989ET [NXP]

150 MHz pixel rate HDMI 1.3a transmitter with 3 ′ 8-bit video inputs and CEC support; 150 MHz的像素速率的HDMI 1.3a发射器, 3 “ 8 - bit视频输入和CEC支持
TDA9989ET
型号: TDA9989ET
厂家: NXP    NXP
描述:

150 MHz pixel rate HDMI 1.3a transmitter with 3 ′ 8-bit video inputs and CEC support
150 MHz的像素速率的HDMI 1.3a发射器, 3 “ 8 - bit视频输入和CEC支持

消费电路 商用集成电路
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TDA9989  
150 MHz pixel rate HDMI 1.3a transmitter with 3 × 8-bit video  
inputs and CEC support  
Rev. 02 — 11 June 2009  
Product data sheet  
1. General description  
The TDA9989 is a very low power and very small size High-Definition Multimedia Interface  
(HDMI) 1.3a transmitter. It is backward compatible DVI 1.0 and can be connected to any  
DVI 1.0 and HDMI sink.  
This device is primarily intended for mobile applications like Digital Video Camera (DVC),  
Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra  
Mobile Personal Computer (UM PC) where size and very low power are mandatory for  
battery autonomy.  
It allows mixing 3 × 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz  
together with one S/PDIF or one I2S-bus audio streams with an audio sampling rate up to  
192 kHz.  
In order to be compatible with most applications, the TDA9989 integrates a full  
programmable input formatter and color space conversion block. The video input formats  
accepted are YCbCr 4 :4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit)  
and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of ITU656-like  
format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR  
mode).  
This device provides additional embedded feature like CEC (Consumer Electronic  
Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby  
from remote control) over the home appliance network connected through this wire. This  
eliminates the need of any additional device to handle this feature thus improving BOM  
(Bill Of Materials) of the whole system and enable the connected devices (CEC enabled)  
to be controlled by only one remote control.  
The TDA9989 supports xvYCC HDMI 1.3a feature.  
It can be switched to very low power Standby or Sleep modes to save power when HDMI  
is not used.  
The TDA9989 includes a true I2C-bus master interface for DDC-bus communication for  
EDID reading.  
This device can be controlled or configured via I2C-bus interface.  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
PLL  
SERIALIZER  
PIXEL, REPETITION  
2
I C-BUS  
CEC  
CEC  
SLAVE  
2
I S  
HDMI  
ENCODER  
SERIALIZER  
HDMI  
TMDS  
link  
AUDIO  
video  
S/PDIF  
COLOR  
SPACE  
CONVERTER  
RGB  
INPUT  
FORMATTER  
2
I C-BUS  
YCbCr  
MASTER DDC  
001aai441  
Fig 1. TDA9989 high-level block diagram  
2. Features  
I Compliance  
N DVI 1.0  
N HDMI 1.3a  
N EIA/CEA-861B  
N CEC (HDMI 1.3a)  
N SimplayHD  
I Video  
N xvYCC HDMI 1.3a feature  
N Video formats with a pixel rate up to 150 MHz:  
RGB 4 : 4 : 4  
YCbCr 4 : 4 : 4  
YCbCr 4 : 2 : 2 semi planar  
YCbCr 4 : 2 : 2 ITU656  
N Maximum resolution:  
1080p for TV  
1600 × 1200 at 60 Hz for PC (UXGA60)  
720p/1080i in ITU656  
N Programmable color space converter:  
RGB to YCbCr  
YCbCr to RGB  
N Programmable input formatter and upsampler/interpolator allows input of any of the  
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats  
N Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs  
or VREF, HREF and FREF could be used for input data synchronization  
N Pixel clock input can be made active on one or both edges (selectable by I2C-bus)  
N Repetition of video samples as required by HDMI specification.  
I Audio:  
N I2S-bus 2 channels and S/PDIF; audio data rate up to 192 kHz per input for both  
standards  
I System operation  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
2 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
N Master DDC-bus interface for EDID read  
N Controllable via I2C-bus  
N Downstream availability through the use of hot plug (HPD) and receiver detection  
(RxSense)  
N Deals with multiple levels of receivers and repeaters  
I Package  
N TFBGA64  
N Size 4.5 × 4.5 × 0.8 mm  
I Power management  
N External voltage supplies 1.8 V, 1.2 V (to support 1080p video format, the 1.2 V  
must be raised to 1.8 V)  
N Low power (45 mW in 480p)  
N Flexible power modes  
I Miscellaneous  
N POR (Power-On Reset)  
N Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant  
N 250 MHz to 1.65 GHz TMDS transmitter operation  
3. Applications  
I Digital Video Camera (DVC),  
I Digital Still Camera (DSC),  
I Portable Multimedia Player (PMP)  
I Mobile Phone  
I Ultra Mobile Personal Computer (UM PC)  
4. Ordering information  
Table 1.  
Ordering information  
Type number Package  
Name  
Description  
Version  
TDA9989ET  
TFBGA64  
plastic thin fine-pitch ball grid array package; 64 balls SOT962-3  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
3 of 48  
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx  
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx  
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x  
AUDIO PROCESSING  
FIFO  
HDMI PACKET INSERTION  
AUDIO CONTENT  
TMDS BLOCK  
Rx SENSE  
TDA9989  
ACLK  
AP1  
WS  
AUDIO  
CAPTURE  
PROCESSING  
DATA  
ISLAND  
INFO FRAME  
ACR  
TXC+  
TXC−  
PACKET  
INSERTION  
CTS/N  
TX0+  
TX0−  
HDMI  
NULL AND ACP  
SERIALIZER  
TX1+  
TX1−  
PLL BLOCK  
VHREF GENERATOR  
TX2+  
CLOCK  
MANAGEMENT  
TX2−  
VCLK  
EXT_SWING  
(1)  
DOWNSAMPLER  
4 : 4 : 4 to 4 : 2 : 2  
2
I C-BUS DDC INTERFACE  
HPD  
3 × 8-bit RGB or YCbCr 4 : 4 : 4  
2 × 12-bit YCbCr 4 : 4 : 2 semi-planar  
HPD  
MANAGEMENT  
REGISTERS  
VSYNC/VREF  
HSYNC/VREF  
DE/FREF  
INTERRUPT  
GENERATION  
INT_HDMI  
VIDEO  
INPUT  
DATA  
COLOR SPACE  
CONVERTER  
YCbCr to RGB  
RGB to YCbCr  
(1)  
VPA[7:0]  
UPSAMPLER  
4 : 2 : 2  
to  
2
CAPTURE  
DDC  
MASTER  
I C-BUS  
SLAVE  
VPB[7:0]  
VPC[7:0]  
4 : 4 : 4  
CEC  
CEC  
VIDEO PROCESSING  
DSCL DSDA CSCL CSDA  
001aai442  
(1) The color space converter can be bypassed.  
The device does not handle HDCP.  
Fig 2. TDA9989 Block diagram  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
6. Pinning information  
6.1 Pinning  
TDA9989  
ball A1  
index area  
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
001aai443  
Transparent top view  
Fig 3. Pin configuration (TFBGA64)  
6.2 Pin description  
Table 2.  
Symbol  
Pin description  
Pin  
H5  
G5  
F5  
Type[1] Description  
ACLK  
I
I
audio clock input  
AP0  
audio port 0 input  
AP1  
I
audio port 1 input  
HPD  
E6  
E7  
I
hot plug detect; 5 V tolerant  
EXT_SWING  
O
TMDS output swing adjustment; place resistor  
(REXT_SWING = 10 kΩ ± 1 %) between this pin and analog  
ground.  
DSDA  
DSCL  
VCLK  
F6  
F7  
D4  
I/O  
DDC-bus data input/output; 5 V tolerant  
DDC-bus clock input; 5 V tolerant  
I
I
input video pixel clock  
HSYNC/HREF F4  
VSYNC/VREF G4  
I
input horizontal synchronization or reference input  
input vertical synchronization or reference input  
data enable or field reference input  
I
I
DE/FREF  
CSCL  
H4  
B5  
A5  
B6  
I
I2C-bus clock input; 1.8 V to 3.3 V tolerant  
I2C-bus data input/output; 1.8 V to 3.3 V tolerant  
CSDA  
I/O  
I/O  
INT_HDMI  
interrupt HDMI output (open-drain); this pin is used as Dual  
function pin selectable through I2C-bus. In calibration mode  
only this pin is used as input for 10 ms ± 1 % calibration pulse.  
In operation mode this pin is used to warn the external  
microprocessor that a special event has occurred for HDMI or  
CEC  
TX0−  
TX0+  
TX1−  
E8  
D8  
C8  
O
O
O
negative data channel 0 for TMDS output  
positive data channel 0 for TMDS output  
negative data channel 1 for TMDS output  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
5 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 2.  
Pin description …continued  
Symbol  
TX1+  
Pin  
B8  
A7  
A6  
G8  
F8  
Type[1] Description  
O
O
O
O
O
I/O  
I
positive data channel 1 for TMDS output  
TX2−  
negative data channel 2 for TMDS output  
positive data channel 2 for TMDS output  
negative clock channel for TMDS output  
positive clock channel for TMDS output  
CEC connection (open-drain) to HDMI connector  
TX2+  
TXC−  
TXC+  
CEC  
H7  
H6  
OSC_IN  
input connected to the external oscillator circuit or external  
clock source  
OSC_OUT  
G6  
O
output from the oscillator amplifier connected to the external  
oscillator circuit  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
VPB[6]  
VPB[7]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
C1  
B1  
B2  
A2  
B3  
A3  
B4  
A4  
E3  
E2  
E1  
D1  
D2  
D3  
C2  
C3  
H3  
H2  
G3  
G2  
G1  
F1  
F2  
F3  
I
I
video port A input bit 0 (LSB)  
video port A input bit 1  
I
video port A input bit 2  
I
video port A input bit 3  
I
video port A input bit 4  
I
video port A input bit 5  
I
video port A input bit 6  
I
video port A input bit 7 (MSB)  
video port B input bit 0 (LSB)  
video port B input bit 1  
I
I
I
video port B input bit 2  
I
video port B input bit 3  
I
video port B input bit 4  
I
video port B input bit 5  
I
video port B input bit 6  
I
video port B input bit 7 (MSB)  
video port C input bit 0 (LSB)  
video port C input bit 1  
I
I
I
video port C input bit 2  
I
video port C input bit 3  
I
video port C input bit 4  
I
video port C input bit 5  
I
video port C input bit 6  
I
video port C input bit 7 (MSB)  
TMDS analog supply voltage (1.8 V)  
I/O digital supply voltage (1.8 V)  
VDDA(TMDS)(1V8) A8, C7  
P
P
P
VDDD(IO)(1V8)  
VDDA(PLL)(1V8)  
E4  
C6  
PLL analog supply voltage (1.8 V), this PLL provides the clock  
for the serializer  
VDDA(1V8)  
G7, H8  
E5  
P
P
analog supply voltage (1.8 V), is used for parallel-to-serial  
shift register and miscellaneous blocks  
VDD(OSC)(CEC)  
CEC oscillator supply voltage (1.8 V)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
6 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 2.  
Pin description …continued  
Symbol  
VDDDC  
VSSD  
Pin  
Type[1] Description  
D5  
P
core digital supply voltage[2]  
B7,  
C4, C5  
G
digital ground supply voltage, is used for digital core; I/O and  
CEC oscillator  
VSSA  
D6, D7  
G
analog ground supply voltage, is used for PLL; serializer,  
transmitter, and parallel-to-serial shift register  
[1] P = power supply, G = ground, I = input, O = output.  
[2] To support 1080p video format, the 1.2 V supply voltage must be raised to 1.8 V.  
7. Functional description  
The TDA9989 is designed to convert digital data (video and audio) provided by Set-Top  
Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable  
Multimedia Player (PMP) or DVD into an HDMI output, which can be used by a TV with  
either an HDMI or DVI input.  
The TDA9989 is able to output HDMI with the formats:  
RGB 4 : 4 : 4  
YCbCr 4 : 4 : 4  
YCbCr 4 : 2 : 2  
The video data input formats are:  
RGB 4 : 4 : 4  
YCbCr 4 : 4 : 4  
YCbCr 4 : 2 : 2 semi-planar  
YCbCr 4 : 2 : 2 ITU656-like  
It can also handle audio formats:  
two I2S-bus channels  
one S/PDIF channel (Dolby Digital: 5.1 CH, DTS, AC3)  
The TDA9989 is also designed to support CEC protocol. For more details about CEC,  
refer to HDMI 1.3a specification.  
7.1 System clock  
The system clock section has a PLL serializer.  
It is a system clock generator which enables the stream produced by the encoder to be  
transmitted on the HDMI data channel at ten times, or above, the sampling rate.  
7.2 Video input formatter  
7.2.1 Description  
The TDA9989 has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0].  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
7 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
The TDA9989 can accept any of the following video input modes (see Table 6):  
RGB, with 8-bit for each component  
YCbCr 4 : 4 : 4, with 8-bit for each component  
YCbCr 4 : 2 : 2 semi-planar, with up to 12-bit for each component (YCbCr)  
YCbCr 4 : 2 : 2 ITU656, with up to 12-bit data depth  
The TDA9989 can be set to latch data at either rising or falling edge, or both.  
7.2.2 Internal assignment  
The aim of the video input processor is to internally map the incoming data to the  
corresponding mode, which can be handled by the video processing. The internal signal  
named VP[23:0] is assigned depending on the input mode as defined below.  
VPA[7:0]  
VIDEO  
VPB[7:0]  
VP[23:0]  
INPUT  
PROCESSOR  
VPC[7:0]  
001aah028  
Fig 4. Internal assignment of VP[23:0]  
Table 3.  
Internal assignment  
Internal assignment  
Internal port  
RGB  
YCbCr 4 : 4 : 4  
YCbCr 4 : 2 : 2  
semi-planar  
YCbCr 4 : 2 : 2  
ITU656  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[19]  
VP[18]  
VP[17]  
VP[16]  
VP[15]  
VP[14]  
VP[13]  
VP[12]  
G[7]  
G[6]  
G[5]  
G[4]  
G[3]  
G[2]  
G[1]  
G[0]  
B[7]  
B[6]  
B[5]  
B[4]  
Y[7]  
Y[11]  
Y[10]  
Y[9]  
Y[8]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
YCbCr[11]  
YCbCr[10]  
YCbCr[9]  
YCbCr[8]  
YCbCr[7]  
YCbCr[6]  
YCbCr[5]  
YCbCr[4]  
YCbCr[3]  
YCbCr[2]  
YCbCr[1]  
YCbCr[0]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
Cb[7]  
Cb[6]  
Cb[5]  
Cb[4]  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
8 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 3.  
Internal assignment …continued  
Internal assignment  
Internal port  
RGB  
YCbCr 4 : 4 : 4  
YCbCr 4 : 2 : 2  
semi-planar  
YCbCr 4 : 2 : 2  
ITU656  
VP[11]  
VP[10]  
VP[9]  
VP[8]  
VP[7]  
VP[6]  
VP[5]  
VP[4]  
VP[3]  
VP[2]  
VP[1]  
VP[0]  
B[3]  
B[2]  
B[1]  
B[0]  
R[7]  
R[6]  
R[5]  
R[4]  
R[3]  
R[2]  
R[1]  
R[0]  
Cb[3]  
Cb[2]  
Cb[1]  
Cb[0]  
Cr[7]  
Cr[6]  
Cr[5]  
Cr[4]  
Cr[3]  
Cr[2]  
Cr[1]  
Cr[0]  
CbCr[11]  
CbCr[10]  
CbCr[9]  
CbCr[8]  
CbCr[7]  
CbCr[6]  
CbCr[5]  
CbCr[4]  
CbCr[3]  
CbCr[2]  
CbCr[1]  
CbCr[0]  
The device can swap and invert, in the event of a little endian stream, the incoming video  
data using I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page  
00h) to match the expectation of the video processing block. Table 4 shows the behavior  
of SWAP_A[2:0] of VIP_CNTRL_0 register, whose function is to map the 4 MSBs  
VP[23:20] to the incoming video port.  
Table 4.  
External  
assignment  
Video input swap to VP[23:20]  
SWAP_A  
selector  
value  
Internal assignment  
Pin  
number  
Pin  
Internal RGB  
port  
YCbCr YCbCr 4 : 2 : 2 YCbCr 4 : 2 : 2  
name  
4 : 4 : 4 semi-planar  
ITU656  
F3  
F2  
F1  
G1  
G2  
G3  
H2  
H3  
C3  
C2  
D3  
D2  
D1  
E1  
E2  
E3  
VPC[7] 000b  
VPC[6]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
G[7]  
G[6]  
G[5]  
G[4]  
G[7]  
G[6]  
G[5]  
G[4]  
G[7]  
G[6]  
G[5]  
G[4]  
G[7]  
G[6]  
G[5]  
G[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPC[5]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPC[4]  
VPC[3] 001b  
VPC[2]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPC[1]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPC[0]  
VPB[7] 010b  
VPB[6]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[5]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPB[4]  
VPB[3] 011b  
VPB[2]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[1]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPB[0]  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
9 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 4.  
Video input swap to VP[23:20] …continued  
External  
assignment  
SWAP_A  
selector  
value  
Internal assignment  
Pin  
number  
Pin  
name  
Internal RGB  
port  
YCbCr YCbCr 4 : 2 : 2 YCbCr 4 : 2 : 2  
4 : 4 : 4 semi-planar  
ITU656  
A4  
B4  
A3  
B3  
A2  
B2  
B1  
C1  
VPA[7] 100b  
VPA[6]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
G[7]  
G[6]  
G[5]  
G[4]  
G[7]  
G[6]  
G[5]  
G[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPA[5]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPA[4]  
VPA[3] 101b  
VPA[2]  
Y0[11] Y1[11]  
Y0[10] Y1[10]  
Cb[11] Y0[11] Cr[11] Y1[11]  
Cb[10] Y0[10] Cr[10] Y1[10]  
VPA[1]  
Y0[9]  
Y0[8]  
Y1[9]  
Y1[8]  
Cb[9]  
Cb[8]  
Y0[9]  
Y0[8]  
Cr[9]  
Cr[8]  
Y1[9]  
Y1[8]  
VPA[0]  
In the same way:  
SWAP_B is used to map incoming video port to the internal port VP[19:16].  
SWAP_C is used to map incoming video port to the internal port VP[15:12].  
SWAP_D is used to map incoming video port to the internal port VP[11:8].  
SWAP_E is used to map incoming video port to the internal port VP[7:4].  
SWAP_F is used to map incoming video port to the internal port VP[3:0].  
The device expects to receive big endian incoming data. However, in cases where the  
input digital stream to the chip is little endian, the use of the mirror bit of the same register  
can help to re-order the input bits as described in Table 5.  
Table 5.  
TDA9989 input/output capability  
Internal port  
Bit setting  
To be mapped to  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
VPB[6]  
VPB[7]  
MIRR_A = 1  
SWAP_A = 1  
VP[23]  
VP[22]  
VP[21]  
VP[20]  
VP[19]  
VP[18]  
VP[17]  
VP[16]  
VP[15]  
VP[14]  
VP[13]  
VP[12]  
VP[11]  
VP[10]  
VP[9]  
MIRR_B = 1  
SWAP_B = 0  
MIRR_C = 1  
SWAP_C = 3  
MIRR_D = 1  
SWAP_D = 2  
VP[8]  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
10 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 5.  
TDA9989 input/output capability …continued  
Bit setting  
Internal port  
VP[7]  
To be mapped to  
VPA[4]  
MIRR_E = 1  
SWAP_E = 5  
VP[6]  
VPA[5]  
VP[5]  
VPA[6]  
VP[4]  
VPA[7]  
MIRR_F = 1  
SWAP_F = 4  
VP[3]  
VPA[0]  
VP[2]  
VPA[1]  
VP[1]  
VPA[2]  
VP[0]  
VPA[3]  
When input ports are not used, it is possible to map them to internal ground via the  
I2C-bus with the appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on  
page 00h.  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
11 of 48  
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
7.2.3 Input format mappings  
Table 6 gives more information concerning input format supported.  
Table 6.  
Inputs of video input formatter  
Color Format Channels  
space  
Sync type Rising Falling Double Transmission Max. pixel  
Max. input Comments  
Reference  
edge edge  
edge  
input format clock (MHz) format  
RGB  
4 : 4 : 4 3 × 8-bit  
external  
X
-
150  
-
-
-
-
-
-
-
-
for 1080p video format Section 7.2.3.1  
1.2 V power supply  
must be raised to  
X
-
150  
embedded X  
-
150  
1.8 V  
X
X
X
-
150  
YCbCr 4 : 4 : 4 3 × 8-bit  
external  
X
-
150  
Section 7.2.3.2  
-
150  
embedded X  
-
150  
-
150  
YCbCr 4 : 2 : 2 up to 1 × 12-bit external  
X
ITU656-like  
54.054  
148.5  
54.054  
148.5  
74.25  
54.054  
148.5  
54.054  
148.5  
74.25  
480p/576p for 720p/1080i format Section 7.2.3.3  
ITU656-like  
1.2 V power supply  
must be raised to  
480p/576p  
1.8 V  
720p/1080i  
X
X
ITU656-like  
720p/1080i  
X
X
ITU656-like  
ITU656-like  
720p/1080i double edge  
Section 7.2.3.4  
embedded X  
480p/576p for 720p/1080i format, Section 7.2.3.5  
1.2 V power supply  
must be raised to  
480p/576p  
1.8 V  
720p/1080i  
ITU656-like  
720p/1080i  
ITU656-like  
720p/1080i double edge  
Section 7.2.3.6  
Section 7.2.3.7  
up to 2 × 8-bit  
external  
X
SMPTE293M 148.5  
SMPTE293M 148.5  
SMPTE293M 148.5  
SMPTE293M 148.5  
1080p  
1080p  
1080p  
1080p  
for 1080p, 1.2 V  
power supply must be  
raised to 1.8 V  
semi-planar  
X
X
embedded X  
Section 7.2.3.8  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.1 RGB 4 : 4 : 4 external synchronization (rising edge)  
Table 7.  
RGB (3 × 8-bit) external synchronization input (rising edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
Video port A  
Pin  
Video port B  
RGB 4 : 4 : 4 Pin  
Video port C  
RGB 4 : 4 : 4 Pin  
Control  
RGB 4 : 4 : 4 Pin  
RGB 4 : 4 : 4  
HSYNC/HREF used  
VSYNC/VREF used  
DE/FREF used  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
B[0]  
B[1]  
B[2]  
B[3]  
B[4]  
B[5]  
B[6]  
B[7]  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
VPB[6]  
VPB[7]  
G[0]  
G[1]  
G[2]  
G[3]  
G[4]  
G[5]  
G[6]  
G[7]  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
R[0]  
R[1]  
R[2]  
R[3]  
R[4]  
R[5]  
R[6]  
R[7]  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
B [7:0]  
B [7:0]  
B [7:0]  
B [7:0]  
...  
...  
...  
B
[7:0]  
[7:0]  
[7:0]  
B
[7:0]  
xxx  
0
1
2
3
xxx  
G [7:0]  
0
G [7:0]  
1
G [7:0]  
2
G [7:0]  
3
G
R
G
R
[7:0]  
[7:0]  
xxx  
xxx  
R [7:0]  
0
R [7:0]  
1
R [7:0]  
2
R [7:0]  
3
xxx  
xxx  
001aag380  
DE could also be generated from HSYNC/HREF and VSYNC/VREF.  
Fig 5. Pixel encoding RGB 4 : 4 : 4 external synchronization input (rising edge)  
7.2.3.2 YCbCr 4 : 4 : 4 external synchronization (rising edge)  
Table 8.  
YCbCr 4 : 4 : 4 (3 × 8-bit) external synchronization input (rising edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.  
Video port A Video port B Video port C  
YCbCr 4 : 4 : 4 Pin YCbCr 4 : 4 : 4 Pin  
Control  
Pin  
YCbCr 4 : 4 : 4 Pin  
YCbCr 4 : 4 : 4  
used  
VPA[0] Cb[0]  
VPA[1] Cb[1]  
VPA[2] Cb[2]  
VPA[3] Cb[3]  
VPA[4] Cb[4]  
VPA[5] Cb[5]  
VPA[6] Cb[6]  
VPA[7] Cb[7]  
VPB[0] Y[0]  
VPB[1] Y[1]  
VPB[2] Y[2]  
VPB[3] Y[3]  
VPB[4] Y[4]  
VPB[5] Y[5]  
VPB[6] Y[6]  
VPB[7] Y[7]  
VPC[0] Cr[0]  
VPC[1] Cr[1]  
VPC[2] Cr[2]  
VPC[3] Cr[3]  
VPC[4] Cr[4]  
VPC[5] Cr[5]  
VPC[6] Cr[6]  
VPC[7] Cr[7]  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
used  
used  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
13 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
VCLK  
HSYNC/HREF  
CONTROL  
VSYNC/VREF  
INPUTS  
DE/FREF  
VPA[7:0]  
Cb [7:0]  
Cb [7:0]  
Cb [7:0]  
Cb [7:0]  
...  
...  
...  
Cb [7:0]  
Cb [7:0]  
xxx  
0
1
2
3
xxx  
VPB[7:0]  
VPC[7:0]  
Y [7:0]  
0
Y [7:0]  
1
Y [7:0]  
2
Y [7:0]  
3
Y
[7:0]  
Y
[7:0]  
xxx  
xxx  
Cr [7:0]  
0
Cr [7:0]  
1
Cr [7:0]  
2
Cr [7:0]  
3
Cr [7:0]  
xxx  
Cr [7:0]  
xxx  
001aai444  
DE could also be generated from HSYNC/HREF and VSYNC/VREF.  
Fig 6. Pixel encoding YCbCr 4 : 4 : 4 external synchronization input (rising edge)  
7.2.3.3 YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising edge)  
YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) mapping  
Table 9.  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A Video port B  
Control  
Pin  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
YCbCr 4 : 2 : 2  
VPA[0] Cb[0]  
VPA[1] Cb[1]  
VPA[2] Cb[2]  
VPA[3] Cb[3]  
Y0[0]  
Cr[0]  
Y1[0]  
VPB[0] Cb[4]  
VPB[1] Cb[5]  
VPB[2] Cb[6]  
VPB[3] Cb[7]  
VPB[4] Cb[8]  
VPB[5] Cb[9]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF used  
VSYNC/VREF used  
Y0[1]  
Cr[1]  
Y1[1]  
Y0[2]  
Cr[2]  
Y1[2]  
DE/FREF  
used  
Y0[3]  
Cr[3]  
Y1[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[6] Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[7] Cb[11] Y0[11] Cr[11] Y1[11]  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
Cb [11:0]  
0
Y [11:0]  
0
Cr [11:0]  
0
Y [11:0]  
1
...  
Cr [11:0]  
xxx  
Y
[1:0]  
xxx  
001aai445  
Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
14 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.4 YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising and falling edge)  
Table 10. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising and falling edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
YCbCr 4 : 2 : 2  
VPA[0] Cb[0] Y0[0]  
VPA[1] Cb[1] Y0[1]  
VPA[2] Cb[2] Y0[2]  
VPA[3] Cb[3] Y0[3]  
Cr[0]  
Y1[0]  
VPB[0] Cb[4] Y0[4]  
VPB[1] Cb[5] Y0[5]  
VPB[2] Cb[6] Y0[6]  
VPB[3] Cb[7] Y0[7]  
VPB[4] Cb[8] Y0[8]  
VPB[5] Cb[9] Y0[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF used  
VSYNC/VREF used  
Cr[1]  
Y1[1]  
Cr[2]  
Y1[2]  
DE/FREF  
used  
Cr[3]  
Y1[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[6] Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[7] Cb[11] Y0[11] Cr[11] Y1[11]  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
Cb [11:0]  
0
Y [11:0]  
0
Cr [11:0]  
0
Y [11:0]  
1
...  
Cr [11:0]  
xxx  
Y
[1:0]  
xxx  
001aai446  
Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising and falling edge)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
15 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.5 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising edge)  
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) mappings  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
YCbCr 4 : 2 : 2  
VPA[0] Cb[0] Y0[0]  
VPA[1] Cb[1] Y0[1]  
VPA[2] Cb[2] Y0[2]  
VPA[3] Cb[3] Y0[3]  
Cr[0]  
Y1[0]  
VPB[0] Cb[4] Y0[4]  
VPB[1] Cb[5] Y0[5]  
VPB[2] Cb[6] Y0[6]  
VPB[3] Cb[7] Y0[7]  
VPB[4] Cb[8] Y0[8]  
VPB[5] Cb[9] Y0[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF not used  
VSYNC/VREF not used  
Cr[1]  
Y1[1]  
Cr[2]  
Y1[2]  
DE/FREF  
not used  
Cr[3]  
Y1[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[6] Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[7] Cb[11] Y0[11] Cr11] Y1[11]  
VCLK  
VPB[7:0]; VPA[3:0]  
Cb [11:0]  
0
Y [11:0]  
0
Cr [11:0]  
0
Y [11:0]  
1
...  
Cr [11:0]  
xxx  
Y
[1:0]  
xxx  
001aai447  
Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
16 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.6 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising and falling edge)  
Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising and falling edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.  
Video port A  
Video port B  
Control  
Pin  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
Pin  
YCbCr 4 : 2 : 2 (ITU656-like)  
YCbCr 4 : 2 : 2  
VPA[0] Cb[0] Y0[0]  
VPA[1] Cb[1] Y0[1]  
VPA[2] Cb[2] Y0[2]  
VPA[3] Cb[3] Y0[3]  
Cr[0]  
Y1[0]  
VPB[0] Cb[4] Y0[4]  
VPB[1] Cb[5] Y0[5]  
VPB[2] Cb[6] Y0[6]  
VPB[3] Cb[7] Y0[7]  
VPB[4] Cb[8] Y0[8]  
VPB[5] Cb[9] Y0[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
HSYNC/HREF not used  
VSYNC/VREF not used  
Cr[1]  
Y1[1]  
Cr[2]  
Y1[2]  
DE/FREF  
not used  
Cr[3]  
Y1[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[6] Cb[10] Y0[10] Cr[10] Y1[10]  
VPB[7] Cb[11] Y0[11] Cr[11] Y1[11]  
VCLK  
VPB[7:0]; VPA[3:0]  
Cb [11:0]  
0
Y [11:0]  
0
Cr [11:0]  
0
Y [11:0]  
1
...  
Cr [11:0]  
xxx  
Y
[1:0]  
xxx  
001aai448  
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising and falling edge)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
17 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.7 YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge)  
Table 13. YCbCr 4 : 2 : 2 semi-planar external synchronization input (rising edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.  
Video port A  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Video port B  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Video port C  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Control  
Pin  
YCbCr 4 : 2 : 2  
VPA[0] Y0[0]  
VPA[1] Y0[1]  
VPA[2] Y0[2]  
VPA[3] Y0[3]  
VPA[4] Cb[0]  
VPA[5] Cb[1]  
VPA[6] Cb[2]  
VPA[7] Cb[3]  
Y1[0]  
Y1[1]  
Y1[2]  
Y1[3]  
Cr[0]  
Cr[1]  
Cr[2]  
Cr[3]  
VPB[0] Y0[4]  
VPB[1] Y0[5]  
VPB[2] Y0[6]  
VPB[3] Y0[7]  
VPB[4] Y0[8]  
VPB[5] Y0[9]  
VPB[6] Y0[10]  
VPB[7] Y0[11]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Y1[10]  
Y1[11]  
VPC[0] Cb[4]  
VPC[1] Cb[5]  
VPC[2] Cb[6]  
VPC[3] Cb[7]  
VPC[4] Cb[8]  
VPC[5] Cb[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
HSYNC/HREF used  
VSYNC/VREF  
DE/FREF  
used  
used  
VPC[6] Cb[10] Cr[10]  
VPC[7] Cb[11] Cr[11]  
VCLK  
HSYNC/HREF  
VSYNC/VREF  
DE/FREF  
CONTROL  
INPUTS  
VPB[7:0]; VPA[3:0]  
VPC[7:0]; VPA[7:4]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
...  
0
1
2
3
4
5
Cb [11:0]  
0
Cr [11:0]  
0
Cb [11:0]  
2
Cr [11:O]  
2
Cb [11:0]  
4
Cr [11:0]  
4
...  
001aai449  
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input synchronization (rising edge)  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
18 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.2.3.8 YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge)  
Table 14. YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) mapping  
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.  
Video port A  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Video port B  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Video port C  
Pin YCbCr 4 : 2 : 2  
semi-planar  
Control  
Pin  
YCbCr 4 : 2 : 2  
VPA[0] Y0[0]  
VPA[1] Y0[1]  
VPA[2] Y0[2]  
VPA[3] Y0[3]  
VPA[4] Cb[0]  
VPA[5] Cb[1]  
VPA[6] Cb[2]  
VPA[7] Cb[3]  
Y1[0]  
Y1[1]  
Y1[2]  
Y1[3]  
Cr[0]  
Cr[1]  
Cr[2]  
Cr[3]  
VPB[0] Y0[4]  
VPB[1] Y0[5]  
VPB[2] Y0[6]  
VPB[3] Y0[7]  
VPB[4] Y0[8]  
VPB[5] Y0[9]  
VPB[6] Y0[10]  
VPB[7] Y0[11]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Y1[10]  
Y1[11]  
VPC[0] Cb[4]  
VPC[1] Cb[5]  
VPC[2] Cb[6]  
VPC[3] Cb[7]  
VPC[4] Cb[8]  
VPC[5] Cb[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
HSYNC/HREF not used  
VSYNC/VREF  
DE/FREF  
not used  
not used  
VPC[6] Cb[10] Cr[10]  
VPC[7] Cb[11] Cr[11]  
VCLK  
VPB[7:0]; VPA[3:0]  
VPC[7:0]; VPA[7:4]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
Y [11:0]  
...  
...  
0
1
2
3
4
5
Cb [11:0]  
0
Cr [11:0]  
0
Cb [11:0]  
2
Cr [11:0]  
2
Cb [11:0]  
4
Cr [11:0]  
4
001aai450  
Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge)  
7.2.4 Synchronization  
The TDA9989 can be synchronized with HSYNC/VSYNC external inputs or with extraction  
of the sync information from embedded sync (SAV/EAV) codes inside the video stream.  
7.2.4.1 Timing extraction generator  
This block can extract the synchronization signals HREF, VREF and FREF from Start  
Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in  
the data stream.  
Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 × 12-bit)  
and YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit).  
7.2.4.2 Data enable generator  
TDA9989 contains a Data Enable (DE) generator; this can generate an internal DE signal  
for a system which does not provide one.  
TDA9989_2  
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Product data sheet  
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19 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.3 Input and output video format  
Due to the flexible video input formatter, the TDA9989 can accept a large range of input  
formats. This flexibility allows the TDA9989 to be compatible with the maximum possible  
number of MPEG decoders. Moreover, these input formats may be changed in many ways  
(color space converter, upsampler, downsampler) before it is transmitted across the HDMI  
link. Table 15 gives the possible inputs and outputs.  
Table 15. Use of color space converter, upsampler and downsampler  
Input  
Output  
Color space  
RGB  
Color space  
RGB  
Format  
Channels  
Format  
4 : 4 : 4  
4 : 4 : 4  
4 : 2 : 2  
4 : 4 : 4  
4 : 4 : 4  
4 : 2 : 2  
4 : 4 : 4  
4 : 4 : 4  
4 : 2 : 2  
4 : 4 : 4  
4 : 4 : 4  
4 : 2 : 2  
Channels  
3 × 8-bit  
3 × 8-bit  
2 × 12-bit  
3 × 8-bit  
3 × 8-bit  
2 × 12-bit  
3 × 8-bit  
3 × 8-bit  
2 × 12-bit  
3 × 8-bit  
3 × 8-bit  
2 × 12-bit  
4 : 4 : 4  
3 × 8-bit  
YCbCr  
YCbCr  
RGB  
YCbCr  
YCbCr  
YCbCr  
4 : 4 : 4  
4 : 2 : 2  
4 : 2 : 2  
3 × 8-bit  
YCbCr  
YCbCr  
up to 1 × 12-bit RGB  
semi-planar  
YCbCr  
YCbCr  
up to 2 × 12-bit RGB  
semi-planar  
YCbCr  
YCbCr  
7.4 Upsampler  
The incoming YCbCr 4 : 2 : 2 (2 × 12-bit) data stream format could be upsampled into  
YCbCr 4 : 4 : 4 (3 × 8-bit) data stream by repeating or linearly interpolating the  
chrominance pixels.  
7.5 Color space converter  
The color space converter is used to convert input video data from one type to another  
color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and  
each coefficient is programmable via the I2C-bus register.  
C11 C12 C13  
C21 C22 C23  
C31 C32 C33  
OinG Y  
OinR Cr  
OinB Cb  
OoutY \G  
OoutCr\R  
OoutCb\B  
Y\G  
Cr\R  
Cb\B  
Y
=
×
+
+
(1)  
R Cr  
B Cb  
7.6 Gamut-related metadata  
Gamut-related metadata is an enhanced colorimetry beyond the default standard with  
higher definition colorimetries. Profile P0 is supported, which means that only one packet  
per video field is sent. Color gamut boundary data are defined the standards:  
xvYCC601 (IEC 61966-2-4 – SD) (using YCbCr)  
xvYCC709 (IEC 61966-2-4 – HD) (using YCbCr)  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
20 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Remark: Gamut-related metadata is an HDMI 1.3a feature.  
7.7 Downsampler  
This block works only with YCbCr input format; the filters downsample the Cb and Cr  
signals by a factor of 2. A delay is added on the Y channel, which corresponds to the  
pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel.  
7.8 Audio input format  
TDA9989 is compatible with the following audio features described in the HDMI 1.3a  
specification:  
S/PDIF  
I2S-bus up to two stereo channels  
The TDA9989 can carry audio in I2S-bus format (one stereo to two stereo channels) or in  
S/PDIF format through one audio pin named AP1. S/PDIF or I2S-bus format can be  
selected via the I2C-bus. Only one audio format can be used at a time: either S/PDIF or  
I2S-bus. Table 16 shows the audio port allocation and Section 7.8.3 gives more details.  
Table 16. Audio port configuration  
Audio port  
Input configuration  
S/PDIF  
I2S-bus  
AP0  
-
WS (word select)  
I2S-bus channel 0  
SCK (I2S-bus clock)  
AP1  
S/PDIF input  
-
ACLK  
All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant. It is possible  
to map an internally unused port to internal ground via I2C-bus with ENA_AP register on  
page 00h for both audio and clock inputs.  
7.8.1 S/PDIF  
In this format TDA9989 supports 2-channel uncompressed PCM data (IEC 60958) layout  
0, or compressed bit stream up to 8 multi channels (Dolby Digital, DTS, AC3 etc.) layout 1.  
The TDA9989 is able to recover the original clock from the S/PDIF signal (no need of  
external clock).  
7.8.2 I2S-bus  
There is one I2S-bus stereo input, which enables 2 uncompressed audio channels to be  
carried. The I2S-bus input interface receives an I2S-bus signal including serial data, word  
select and serial clock.  
Typical waveforms for the I2S-bus signals at 64fs are given by Figure 13.  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
21 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL  
(n1)  
(n1)  
(n)  
(n)  
(n+1)  
(n+1)  
word select  
f
s
MSB  
24-bit audio sample word  
LSB  
0
0
0
audio clock  
64f  
s
001aah029  
a. Philips format.  
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL  
(n1)  
(n1)  
(n)  
(n)  
(n+1)  
(n+1)  
word select  
f
s
MSB  
24-bit audio sample word  
LSB  
0
0
0
audio clock  
64f  
s
001aah030  
b. Left justified format.  
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL  
(n1)  
(n1)  
(n)  
(n)  
(n+1)  
(n+1)  
word select  
f
s
0
0
0
MSB  
24-bit audio sample word  
LSB  
audio clock  
64f  
s
001aah031  
c. Right justified format.  
Fig 13. I2S-bus formats  
The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data  
input with a clock frequency of at least 32 times the input sample frequency fs.  
Audio samples with a precision better than 24-bit are truncated to 24-bit. If the input clock  
has a frequency of 32fs, only 16-bit audio-samples can be received. In this case, the 8  
LSBs will be set to 0. If the input clock has a frequency of 64fs and is left justified or  
Philips, the audio word is truncated to 24-bit format and other bits padded with zeros. If  
the input clock has a frequency of 64fs and is right justified, audio sample must be strictly  
24-bit length.  
The serial data signal carries the serial baseband audio data, sample by sample left/right  
interleaved.  
The word select signal indicates whether left or right channel information is transferred  
over the serial data line.  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
22 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.8.3 Audio port internal assignment  
The aim of the internal audio input assignment is to internally map any of the incoming  
data from the audio port AP1 to I2S-bus channel 0 or S/PDIF internal ports by setting the  
appropriate I2C-bus register.  
TDA9989  
AUDIO  
INTERNAL PORTS  
2
I S-BUS CHANNEL 0  
AP1  
S/PDIF  
2
I C select  
001aai451  
Fig 14. Audio input swap to I2S-bus channel 0 or S/PDIF  
7.9 Power management  
The TDA9989 HDMI and CEC cores can be independently powered down by the I2C-bus  
register. In Standby mode all activities are reduced by switching off all PLLs, HDMI and  
CEC cores and disconnecting the biasing structure of the output stage. The TDA9989 has  
a very low power consumption, which is suitable for portable applications.  
Table 17 gives the typical power consumption of the device in different configurations.  
Table 17. TDA9989 typical power consumption in different configurations  
Typical power Configuration  
Comment  
130 µW  
Standby mode:  
I2C-bus ON  
default configuration: after power-up; PLLs  
HDMI and CEC cores are OFF; can be  
switched ON via I2C-bus register  
500 µW  
Sleep mode without CEC:  
no sink connected; CEC is OFF  
HDMI interruption (HPD,  
RxSense only);  
1.4 mW  
60 mW  
Sleep mode with CEC:  
no sink connected; CEC is ON  
HDMI interruption (HPD,  
RxSense only)  
CEC interruption  
Low power 1080i mode:  
Video format 1080i  
sink connected; CEC is OFF  
Video input  
YCbCr 4 : 2 : 2  
Video output  
YCbCr 4 : 2 : 2  
No CEC  
120 mW  
Full speed mode:  
all blocks enabled and running  
Video format 1080p  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
23 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
7.10 Interrupt controller  
Pin INT_HDMI is used to alert the micro controller that a critical event concerning the  
HDMI or CEC has occurred. The software provided with the device read a status register  
(I2C-bus) to determine which block between HDMI and CEC has caused the interruption  
before processing it. Some of theses interrupts are maskable. The interrupt types are  
described in Table 18.  
Table 18. Interruptions  
Interrupt domain  
HPD  
Interrupt name  
hpd  
Definition  
transition on HPD input maskable  
transition on RxSense maskable  
Maskable feature  
RxSense  
rx_sense  
Interrupt  
sw_intsoftware  
test purpose (output an maskable  
interrupt signal)  
EDID  
CEC  
edid_block_rd  
cec_int  
EDID block read finished maskable  
CEC message received not maskable  
7.10.1 Hot plug/unplug detect  
The hot plug detect (HPD) pin is 5 V input tolerant. The HPD signal, when asserted, tells  
the transmitter that the receiver is connected. When changing from LOW-to-HIGH, the  
TDA9989 has to read the EDID of the receiver in order to select the video format that the  
receiver can handle.  
7.10.2 Receiver sensitivity  
The TDA9989 has the capability to sense the receiver connectivity and working behavior.  
This feature (RxSense) detects the presence of the 50 pull-up resistor RT on the TMDS  
clock channel of the downstream side.  
RECEIVER  
V
CC  
R
pu  
R
pu  
HDMI cable  
V
DD  
1.8 V  
pole τ =  
80 ns  
Vinp_rxs  
35 kΩ  
35 kΩ  
power_down  
RXS_FIL  
Vinn_rxs  
INTERNAL  
BANDGAP  
0.935 V ±4 %  
I_transmit  
TDA9989  
001aai452  
Fig 15. Receiver sensitivity detection  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
24 of 48  
TDA9989  
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HDMI 1.3a transmitter with CEC support  
As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set  
to logic 1.  
As soon as the cable is unplugged or receiver side powered off (assuming in this case that  
VCC is switched off), the RxSense generates an interrupt inside the TDA9989, changing  
the value of bit RXS_FIL to logic 0 (See Table 19). This allows the application to stop  
sending unnecessary video content.  
This feature is very useful when the receiver recovers from an off-state and does not  
generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will  
generate an interrupt so that the chip restarts sending video.  
Table 19. Receiver detection according to averaged terminal voltage  
Average voltage  
(Vinp_rxs + Vinn_rxs) / 2  
bit RXS_FIL: receiver  
powered on  
bit RXS_FIL: receiver  
powered off  
V 975 mV  
1
0
0
0
895 mV < V < 975 mV  
V 895 mV  
undefined  
0
Remark: According to the HDMI specification, only the HPD interrupt allows the  
application to read the EDID. The RxSense interrupt is not mandatory to initialize the  
EDID reading procedure.  
7.11 CEC  
TDA9989 with its embedded CEC block provides a complete solution to enable Consumer  
Electronic Control (CEC) in product (DSC, DVC, PMP, UM PC). This eliminates the need  
of any additional device to handle this feature thus improving BOM (Bill Of Materials).  
CEC capability allows AV products (CEC enable) to communicate together over the home  
appliance network which could be controlled using only one remote control.  
The CEC block manages low level transactions (compliant to CEC timing specification)  
over the one bidirectional line It translates CEC protocol in I2C-bus for the host processor  
and vice versa. It manages CEC message reception and transmission compliant to CEC  
protocol and provides the message to the system micro controller (host processor).  
For power consumption optimization purpose CEC could be enable or disable through  
I2C-bus register.  
The following sections describe CEC  
Features  
Clocking scheme  
7.11.1 Features  
Receive and transmit CEC messages to host processor  
Supports multiple CEC logical addresses  
Supports CEC messages up to 16 bytes long  
Programmable retry count  
Comprehensive arbitration and collision handling  
TDA9989_2  
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Product data sheet  
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25 of 48  
TDA9989  
NXP Semiconductors  
7.11.2 Clock  
HDMI 1.3a transmitter with CEC support  
CEC clock must be running in Sleep mode (with CEC) to wake up the TDA9989 using  
CEC specific message as described in “HDMI 1.3a specification”.  
CEC module can be clocked using:  
External clocks:  
12 MHz crystal.  
12 MHz to 50 MHz clock available on PCB  
Internal clock:  
FRO (Free Running Oscillator). FRO frequency varies per device basic  
(temperature, process, voltage) and is ranges from 12.64 MHz to 12.9 MHz.  
CEC operates normally (i.e. matches the timing requested CEC specification) if and only if  
its clock frequency is 12 MHz.  
So, for clock frequency higher than 12 MHz a calibration is needed. A calibration module  
located between the clock source and the CEC module is used to divide the incoming  
clock to cope the right frequency range see Figure 16.  
TDA9989  
CEC clock calibration module  
(1)  
OSC_IN  
CEC CLK  
12 MHz  
CEC  
MODULE  
DIVIDER  
FRO  
OSC_OUT  
2
I C  
2
I C  
2
INT_HDMI  
I C  
HOST PROCESSOR  
001aai453  
(1) Crystal or other system clock source  
Fig 16. Modules involved in CEC clock calibration process  
Calibration procedure is completely handled by the software delivered together with the  
device, it has the following steps:  
Host processor set the TDA9989 in calibration mode  
Host processor generates a negative pulse of 10 ms ± 1 % on INT_HDMI pin  
Host processor deselects the calibration mode when it is completed, the chip is ready  
to operate.  
CEC clock calibration must be performed at each power-up and each time the TDA9989  
moves from Standby or Sleep (without CEC) state to normal operating mode.  
TDA9989_2  
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Product data sheet  
Rev. 02 — 11 June 2009  
26 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Non successful calibration will lead to CEC signal no matching timings specification as  
consequence CEC not functional.  
7.11.3 CEC interrupt  
Pin INT_HDMI is used by the TDA9989 to warm the host processor HDMI or CEC events  
(CEC message is available to read) have occurred.  
Software reads interrupt status register determine which block between HDMI or CEC has  
raised the interruption before processing it.  
7.11.4 Power-On Reset (POR)  
After power-up, the TDA9989 is activated by hard reset by POR module. This is used to  
set the TDA9989 to a known state.  
7.11.5 Repeater function  
The TDA9989 can be used in a repeater device according to HDMI 1.3a.  
7.12 HDMI core  
7.12.1 Output TMDS buffers  
7.12.1.1 Digitally controlled signal amplitude  
The TMDS signal output peak-to-peak voltage (Vswing) is programmable by the software  
using I2C-bus register vswing_crtl[3:0]. Vswing varies from 370 mV to 640 mV with ±5 %  
accuracy in 18 mV steps according to the following formula:  
Vswing = 370 mV + 18 mV × vswing_ctrl[3:0]  
An external resistor (10 kΩ ± 1 %) must be connected between pin EXT_SWING and  
analog ground.  
7.12.2 Pixel repetition  
To transmit video formats with pixel rates below 25 megasamples per second or to  
increase the number of audio sample packets in each frame, the TDA9989 uses pixel  
repetition to increase the transmitted pixel clock (see Table 20).  
Table 20. Pixel repetition  
PR[3]  
PR[2]  
PR[1]  
PR[0]  
Pixel repetition factor  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no repetition: pixel sent once  
2 times: pixel repeated once  
3 times  
4 times  
5 times  
6 times  
7 times  
8 times  
TDA9989_2  
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Product data sheet  
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27 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 20. Pixel repetition …continued  
PR[3]  
PR[2]  
PR[1]  
PR[0]  
Pixel repetition factor  
9 times  
1
0
0
0
0
0
1
1
10 times  
others  
reserved  
7.12.3 DDC-bus channel  
The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode  
(100 kHz). The DDC-bus is used as a master interface when reading the EDID.  
When the device is power-off DSDA and DSCL ports:  
become in high-impedance  
can withstand 5 V from the sink.  
7.13 E-EDID  
7.13.1 E-EDID reading  
As a master interface for the EDID process, the DDC-bus is compliant with the I2C-bus  
specification and has the possibility of repeat/start condition to enable quick access to the  
EDID content, as well as the possibility of reading a large EDID (with the use of segment  
pointer).  
The TDA9989 has a whole I2C-bus page (page 09h) dedicated to the EDID where one  
block can be stored. The block can be read by the microprocessor to determine the  
supported video and audio format of the downstream site.  
Remark: When the block is read by the TDA9989, it generates an interrupt to warn the  
main processor that the chip is ready to transmit the content. Once the content is read out  
by the main processor, it can allow other blocks to be read if required.  
7.13.2 HDMI and DVI receiver discrimination  
This information is located in the E-EDID receiver part, in the ‘vendor-specific data block’  
within the first CEA EDID timing extension.  
If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will  
support HDMI, otherwise the device will be treated as a DVI device.  
However, even through the TDA9989 have directly access to that information, it is the task  
of the micro controller to ask to switch from DVI to HDMI mode.  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
28 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
8. I2C-bus interface and register definitions  
8.1 I2C-bus protocol  
The I2C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast-mode  
(400 kHz) and Standard-mode (100 kHz) are supported.  
The registers of the TDA9989 can be accessed via the I2C-bus. All registers are R/W  
except for those which are confidential.  
HDMI and CEC cores I2C-bus addresses are given in Table 21 and Table 22.  
Table 21. HDMI core I2C-bus address  
HDMI core address  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
1
1
1
0
0
0
0
0/1  
Table 22. CEC core I2C-bus address  
CEC core address  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
0
1
1
0
1
0
0
0/1  
For read access, the master writes the address of the TDA9989 HDMI or CEC core, and  
the subaddress to access the specific register and then the data.  
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9  
SCL  
SDA  
SLAVE ADDRESS  
SUBADDRESS  
DATA  
STOP  
001aaf292  
Fig 17. I2C-bus access  
8.2 Memory page management  
The I2C-bus memory is split into several pages for HDMI core only, and the selection  
between pages is made with common register CURPAGE_ADR. It is only necessary to  
write in this register once to change the current page. So multiple read or write operations  
in the same page need a write register CURPAGE_ADR once at the beginning.  
The following memory pages are available for the TDA9989:  
Page 00h: general control  
Page 02h: PLL settings  
Page 09h: EDID control page  
Page 10h: information frames and packets  
Page 11h: audio settings and content info packets  
Page 13h: gamut-related metadata packets  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
29 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
The CEC core does not need memory page mechanism due to its reduced number of  
registers.  
8.3 ID version  
The ID version readable via I2C-bus is defined by the concatenation of VERSION_MSB  
and VERSION registers.The ID version value is 131h.  
8.4 Clock stretching  
Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction  
cannot continue until the line is released HIGH again.  
For example: on the byte level, a device may be able to receive bytes of data at a fast rate,  
but needs more time to store a received byte or prepare another byte to be transmitted.  
Slaves can then hold the CSCL line LOW after reception and acknowledgment of a byte to  
force the master into a wait state until the slave is ready for the next byte transfer.see  
Table 31  
Clock stretching must be supported by I2C-bus master especially when CEC feature of  
TDA9989 is used. If CEC feature of TDA9989 is not used, I2C-bus master does not need  
to support clock stretching.  
9. Input format  
In Table 23 the port VPA has been mapped to Cb (YCbCr space)/B (RGB space), VPB  
has been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr  
(YCbCr space)/R (RGB space).  
Table 23. Input format  
L: recommend tied to LOW voltage  
Input pins Signal  
RGB  
YCbCr  
4 : 4 : 4  
4 : 4 : 4  
4 : 2 : 2 (semi-planar)  
4 : 2 : 2 (ITU 656-like)  
Video port A  
VPA[0]  
VPA[1]  
VPA[2]  
VPA[3]  
VPA[4]  
VPA[5]  
VPA[6]  
VPA[7]  
Video port B  
VPB[0]  
VPB[1]  
VPB[2]  
VPB[3]  
VPB[4]  
VPB[5]  
Cb[0]/B[0]  
B[0]  
B[1]  
B[2]  
B[3]  
B[4]  
B[5]  
B[6]  
B[7]  
Cb[0]  
Cb[1]  
Cb[2]  
Cb[3]  
Cb[4]  
Cb[5]  
Cb[6]  
Cb[7]  
Y0[0]  
Y0[1]  
Y0[2]  
Y0[3]  
Cb[0]  
Cb[1]  
Cb[2]  
Cb[3]  
Y1[0]  
Y1[1]  
Y1[2]  
Y1[3]  
Cr[0]  
Cr[1]  
Cr[2]  
Cr[3]  
Cb[0]  
Cb[1]  
Cb[2]  
Cb[3]  
L
Y0[0]  
Y0[1]  
Y0[2]  
Y0[3]  
L
Cr[0]  
Cr[1]  
Cr[2]  
Cr[3]  
L
Y1[0]  
Y1[1]  
Y1[2]  
Y1[3]  
L
Cb[1]/B[1]  
Cb[2]/B[2]  
Cb[3]/B[3]  
Cb[4]/B[4]  
Cb[5]/B[5]  
Cb[6]/B[6]  
Cb[7]/B[7]  
L
L
L
L
L
L
L
L
L
L
L
L
Y[0]/G[0]  
Y[1]/G[1]  
Y[2]/G[2]  
Y[3]/G[3]  
Y[4]/G[4]  
Y[5]/G[5]  
G[0]  
G[1]  
G[2]  
G[3]  
G[4]  
G[5]  
Y[0]  
Y[1]  
Y[2]  
Y[3]  
Y[4]  
Y[5]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
Cb[4]  
Cb[5]  
Cb[6]  
Cb[7]  
Cb[8]  
Cb[9]  
Y0[4]  
Y0[5]  
Y0[6]  
Y0[7]  
Y0[8]  
Y0[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
Y1[4]  
Y1[5]  
Y1[6]  
Y1[7]  
Y1[8]  
Y1[9]  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
30 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 23. Input format …continued  
L: recommend tied to LOW voltage  
Input pins Signal  
RGB  
4 : 4 : 4  
G[6]  
YCbCr  
4 : 4 : 4  
Y[6]  
4 : 2 : 2 (semi-planar)  
4 : 2 : 2 (ITU 656-like)  
VPB[6]  
VPB[7]  
Video port C  
VPC[0]  
VPC[1]  
VPC[2]  
VPC[3]  
VPC[4]  
VPC[5]  
VPC[6]  
VPC[7]  
Y[6]/G[6]  
Y[7]/G[7]  
Y0[10]  
Y0[11]  
Y1[10]  
Y1[11]  
Cb[10]  
Cb[11]  
Y0[10]  
Y0[11]  
Cr[10] Y1[10]  
Cr[11] Y1[11]  
G[7]  
Y[7]  
Cr[0]/R[0]  
Cr[1]/R[1]  
Cr[2]/R[2]  
Cr[3]/R[3]  
Cr[4]/R[4]  
Cr[5]/R[5]  
Cr[6]/R[6]  
Cr[7]/R[7]  
R[0]  
R[1]  
R[2]  
R[3]  
R[4]  
R[5]  
R[6]  
R[7]  
Cr[0]  
Cr[1]  
Cr[2]  
Cr[3]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cb[4]  
Cb[5]  
Cb[6]  
Cb[7]  
Cb[8]  
Cb[9]  
Cr[4]  
Cr[5]  
Cr[6]  
Cr[7]  
Cr[8]  
Cr[9]  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Cb[10] Cr[10]  
Cb[11] Cr[11]  
9.1 Timing parameters for video supported  
The TDA9989 supports all EIA/CEA-861B standards and ATSC video input formats.  
Table 24. Timing parameters for EIA/CEA-861B  
EIA/CEA-861B  
Video code  
Format  
V frequency H total  
(Hz)  
V total  
H frequency Pixel  
Pixel  
repetition  
(kHz)  
frequency  
(MHz)  
59.94 Hz systems  
1 (VGA)  
640 × 480p  
720 × 480p  
1280 × 720p  
1920 × 1080i  
1440 × 480i  
1440 × 240p  
1440 × 240p  
2880 × 480i  
2880 × 240p  
2880 × 240p  
1440 × 480p  
1920 × 1080p  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
59.9401  
60.000  
800  
525  
525  
750  
1125  
525  
262  
263  
525  
262  
263  
525  
1125  
31.469  
31.469  
44.955  
33.716  
15.734  
15.734  
15.734  
15.734  
15.734  
15.734  
31.469  
67.432  
25.175  
27.000  
74.175  
74.175  
27.000  
27.000  
27.000  
54.000  
54.000  
54.000  
54.000  
148.350  
1
2, 3  
858  
1
4
1650  
2200  
1716  
1716  
1716  
3452  
3452  
3452  
1716  
2200  
1
5
1
6, 7 (NTSC)  
2
8, 9  
2
8, 9  
2
10, 11  
4[1]  
4[1]  
4[1]  
2
12, 13  
12, 13  
14, 15  
16  
1
60 Hz systems  
1 (VGA)  
640 × 480p  
720 × 480p  
1280 × 720p  
1920 × 1080i  
1440 × 480i  
1440 × 240p  
1440 × 240p  
60.000  
60.000  
60.000  
60.000  
60.000  
60.000  
60.000  
800  
525  
525  
750  
1125  
525  
262  
263  
31.500  
31.500  
45.000  
33.750  
15.750  
15.750  
15.750  
25.200  
27.027  
74.250  
74.250  
27.027  
27.027  
27.027  
1
1
1
1
2
2
2
2, 3  
858  
4
1650  
2200  
1716  
1716  
1716  
5
6, 7 (NTSC)  
8, 9  
8, 9  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
31 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 24. Timing parameters for EIA/CEA-861B …continued  
EIA/CEA-861B  
Video code  
Format  
V frequency H total  
(Hz)  
V total  
H frequency Pixel  
Pixel  
repetition  
(kHz)  
frequency  
(MHz)  
10, 11  
2880 × 480i  
2880 × 240p  
2880 × 240p  
1440 × 480p  
1920 × 1080p  
60.000  
60.000  
60.000  
60.000  
60.000  
3452  
3452  
3452  
1716  
2200  
525  
262  
263  
525  
1125  
15.750  
15.750  
15.750  
31.500  
67.500  
54.054  
54.054  
54.054  
54.054  
148.50  
4[1]  
4[1]  
4[1]  
2
12, 13  
12, 13  
14, 15  
16  
1
50 Hz systems  
17, 18  
720 × 576p  
1280 × 720p  
1920 × 1080i  
1440 × 576i  
1440 × 288p  
1440 × 288p  
1440 × 288p  
2880 × 576i  
2880 × 288p  
2880 × 288p  
720 × 288p  
1440 × 576p  
1920 × 1080p  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
50.000  
864  
625  
750  
1125  
625  
312  
313  
314  
625  
312  
313  
314  
625  
1125  
31.250  
37.500  
28.125  
15.625  
15.625  
15.625  
15.625  
15.625  
15.625  
15.625  
15.625  
31.250  
56.250  
27.000  
74.250  
74.250  
27.000  
27.000  
27.000  
27.000  
54.000  
54.000  
54.000  
54.000  
54.000  
148.50  
1
19  
1980  
2640  
1728  
1728  
1728  
1728  
3456  
3456  
3456  
3456  
1728  
2640  
1
20  
1
21, 22 (PAL)  
2
23, 24  
2
23, 24  
2
23, 24  
2
25, 26  
4[1]  
4[1]  
4[1]  
4
27, 28  
27, 28  
27, 28  
29, 30  
2
31  
1
Various systems  
32  
32  
33  
34  
34  
1920 × 1080p  
1920 × 1080p  
1920 × 1080p  
1920 × 1080p  
1920 × 1080p  
23.976  
24  
2750  
2750  
2640  
2200  
2200  
1125  
1125  
1125  
1125  
1125  
26.973  
27  
74.175824  
74.25  
1
1
1
1
1
25  
28.125  
33.716  
33.75  
74.25  
29.97  
30  
74.175824  
74.25  
[1] Format can also be defined with a repetition factor of up to 10.  
Table 25. Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B  
Standard  
Format  
V frequency H total  
(Hz)  
V total  
H frequency Pixel  
Pixel  
repetition  
(kHz)  
frequency  
(MHz)  
74.250  
74.175  
74.250  
74.175  
SMPTE-296M  
SMPTE-296M  
SMPTE-296M  
SMPTE-296M  
1280 × 720p  
1280 × 720p  
1280 × 720p  
1280 × 720p  
30.000  
29.970  
25.000  
23.976  
3300  
3300  
3960  
4125  
750  
750  
750  
750  
22.500  
22.478  
18.750  
17.982  
1
1
1
1
9.2 Timing parameters for PC standards supported  
TDA9989 can support all major PC Standards below 150 MHz.  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
32 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 26. Timing parameters for PC standards below 150 MHz  
Standard  
Format  
V frequency  
(Hz)  
H total  
V total  
H frequency  
(kHz)  
Pixel frequency Pixel  
(MHz)  
repetition  
640 × 350p  
640 × 400p  
720 × 400p  
640 × 480p  
640 × 480p  
640 × 480p  
640 × 480p  
800 × 600p  
800 × 600p  
800 × 600p  
800 × 600p  
800 × 600p  
800 × 600p  
848 × 480p  
1024 × 768p  
1024 × 768p  
1024 × 768p  
1024 × 768p  
1024 × 768i  
1024 × 768p  
85.080  
85.080  
85.039  
59.940  
72.809  
75.000  
85.008  
56.250  
60.317  
72.188  
75.000  
85.061  
119.972  
60.000  
60.004  
70.069  
75.029  
84.997  
86.957  
119.989  
832  
445  
445  
446  
525  
520  
500  
509  
625  
628  
666  
625  
631  
636  
517  
806  
806  
800  
808  
817  
813  
37.861  
37.861  
37.927  
31.469  
37.861  
37.500  
43.269  
35.156  
37.879  
48.077  
46.875  
53.674  
76.302  
31.020  
48.363  
56.476  
60.023  
68.677  
35.522  
97.551  
31.500  
31.500  
35.500  
25.175  
31.500  
31.500  
36.000  
36.000  
40.000  
50.000  
49.500  
56.250  
73.250  
33.750  
65.000  
75.000  
78.750  
94.500  
44.900  
115.500  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
832  
936  
0.31M3  
VGA  
800  
832  
840  
832  
0.48M3  
SVGA  
1024  
1056  
1040  
1056  
1048  
960  
0.48M3-R  
0.41M9  
1088  
1344  
1328  
1312  
1376  
1264  
1184  
0.79M3  
XGA  
0.79M3-R  
XGA  
1.00M3  
1152 × 864p  
1280 × 768p  
1280 × 768p  
1280 × 768p  
1280 × 768p  
1280 × 768p  
1280 × 800p  
1280 × 800p  
1280 × 800p  
1280 × 800p  
1280 × 800p  
1280 × 960p  
1280 × 960p  
1280 × 1024p  
1280 × 1024p  
1360 × 768p  
1360 × 768p  
1400 × 1050p  
1400 × 1050p  
75.000  
59.995  
119.798  
59.870  
74.893  
84.837  
59.910  
119.909  
59.810  
74.934  
84.880  
60.000  
85.002  
60.020  
75.025  
60.015  
119.967  
59.948  
59.978  
1600  
1440  
1440  
1664  
1696  
1712  
1440  
1440  
1680  
1696  
1712  
1800  
1728  
1688  
1688  
1792  
1520  
1560  
1864  
900  
67.500  
47.396  
97.396  
47.776  
60.289  
68.633  
49.306  
101.563  
49.702  
62.795  
71.554  
60.000  
85.938  
63.981  
79.976  
47.712  
97.533  
64.744  
65.317  
108.000  
68.250  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.98M9-R  
790  
813  
140.250  
79.500  
0.98M9  
798  
805  
102.250  
117.500  
71.000  
809  
1.02MA-R  
1.02MA  
823  
847  
146.250  
83.500  
831  
838  
106.500  
122.500  
108.000  
148.500  
108.000  
135.000  
85.500  
843  
1.23M3  
1000  
1011  
1066  
1066  
795  
1.31M4  
SXGA  
1.04M9  
1.04M9-R  
1.47M3-R  
1.47M3  
813  
148.250  
101.000  
121.750  
1080  
1089  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
33 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 26. Timing parameters for PC standards below 150 MHz …continued  
Standard  
Format  
V frequency  
(Hz)  
H total  
V total  
H frequency  
(kHz)  
Pixel frequency Pixel  
(MHz)  
repetition  
1.29MA-R  
1.29MA  
1440 × 900p  
1440 × 900p  
1440 × 900p  
1680 × 1050p  
1680 × 1050p  
59.901  
59.887  
74.984  
59.883  
59.954  
1600  
1904  
1936  
1840  
2240  
926  
55.469  
55.935  
70.635  
64.674  
65.290  
88.750  
-
-
-
-
-
934  
106.500  
136.750  
119.000  
146.250  
942  
1.76MA-R  
1.76MA  
1080  
1089  
10. Limiting values  
Table 27. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
V
VDDA(TMDS)(1V8) TMDS analog supply voltage (1.8 V)  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
2  
+3.8  
+3.8  
+3.8  
+3.8  
+3.8  
+3.8  
+2  
VDDA(PLL)(1V8)  
VDDA(1V8)  
VDDD(IO)(1V8)  
VDD(OSC)(CEC)  
VDDDC  
PLL analog supply voltage (1.8 V)  
analog supply voltage (1.8 V)  
I/O digital supply voltage (1.8V)  
CEC oscillator supply voltage  
core digital supply voltage  
V
V
V
V
[1]  
V
VDD  
supply voltage difference  
V
Vesd  
electrostatic discharge voltage  
HBM  
-
±2500  
V
[1] see Table 6  
11. Thermal characteristics  
Table 28. Thermal characteristics  
Symbol  
Parameter  
Conditions  
Min Typ  
Max  
Unit  
Rth(j-a)  
thermal resistance from junction to ambient  
in free air; Jedec  
4L board  
-
58.6  
-
K/W  
Rth(j-c)  
Tstg  
thermal resistance from junction to case  
storage temperature  
-
18  
-
-
K/W  
°C  
-
+150  
+85  
+125  
Tamb  
Tj  
ambient temperature  
20  
-
°C  
junction temperature  
-
-
°C  
12. Static characteristics  
Table 29. Supplies  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
VDDD(1V8)  
VDDDC  
Parameter  
Conditions  
Min  
1.7  
1.1  
1.7  
1.7  
Typ  
1.8  
1.2  
1.8  
1.8  
Max  
1.9  
1.3  
1.9  
1.9  
Unit  
digital supply voltage (1.8 V)  
core digital supply voltage  
V
V
V
V
[1]  
[1]  
VCLK 74.25 MHz  
VCLK > 74.25 MHz  
VDDA(TMDS)(1V8) TMDS analog supply voltage (1.8 V)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
34 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 29. Supplies …continued  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
1.7  
1.7  
1.7  
30  
7
Typ  
1.8  
1.8  
1.8  
45  
8
Max  
1.9  
1.9  
1.9  
60  
9
Unit  
V
VDDA(PLL)(1V8)  
VDDA(1V8)  
VDD(OSC)(CEC)  
IDDD(1V8)  
PLL analog supply voltage (1.8 V)  
analog supply voltage (1.8 V)  
CEC oscillator supply voltage  
digital supply current (1.8 V)  
TMDS analog supply current (1.8V)  
PLL analog supply current (1.8 V)  
analog supply current (1.8 V)  
CEC oscillator supply current  
PLL analog and serializer  
V
V
[2]  
[2]  
[2]  
[2]  
[2]  
µA  
mA  
mA  
mA  
mA  
IDDA(TMDS)(1V8)  
IDDA(PLL)(1V8)  
IDDA(1V8)  
7
8
9
8
9
10  
0.3  
IDD(OSC)(CEC)  
0.1  
0.2  
Supplies 1.2 V (VDDDC) and 1.8 V  
IDDDC(1V2) core digital supply current (1.2 V)  
Pcons  
[3]  
[3]  
10  
-
15  
20  
mA  
mW  
mW  
µW  
µW  
mW  
power consumption  
55  
65  
Sleep mode with CEC  
Sleep mode without CEC  
Standby mode  
-
1.5  
500  
130  
190  
3
-
600  
200  
215  
-
[5]  
Ptot  
total power dissipation  
-
All supplies 1.8 V  
IDDDC(1V8) core digital supply current (1.8 V)  
[2]  
[3]  
[2]  
[3]  
35  
20  
-
40  
45  
mA  
25  
30  
mA  
Pcons  
power consumption  
120  
75  
140  
90  
mW  
mW  
mW  
µW  
µW  
mW  
mW  
-
Sleep mode with CEC  
Sleep mode without CEC  
Standby mode  
-
2.7  
700  
135  
255  
210  
4
-
950  
260  
290  
240  
-
[4]  
[5]  
Ptot  
total power dissipation  
-
-
[1] see Table 6  
[2] Input format: 1080p, any color space; output format: 1080p any color space.  
[3] Input format: 1080i YCbCr 4 : 2 : 2; output format: YCbCr 4 : 2 : 2; CEC feature disable.  
[4] Same as Table note [2] with TMDS output current added.  
[5] Same as Table note [3] with TMDS output current added.  
Table 30. Digital inputs and outputs  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Not 5 V tolerant CMOS 1.8 V and CMOS 3.3 V tolerant digital input pins HSYNC, VSYNC, AP[1:0], ACLK, VPA[7:0],  
VPB[7:0], VPC[7:0], VCLK, DE  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input capacitance  
-
-
0
-
0.75  
-
V
1.4  
1  
1  
-
-
V
-
+1  
+1  
-
µA  
µA  
pF  
IIH  
-
Ci  
4.5  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
35 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 30. Digital inputs and outputs …continued  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
5 V tolerant input pin HPD  
VIL  
VIH  
Ci  
LOW-level input voltage  
-
-
0
2
-
-
0.8  
V
HIGH-level input voltage  
input capacitance  
-
-
-
V
4.5  
pF  
CMOS 1.8 V and CMOS 3.3 V tolerant digital input/output pin INT_HDMI  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
-
-
0
-
-
-
0.85  
-
V
V
V
VIH  
1.4  
0
VOL  
LOW-level output voltage CL = 10 pF; IOL = 2 mA  
0.4  
5 V tolerant master bus: DDC-bus pins DSDA, DSCL[1]  
VOL  
VIL  
LOW-level output voltage  
LOW-level input voltage  
HIGH-level input voltage  
0
-
-
-
0.4  
0.6  
5.5  
V
V
V
0
VIH  
1.4  
1.8 V to 3.3 V tolerant slave bus: I2C-bus input/output pins CSCL, CSDA[1]  
VOL  
VIL  
LOW-level output voltage  
LOW-level input voltage  
HIGH-level input voltage  
0
-
-
-
0.4  
0.6  
5.5  
V
V
V
0
VIH  
1.4  
CEC input/output[2] pin  
VOL  
VOH  
VIL  
LOW-level output voltage  
0
-
0.4  
3.6  
0.60  
3.6  
-
V
V
V
V
V
HIGH-level output voltage  
LOW-level input voltage  
HIGH-level input voltage  
input hysteresis voltage  
2.5  
0
-
-
VIH  
2.5  
-
-
[2]  
Vhys(i)  
0.27  
TMDS output pins: TX0, TX0+, TX1, TX1+, TX2, TX2+, TXCand TXC+  
VO(dif) differential output voltage REXT_SWING = 10 kΩ ± 1 %  
VO(cm)  
400  
-
514  
600  
-
mV  
V
common-mode output  
voltage  
REXT_SWING = 10 kΩ ± 1 %  
3.05  
[1] See Section 7.1 and refer to the I2C-bus specification version 2.1 (document order number 9398 393 40011).  
[2] For information, input hysteresis is normally supplied by the microprocessor input circuit: in this circumstance, external hysteresis  
circuitry is not needed.  
13. Dynamic characteristics  
Table 31. Timing characteristics  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Clock input: pin VCLK  
fclk(max)  
tsu(D)  
th(D)  
maximum clock frequency  
-
-
-
150  
-
MHz  
ns  
data input set-up time  
data input hold time  
clock duty cycle  
see Figure 18 and 19  
see Figure 18 and 19  
positive edge  
1.5  
1
-
-
-
ns  
[1]  
δclk  
30  
-
50  
12  
70  
50  
%
fclk  
clock frequency  
CEC  
MHz  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
36 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 31. Timing characteristics …continued  
Tamb = 20 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus[2]  
fSCL  
Ci  
SCL frequency  
Standard-mode  
-
-
-
100  
-
kHz  
pF  
capacitance for each I/O pin  
7
I2C-bus: pins CSCL, CSDA (5 V tolerant) slave bus[2]  
fSCL  
SCL frequency  
Standard-mode  
Fast-mode  
CEC  
-
-
-
-
100  
400  
-
kHz  
kHz  
µs  
-
tstretch  
stretch time  
80  
CEC input/output[3]  
tr  
tf  
rise time  
fall time  
10 % to 90 %  
10 % to 90 %  
-
-
-
-
50  
2
µs  
µs  
TMDS output pins: TXCand TXC+  
fclk(max) maximum clock frequency  
on the TMDS link  
-
-
-
-
150  
MHz  
GHz  
TMDS output pins: TX0, TX0+, TX1, TX1+, TX2and TX2+  
fclk(max) maximum clock frequency  
1.50  
[1] δclk = tclk(H) / (tclk(H) + tclk(L)).  
[2] See Section 7.1 and refer to the I2C-bus specification version 2.1 (document order number 9398 393 40011).  
[3] For details about CEC electrical specification, see HDMI 1.3a specification.  
EDGE = 0  
VCLK  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
DE, HSYNC, VSYNC  
t
t
h(D)  
su(D)  
EDGE = 1  
VCLK  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
DE, HSYNC, VSYNC  
t
t
h(D)  
su(D)  
data is not allowed to change in this period  
data can change to meet the minimum set-up and hold time requirement  
001aah035  
Fig 18. Set-up and hold time definition diagram for single-edge clock mode  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
37 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
VCLK  
VPA[7:0]  
VPB[7:0]  
VPC[7:0]  
DE, HSYNC, VSYNC  
t
t
t
t
h(D)  
su(D)  
h(D)  
su(D)  
data is not allowed to change in this period  
data can change to meet the minimum set-up and hold time requirement  
001aah036  
Fig 19. Set-up and hold time definition diagram for double-edge clock mode  
14. Application information  
14.1 Transmitter connection with external world  
Figure 20, Figure 21 and Figure 22 refer to a simple receiver application. However, the  
TDA9989 can be part of a repeater application as described in “HDMI 1.3a specification”.  
TRANSMITTER SIDE  
DOWNSTREAM SIDE  
2
I C-bus  
video 24-bit  
sync  
MASTER  
TMDS channel 0  
TMDS channel 1  
TMDS channel 2  
2
I C-BUS  
MAIN  
PROCESSOR  
SLAVE  
audio  
HDMI  
TDA9989  
TMDS clock  
HPD  
RECEIVER/  
REPEATER  
OSC_IN  
DDC  
CEC  
OSCILLATOR  
DDC channel  
CEC  
slave  
MASTER  
OSC_OUT  
001aai454  
Fig 20. Connecting TDA9989 transmitter using external oscillator for CEC  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
38 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
TRANSMITTER SIDE  
DOWNSTREAM SIDE  
2
I C-bus  
video 24-bit  
sync  
MASTER  
MAIN  
TMDS channel 0  
TMDS channel 1  
2
I C-BUS  
SLAVE  
audio  
PROCESSOR  
TMDS channel 2  
HDMI  
RECEIVER/  
REPEATER  
HPD  
TDA9989  
TMDS clock  
OSC_IN  
OSC_OUT  
EXTERNAL  
CLOCK  
DDC  
MASTER  
DDC channel  
CEC  
SLAVE  
001aaj022  
Fig 21. Connecting TDA9989 transmitter using external clock source  
TRANSMITTER SIDE  
DOWNSTREAM SIDE  
2
I C-bus  
video 24-bit  
sync  
MASTER  
MAIN  
TMDS channel 0  
TMDS channel 1  
TMDS channel 2  
2
I C-BUS  
SLAVE  
audio  
PROCESSOR  
HDMI  
RECEIVER/  
REPEATER  
TDA9989  
TMDS clock  
HPD  
OSC_IN  
DDC  
MASTER  
DDC channel  
CEC  
SLAVE  
OSC_OUT  
001aai614  
Fig 22. Connecting TDA9989 transmitter using internal FRO for CEC  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
39 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
15. Package outline  
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls  
SOT962-3  
D
B
A
ball A1  
index area  
A
2
E
A
A
1
detail X  
e
1
1/2 e  
C
M
M
v
C A  
C
B
e
b
y
y
w
C
1
H
e
G
F
E
D
C
B
A
e
2
1/2 e  
ball A1  
index area  
1
2
3
4
5
6
7
8
X
0
2.5  
scale  
5 mm  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max 1.10 0.30 0.80 0.35  
nom 0.95 0.25 0.70 0.30  
4.6  
4.5  
4.4  
4.6  
4.5  
4.4  
mm  
0.5  
3.5  
3.5  
0.15 0.05 0.08  
0.1  
min  
0.85 0.20 0.65 0.25  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
JEITA  
08-05-26  
08-06-18  
SOT962-3  
- - -  
- - -  
- - -  
Fig 23. Package outline SOT962-3 (TFBGA64)  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
40 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
16. Abbreviations  
Table 32. Abbreviations  
Acronym  
AC3  
Description  
Active Coding-3  
ACP  
Audio Content Protection  
Audio Clock Recovery  
ACR  
ATSC  
AV  
Advanced Television Systems Committee  
Audio Video  
BOM  
CEA  
Bill Of Materials  
Consumer Electronics Association  
Consumer Electronics Control  
Clock Time Stamp integer divider  
Display Data Channel  
CEC  
CTS/N  
DDC  
DDR  
DE  
Double Data Rate  
Data Enable  
DSC  
DTS  
Digital Still Camera  
Digital Transmission System  
Desk Top Video  
DTV  
DVC  
Digital Video Camera  
DVD  
Digital Versatile Disc  
DVI  
Digital Visual Interface  
EAV  
End Active Video  
EDID  
E-EDID  
EIA  
Extended Display Identification Data  
Enhanced Extended Display Identification Data  
Electronic Industries Alliance  
First In, First Out  
FIFO  
FREF  
FRO  
Field REFerence  
Free Running Oscillator  
Human Body Model  
HBM  
HDCP  
HDMI  
HPD  
HREF  
HSYNC  
LSB  
High-bandwidth Digital Content Protection  
High-Definition Multimedia Interface  
Hot Plug Detection  
Horizontal REFerence  
Horizontal SYNChronization  
Least Significant Bit  
LV-CMOS  
MPEG  
MSB  
PC  
Low Voltage Complementary Metal-Oxide Semiconductor  
Moving Picture Experts Group  
Most Significant Bit  
Personal Computer  
PCB  
Printed Circuit Board  
PCM  
PLL  
Pulse Code Modulation  
Phase-Locked Loop  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
41 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Table 32. Abbreviations …continued  
Acronym  
Description  
PMP  
Portable Multimedia Player  
Power-On Reset  
POR  
RGB  
R = red, G = green, B = blue  
Start Active Video  
SAV  
SDR  
Single Data Rate  
SMPTE  
S/PDIF  
STB  
Society of Motion Picture and Television Engineers  
Sony / Philips Digital Interface  
Set-Top Box  
TMDS  
UM PC  
UXGA60  
VHREF  
VREF  
VSYNC  
YCbCr  
WS  
Transition Minimized Differential Signalling  
Ultra Mobile Personal Computer  
Ultra Extended Graphics Array  
Vertical Horizontal REFerence  
Vertical REFerence  
Vertical SYNChronization  
Y = luminance, Cb = Chroma component blue, Cr = Chroma component red  
Word Select  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
42 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
17. Revision history  
Table 33. Revision history  
Document ID  
TDA9989_2  
Release date  
20090611  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
TDA9989_1  
Modifications:  
Table 29, Table 30 and Table 31: updated  
Table 28, Table 29, Table 30 and Table 31: changed the temperature min 0 °C to 20 °C  
Table 28, Table 29, Table 30 and Table 31: changed the temperature max 70 °C to +85 °C  
Clock frequency maximum: changed 165 MHz to 150 MHz  
TDA9989_1  
20090225  
Preliminary data sheet  
-
-
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
43 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
18. Legal information  
19. Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Applications — Applications that are described herein for any of these  
19.1 Definitions  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
19.2 Disclaimers  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
19.3 Licenses  
Purchase of NXP ICs with HDMI technology  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Use of an NXP IC with HDMI technology in equipment that complies with  
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.  
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:  
admin@hdmi.org.  
19.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
44 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
Notes  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
45 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
21. Tables  
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3  
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Table 3. Internal assignment . . . . . . . . . . . . . . . . . . . . . .8  
Table 4. Video input swap to VP[23:20] . . . . . . . . . . . . . .9  
Table 5. TDA9989 input/output capability . . . . . . . . . . .10  
Table 6. Inputs of video input formatter . . . . . . . . . . . . .12  
Table 7. RGB (3 ¥ 8-bit) external synchronization  
input (rising edge) mapping . . . . . . . . . . . . . . .13  
Table 8. YCbCr 4 : 4 : 4 (3 ¥ 8-bit) external  
synchronization input (rising edge) mapping . .13  
Table 9. YCbCr 4 : 2 : 2 ITU656-like external  
synchronization input (rising edge) mapping . .14  
Table 10. YCbCr 4 : 2 : 2 ITU656-like external  
synchronization input (rising and falling edge)  
mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded  
synchronization input (rising edge) mappings .16  
Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded  
synchronization input  
(rising and falling edge) mapping . . . . . . . . . . .17  
Table 13. YCbCr 4 : 2 : 2 semi-planar external  
synchronization input (rising edge) mapping . .18  
Table 14. YCbCr 4 : 2 : 2 semi-planar embedded  
synchronization input (rising edge) mapping . .19  
Table 15. Use of color space converter, upsampler  
and downsampler . . . . . . . . . . . . . . . . . . . . . .20  
Table 16. Audio port configuration . . . . . . . . . . . . . . . . . .21  
Table 17. TDA9989 typical power consumption in  
different configurations . . . . . . . . . . . . . . . . . .23  
Table 18. Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
Table 19. Receiver detection according to averaged  
terminal voltage . . . . . . . . . . . . . . . . . . . . . . . .25  
Table 20. Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . .27  
Table 21. HDMI core I2C-bus address . . . . . . . . . . . . . . .29  
Table 22. CEC core I2C-bus address . . . . . . . . . . . . . . .29  
Table 23. Input format . . . . . . . . . . . . . . . . . . . . . . . . . . .30  
Table 24. Timing parameters for EIA/CEA-861B . . . . . . .31  
Table 25. Timing parameters for ATSC DTV standards,  
which are not defined in EIA/CEA-861B . . . . .32  
Table 26. Timing parameters for PC standards below  
150 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Table 27. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34  
Table 28. Thermal characteristics . . . . . . . . . . . . . . . . . .34  
Table 29. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
Table 30. Digital inputs and outputs . . . . . . . . . . . . . . . .35  
Table 31. Timing characteristics . . . . . . . . . . . . . . . . . . .36  
Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .41  
Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . .43  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
46 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
22. Figures  
Fig 1. TDA9989 high-level block diagram. . . . . . . . . . . . .2  
Fig 2. TDA9989 Block diagram . . . . . . . . . . . . . . . . . . . .4  
Fig 3. Pin configuration (TFBGA64). . . . . . . . . . . . . . . . .5  
Fig 4. Internal assignment of VP[23:0]. . . . . . . . . . . . . . .8  
Fig 5. Pixel encoding RGB 4 : 4 : 4 external  
synchronization input (rising edge) . . . . . . . . . . .13  
Fig 6. Pixel encoding YCbCr 4 : 4 : 4 external  
synchronization input (rising edge) . . . . . . . . . . .14  
Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like  
external synchronization input (rising edge) . . . .14  
Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like  
external synchronization input (rising and  
falling edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like  
embedded synchronization input (rising edge) . .16  
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like  
embedded synchronization input (rising and  
falling edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar  
external input synchronization (rising edge) . . . .18  
Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar  
embedded synchronization input (rising edge) . .19  
Fig 13. I2S-bus formats . . . . . . . . . . . . . . . . . . . . . . . . . .22  
Fig 14. Audio input swap to I2S-bus channel 0 or  
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
Fig 15. Receiver sensitivity detection. . . . . . . . . . . . . . . .24  
Fig 16. Modules involved in CEC clock calibration  
process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
Fig 17. I2C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .29  
Fig 18. Set-up and hold time definition diagram for  
single-edge clock mode . . . . . . . . . . . . . . . . . . . .37  
Fig 19. Set-up and hold time definition diagram for  
double-edge clock mode . . . . . . . . . . . . . . . . . . .38  
Fig 20. Connecting TDA9989 transmitter using  
external oscillator for CEC . . . . . . . . . . . . . . . . . .38  
Fig 21. Connecting TDA9989 transmitter using  
external clock source . . . . . . . . . . . . . . . . . . . . . .39  
Fig 22. Connecting TDA9989 transmitter using  
internal FRO for CEC. . . . . . . . . . . . . . . . . . . . . .39  
Fig 23. Package outline SOT962-3 (TFBGA64). . . . . . . .40  
TDA9989_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 11 June 2009  
47 of 48  
TDA9989  
NXP Semiconductors  
HDMI 1.3a transmitter with CEC support  
23. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
7.11.1  
7.11.2  
7.11.3  
7.11.4  
7.11.5  
7.12  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
CEC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 27  
Repeater function. . . . . . . . . . . . . . . . . . . . . . 27  
HDMI core . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Output TMDS buffers . . . . . . . . . . . . . . . . . . . 27  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
7.12.1  
7.12.1.1 Digitally controlled signal amplitude. . . . . . . . 27  
7.12.2  
7.12.3  
7.13  
7.13.1  
7.13.2  
Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 27  
DDC-bus channel. . . . . . . . . . . . . . . . . . . . . . 28  
E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 28  
HDMI and DVI receiver discrimination . . . . . . 28  
I2C-bus interface and register definitions. . . 29  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 29  
Memory page management . . . . . . . . . . . . . . 29  
ID version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Clock stretching . . . . . . . . . . . . . . . . . . . . . . . 30  
7
7.1  
7.2  
7.2.1  
7.2.2  
7.2.3  
7.2.3.1  
Functional description . . . . . . . . . . . . . . . . . . . 7  
System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Video input formatter . . . . . . . . . . . . . . . . . . . . 7  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Internal assignment . . . . . . . . . . . . . . . . . . . . . 8  
Input format mappings . . . . . . . . . . . . . . . . . . 12  
RGB 4 : 4 : 4 external synchronization  
(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
YCbCr 4 : 4 : 4 external synchronization  
(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
YCbCr 4 : 2 : 2 ITU656-like external  
synchronization (rising edge) . . . . . . . . . . . . . 14  
YCbCr 4 : 2 : 2 ITU656-like external  
synchronization (rising and falling edge) . . . . 15  
YCbCr 4 : 2 : 2 ITU656-like embedded  
synchronization (rising edge) . . . . . . . . . . . . . 16  
YCbCr 4 : 2 : 2 ITU656-like embedded  
synchronization (rising and falling edge) . . . . 17  
YCbCr 4 : 2 : 2 semi-planar external  
8
8.1  
8.2  
8.3  
8.4  
7.2.3.2  
7.2.3.3  
7.2.3.4  
7.2.3.5  
7.2.3.6  
7.2.3.7  
7.2.3.8  
9
9.1  
9.2  
Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Timing parameters for video supported . . . . . 31  
Timing parameters for PC standards  
supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
10  
11  
12  
13  
14  
14.1  
15  
16  
17  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34  
Thermal characteristics . . . . . . . . . . . . . . . . . 34  
Static characteristics . . . . . . . . . . . . . . . . . . . 34  
Dynamic characteristics. . . . . . . . . . . . . . . . . 36  
Application information . . . . . . . . . . . . . . . . . 38  
Transmitter connection with external world . . 38  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 43  
synchronization (rising edge) . . . . . . . . . . . . . 18  
YCbCr 4 : 2 : 2 semi-planar embedded  
synchronization (rising edge) . . . . . . . . . . . . . 19  
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 19  
Timing extraction generator . . . . . . . . . . . . . . 19  
Data enable generator . . . . . . . . . . . . . . . . . . 19  
Input and output video format. . . . . . . . . . . . . 20  
Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Color space converter. . . . . . . . . . . . . . . . . . . 20  
Gamut-related metadata. . . . . . . . . . . . . . . . . 20  
Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Audio input format. . . . . . . . . . . . . . . . . . . . . . 21  
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Audio port internal assignment. . . . . . . . . . . . 23  
Power management . . . . . . . . . . . . . . . . . . . . 23  
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 24  
Hot plug/unplug detect . . . . . . . . . . . . . . . . . . 24  
Receiver sensitivity. . . . . . . . . . . . . . . . . . . . . 24  
CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
7.2.4  
7.2.4.1  
7.2.4.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.8  
7.8.1  
7.8.2  
7.8.3  
7.9  
7.10  
7.10.1  
7.10.2  
7.11  
18  
19  
19.1  
19.2  
19.3  
19.4  
Legal information . . . . . . . . . . . . . . . . . . . . . . 44  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
20  
21  
22  
23  
Contact information . . . . . . . . . . . . . . . . . . . . 44  
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 11 June 2009  
Document identifier: TDA9989_2  

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