AU5780AD [NXP]
SAE/J1850/VPW transceiver; SAE / J1850 / VPW收发器
| 型号： | AU5780AD |
| 厂家： | 
NXP |
| 描述： | SAE/J1850/VPW transceiver |
| 文件： | 总12页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
AU5780A
SAE/J1850/VPW transceiver
Product data
2001 Jun 19
Supersedes data of 1999 Jan 28
Philips
Semiconductors
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
FEATURES
DESCRIPTION
The AU5780A is a line transceiver being primarily intended for
in-vehicle multiplex applications. It provides interfacing between a
link controller and the physical bus wire. The device supports the
SAE/J1850 VPWM standard with a nominal bus speed of 10.4 kbps.
• Supports SAE/J1850 VPW standard for in-vehicle class B
multiplexing
• Bus speed 10.4 kbps nominal
• Drive capability 32 bus nodes
• Low RFI due to output waveshaping with adjustable slew rate
PIN CONFIGURATION
• Direct battery operation with protection against +50V load dump,
jump start and reverse battery
• Bus terminals proof against automotive transients up to
1
8
7
6
BATT
TX
GND
–200V/+200V
• Thermal overload protection
2
3
BUS_OUT
/LB
• Very low bus idle power consumption
• Diagnostic loop-back mode
AU5780A
R/F
• 4X mode (41.6 kbps) reception capability
• ESD protected to 9 KV on bus and battery pins
• 8-pin SOIC
RX
4
5
BUS_IN
SO8
SL01207
QUICK REFERENCE DATA
SYMBOL
PARAMETER
Operating supply voltage
Operating ambient temperature
Battery voltage
CONDITIONS
MIN.
6
TYP.
12
MAX.
24
UNIT
V
V
°C
V
BATT.op
A
T
–40
+125
+50
220
+20
8.0
V
load dump; 1s
=12V
BATT.ld
BATT.lp
I
Bus idle supply current
Bus voltage
V
µA
V
BATT
V
V
0 < V
< 24V
–20
7.3
27
B
BATT
Bus output voltage
300Ω < R < 1.6kΩ
V
BOH
L
–I
Bus output source current
Bus input threshold
0V < V < +6.0V
50
mA
V
BO.LIM
BI
BO
V
3.65
13
4.1
t
Delay TX to BUS_OUT, normal battery
Measured at 3.875V
Measured between
21
µs
µs
bo
t , t
BUS_OUT transition times, rise and fall,
normal battery
11
18
r
f
1.5 V and (V
– 2.75 V),
BATT
9 < V
< 16 V,
BATT
t tested at an additional bus
r
load of R
= 400 W and
LOAD
C
= 22000 pF
LOAD
ORDERING INFORMATION
DESCRIPTION
SO8: 8-pin plastic small outline package
TEMPERATURE RANGE
–40 to +125°C
ORDER CODE
DWG #
AU5780AD
SOT96-1
2
2001 Jun 19
853-2261 26558
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
BLOCK DIAGRAM
BATTERY (+12V)
BATT
1
VOLTAGE
LOW–POWER
TIMER
TEMP.
REFERENCE
PROTECTION
BUS_OUT
TX
2
3
OUTPUT
BUFFER
7
TX–
BUFFER
Rb
Rs
R/F
INPUT
/LB
6
Rf
BUFFER
Vcc
Rd
BUS_IN
5
4
INPUT
FILTER
RX
VOLTAGE
REFERENCE
AU5780
8
GND
SL01208
3
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
PIN DESCRIPTION
SYMBOL
BATT
TX
PIN
1
DESCRIPTION
Battery supply input (12V nom.)
2
Transmit data input; low: transmitter passive; high: transmitter active
Rise/fall slew rate set input
R/F
3
RX
4
Receive data output; low: active bus condition detected; float/high: passive bus condition detected
BUS_IN
/LB
5
Bus line receive input
6
Loop-back test mode control input; low: loop-back mode; high: normal communication mode
BUS_OUT
GND
7
Bus line transmit output
Ground
8
the automotive environment. Specifically, the BATT input is
FUNCTIONAL DESCRIPTION
protected against 50V load dump, jump start and reverse battery
condition. The BUS_OUT output is protected against wiring fault
conditions, e.g., short circuit to battery voltage as well as typical
automotive transients (i.e., –200V / +200V). In addition, an
overtemperature shutdown function with hysteresis is incorporated
which protects the device under system fault conditions. The chip
temperature is sensed at the bus drive transistor in the output buffer.
In case of the chip temperature reaching the trip point, the AU5780A
will latch-off the transceiver function. The device is reset on the first
rising edge on the TX input after a small decrease of the chip
temperature.
The AU5780A is an integrated line transceiver IC that interfaces an
SAE/J1850 protocol controller IC to the vehicle’s multiplexed bus
line. It is primarily intended for automotive “Class B” multiplexing
applications in passenger cars using VPW (Variable Pulse Width)
modulated signals with a nominal bit rate of 10.4 kbps. The
AU5780A also receives messages in the so-called 4X mode where
data is transmitted with a typical bit rate of 41.6 kbps. The device
provides transmit and receive capability as well as protection to a
J1850 electronic module.
A J1850 link controller feeds the transmit data stream to the
transceiver’s TX input. The AU5780A transceiver waveshapes the
TX data input signal with controlled rise & fall slew rates and
rounded shape. The bus output signal is transmitted with both
voltage and current control. The BUS_IN input is connected to the
physical bus line via an external resistor. The external resistor and
an internal capacitance provides filtering against RF bus noise. The
incoming signal is output at the RX pin being connected to the
J1850 link controller.
The AU5780A also provides a loop-back mode for diagnostic
purpose. If the /LB pin is open circuit or pulled low, then TX signal is
internally looped back to the RX output independent of the signals
on the bus. In this mode the electronic module is disconnected from
the bus, i.e., the TX signal is not output to the physical bus line. In
this mode, it can be used, e.g., for self-test purpose.
The AU5780A is an enhanced successor of the AU5780. The
AU5780A provides improved wave shaping when exiting the low
power standby mode for reduced EMI. Several parameters that
were formerly only characterized to the maximum normal operating
supply of 16 volts, have now been characterized to 24 volt supplies.
These parameters which are tested and guaranteed to 24 volts are
identified with appropriate test conditions in the “conditions” columns
of the Characteristics tables, otherwise the conditions at the top of
the characteristic table applies to all parameters.
If the TX input is idle for a certain time, then the AU5780A enters a
low-power mode. This mode is dedicated to help meet ignition-off
current draw requirements. The BUS_IN input comparator is kept
alive in the low-power mode. Normal power mode will be entered
again upon detection of activity, i.e., rising edge at the TX input. The
device is able to receive and transmit a valid J1850 message when
initially in low-power mode.
The AU5780A features special robustness at its BATT and
BUS_OUT pins hence the device is well suited for applications in
4
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
CONTROL INPUT SUMMARY
RX
(out)
TX
/LB
MODE
BIT VALUE
BUS_OUT
0
1
0
0
0
1
1
Loop-back
Loop-back
TX passive (default state)
TX active
float
float
float
high
float (high)
low
1
Communication
Communication
Transmitter passive
Transmitter active
bus state
1
low
NOTE:
1. RX outputs the bus state. If the bus level is below the receiver threshold (i.e., all transmitters passive), then RX will be floating (i.e., high,
considering external pull-up resistance). Otherwise, if the bus level is above the receiver threshold (i.e., at least one transmitter is active),
then RX will be low.
ABSOLUTE MAXIMUM RATINGS
According to the IEC 134 Absolute Maximum System; operation is not guaranteed under these conditions; all voltages are referenced to pin 8
(GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
–20
MAX.
+24
UNIT
V
V
V
V
V
V
V
V
V
V
supply voltage
V
V
V
V
V
V
V
V
V
V
BATT
short-term supply voltage
transient supply voltage
transient supply voltage
transient supply voltage
Bus voltage
load dump; t < 1s
+50
BATT.ld
BATT.tr1
BATT.tr2
BATT.tr3
B
SAE J1113 pulse 1
SAE J1113 pulses 2
–100
+150
+200
+20
SAE J1113 pulses 3A, 3B
–200
–20
1
R > 10 kΩ ; Rb >10Ω
f
transient bus voltage
SAE J1113 pulse 1
–50
B.tr1
transient bus voltage
SAE J1113 pulses 2
SAE J1113 pulses 3A, 3B
+100
+200
7
B.tr2
transient bus voltage
–200
–0.3
–9
B.tr3
DC voltage on pins TX, R/F, RX, /LB
ESD capability of BATT pin
I
ESD
ESD
ESD
Air gap discharge,
R=2kΩ, C=150pF
+9
kV
kV
kV
BATT
ESD capability of BUS_OUT and BUS_IN pins Air gap discharge,
R=2kΩ, C=150pF, R > 10 kW
–9
–2
+9
+2
bus
f
ESD capability of TX, RX, R/F, and /LB pins
Human Body,
logic
R=1.5kΩ, C=100pF
P
maximum power dissipation
thermal impedance
at T
= +125 °C
164
mW
°C/W
°C
tot
amb
Θ
152
JA
T
amb
operating ambient temperature
storage temperature
–40
–40
–40
+125
+150
+150
265
T
stg
°C
T
vj
junction temperature
°C
T
LEAD
Lead temperature
Soldering, 10 seconds maximum
No latch-up, |V | = 25 V
°C
I
I
Bus output clamp current
Battery clamp current
100
mA
mA
CL(BUS)
CL(BATT)
BUS
No latch-up or snap back,
|V | = 25 V
100
BATT
NOTE:
1. For bus voltages –20V < V
< –17V and +17V < V
< +20V the current is limited by the external resistors R and R .
bus b f
bus
5
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
CHARACTERISTICS
–40°C < T
< +125°C; 6V < V
< 16V; V > 3V; 0 < V
< +8.5V;
amb
BATT
/LB
BUS
R = 56.2 kW R = 10 kW; R = 15 kW; R = 10W; 300 W< R < 1.6 kW;
S
d
f
b
L
all voltages are referenced to pin 8 (GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
supply current; bus idle TX low; Note 1
TYP.
MAX.
220
UNIT
µA
I
I
I
I
BATT.id
supply current; passive state
supply current; no load
TX low
1.5
8
mA
mA
mA
BATT.p
TX high
BATT.oc
BATT(SB)
supply current; bus output short to battery
BUS to V
; no I
10
BATT
BO
current, V = high
TX
I
supply current; bus short to GND
Thermal shutdown
TX high, V = 0V
60
mA
°C
°C
%
BATT.sc
BO
T
155
5
170
15
sd
T
T
Thermal shutdown hysteresis
Thermal shutdown, transmit duty cycle, at 24 V
hys
Bus load, R
= 300 W, 33
DTYCY24
LOAD
C
V
= 16.55 nF,
= 24 V, T = 128 ms
LOAD
BATT
T
Thermal shutdown, transmit duty cycle, at 20 V
Bus load, R
= 300 W, 45
%
DTYCY20
LOAD
C
V
= 16.55 nF,
= 20 V, T = 128 ms
LOAD
BATT
Pins TX and /LB
V
V
V
V
High level input voltage
Low level input voltage, TX pin
Low level input voltage, LB pin
Input hysteresis
6 V < V
6 V < V
< 24 V
< 24 V
t 24 V
3
V
ih
BATT
0.9
0.8
V
ILTX
ilB
h
BATT
6V t V
V
BATT
0.4
V
C
TX input capacitance
Intrinsic to part
V = 5V
5
pf
µA
µA
TX
I
ih2
I
ih6
TX high level input current
/LB high level input current
12
4
50
10
i
V = 5V
i
Pin RX
V
Low level output voltage
High level output leakage
RX output current
I = 1.6 mA
0.4
+10
20
V
ol
o
I
ih
I
rx
V = 5V, BUS_IN = low
o
–10
4
µA
mA
V = 5V
o
Pin BUS_OUT
V
BUS_OUT in loop-back mode; TX high or low
BUS_OUT voltage; passive
/LB low or floating;
0.1
0.075
8
V
V
V
olb
0<V
< 24V; R =1.6kΩ
BATT
L
V
ol
TX low or floating;
0<V < 24V; R =1.6kΩ
BATT
L
V
oh
BUS_OUT voltage; active
TX high; Note 2
9V<V < 24V;
7.3
BATT
300Ω < R <1.6kΩ;
L
V
BUS_OUT voltage; low battery
TX high;
V
BATT
– 1.7
8
V
ohLOWB
6V<V
<9V;
BATT
300Ω < R < 1.6kΩ;
L
Note 2
– I
– I
BUS_OUT source current; bus positive
BUS_OUT source current; bus negative
TX high; 9V<V
<24V
<24V
27
28
50
55
mA
mA
BO.LIM
BATT
0V< V
<+6.0V
bus
TX high; 9V<V
–17V< V
BO.LIMn
BATT
< 0V
bus
6
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
SYMBOL
PARAMETER
CONDITIONS
MIN.
–10
TYP.
MAX.
UNIT
µA
– I
BO.LK.HO
BUS_OUT leakage current; TX high; bus low or
operational
–17 < V
< 8.5 V;
< 24 V
I
BO.LIM
BUS
TX = high;
0 V < V
BATT
– I
BUS_OUT leakage current; TX high; bus positive
BUS_OUT leakage current; TX low; bus positive
8.5 V < V
< 17 V;
< 24 V
–10
–10
10
µA
BO.LK.HH
BUS
TX = high;
0 V < V
BATT
– I
– I
– I
TX low; 0V<V
<24V;
BATT
<+17V
+10
+100
100
20
µA
µA
µA
pF
BO.LK
0.1V< V
bus
BUS_OUT leakage current; TX low; bus negative TX low; 0.1V<V
<24V; –10
BATT
BO.N
–17V< V
< 0V
bus
BUS_OUT leakage current with loss of ground
Bus output capacitance
–17 V < V
< 17 V;
–10
BO.LOG
BUS
0 V <V
< 1 V
BATT
C
BUSOUT
Pin BUS_IN
V
V
V
Input high voltage
Input low voltage
Input hysteresis
Input bias current
4.1
V
ih
3.65
V
il
100
–5
mV
µA
µA
h
I
I
–17V < V
< +17V
+5
BIN
bus
BUS_IN input current maximum with and without
loss of ground
–17 < V
< 17 V;
< 24 V;
–100
100
BIN(MAX)
BUS
0 V < V
BATT
VTX high or low
C
,
Bus input capacitance
10
20
pF
BUSIN
T
,
Bus line to RX propagation delay, normal and 4X
modes
Measured at V
0.4
1.7
ms
DRXON
BUSIN_HIGH
to RX;
t
or V
DRXOFF
BUSIN_LOW
6 < V
< 24 V; of
BATT
R
= 10 KW to 5 V
LOAD
7
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
DYNAMIC CHARACTERISTICS
–40°C < T
< +125°C; 9V < V
< 16V; V > 3V; 0V <V
< +8.5V;
amb
BATT
/LB
BUS
R
= 56.2 kW; R = 10 kW; R = 15 kW; R = 10W; BUS_OUT: 300W < R < 1.6 kW;
d f b L
S
1.7 ms < (R * C ) < 5.2 ms; 2.2 nF < C < 16.55 nF; R : C < 40pF; unless otherwise specified.
L
L
L
X
L
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pins TX, RX, /LB
t
Delay TX to RX rising and falling edge in
loop-back mode
/LB low
6 V < V
15
1
24
10
µs
pI
< 24 V
BATT
t
Delay /LB to BUS_OUT
TX high, toggle /LB
µs
dIb
Pin BUS_OUT
t
t
Delay TX to BUS_OUT, normal battery
Delay TX to BUS_OUT, high battery
Measured at 3.875V, Note 3
Measured at 3.875V,
13
13
21
21
µs
µs
bo
bo_hibatt
16V < V < 24V, Note 3
BATT
t
Delay TX to BUS_OUT, low battery
Measured at 3.875V,
6V < V < 9V, Note 3
13
11
22
18
µs
µs
bo_lobatt
BATT
t , t
r
BUS_OUT transition times, rise and fall, normal Measured between
f
battery
1.5 V and (V
– 2.75 V),
BATT
9 < V
< 16 V,
BATT
t tested at an additional bus load
r
of R
= 400 W and
LOAD
C
= 22000 pF
LOAD
t
t
,
,
BUS_OUT transition times, rise and fall, high
battery
Measured between
1.5 V and 6.25 V,
11
18
µs
r_hibatt
f_hibatt
16 < V
< 24 V,
BATT
t tested at an additional bus load
r
of R
= 400 W and
LOAD
C
= 22000 pF
LOAD
t
t
BUS_OUT transition times, rise and fall, low
battery
Measured between
1.5 V and 6.25 V,
(V
BATT
(V
BATT
µs
r_lobatt
f_lobatt
– 4.25)
– 4.25)
6 < V
< 9 V,
/ 0.43
/ 0.264
BATT
t tested at an additional bus load
r
of R
= 400 W and
LOAD
C
= 22000 pF
LOAD
I
Bus output current slew rate
Bus emissions voltage output
6V < V
< 16V; R = 56.2 kW
0.90
2.4
mA/µs
sr
BATT
S
R = 100W; measured at 30% and
L
70% of waveform, DC offset
0 to –2V
V
V
0 V < DC_offset < 1 V,
9 V < V
R = 500 W, C = 6 nF
L
–50
–50
dBV
dBV
dB_limit
< 24 V,
BATT
L
Bus emissions voltage output, negative bus
offset
–1 V < DC_offset < 0 V,
9 V < V < 24 V,
dB_limit–1
BATT
R = 500 W, C = 6 nF
L
L
N
N
Bus noise rejection from battery
Bus noise isolation from battery
30 Hz < f < 250kHz
20
17
dB
dB
R
I
250 kHz < f < 200 MHz
8
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pin BUS_IN
C
Bus Input capacitance
10
20
pF
BIN
T
;
Bus line to RX propagation delay, normal and
4x modes
Measured at V
or
BUSIN_HIGH
0.4
1.7
µs
DRXON
t
V
to RX;
DRXOFF
BUSIN_LOW
6 < V
< 24 V; of
BATT
R
= 10 kW to 5V
LOAD
T
Bus line to RX propagation delay mismatch,
normal and 4x modes
t
–t
–1.3
1
+1.3
4
µs
∆
DRX_
DRXOFF DRXON
Pin BATT
t
time-out to low power state
TX low
ms
low_power
NOTES;
1. TX < 0.9V for more than 4 ms
2. For 6V < V < 9V the bus output voltage is limited by the supply voltage.
BATT
For 16V < V
< 24V (jump start) the load is limited by the package power dissipation
BATT
ratings; the duration of this condition is recommended to be less than 90 seconds.
3. Tested with a bus load of R = 400 W and C = 22,000 pF.
LOAD
LOAD
9
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
APPLICATION INFORMATION
SAEJ1850 LINK CONTROLLER
VPWO
VPWI
R
d
+5V
10NF
10k
C
s
2)
R , 56.2 kW, 1%
s
TX
R/F
RX
/LB
+12V
BATT
AU5780A
TRANSCEIVER
GND
BUS_IN
BUS_OUT
15k
10W
NOTE 1
R
R
L
f
C
L
SAE/J1850 VPW BUS LINE
SL01209
NOTES:
1. Value depends, e.g., on type of bus node. Example: primary node R =1.5kW , secondary node R =10.7kW.
L
L
2. For connection of /LB there are different options, e.g., connect to V or to low-active reset or to a port pin.
CC
3. The value of C is suggested to be in the range 330 pF < C < 470 pF.
L
L
10
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
11
2001 Jun 19
Philips Semiconductors
Product data
SAE/J1850/VPW transceiver
AU5780A
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on
the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-01
Document order number:
9397 750 08501
Philips
Semiconductors
相关型号：
AU5780AD,112
IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 3.90 MM, PLASTIC, SOIC-8, Interface IC:Other
NXP
AU5780AD/N,118
IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 3.90 MM, PLASTIC, SOIC-8, Interface IC:Other
NXP
©2020 ICPDF网 联系我们和版权申明