74ALVCH16374DGG-T [NXP]
IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver;型号: | 74ALVCH16374DGG-T |
厂家: | NXP |
描述: | IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver 触发器 |
文件: | 总17页 (文件大小:150K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 03 — 27 April 2010
Product data sheet
1. General description
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)
input and an output enable (OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is
HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not
affect the state of the flip-flops.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at VCC = 3.0 V
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Temperature range Package
Name
Description
Version
74ALVCH16374DL
74LVCH16374DGG
−40 °C to +85 °C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
−40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
4. Functional diagram
1
24
1OE
2OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1CP
48
2CP
25
001aal770
Fig 1. Logic symbol
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
2 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
1
1OE
1CP
2OE
2CP
1EN
48
24
25
C1
2EN
C2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1D
1
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
5
6
8
9
11
12
13
14
16
17
19
20
22
23
2D
2
001aal772
Fig 2. IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig 3. Bus hold circuit
1D0
D
Q
1Q0
2D0
D
Q
2Q0
CP
CP
FF1
FF9
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
001aal771
Fig 4. Logic diagram
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
3 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
74ALVCH16374
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1CP
1D0
1D1
GND
1D2
1D3
1Q0
1Q1
GND
1Q2
1Q3
3
4
5
6
7
V
CC
V
CC
8
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2D4
2D5
GND
2D6
2D7
2CP
001aal769
Fig 5. Pin configuration
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
4 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE
1Q0 to 1Q7
2Q0 to 2Q7
GND
1, 24
output enable input (active LOW)
3-state flip-flop outputs
3-state flip-flop outputs
ground (0 V)
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
VCC
positive supply voltage
data inputs
1D0 to 1D7
2D0 to 2D7
1CP, 2CP
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48, 25
data inputs
clock input
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Inputs
Internal
Outputs Q0 to Q7
Operating mode
flip-flops
nOE
L
nCP
↑
Dn
l
L
L
load and read register
load register and disable outputs
L
↑
h
l
H
L
H
Z
Z
H
↑
H
↑
h
H
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
5 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
control inputs
data inputs
+4.6
VCC + 0.5
±50
V
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
mA
V
[1]
−0.5
-
VCC + 0.5
±50
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
−100
−65
-
storage temperature
total power dissipation
+150
Tamb = −40 °C to +125 °C;
SSOP48 package
[2]
[3]
-
-
850
600
mW
mW
TSSOP48 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 11.3 mW/K.
[3] Above 55 °C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
maximum speed performance
CL = 30 pF
2.3
3.0
1.2
0
-
-
-
-
-
-
-
-
-
2.7
3.6
3.6
VCC
5.5
VCC
+85
20
V
CL = 50 pF
V
low voltage applications
data inputs
V
VI
input voltage
V
control inputs
0
V
VO
output voltage
0
V
Tamb
Δt/ΔV
ambient temperature
in free air
−40
0
°C
ns/V
ns/V
input transition rise and fall rate VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
0
10
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
6 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input
voltage
VCC = 1.2 V
VCC
-
-
V
V
V
V
V
V
V
V
VCC = 1.8 V
0.7VCC
0.9
1.2
1.5
-
-
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
1.7
-
-
2.0
VIL
LOW-level input
voltage
-
-
-
-
0
VCC = 1.8 V
0.9
1.2
1.5
0.2VCC
0.7
0.8
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
VOH
HIGH-level output
voltage
IO = −100 μA; VCC = 1.8 V to 3.6 V
IO = −6 mA; VCC = 1.8 V
IO = −6 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 2.3 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
VCC − 0.2
VCC − 0.4
VCC
-
-
-
-
-
-
-
V
V
V
V
V
V
V
VCC − 0.1
VCC − 0.3 VCC − 0.08
VCC − 0.5 VCC − 0.17
VCC − 0.5 VCC − 0.14
VCC − 0.6 VCC − 0.26
VCC − 1.0 VCC − 0.28
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.8 V to 3.6 V
IO = 6 mA; VCC = 1.8 V
IO = 6 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 2.3 V
IO = 24 mA; VCC = 3.0 V
VCC = 1.8 V to 3.6 V
control input; VI = 5.5 V or GND
data input; VI = VCC or GND
VI = VIH or VIL; VO = VCC or GND
VCC = 1.8 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VCC or GND
-
-
-
-
-
-
-
0
0.20
0.30
0.20
0.40
0.40
0.60
0.55
V
V
V
V
V
V
V
0.09
0.07
0.15
0.14
0.23
0.27
II
input leakage current
-
-
0.1
0.1
5
5
μA
μA
IOZ
ILIZ
ICC
OFF-state output
current
-
-
0.1
0.1
5
μA
μA
10
OFF-state input
leakage current
VCC = 1.8 V to 2.7 V
VCC = 3.6 V
-
-
0.1
0.1
10
15
μA
μA
supply current
VI = VCC or GND; IO = 0 A;
VCC = 1.8 V to 2.7 V
VCC = 2.7 V to 3.6 V
-
-
0.1
0.2
20
40
μA
μA
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
7 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
ΔICC
additional supply
current
VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V
to 3.6 V
per control input
per data I/O input
-
-
5
500
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
pF
150
750
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
IBHL
IBHH
IBHLO
IBHHO
CI
bus hold LOW current VCC = 2.3 V; VI = 0.7 V
VCC = 3.0 V; VI = 0.8 V
45
-
-
-
-
-
-
-
-
-
-
75
150
bus hold HIGH current VCC = 2.3 V; VI = 1.7 V
VCC = 3.0 V; VI = 2.0 V
−45
−75
300
450
−300
−450
-
-
−175
bus hold LOW
overdrive current
VCC = 2.7 V
VCC = 3.6 V
VCC = 2.7 V
VCC = 3.6 V
-
-
bus hold HIGH
overdrive current
-
-
input capacitance
5.0
[1] All typical values are measured at Tamb = 25 °C.
[2] Valid for data inputs of bus hold parts only.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 9.
Symbol
Parameter
Conditions
Min
Typ[1]
Max Unit
Tamb = −40 °C to +85 °C
fmax
maximum frequency see Figure 6
VCC = 1.8 V
125
150
150
200
250
300
300
350
-
-
-
-
MHz
MHz
MHz
MHz
[2]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
nCP to nQn; see Figure 6
VCC = 1.2 V
tpd
propagation delay
-
7.7
3.6
2.3
2.3
2.4
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
6.5
4.3
3.8
3.4
[2]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
nOE to nQn; see Figure 7
VCC = 1.2 V
ten
enable time
-
8.7
4.0
2.6
2.9
2.3
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
7.2
4.8
4.8
4.0
[2]
[3]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
8 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 7.
Dynamic characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 9.
Symbol
Parameter
Conditions
Min
Typ[1]
Max Unit
[4]
tdis
disable time
nOE to nQn; see Figure 7
VCC = 1.2 V
-
6.2
3.1
2.1
2.9
2.6
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
5.4
4.0
4.5
4.1
[2]
[3]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nCP HIGH or LOW; see Figure 6
VCC = 1.8 V
tW
pulse width
set-up time
hold time
4.0
3.0
3.0
2.5
2.0
1.6
1.6
1.4
-
-
-
-
ns
ns
ns
ns
[2]
[3]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
Dn to nCP; see Figure 8
VCC = 1.8 V
tsu
1.5
1.2
1.5
1.2
0.2
0.2
0.4
0.2
-
-
-
-
ns
ns
ns
ns
[2]
[3]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
Dn to nCP; see Figure 8
VCC = 1.8 V
th
0.6
0.8
0.6
0.8
−0.2
−0.1
−0.2
0.0
-
-
-
-
ns
ns
ns
ns
[2]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[5]
VCC = 3.0 V to 3.6 V
per flip-flop; VI = GND to VCC
outputs enabled
CPD
power dissipation
capacitance
-
-
16
10
-
-
pF
pF
outputs disabled
[1] All typical values are measured at Tamb = 25 °C.
[2] Typical values are measured at VCC = 2.5 V.
[3] Typical values are measured at VCC = 3.3 V.
[4] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
9 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
11. Waveforms
1 / f
max
V
I
nCP
input
V
V
M
V
t
M
M
GND
t
W
t
PHL
PLH
V
OH
nQn
V
M
V
M
output
V
OL
001aal773
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 6. Propagation delay, clock input (nCP) to data output (nQn), and pulse width
V
I
nOE input
V
V
M
M
GND
t
t
PZL
PLZ
V
CC
nQn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nQn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 7. 3-state enable and disable times
V
I
nCP
V
M
V
M
V
M
input
GND
t
su
t
su
t
h
t
h
V
I
nDn
input
V
M
V
M
V
M
V
M
GND
001aal774
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8. Data setup and hold times for input (nDn) to input (nCP)
74ALVCH16374_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
10 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 8.
Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
2.3 V to 2.7 V and VCC
< 2.3 V
0.5
0.5
VOL + 0.15 V
VOH − 0.15 V
2.7 V
2.7 V
2.7 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOL + 0.3 V
VOH − 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
12. Test information
V
EXT
V
CC
R
R
L
L
V
V
O
I
G
DUT
R
C
L
T
mna616
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Load circuit for measuring switching times
Table 9.
Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
tPHZ, tPZH
2.3 V to 2.7 V and
< 2.3 V
VCC
≤ 2.0 ns
30 pF
500 Ω
2 × VCC
GND
2.7 V
2.7 V
2.7 V
2.5 ns
2.5 ns
50 pF
50 pF
500 Ω
500 Ω
open
open
2 × VCC
2 × VCC
GND
GND
3.0 V to 3.6 V
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
11 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
13. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
p
A
2
A
A
(A )
3
1
θ
pin 1 index
L
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 10. Package outline SOT370-1 (SSOP48)
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
12 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 11. Package outline SOT362-1 (TSSOP48)
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
13 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date
20100427
Data sheet status
Change notice
Supersedes
74ALVCH16374_3
Modifications:
Product data sheet
-
74ALVCH16374_2
–
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
–
–
Legal texts have been adapted to the new company name where appropriate.
Table 7 “Dynamic characteristics”: voltage ranges corrected.
74ALVCH16374_2
19980618
Product specification
-
74ALVCH16374_1
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
14 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
16.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
15 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
16 of 17
74ALVCH16374
NXP Semiconductors
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test information. . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 April 2010
Document identifier: 74ALVCH16374_3
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