74ALVCH16374DLG4 [TI]

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS; 16位边沿触发D型触发器具有​​三态输出
74ALVCH16374DLG4
型号: 74ALVCH16374DLG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
16位边沿触发D型触发器具有​​三态输出

触发器 输出元件
文件: 总14页 (文件大小:318K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Operates From 1.65 to 3.6 V  
Max tpd of 4.2 ns at 3.3 V  
±24-mA Output Drive at 3.3 V  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
CC  
V
CC  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
1Q5  
1Q6  
GND 10  
1Q7  
1Q8  
2Q1  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
11  
12  
13  
DESCRIPTION/ORDERING INFORMATION  
2Q2 14  
GND 15  
2Q3 16  
2Q4 17  
This 16-bit edge-triggered D-type flip-flop is designed  
for 1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16374 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. It can be used as  
two 8-bit flip-flops or one 16-bit flip-flop. On the  
positive transition of the clock (CLK) input, the  
Q outputs of the flip-flop take on the logic levels at  
the data (D) inputs. OE can be used to place the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the  
high-impedance state, the outputs neither load nor  
drive the bus lines significantly. The high-impedance  
state and the increased drive provide the capability to  
drive bus lines without need for interface or pullup  
components.  
V
CC  
V
CC  
18  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
2Q5 19  
2Q6 20  
GND 21  
2Q7 22  
2Q8 23  
2OE 24  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH16374DL  
TOP-SIDE MARKING  
ALVCH16374  
Tube  
SSOP - DL  
Tape and reel  
Tape and reel  
Tape and reel  
SN74ALVCH16374DLR  
SN74ALVCH16374DGGR  
SN74ALVCH16374DGVR  
SN74ALVCH16374KR  
74ALVCH16374ZQLR  
TSSOP - DGG  
TVSOP - DGV  
VFBGA - GQL  
ALVCH16374  
VH374  
-40°C to 85°C  
Tape and reel  
VH374  
VFBGA - ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guideline are available at  
www.ti.com/sc/package.  
GQL OR ZQL PACKAGE  
TERMINAL ASSIGNMENTS(1)  
(TOP VIEW)  
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE  
1Q2  
1Q4  
1Q6  
1Q8  
2Q1  
2Q3  
2Q5  
2Q7  
2OE  
NC  
NC  
NC  
NC  
1CLK  
1D2  
1D4  
1D6  
1D8  
2D1  
2D3  
2D5  
2D7  
2CLK  
A
B
C
D
E
F
1Q1  
1Q3  
1Q5  
1Q7  
2Q2  
2Q4  
2Q6  
2Q8  
NC  
GND  
VCC  
GND  
GND  
VCC  
GND  
1D1  
1D3  
1D5  
1D7  
2D2  
2D4  
2D6  
2D8  
NC  
G
H
J
GND  
VCC  
GND  
NC  
GND  
VCC  
GND  
NC  
G
H
J
K
K
(1) NC - No internal connection  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
H or L  
X
L
X
X
Q0  
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
24  
2OE  
1OE  
25  
48  
2CLK  
1CLK  
C1  
1D  
C1  
1D  
2
13  
2Q1  
1Q1  
47  
36  
2D1  
1D1  
To Seven Other Channels  
Pin numbers shown are for the DGG, DGV, and DL packages.  
To Seven Other Channels  
2
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
-0.5  
-0.5  
MAX  
4.6  
UNIT  
V
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
4.6  
V
VO  
IIK  
Output voltage range(2)(3)  
-0.5 VCC + 0.5  
V
Input clamp current  
VI < 0  
-50  
-50  
±50  
±100  
70  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through each VCC or GND  
DGG package  
DGV package  
DL package  
58  
θJA  
Package thermal impedance(4)  
°C/W  
°C  
63  
GQL/ZQL package  
42  
Tstg  
Storage temperature range  
-65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) This value is limited to 4.6 V, maximum.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
RECOMMENDED OPERATING CONDITIONS(1)  
MIN  
MAX  
UNIT  
VCC  
Supply voltage  
1.65  
3.6  
V
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0.65 × VCC  
VIH  
High-level input voltage  
1.7  
2
V
V
0.35 × VCC  
0.7  
0.8  
VCC  
VCC  
-4  
VIL  
Low-level input voltage  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
-12  
-12  
-24  
4
IOH  
High-level output current  
Low-level output current  
mA  
mA  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
12  
IOL  
12  
24  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
10  
ns/V  
TA  
-40  
85  
°C  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
3
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 3.6 V VCC - 0.2  
MIN TYP(1)  
MAX UNIT  
IOH = -100 µA  
IOH = -4 mA  
IOH = -6 mA  
1.65 V  
2.3 V  
1.2  
2
VOH  
2.3 V  
1.7  
2.2  
2.4  
2
V
IOH = -12 mA  
2.7 V  
3 V  
IOH = -24 mA  
IOL = 100 µA  
IOL = 4 mA  
IOL = 6 mA  
3 V  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.2  
0.45  
0.4  
V
VOL  
2.3 V  
0.7  
IOL = 12 mA  
2.7 V  
0.4  
IOL = 24 mA  
VI = VCC or GND  
VI = 0.58 V  
3 V  
0.55  
II  
3.6 V  
±5  
µA  
µA  
1.65 V  
1.65 V  
2.3 V  
25  
-25  
45  
VI = 1.07 V  
VI = 0.7 V  
II(hold)  
VI = 1.7 V  
2.3 V  
-45  
75  
VI = 0.8 V  
3 V  
VI = 2 V  
3 V  
-75  
VI = 0 to 3.6 V(2)  
VO = VCC or GND  
VI = VCC or GND,  
3.6 V  
±500  
±10  
40  
IOZ  
3.6 V  
µA  
µA  
µA  
ICC  
IO = 0  
3.6 V  
ICC  
One input at VCC - 0.6 V,  
Other inputs at VCC or GND  
3 V to 3.6 V  
750  
Control inputs  
Data inputs  
Outputs  
3
6
7
Ci  
VI = VCC or GND  
3.3 V  
3.3 V  
pF  
pF  
Co  
VO = VCC or GND  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 1.8 V  
VCC = 2.7 V  
UNIT  
MIN  
TYP  
MIN MAX  
MIN MAX MIN MAX  
150 150  
(1)  
fclock  
tw  
Clock frequency  
150  
MHz  
ns  
(1)  
(1)  
(1)  
Pulse duration, CLK high or low  
Setup time, data before CLK↑  
Hold time, data after CLK↑  
3.3  
2.1  
0.6  
3.3  
2.2  
0.5  
3.3  
1.9  
0.5  
tsu  
th  
ns  
ns  
(1) This information was not available at the time of publication.  
4
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 1.8 V  
VCC = 2.7 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
TYP  
MIN  
MAX  
MIN  
MAX  
MIN  
150  
1
MAX  
(1)  
fmax  
tpd  
150  
1
150  
MHz  
ns  
(1)  
(1)  
(1)  
CLK  
OE  
Q
Q
Q
5.3  
6.2  
5.3  
4.9  
5.9  
4.7  
4.2  
4.8  
4.3  
ten  
1
1
ns  
tdis  
OE  
1
1.2  
ns  
(1) This information was not available at the time of publication.  
OPERATING CHARACTERISTICS  
TA = 25°C  
VCC = 1.8 V  
VCC = 2.5 V VCC = 3.3 V  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
TYP  
TYP  
31  
TYP  
30  
(1)  
Outputs enabled  
Cpd Power dissipation capacitance  
CL = 50 pF, f = 10 MHz  
pF  
(1)  
Outputs disabled  
16  
18  
(1) This information was not available at the time of publication.  
5
SN74ALVCH16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES021LJULY 1995REVISED SEPTEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
S1  
GND  
t
Open  
V
LOAD  
GND  
pd  
/t  
/t  
C
t
t
L
PLZ PZL  
R
L
(see Note A)  
PHZ PZH  
LOAD CIRCUIT  
INPUT  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
V
I
t /t  
r f  
1.8 V  
2.5 V ± 0.2 V  
2.7 V  
V
V
2.7 V  
2.7 V  
V
/2  
/2  
2 × V  
2 × V  
6 V  
6 V  
1 k  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
CC  
CC  
CC  
V
CC  
CC  
CC  
1.5 V  
1.5 V  
3 V ± 0.3 V  
0.3 V  
t
w
V
I
V
I
V
M
V
M
Input  
Timing  
Input  
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
V
I
Output  
Control  
(low-level  
enabling)  
Data  
Input  
V
I
V
V
M
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
S1 at V  
LOAD  
(see Note B)  
V
V
/2  
LOAD  
V
I
V
M
Input  
V
M
V
M
V + V  
OL  
0 V  
OL  
t
t
PZH  
PHZ  
t
t
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− V  
V
M
Output  
V
M
V
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Dec-2006  
PACKAGING INFORMATION  
Orderable Device  
74ALVCH16374DGGRE4  
74ALVCH16374DGVRE4  
74ALVCH16374DLG4  
74ALVCH16374DLRG4  
74ALVCH16374ZQLR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
DGG  
48  
48  
48  
48  
56  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TVSOP  
SSOP  
SSOP  
DGV  
DL  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
BGA MI  
CROSTA  
R JUNI  
OR  
ZQL  
1000 Green (RoHS &  
no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
SN74ALVCH16374DGGR  
SN74ALVCH16374DGVR  
SN74ALVCH16374DL  
SN74ALVCH16374DLR  
SN74ALVCH16374KR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TVSOP  
SSOP  
DGG  
DGV  
DL  
48  
48  
48  
48  
56  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
BGA MI  
CROSTA  
R JUNI  
OR  
GQL  
1000  
TBD  
SNPB  
Level-1-240C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Dec-2006  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Low Power Wireless www.ti.com/lpw  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2006, Texas Instruments Incorporated  

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