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74ALVCH16374DT [ETC]

16-Bit D-Type Flip-Flop ; 16位D型触发器\n
74ALVCH16374DT
型号： 74ALVCH16374DT
厂家： ETC    ETC
描述：

16-Bit D-Type Flip-Flop
16位D型触发器\n

触发器
文件： 总12页 (文件大小：145K)
中文：  中文翻译
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74ALVCH16374  
Low-Voltage 16-Bit D-Type  
Flip-Flop with Bus Hold  
1.8/2.5/3.3 V  
(3–State, Non–Inverting)  
http://onsemi.com  
MARKING DIAGRAM  
The 74ALVCH16374 is an advanced performance, non–inverting  
16–bit D–type flip–flop. It is designed for very high–speed, very  
low–power operation in 1.8 V, 2.5 V or 3.3 V systems. The  
VCXH16374 is byte controlled, with each byte functioning  
identically, but independently. Each byte has separate Output Enable  
and Clock Pulse inputs. These control pins can be tied together for full  
16–bit operation.  
The 74ALVCH16374 consists of 16 edge–triggered flip–flops with  
individual D–type inputs and 3.6 V–tolerant 3–state outputs. The  
clocks (CPn) and Output Enables (OEn) are common to all flip–flops  
within the respective byte. The flip–flops will store the state of  
individual D inputs that meet the setup and hold time requirements on  
the LOW–to–HIGH Clock (CP) transition. With the OE LOW, the  
contents of the flip–flops are available at the outputs. When the OE is  
HIGH, the outputs go to the high impedance state. The OE input level  
does not affect the operation of the flip–flops. The data inputs include  
active bushold circuitry, eliminating the need for external pull–up  
resistors to hold unused or floating inputs at a valid logic state.  
48  
48  
74ALVCH16374DT  
AWLYYWW  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
1
= Assembly Location  
A
WL = Wafer Lot  
YY = Year  
WW = Work Week  
PIN NAMES  
Pins  
• Designed for Low Voltage Operation: V  
• 3.6 V Tolerant Inputs and Outputs  
= 1.65 – 3.6 V  
Function  
CC  
OEn  
CPn  
D0–D15  
O0–O15  
Output Enable Inputs  
Clock Pulse Inputs  
Inputs  
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V  
3.9 ns max for 2.3 to 2.7 V  
Outputs  
7.8 ns max for 1.65 to 1.95 V  
• Static Drive: ±24 mA Drive at 3.0 V  
±18 mA Drive at 2.3 V  
±6 mA Drive at 1.65 V  
ORDERING INFORMATION  
• Supports Live Insertion and Withdrawal  
Device  
Package  
Shipping  
39 / Rail  
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
74ALVCH16374DT  
74ALVCH16374DTR  
TSSOP  
TSSOP  
Logic State  
2500 / Reel  
†
• I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
• Near Zero Static Supply Current in All Three Logic States (20 µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds ±250 mA @ 125°C  
• ESD Performance: Human Body Model >2000 V;  
Machine Model >200 V  
• Second Source to Industry Standard 74ALVCH16374  
†To ensure the outputs activate in the 3–state condition, the output enable pins  
should be connected to V  
determined by the current sinking capability of the output connected to the OE pin.  
through a pull–up resistor. The value of the resistor is  
CC  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
November, 2001 – Rev. 1  
74ALVCH16374/D  
74ALVCH16374  
1
24  
25  
OE1  
CP1  
OE2  
CP2  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
OE1  
O0  
CP1  
D0  
48  
3
O1  
D1  
2
13  
14  
16  
17  
19  
20  
22  
23  
nCP  
D
nCP  
D
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
O8  
47  
Q
Q
Q
Q
Q
36  
Q
Q
Q
Q
Q
4
GND  
O2  
GND  
D2  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
5
6
3
O3  
D3  
nCP  
D
nCP  
D
O9  
46  
44  
43  
41  
40  
38  
37  
35  
33  
32  
30  
29  
27  
26  
7
V
CC  
V
CC  
8
O4  
O5  
D4  
5
9
nCP  
D
nCP  
D
D5  
O10  
O11  
O12  
O13  
O14  
O15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D10  
D11  
D12  
D13  
D14  
D15  
GND  
O6  
GND  
D6  
6
nCP  
D
nCP  
D
O7  
D7  
O8  
D8  
O9  
D9  
8
nCP  
D
nCP  
D
GND  
O10  
O11  
GND  
D10  
D11  
9
nCP  
D
nCP  
D
V
CC  
V
CC  
Q
Q
Q
Q
Q
Q
O12  
O13  
GND  
O14  
O15  
OE2  
D12  
D13  
GND  
D14  
D15  
CP2  
11  
12  
nCP  
D
nCP  
D
nCP  
D
nCP  
D
Figure 1. 48–Lead Pinout  
Figure 2. Logic Diagram  
(Top View)  
1
EN1  
OE1  
48  
25  
24  
EN2  
EN3  
EN4  
CP1  
CP2  
OE2  
2
47  
46  
44  
43  
41  
40  
38  
37  
36  
35  
33  
32  
30  
29  
27  
26  
1
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
5
6
1
1
1
8
9
11  
12  
13  
14  
16  
17  
19  
20  
22  
23  
3
4
O8  
O9  
D8  
D9  
O10  
O11  
O12  
O13  
O14  
O15  
D10  
D11  
D12  
D13  
D14  
D15  
Figure 3. IEC Logic Diagram  
Inputs  
Outputs  
Inputs  
Outputs  
CP1  
↑
OE1  
L
D0:7  
H
O0:7  
H
CP2  
↑
OE2  
L
D8:15  
O8:15  
H
L
H
L
↑
L
L
L
↑
L
X
L
X
O0  
Z
X
L
X
X
O0  
Z
X
H
X
X
H
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; ↑ = Low–to–High Transition; X = High or Low Voltage Level and  
Transitions Are Acceptable, for I  
reasons, DO NOT FLOAT Inputs. O0 = No Change.  
CC  
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2
74ALVCH16374  
MAXIMUM RATINGS (Note 1)  
Symbol  
Parameter  
Value  
*0.5 to )4.6  
*0.5 to )4.6  
*0.5 to )4.6  
*50  
Unit  
V
V
V
V
DC Supply Voltage  
CC  
DC Input Voltage  
V
I
DC Output Voltage  
V
O
I
I
I
I
I
DC Input Diode Current  
DC Output Diode Current  
DC Output Sink Current  
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature Range  
V < GND  
mA  
mA  
mA  
mA  
mA  
_C  
_C  
_C  
_C/W  
IK  
I
V
< GND  
O
*50  
OK  
O
$50  
$100  
CC  
GND  
$100  
T
T
T
q
*65 to )150  
260  
STG  
Lead Temperature, 1 mm from Case for 10 Seconds  
Junction Temperature Under Bias  
Thermal Resistance (Note 2)  
Moisture Sensitivity  
L
J
)150  
90  
JA  
MSL  
Level 1  
F
R
Flammability Rating  
Oxygen Index: 30% – 35%  
UL–94–VO (0.125 in)  
V
ESD  
ESD Withstand Voltage  
Human Body Model (Note 3)  
Machine Model (Note 4)  
Charged Device Model (Note 5)  
u2000  
u200  
N/A  
V
I
Latch–Up Performance  
Above V  
and Below GND at 85_C (Note 6)  
$250  
mA  
LATCH–UP  
CC  
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those  
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional  
operation should be restricted to the Recommended Operating Conditions.  
1. I absolute maximum rating must be observed.  
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.  
3. Tested to EIA/JESD22–A114–A.  
4. Tested to EIA/JESD22–A115–A.  
5. Tested to JESD22–C101–A.  
6. Tested to EIA/JESD78.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
Max  
Unit  
V
CC  
Supply Voltage  
Operating  
Data Retention Only  
2.3  
1.5  
3.6  
3.6  
V
V
V
T
Input Voltage  
(Note 7)  
0
0
3.6  
3.6  
V
V
I
Output Voltage  
(HIGH or LOW State)  
O
Operating Free–Air Temperature  
Input Transition Rise or Fall Rate  
*
4
0
)
8
5
_C  
ns/V  
A
Dt/DV  
V
V
V
= 2.5 V $ 0.2 V  
= 3.0 V $ 0.3 V  
= 5.0 V $ 0.5 V  
0
0
0
20  
10  
5
CC  
CC  
CC  
7. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.  
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3
74ALVCH16374  
DC ELECTRICAL CHARACTERISTICS  
T
= *40_C to )85_C  
A
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
V
HIGH Level Input Voltage  
(Note 8)  
1.65 V v V  
CC  
t 2.3 V  
0.65 ꢀ V  
V
IH  
CC  
2.3 V v V  
2.7 V t V  
v 2.7 V  
v 3.6 V  
1.7  
2.0  
CC  
CC  
LOW Level Input Voltage  
(Note 8)  
1.65 V v V  
CC  
t
2
.
3
V
0.35 ꢀ V  
0.7  
V
V
IL  
CC  
2.3 V v V  
2.7 V t V  
v 2.7 V  
v 3.6 V  
CC  
CC  
0.8  
HIGH Level Output Voltage  
1.65 V v V  
CC  
v 3.6 V; I  
OH  
= *100 mA  
V
CC  
* 0.2  
OH  
V
= 1.65 V; I  
OH  
= *4 mA  
1.20  
2.0  
1.7  
2.2  
2.4  
2.0  
CC  
V
CC  
= 2.3 V; I  
= 2.3 V; I  
= 2.7 V; I  
= 3.0 V; I  
= 3.0 V; I  
= *6 mA  
OH  
OH  
OH  
OH  
OH  
V
CC  
= *12 mA  
= *12 mA  
= *12 mA  
= *24 mA  
V
CC  
V
CC  
V
CC  
V
OL  
LOW Level Output Voltage  
1.65 V v V  
CC  
v 3.6 V; I  
OL  
= 100 mA  
0.2  
0.45  
0.4  
V
V
CC  
= 1.65 V; I = 4 mA  
OL  
V
= 2.3 V; I  
= 2.3 V; I  
= 2.7 V; I  
= 3.0 V; I  
= 6 mA  
CC  
OL  
OL  
OL  
OL  
V
CC  
= 12 mA  
= 12 mA  
= 24 mA  
0.7  
V
CC  
0.4  
V
CC  
0.55  
$500  
$5.0  
V
OL  
LOW Level Output Voltage  
Input Leakage Current  
V
CC  
= 3.6 V; V = 0 to 3.6 V  
mA  
mA  
mA  
I
I
I
1.65 V v V  
v 3.6 V; 0 V v V v 3.6 V  
I
CC  
I
Minimum Bus–hold Input  
Current  
V
= 3.0 V, V = 0.8 V  
IN  
= 3.0 V, V = 2.0 V  
75  
*75  
45  
I(HOLD)  
CC  
V
CC  
IN  
V
CC  
= 2.3 V, V = 0.7 V  
IN  
V
= 2.3 V, V = 1.7 V  
IN  
*45  
25  
CC  
V
CC  
= 1.65 V, V = 0.58 V  
IN  
V
CC  
= 1.65 V, V = 1.07 V  
*
2
5
IN  
I
3–State Output Current  
1.65 V v V  
v
3
.
6
V
;
0
V
v
V
v
3
.
6
V
;
V
=
V
o
r
V
$10  
10  
mA  
mA  
mA  
OZ  
CC  
O
I
IH IL  
I
Power–Off Leakage Current  
V
CC  
= 0 V; V or V = 3.6 V  
OFF  
CC  
I
O
I
Quiescent Supply Current  
(Note 9)  
1.65 V v V  
v 3.6 V; V = GND or V  
CC  
40  
CC  
CC  
I
1.65 V v V  
v
3
.
6
V
;
3
.
6
V
v
V
,
V
v
3
.
6
V
$40  
750  
I
O
DI  
CC  
Increase in I  
CC  
per Input  
2.7 V t V  
CC  
≤ 3.6 V; V = V  
IH CC  
*
0
.
6
V
mA  
8. These values of V are used to test DC electrical characteristics only.  
I
9. Outputs disabled or 3–state only.  
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4
74ALVCH16374  
AC CHARACTERISTICS (Note 10; t = t = 2.0 ns; C = 30 pF; R = 500 Ω)  
R
F
L
L
Limits  
T
A
= –40°C to +85°C  
V
CC  
= 3.0 V to 3.6 V  
V
CC  
= 2.3 V to 2.7 V  
V
CC  
= 1.65 V to 1.95 V  
Wave–  
form  
Symbol  
Parameter  
Min  
250  
Max  
Min  
200  
Max  
Min  
100  
Max  
Unit  
MHz  
ns  
f
Clock Pulse Frequency  
1
1
max  
t
t
Propagation Delay  
CP to On  
0.5  
0.5  
3.0  
3.0  
0.5  
0.5  
3.9  
3.9  
0.5  
0.5  
7.8  
7.8  
PLH  
PHL  
t
t
Output Enable Time to  
High and Low Level  
2
2
0.5  
0.5  
3.5  
3.5  
0.5  
0.5  
4.6  
4.6  
0.5  
0.5  
9.2  
9.2  
ns  
ns  
PZH  
PZL  
t
t
Output Disable Time From  
High and Low Level  
0.5  
0.5  
3.5  
3.5  
0.5  
0.5  
3.8  
3.8  
1.5  
1.5  
6.8  
6.8  
PHZ  
PLZ  
t
t
t
Setup Time, High or Low Dn to CP  
Hold Time, High or Low Dn to CP  
CP Pulse Width, High  
3
3
3
1.5  
1.0  
1.5  
0.5  
0.5  
0.5  
2.5  
1.0  
4.0  
ns  
ns  
ns  
ns  
s
h
w
t
t
Output–to–Output Skew  
(Note 11)  
0.5  
0.5  
0.5  
0.5  
0.75  
0.75  
OSHL  
OSLH  
10.For C = 50 pF, add approximately 300 ps to the AC maximum specification.  
L
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.  
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t  
guaranteed by design.  
) or LOW–to–HIGH (t  
); parameter  
OSHL  
OSLH  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Input Capacitance  
Condition  
Note 12  
Typical  
Unit  
pF  
C
C
C
6
7
IN  
Output Capacitance  
Note 12  
pF  
OUT  
PD  
Power Dissipation Capacitance  
Note 12, 10 MHz  
20  
pF  
12.V  
= 1.8, 2.5 or 3.3 V; V = 0 V or V  
I
.
CC  
CC  
V
IH  
V
IH  
Vm  
Vm  
OEn  
Dn  
Vm  
Vm  
0 V  
0 V  
t
t
PZH  
PHZ  
t
h
t
s
V
OH  
Vy  
V
IH  
Vm  
On  
CPn  
Vm  
Vm  
≈ 0 V  
0 V  
f
t
t
max  
PZL  
PLZ  
t , t  
PLH PHL  
≈ V  
CC  
V
OH  
Vm  
On  
On  
Vm  
Vx  
V
OL  
V
OL  
WAVEFORM 1 - PROPAGATION DELAYS, SETUP AND HOLD TIMES  
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns  
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES  
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns  
t
R
t
R
F
W
F
W
Figure 4. AC Waveforms  
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5
74ALVCH16374  
V
IH  
CPn  
CPn  
Vm  
Vm  
Vm  
t
t
0 V  
w
V
IH  
w
Vm  
0 V  
WAVEFORM 3 - PULSE WIDTH  
= t = 2.0 ns (or fast as required) from 10% to 90%  
F
t
R
Figure 5. AC Waveforms  
V
CC  
2.5 V ±0.2 V  
3.3 V ±0.3 V  
2.7 V  
1.8 V ±0.15 V  
Symbol  
V
IH  
V
V
CC  
/2  
CC  
/2  
V
m
1.5 V  
V
CC  
V
CC  
+ 0.15 V  
V
x
V
+ 0.3 V  
– 0.3 V  
V
+ 0.15 V  
– 0.15 V  
V
OL  
OL  
OL  
V
y
V
OH  
V
OH  
V
OH  
– 0.15 V  
V
CC  
6 V or V × 2  
CC  
OPEN  
GND  
R
L
PULSE  
GENERATOR  
DUT  
R
T
C
L
R
L
TEST  
SWITCH  
t , t  
PLH PHL  
Open  
t , t  
PZL PLZ  
6 V at V = 3.3 ±0.3 V;  
CC  
V
CC  
× 2 at V  
CC  
= 2.5 ±0.2V; 1.8 V ±0.15 V  
t
, t  
GND  
PZH PHZ  
C
R
R
= 50 pF for V  
= 500 Ω or equivalent  
= 3.0 ± 0.3 V  
L
L
T
CC  
= Z  
of pulse generator (typically 50 Ω)  
OUT  
Figure 6. Test Circuit  
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6
74ALVCH16374  
AC CHARACTERISTICS (t = t = 2.0 ns; C = 50 pF; R = 500 Ω)  
R
F
L
L
Limits  
T
A
= –40°C to +85°C  
V
= 3.0 V to 3.6 V  
V
= 2.7 V  
CC  
Min  
150  
CC  
Symbol  
Parameter  
Waveform  
Max  
Min  
Max  
Unit  
MHz  
ns  
f
Clock Pulse Frequency  
4
4
150  
max  
t
t
Propagation Delay  
CP to On  
1.0  
1.0  
4.2  
4.2  
4.9  
4.9  
PLH  
PHL  
t
t
Output Enable Time to  
High and Low Level  
5
5
1.0  
1.0  
4.8  
4.8  
5.9  
5.9  
ns  
ns  
ns  
PZH  
PZL  
t
t
Output Disable Time From  
High and Low Level  
1.0  
1.0  
4.3  
4.3  
4.7  
4.7  
PHZ  
PLZ  
t
t
Output–to–Output Skew  
(Note 13)  
0.5  
0.5  
0.5  
0.5  
OSHL  
OSLH  
13.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.  
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t  
guaranteed by design.  
) or LOW–to–HIGH (t ); parameter  
OSHL OSLH  
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7
74ALVCH16374  
10 PITCHES  
CUMULATIVE  
TOLERANCE ON  
TAPE  
±0.2 mm  
(±0.008")  
P
0
K
t
P
2
D
TOP  
COVER  
TAPE  
E
A
B
SEE NOTE 2  
+
0
F
W
+
+
K
0
SEE  
B
1
0
D
1
NOTE 2  
P
FOR COMPONENTS  
2.0 mm × 1.2 mm  
AND LARGER  
EMBOSSMENT  
USER DIRECTION OF FEED  
CENTER LINES  
OF CAVITY  
FOR MACHINE REFERENCE  
ONLY  
INCLUDING DRAFT AND RADII  
CONCENTRIC AROUND B  
0
*TOP COVER  
TAPE THICKNESS (t )  
1
0.10 mm  
(0.004") MAX.  
R MIN.  
TAPE AND COMPONENTS  
SHALL PASS AROUND RADIUS R"  
WITHOUT DAMAGE  
EMBOSSED  
CARRIER  
BENDING RADIUS  
EMBOSSMENT  
100 mm  
(3.937")  
MAXIMUM COMPONENT ROTATION  
10°  
1 mm MAX  
TYPICAL  
COMPONENT CAVITY  
CENTER LINE  
TAPE  
1 mm  
(0.039") MAX  
250 mm  
(9.843")  
TYPICAL  
COMPONENT  
CENTER LINE  
CAMBER (TOP VIEW)  
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm  
Figure 7. Carrier Tape Specifications  
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)  
Tape  
Size  
B
1
Max  
D
D
E
F
K
P
P
0
P
2
R
T
W
1
24mm  
20.1mm 1.5 + 0.1mm  
(0.791")  
1.5mm  
Min  
(0.060")  
1.75  
11.5  
11.9 mm  
Max  
(0.468")  
16.0  
±0.1 mm  
(0.63  
4.0  
±0.1 mm  
(0.157  
2.0  
±0.1 mm  
(0.079  
30 mm  
(1.18")  
0.6 mm  
(0.024")  
24.3 mm  
(0.957")  
-0.0  
(0.059  
+0.004" -0.0)  
±0.1 mm ±0.10 mm  
(0.069  
±0.004")  
(0.453  
±0.004")  
±0.004")  
±0.004")  
±0.004")  
14.Metric Dimensions Govern–English are in parentheses for reference only.  
15.A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to  
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.  
http://onsemi.com  
8
74ALVCH16374  
t MAX  
13.0 mm ±0.2 mm  
(0.512" ±0.008")  
1.5 mm MIN  
(0.06")  
20.2 mm MIN  
(0.795")  
50 mm MIN  
(1.969")  
A
FULL RADIUS  
G
Figure 8. Reel Dimensions  
REEL DIMENSIONS  
Tape Size  
A Max  
G
t Max  
24 mm  
360 mm  
(14.173")  
24.4 mm + 2.0 mm, -0.0  
(0.961" + 0.078", -0.00)  
30.4 mm  
(1.197")  
DIRECTION OF FEED  
BARCODE LABEL  
POCKET  
HOLE  
Figure 9. Reel Winding Direction  
http://onsemi.com  
9
74ALVCH16374  
TAPE TRAILER  
(Connected to Reel Hub)  
NO COMPONENTS  
160 mm MIN  
TAPE LEADER  
NO COMPONENTS  
400 mm MIN  
COMPONENTS  
CAVITY TOP TAPE  
TAPE  
DIRECTION OF FEED  
Figure 10. Tape Ends for Finished Goods  
User Direction of Feed  
Figure 11. Reel Configuration  
F
K
G
L
48 Leads  
Figure 12. Package Footprint  
http://onsemi.com  
10  
74ALVCH16374  
PACKAGE DIMENSIONS  
TSSOP  
DT SUFFIX  
CASE 1201–01  
ISSUE A  
48X K REF  
K
K1  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
M
S
S
V
0.12 (0.005)  
T U  
J
J1  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD FLASH, PROTRUSIONS OR GATE  
BURRS. MOLD FLASH OR GATE BURRS  
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.  
4. DIMENSION K DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN  
EXCESS OF THE K DIMENSION AT MAXIMUM  
MATERIAL CONDITION.  
48  
25  
SECTION N–N  
B
–U–  
L
N
5. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
1
24  
6. DIMENSIONS A AND B ARE TO BE  
DETERMINED AT DATUM PLANE -W-.  
MILLIMETERS  
INCHES  
A
–V–  
PIN 1  
DIM MIN  
MAX  
12.60  
6.20 0.236  
1.10 ---  
MIN  
0.488  
MAX  
0.496  
0.244  
0.043  
0.006  
0.030  
IDENT.  
A
B
12.40  
6.00  
---  
N
C
M
F
D
0.05  
0.50  
0.15 0.002  
0.75 0.020  
F
0.25 (0.010)  
DETAIL E  
G
H
0.50 BSC  
0.0197 BSC  
0.37  
0.09  
0.09  
0.17  
0.17  
7.95  
0
--- 0.015  
0.20 0.004  
0.16 0.004  
0.27 0.007  
0.23 0.007  
8.25 0.313  
---  
0.008  
0.006  
0.011  
0.009  
0.325  
8
J
J1  
K
D
C
K1  
L
–W–  
0.076 (0.003)  
M
8
0
_
_
_
_
DETAIL E  
–T–  
SEATING  
PLANE  
H
G
http://onsemi.com  
11  
74ALVCH16374  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes  
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular  
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,  
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or  
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable  
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031  
Phone: 81–3–5740–2700  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada  
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
Email: r14525@onsemi.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800–282–9855 Toll Free USA/Canada  
74ALVCH16374/D  

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