SM72442MTE_技术文档

May 12, 2011

SM72442

Programmable Maximum Power Point Tracking Controller

for Photovoltaic Solar Panels

General Description

Features

The SM72442 is a programmable MPPT controller capable of

controlling four PWM gate drive signals for a 4-switch buck-

boost converter. The SM72442 also features a proprietary

algorithm called Panel Mode which allows for the panel to be

connected directly to the output of your power optimizer cir-

cuit. Along with the SM72295 (Photovoltaic Full Bridge Driv-

er), it creates a solution for an MPPT configured DC-DC

converter with efficiencies up to 99.5%. Integrated into the

chip is an 8-channel, 12 bit A/D converter used to sense input

and output voltages and currents, as well as board configu-

ration. Externally programmable values include maximum

output voltage and current as well as different settings forslew

rate, soft-start and Panel Mode.

Renewable Energy Grade

■

Programmable maximum power point tracking

Photovoltaic solar panel voltage and current diagnostic

Single inductor four switch buck-boost converter control

I2C interface for communication

VOUT Overvoltage protection

Over-current protection

Package

TSSOP-28

■

Block Diagram

30134302

FIGURE 1. Block Diagram

301343

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2

Connection Diagram

30134303

FIGURE 3. Top View

TSSOP-28

Ordering Information

Order Number

Description

NSC Package Drawing

Supplied As

Package Top Marking

SM72442MTX

TSSOP-28

MTC28

2500 Units in Tape and

Reel

SO2442

SM72442MTE

SM72442MT

MTC28

250 Units in Tape and

Reel

SO2442

48 Units in Rail

3

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Pin Descriptions

1

Name

RST

Description

Active low signal. External reset input signal to the digital circuit.

Reserved for test only. This pin should be grounded.

2

NC1

3

VDDD

Digital supply voltage. This pin should be connected to a 5V supply, and bypassed to VSSD with a 0.1 µF monolithic

ceramic capacitor.

4

5

VSSD

NC2

I2C0

I2C1

SCL

SDA

NC3

Digital ground. The ground return for the digital supply and signals.

No Connect. This pin should be pulled up to the 5V supply using 10k resistor.

Addressing for I2C communication.

6

7

Addressing for I2C communication.

8

I2C clock.

9

I2C data.

10

11

Reserved for test only. This pin should be grounded.

PM_OUT When Panel Mode is active, this pin will output a 400 kHz square wave signal with amplitude of 5V. Otherwise, it

stays low.

12

VDDA

Analog supply voltage. This voltage is also used as the reference voltage. This pin should be connected to a 5V

supply, and bypassed to VSSA with a 1 µF and 0.1 µF monolithic ceramic capacitor.

13

14

VSSA

A0

Analog ground. The ground return for the analog supply and signals.

A/D Input Channel 0. Connect a resistor divider to 5V supply to set the maximum output voltage. Please refer to

the application section for more information on setting the resistor value.

15

16

AVIN

A2

Input voltage sensing pin.

A/D Input Channel 2. Connect a resistor divider to a 5V supply to set the condition to enter and exit Panel Mode

(PM). Refer to configurable modes for SM72442 in the application section.

17

18

AVOUT Output voltage sensing pin.

A4

A/D Input Channel 4. Connect a resistor divider to a 5V supply to set the maximum output current. Please refer to

the application section for more information on setting the resistor value.

Input current sensing pin.

19

20

AIIN

A6

A/D Input Channel 6. Connect a resistor divider to a 5V supply to set the output voltage slew rate and various PM

configurations. Refer to configurable modes for SM72442 in the application section.

21

22

23

24

25

26

27

28

AIOUT Output current sensing pin.

I2C2

NC4

LIB

Addressing for I2C communication.

No Connect. This pin should be connected with 60.4k pull-up resistor to 5V.

Low side boost PWM output.

HIB

HIA

LIA

High side boost PWM output.

High side buck PWM output.

Low side buck PWM output.

PM

Panel Mode Pin. Active low. Pulling this pin low will force the chip into Panel Mode.

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4

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Recommended Operating

Conditions

Operating Temperature

-40°C to 105°C

V_ASupply Voltage

V_DSupply Voltage

Digital Input Voltage

Analog Input Voltage

Junction Temperature

+4.75V to +5.25V

+4.75V to V_A

0 to V_A

Analog Supply Voltage V_A

(VDDA - VSSA)

Digital Supply Voltage V_D

(VDDD - VSSD)

-0.3 to 6.0V

-0.3 to V_A+0.3V

max 6.0V

-0.3 to V_A+0.3V

0 to V_A

Voltage on Any Pin to GND

-40°C to 125°C

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Storage Temperature Range

ESD Rating

±10 mA

±20 mA

-65°C to +150°C

(Note 2)

Human Body Model

2 kV

Specifications in standard typeface are for T_J= 25°C, and those in boldface type apply over the full operating junction temperature

range.(Note 3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ANALOG INPUT CHARACTERISTICS

AVin, AIin

0 to V_A

Input Range

AVout, AIout

-

V

I_DCL

DC Leakage Current

-

±1

-

µA

pF

Track Mode

Hold Mode

33

3

C_INA

Input Capacitance (Note 4)

-

DIGITAL INPUT CHARACTERISTICS

V_IL

Input Low Voltage

-

2.8

-

0.8

-

V

V_IH

C_IND

I_IN

Input High Voltage

-

2

Digital Input Capacitance (Note 4)

Input Current

4

pF

µA

-

±0.01

±1

DIGITAL OUTPUT CHARACTERISTICS

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_SOURCE= 200 µA V_A= V_D= 5V

V_D- 0.5

-

V

I_SINK= 200 µA to 1.0 mA V_A= V_D= 5V

-

0.4

Hi-Impedance Output Leakage

Current

I_OZH, I_OZL

C_OUT

V_A= V_D= 5V

±1

4

µA

pF

Hi-Impedance Output

Capacitance (Note 4)

2

5

POWER SUPPLY CHARACTERISTICS (C_L= 10 pF)

Analog and Digital Supply

Voltages

V_A,V_D

4.75

5.25

V

V_A≥ V_D

I_A+ I_D

P_C

Total Supply Current

Power Consumption

V_A= V_D= 4.75V to 5.25V

-

11.5

57.5

15

mA

78.75

mW

PWM OUTPUT CHARACTERISTICS

f_PWMPWM switching frequency

220

kHz

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 4: Not tested. Guaranteed by design.

5

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photovoltaic module. MPPT performance is very fast. Con-

vergence to the maximum power point of the module typically

occurs within 0.01s. This enables the controller to maintain

optimum performance under fast-changing irradiance condi-

tions.

Operation Description

OVERVIEW

The SM72442 is a programmable MPPT controller capable of

outputting four PWM gate drive signals for a 4-switch buck-

boost converter with an independent Panel Mode. The typical

application circuit is shown in Figure 2.

Transitions between buck, boost, and Panel Mode are

smoothed and advanced digital PWM dithering techniques

are employed to increase effective PWM resolution. Output

voltage and current limiting functionality are integrated into

the digital control logic. The controller is capable of handling

both shorted and no-load conditions and will recover smoothly

from both conditions.

The SM72442 uses an advanced digital controller to generate

its PWM signals. A maximum power point tracking (MPPT)

algorithm monitors the input current and voltage and controls

the PWM duty cycle to maximize energy harvested from the

30134304

FIGURE 4. High Level State Diagram for Startup

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6

STARTUP

CURRENT LIMIT SETTING

SM72442 has a soft start feature that will ramp its output volt-

age for a fixed time of 250ms.

Maximum output current can be set by changing the resistor

divider on A4 (pin 18). Refer to Figure 2. Overcurrent at the

output is detected when the voltage on AIOUT (pin 21) equals

the voltage on A4 (pin 18). The voltage on A4 can be set by

a resistor divider connected to 5V whereas the voltage on

AIOUT can be set by a current sense amplifier.

If no output current is detected during soft-start time, the chip

will then be in Panel Mode for 60 seconds. A counter will start

once the minimum output current threshold is met (set by ADC

input channel 4). During these 60 seconds, any variation on

the output power will not cause the chip to enter MPPT mode.

Once 60 seconds have elapsed, at a certain power level vari-

ation at the output (set by ADC input channel 2) will engage

the chip in MPPT mode.

AVIN PIN

AVIN is an A/D input to sense the input voltage of the

SM72442. A resistor divider can be used to scale max voltage

to about 4V, which is 80% of the full scale of the A/D input.

If the output current exceeded the current threshold set at

A/D Channel 6 (A6) during soft-start, the chip will then engage

in MPPT mode.

CONFIGURABLE SETTINGS

A/D pins A0, A2, A4, and A6 are used to configure the be-

havior of the SM72442 by adjusting the voltage applied to

them. One way to do this is through resistor dividers as shown

in Figure 2, where RT1 to RT4 should be in the range of 20

kΩ.

Different conditions to enter and exit Panel Mode can be set

on the ADC input channel 2. Listed below are different con-

ditions that a user can select on pin A2. “1:1”refers to the state

in which the DC/DC converter operates with its output voltage

equal to its input voltage (also referred to as “Buck-Boost”

mode on Figure 4.)

A2

Entering Panel Mode

2s in 1:1 Mode

Exiting Panel Mode

3.1% power variation

1.6% power variation

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

1.56 V

0.94 V

0.31 V

1s in 1:1 Mode

0.4s in 1:1 Mode

0.2s in 1:1 Mode

2s in 1:1 Mode

30134305

1s in 1:1 Mode

FIGURE 5. Startup Sequence

0.4s in 1:1 Mode

0.2s in 1:1 Mode

MAXIMUM OUTPUT VOLTAGE

Maximum output voltage on the SM72442 is set by resistor

divider ratio on pin A0. (Please refer to Figure 2 Typical Ap-

plication Circuit).

The user can also select the output voltage slew rate, mini-

mum current threshold and duration of Panel Mode after the

soft-start period has finished, by changing the voltage level

on pin A6 which is the input of ADC channel 6.

Where RT1 and RB1 are the resistor divider on the ADC pin

A0 and RFB1 and RFB2 are the output voltage sense resis-

tors. A typical value for RFB2 is about 2 kΩ

A6

Output Voltage

Slew Rate Limit

Starting Panel

Mode Time

MPPT Exit

Threshold

MPPT Start

Threshold

Starting boost ratio

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

1.56 V

0.94 V

0.31 V

Slow

Not applicable

0 mA

1:1

60s

75mA

125mA

500mA

Slow

0s

120s

300mA

1:1

Slow

1:1

Slow

Not applicable

60s

1:1.2

1:1

Slow

Fast

60s

1:1

No slew rate limit

60s

1:1

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PARAMETER DEFINITIONS

PANEL MODE PIN (PM) PIN

Output Voltage Slew Rate Limit Settling Time: Time con-

stant of the internal filter used to limit output voltage change.

For fast slew rate, every 1V increase, the output voltage will

be held for 30 ms whereas in a slow slew rate, the output

voltage will be held for 62 ms for every 1V increase. (See

Figure 6).

The SM72442 can be forced into Panel Mode by pulling the

PM pin low. One sample application is to connect this pin to

the output of an external temperature sensor; therefore when-

ever an over-temperature condition is detected the chip will

enter a Panel Mode.

Once Panel Mode is enabled either when buck-boost mode

is entered for a certain period of time (adjustable on channel

2 of ADC) or when PM is pulled low, the PM_OUT pin will

output a 400 kHz square wave signal. Using a gate driver and

transformer, this square wave signal can then be used to drive

a Panel Mode FET as shown in Figure 7.

Starting PM Time: After initial power-up or reset, the output

soft-starts and then enters Panel Mode for this amount of

time.

MPPT Exit Threshold and MPPT Start Threshold: These

are the hysteretic thresholds for Iout_th.

Starting Boost Ratio – This is the end-point of the soft-start

voltage ramp. 1:1 ratio means it stops when Vout = Vin, 1:1.2

means it stops when Vout = 1.2 x Vin.

30134313

FIGURE 6. Slew Rate Limitation Circuit

30134307

FIGURE 7. Sample Application for Panel Mode Operation

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8

RESET PIN

specially important when sampling dynamic signals. Also im-

portant when sampling dynamic signals is a band-pass or low-

pass filter which reduces harmonic and noise in the input.

These filters are often referred to as anti-aliasing filters.

When the reset pin is pulled low, the chip will cease its normal

operation and turn-off all of its PWM outputs including the

output of PM_OUT pin. Below is an oscilloscope capture of a

forced reset condition.

30134309

FIGURE 9. Equivalent Input Circuit

DIGITAL INPUTS and OUTPUTS

The digital input signals have an operating range of 0V to

V_A, where V_A= VDDA – VSSA. They are not prone to latch-

up and may be asserted before the digital supply V_D, where

V_D= VDDD – VSSD, without any risk. The digital output sig-

nals operating range is controlled by V_D. The output high

voltage is V_D– 0.5V (min) while the output low voltage is 0.4V

(max).

30134308

FIGURE 8. Forced Reset Condition

As seen in Figure 8, the initial value for output voltage and

load current are 28V and 1A respectively. After the reset pin

is grounded both the output voltage and load current de-

creases immediately. MOSFET switching on the buck-boost

converter also stops immediately. VLOB indicates the low

side boost output from the SM72295.

SDA and SCL OPEN DRAIN OUTPUT

SCL and SDA output is an open-drain output and does not

have internal pull-ups. A “high” level will not be observed on

this pin until pull-up current is provided by some external

source, typically a pull-up resistor. Choice of resistor value

depends on many system factors; load capacitance, trace

length, etc. A typical value of pull- up resistor for SM72442

ranges from 2 kΩ to 10 kΩ. For more information, refer to the

I2C Bus specification for selecting the pull-up resistor value .

The SCL and SDA outputs can operate while being pulled up

to 5V and 3.3V.

ANALOG INPUT

An equivalent circuit for one of the ADC input channels is

shown in Figure 9. Diode D1 and D2 provide ESD protection

for the analog inputs. The operating range for the analog in-

puts is 0V to V_A. Going beyond this range will cause the ESD

diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 9 has a typical value of 3 pF and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch; it is typ-

ically 500Ω. Capacitor C2 is the ADC sampling capacitor; it is

typically 30 pF. The ADC will deliver best performance when

driven by a low-impedance source (less than 100Ω). This is

I2C CONFIGURATION REGISTERS

The operation of the SM72442 can be configured through its

I2C interface. Complete register settings for I2C lines are

shown below.

reg0 Register Description

Bits

55:40

39:30

Field

RSVD

ADC6

Reset Value

16'h0

R/W

R

Bit Field Description

Reserved for future use.

10'h0

R

Analog Channel 6 (slew rate detection time constant,

see adc config worksheet)

29:20

19:10

9:0

ADC4

ADC2

ADC0

10'h0

R

Analog Channel 4 (iout_max: maximum allowed output

current)

Analog Channel 2 (operating mode, see adc_config

worksheet)

Analog Channel 0 (vout_max: maximum allowed

output voltage)

reg1 Register Description

Bits

55:43

42

Field

RSVD

Reset Value

13'h0

R/W

R

Bit Field Description

Reserved for future use.

over temperature input to IC

burnin_n

1'h0

R

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reg1 Register Description

Bits

41

Field

pt_n

Reset Value

1'h0

R/W

R

Bit Field Description

over voltage protection input to IC

Internal mppt_start signal (test only)

Voltage out

40

mppt_ok

Vout

Iout

1'h0

R

39:30

29:20

19:10

9:0

10'h0

R

10'h0

R

Current out

Vin

10'h0

R

Voltage in

Iin

10'h0

R

Current in

reg3 Register Description

Bits

55:47

46

Field

RSVD

Reset Value

9'd0

R/W

Bit Field Description

Reserved

overide_adcprog

1'b0

When set to 1'b1,the below overide registers used

instead of ADC

45

44:43

42

RSVD

1'b0

2'd0

1'b0

R/W

Reserved

power_thr_sel

Register override alternative for ADC2[9] when reg3

[46] is set ( 1/2^^5 or 1/2^^6 )

41:40

39:30

29:20

bb_in_ptmode_s

el

2'd0

R/W

Register override alternative for ADC2[8:7] when reg3

[46] is set ( 5%,10%,25% or 50%)

iout_max

10'd1023

Register override alternative when reg3[46] is set for

maximum current threshold instead of ADC ch4

vout_max

Register override alternative when reg3[46] is set for

maximum voltage threshold instead of ADC ch0

19:17

16:14

13:5

4

tdoff

tdon

3'h3

R/W

Dead time Off Time

Dead time On time

dc_open

9'hFF

1'b0

Open loop duty cycle (test only)

Overrides PM pin 28 and use reg3[3]

pass_through_se

l

3

pass_through_m

anual

1'b0

R/W

Control Panel Mode when pass_through_sel bit is 1'b1

2

1

0

bb_reset

1'b0

R/W

Soft reset

clk_oe_manual

Enable the PLL clock to appear on pin 5

Open Loop

operation

Open Loop operation (MPPT disabled, receives duty

cycle command from reg 3b13:5); set to 1 and then

assert & deassert bb_reset to put the device in

openloop (test only)

reg4 Register Description

Bits

55:32

31:24

23:16

15:8

Field

RSVD

Reset Value

24'd0

8'h0

R/W

Bit Field Description

Reserved

Vout offset

Iout offset

Vin offset

Iin offset

Voltage out offset

Current out offset

Voltage in offset

Current in offset

8'h0

7:0

8'h0

reg5 Register Description

Bits

55:40

39:30

29:20

19:10

9:0

Field

Reset Value

15'd0

R/W

Bit Field Description

Reserved

RSVD

iin_hi_th

iin_lo_th

iout_hi_th

iout_lo_th

10'd40

Current in high threshold for start

Current in low threshold for start

Current out high threshold for start

Current out low threshold for start

10'd24

10'd40

10'd24

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10

Using the I2C port, the user will be able to control the duty

cycle of the PWM signal. Input and output voltage and current

offset can also be controlled using I2C on register 4. Control

registers are available for additional flexibility.

The data registers in the SM72442 are selected by the Com-

mand Register. The Command Register is offset from base

address 0xE0. Each data register in the SM72442 falls into

one of two types of user accessibility:

The thresholds iin_hi_th, iin_lo_th, iout_hi_th, iout_lo_th, in

reg5 are compared to the values read in by the ADC on the

AIIN and AIOUT pins. Scaling is set by the scaling of the ana-

log signal fed into AIIN and AIOUT. These 10–bit values

determine the entry and exit conditions for MPPT.

1) Read only (Reg0, Reg1)

2) Write/Read same address (Reg3, Reg4, Reg5)

There are 7 bytes in each register (56 bits), and data must be

read and written in blocks of 7 bytes. Figure 10 depicts the

ordering of the bytes transmitted in each frame and the bits

within each byte. In the read sequence depicted in Figure

11 the data bytes are transmitted in Frames 5 through 11,

starting from the LSByte, DATA1, and ending with MSByte,

DATA7. In the write sequence depicted in Figure 12, the data

bytes are transmitted in Frames 4 through 11. Only the

100kHz data rate is supported. Please refer to “The I2C Bus

Specification” version 2.1 (Doc#: 939839340011) for more

documentation on the I2C bus.

COMMUNICATING WITH THE SM72442

The SCL line is an input, the SDA line is bidirectional, and the

device address can be set by I2C0, I2C1 and I2C2 pins. Three

device address pins allow connection of up to 7 SM72444s to

the same I2C master. A pull-up resistor (10k) to a 5V supply

is used to set a bit 1 on the device address. Device addressing

for slaves are as follows:

I2C0

I2C1

I2C2

Hex

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0

1

0

1

0

1

0

1

0

1

0

1

30134316

FIGURE 10. Endianness Diagram

30134312

FIGURE 11. I2C Read Sequence

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30134314

FIGURE 12. I2C Write Sequence

Noise coupling into digital lines greater than 400 mVp-p (typ-

ical hysteresis) and undershoot less than 500 mV GND, may

prevent successful I2C communication with SM72442. I2C no

acknowledge is the most common symptom, causing unnec-

essary traffic on the bus although the I2C maximum frequency

of communication is rather low (400 kHz max), care still needs

to be taken to ensure proper termination within a system with

multiple parts on the bus and long printed board traces. Ad-

ditional resistance can be added in series with the SDA and

SCL lines to further help filter noise and ringing. Minimize

noise coupling by keeping digital races out of switching power

supply areas as well as ensuring that digital lines containing

high speed data communications cross at right angles to the

SDA and SCL lines.

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Physical Dimensions

30134350

NS Package Drawing MTC28

13

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型号：	SM72442MTE
厂家：	National Semiconductor
描述：	Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels 可编程最大功率点跟踪控制器，用于光伏太阳能电池板电池控制器
文件：	总14页 (文件大小：420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SM72442MTE [NSC]

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SM72442MTX

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SM72445_15