LMH6586VS [NSC]
32x16 Video Crosspoint Switch; 32x16视频交叉点开关
| 型号： | LMH6586VS |
| 厂家： | 
National Semiconductor |
| 描述： | 32x16 Video Crosspoint Switch |
| 文件： | 总24页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 24, 2008
LMH6586
32x16 Video Crosspoint Switch
General Description
Features
The LMH6586 is a non-blocking 32x16 analog video cross-
point switch. It can be used to route standard composite video
signals, (NTSC and PAL) and any one of the 32 inputs can
be routed to any one of the 16 outputs. The LMH6586 can
operate in broadcast mode as well as individual mode. The
outputs have programmable 1X or 2X gain output buffers and
can drive loads of 150Ω. Each input has an integrated DC-
restore clamp for AC-coupled operation.
32x16 Non-blocking Switch with buffered inputs and
■
outputs.
100 kHz I2C compatible interface
Individually addressable outputs
Input video clamp
■
■
■
■
■
■
■
■
Selectable output buffer gain (+1V/V or +2V/V)
−3 dB Bandwidth = 66 MHz
DG = 0.05%, DP = 0.05° @ RL = 150Ω
−70 dB off-isolation @ 6 MHz
I2C compatible interface with 2-bit programmable slave
address
The LMH6586 operates from a common single +5V supply for
its analog sections as well as its digital logic and I2C interface.
The LMH6586 also has two types of input signal detection
ideal for security camera monitoring. It can be configured to
output a flag upon the loss of sync with an external voltage
control pin used to set the sync detection threshold level. It
can also be configured to output a flag upon the detection of
presence or absence of video with an 8-level programmable
video detection threshold.
Single +5V supply operation
■
■
■
Input and output amp power shutdowns
Video detect with 8 adjustable programmable threshold
level
The crosspoint switch matrix configuration is programmed via
a 100 kHz I2C compatible interface. The device address is 2-
bit programmable, accommodating up to four LMH6586’s on
a common I2C bus, facilitating expansion of the Crosspoint
matrix.
Sync detect with adjustable programmable threshold level
Extra video output for external sync separator (OUT16)
■
■
Applications
CCTV security systems
■
■
The LMH6586 is offered in a space-saving 80-pin TQFP.
Video routing
Typical Operating Circuit
30056946
LMH™ is a trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation
300569
www.national.com
30056902
FIGURE 1. Functional Diagram
www.national.com
2
Connection Diagram
30056901
Ordering Information
Package
Part Number
Package Marking
Transport Media
NSC Drawing
80-Pin TQFP
LMH6586VS
LMH6586VS
160 Units/Tray
VHB80A
3
www.national.com
Pin Description
Pin #
1
Pin Description
Pin #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Description
GND
VIDEO INPUT 31
VIDEO INPUT 30
VIDEO INPUT 29
VIDEO INPUT 28
VIDEO INPUT 27
VIDEO INPUT 26
VIDEO INPUT 25
VIDEO INPUT 24
VDD +5V SUPPLY
GND
2
VDD +5V SUPPLY
VIDEO INPUT 0
VIDEO INPUT 1
VIDEO INPUT 2
VIDEO INPUT 3
VIDEO INPUT 4
VIDEO INPUT 5
VIDEO INPUT 6
VIDEO INPUT 7
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VIDEO INPUT 23
VIDEO INPUT 22
VIDEO INPUT 21
VIDEO INPUT 20
VIDEO INPUT 19
VIDEO INPUT 18
VIDEO INPUT 17
VIDEO INPUT 16
VDD +5V Supply
GND
VDD +5V SUPPLY
VIDEO INPUT 8
VIDEO INPUT 9
VIDEO INPUT 10
VIDEO INPUT 11
VIDEO INPUT 12
VIDEO INPUT 13
VIDEO INPUT 14
VIDEO INPUT 15
GAIN
REF_CAP1
VIDEO OUTPUT 16
VIDEO OUTPUT 15
VIDEO OUTPUT 14
VIDEO OUTPUT 13
VIDEO OUTPUT 12
VIDEO OUTPUT 11
VIDEO OUTPUT 10
VIDEO OUTPUT 9
VIDEO OUTPUT 8
GND
VDD +5V SUPPLY
GND
REF_CAP2 (external coupling cap 0.1 μF)
SSR (Sync separator reference)
V_CLAMP
R_EXT (external resistor for bias)
GND
VDD +5V SUPPLY
POWER SAVE ENABLE (complete chip)
ADDRESS SELECT [0]
ADDRESS SELECT [1]
SDA
VDD +5V SUPPLY
VIDEO OUTPUT 7
VIDEO OUTPUT 6
VIDEO OUTPUT 5
VIDEO OUTPUT 4
VIDEO OUTPUT 3
VIDEO OUTPUT 2
VIDEO OUTPUT 1
VIDEO OUTPUT 0
SCL
INPUT DETECT FLAG
DIGITAL VDD +5V SUPPLY
DIGITAL GND
GND
VDD +5V SUPPLY
RESET
www.national.com
4
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
−65°C to +150°C
300°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+150°C
Operating Ratings (Note 1)
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Supply Voltage (VDD
)
+5V ±10%
−40°C ≤ TA ≤85°C
25°C/W
2500V
250V
5V
Ambient Temperature Range
Supply Voltage (VDD
)
θJA
Video Input Voltage Range, VIN
−0.3V to VDD +0.3V
Electrical Characteristics Unless otherwise specified, all limits guaranteed for TA = 25°C, VDD = +5V,
REXT = 10 kΩ 1%, VCLAMP = 0.3V, RL = 150Ω, CL = 12 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Specifications
VDD
IDD
Operating Supply Voltage
Supply Current
4.5
5.5
360
1.4
2.07
1.03
3
V
No Load, AV = 1 V/V
300
mA
μA
Power Save Supply Current
Gain
No Load, AV = 1 V/V
2x Gain Buffer
1x Gain Buffer
AV = 1 V/V
AV
1.92
0.95
2.00
0.99
1.2
V/V
Gain Matching (Ch to Ch)
Output Offset Voltage
%
ΔAV_CH-CH
VOS
AV = 1 V/V, No Load (referenced to
DC restored input)
60
mV
VDET_LSB Video Detect Threshold LSB
VDET Video Detect Threshold Offset
85
95
105
mV
mV
Video detection threshold offset
measured above sync tip
±50
AC Specifications
BWSS
BWLS
tr/tf
Small Signal Bandwidth (−3 dB)
VOUT = 20 mVPP
66
29
MHz
MHz
ns
Large Signal Bandwidth (−3 dB)
Rise/Fall Time
VOUT = 1.5 VPP
10% to 90%, VOUT = 2 VPP
50% to 50%, VOUT = 2 VPP
50% to 50%, VOUT = 2 VPP
f = 6 MHz, AV = 2 V/V
f = 6 MHz, AV = 2 V/V
AV = 2 V/V, 3.5 MHz
AV = 2 V/V, 3.5 MHz
35
tp
Propagation Delay
5
ns
tpCh-Ch
CT
Ch-Ch Propagation Delay
Adjacent CH Crosstalk
5
ns
−58
−70
0.05
0.05
dB
Off Iso
DG
Input-Output Off-Isolation
Differential Gain Error for NTSC
Differential Phase Error for NTSC
dB
%
DP
deg
I2C Interface and Digital Pin Logic Levels
VIL
VIH
IIN
Low Input Voltage
High Input Voltage
Input Current
1.5
V
V
3.3
±1
µA
V
VOL
Low Output Voltage
IOL = 3 mA
0.5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX) and θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: All voltages are measured with respect to GND, unless otherwise specified.
5
www.national.com
30056944
FIGURE 2. Logic Diagram
www.national.com
6
Typical Performance Characteristics
Small Signal Bandwidth
Small Signal Bandwidth
Medium Signal Bandwidth
Large Signal Bandwidth
30056906
30056907
Medium Signal Bandwidth
30056908
30056909
Large Signal Bandwidth
30056911
30056910
7
www.national.com
Small Signal Gain Flatness
Small Signal Gain Peaking
Large Signal Gain Flatness
Small Signal Gain Flatness
Small Signal Gain Peaking
Large Signal Gain Flatness
30056912
30056913
30056915
30056917
30056914
30056916
www.national.com
8
Large Signal Gain Peaking
Adjacent Channel Crosstalk
All Hostile Crosstalk
Large Signal Gain Peaking
Adjacent Channel Crosstalk
All Hostile Crosstalk
30056918
30056920
30056922
30056919
30056921
30056923
9
www.national.com
Off Isolation
Small Signal Pulse Response
30056925
30056924
Small Signal Pulse Response
Small Signal Pulse Response
30056926
30056927
Small Signal Pulse Response
Small Signal Pulse Response with Capacitive Load
30056928
30056929
www.national.com
10
Small Signal Pulse Response with Capacitive Load
Medium Signal Pulse Response
30056930
30056931
Medium Signal Pulse Response
Medium Signal Pulse Response
30056933
30056932
Medium Signal Pulse Response
Medium Signal Pulse Response with Capacitive Load
30056934
30056935
11
www.national.com
Medium Signal Pulse Response with Capacitive Load
Large Signal Pulse Response
30056936
30056937
Large Signal Pulse Response
Large Signal Pulse Response
30056939
30056938
Large Signal Pulse Response
Large Signal Pulse Response with Capacitive Load
30056940
30056941
www.national.com
12
Large Signal Pulse Response with Capacitive Load
Differential Phase
Differential Phase
Differential Gain
30056942
30056947
Differential Phase
30056948
30056949
Differential Phase
30056950
30056951
13
www.national.com
Differential Gain
Differential Gain
30056952
30056953
0.6 black level to 1.3 white Level
Differential Gain
0.6 black level to 1.3 white Level
Harmonic Distortion
30056955
30056954
0.6 black level to 1.3 white Level
Harmonic Distortion
30056956
Note:
Large Signal Input Voltage = 750 mV
Medium Signal Input Voltage = 200 mV
Small Signal Input voltage = 20 mV
www.national.com
14
Application Information
FUNCTIONAL OVERVIEW
SYNC DETECTION
The LMH6586 is a 32 input 16 output analog video Crosspoint
switch. Each input and each output is fully buffered. The out-
put buffers can be programmed to provide 1X or 2X gain.
Each input and each output can be placed in power save
mode individually using the input and output power save reg-
ister respectively. The Flag pin (pin 75) is used for video
detection and sync detection. The LMH6586 has an additional
17th output which has only a 1X gain output buffer which can
be sent to an external sync separator.
The LMH6586 also features a sync detection circuit that can
detect the loss of sync relative to the presence of sync. An
external voltage control (pin 65, SSR) is used to set the de-
sired threshold level using a resistor divider network. For
correct operation the recommended voltage level at the SSR
pin is 0.35V.
INPUT DETECT FLAG
Pin 75 is an output flag pin whose level will be a logic HIGH,
if either video detection or sync detection is triggered based
on the user-defined video and sync detection configurations
and threshold levels (0x1D). The outputs of both the video
detection and sync detection blocks of all 32 input channels
can be OR’d into this single output flag pin. Registers 0x10 to
0x13 are used to enable or disable the Input Detect Flag fea-
ture for video detect, where the register bit for the input
channel is set to a logic LOW if the feature is to be disabled,
or HIGH if it is to enabled. Similarly, registers 0x14 to 0x17
are used for sync detect. Therefore, the flag will only operate
for the channel(s) and type(s) of detection that are specifically
enabled. The typical flag switching time is 300 ms.
OUTPUT BUFFER GAIN
The LMH6586 has an output buffer with a selectable gain of
1X or 2X. When the GAIN SELECT pin (pin 61) is set to logic
LOW, output channels 0 -15 will have a gain of 1X, and when
it is set to logic HIGH, they will have a gain of 2X. Output
channel 16 has only a 1X gain buffer. This channel output can
be optionally sent to an external sync separator through a 0.1
µF capacitor.
VIDEO DETECTION
The LMH6586 features a video detection circuit that can de-
tect the presence of video relative to the absence of video or
the loss of video relative to the presence of video. The detec-
tion threshold level can be set with a 3-bit programmable
register. Video detection may be implemented in an applica-
tion where there is low level or black level video at steady
state, and when there is a change in video level detected by
the LMH6586, a video recorder is triggered to begin record-
ing. In other implementations, the loss of video may be useful
to detect.
SWITCH MATRIX
The LMH6586 has 512 CMOS analog switches, forming a
32x16 crosspoint switch. The LMH6586 is a non-blocking
Crosspoint switch which means that any one of the 32 inputs
can be routed to any of the 16 outputs. The programming is
done using an I2C interface bus.
DC RESTORATION
The LMH6586 is used only in AC coupled mode using a cou-
pling capacitor of 0.1 µF. Please refer to the following section
for details on how to select a coupling capacitor. Since the
composite video signal swings in the positive direction from
0V to 700 mV and in the negative direction from 0V to −300
mV some level shifting is typically required in a single supply
device such as the LMH6586. The LMH6586 offers an inte-
grated DC restore circuit to enable AC coupled operation.
Each of the 32 video input channels can be configured indi-
vidually to detect video or the loss of video. Registers 0x0C
to 0x0F are used for setting these configurations, where the
register bit for the input channel is set to a logic LOW if loss
of video detection is desired or set to a logic HIGH if presence
of video detection is desired. The 3 least significant bits in
register, 0x1D, are used to set the detection threshold level
in 95 mV increments above the sync tip. Registers 0x04 to
0x07 are read-only registers, whose bits output a logic HIGH
to indicate that video or the loss of video has been detected
on each video input channel.
For video signals without sync tips the LMH6586 cannot be
used. For correct operation the REF_CAP1 pin (pin 21)
should be connected to ground through a 0.1 µF capacitor.
AC COUPLING
TABLE 1. Video Detect Reference Voltage
The LMH6586 offers an integrated DC restoration clamp cir-
cuit, which is used to clamp the sync tip of the input video
signal to the V_CLAMP level during AC coupled operation.
For this operation, the CLAMP ENABLE (pin 21) must be set
to logic HIGH. For AC-coupled operation, the LMH6586 re-
quires video signals with sync tips.
0x1D [2:0]
Threshold level above the sync tip*
0
0
0
1
1
0
0
1
1
0
491 mV
587 mV
683 mV
778 mV
873 mV
968 mV
1062 mV
1156 mV
0
0
0
1
1
1
1
1
0
1
0
1
0
1
When AC-coupling, the LMH6586 will restore the DC level by
clamping the sync tip of the input video signal to the
V_CLAMP level, which is adjustable within the range of 0.3V
to 1V at pin 66 via an external voltage. For optimum perfor-
mance and minimized power consumption, V_CLAMP is rec-
ommended to be set at 300 mV. Therefore, the bottom of the
sync tip will be clamped to 300 mV above ground, and the
peak white video level would be at 1.3V.
* See Electrical Characteristics – DC Specifications
15
www.national.com
Cap Discharge Time T = Line Period – Sync Timing
T = 63.5 µs – 4.7 µs
T= 58.8 µs
Discharge current I = 1.37 µA
Charge Q = I*T
Q = 1.37 µA * 58.8 µs
Q = 80.55 pC
Q = C*V
C = Q/V
Typical acceptable voltage drop V = 0.1% of 700 mV
V = 0.7 mV
30056958
Capacitor Value C = 80.55 pC/ 0.7 mV
C = 0.115 µF
FIGURE 3. Input Video Signal Before DC Restore Clamp
Thus the suggested AC coupling capacitor value is 0.1 µF.
VIDEO INPUTS AND OUTPUTS
The LMH6586 has 32 inputs which accept standard compos-
ite video signals (NTSC and PAL). Each input is buffered
before the switch matrix. Each input can be routed to all 16
outputs at a time. Each input can be individually placed in
power save mode by shutting down the respective input am-
plifier using the input power save registers. The inputs of the
LMH6586 are high impedance. The LMH6586 works only in
AC coupled mode thus each video input needs to be con-
nected to a 0.1 µF coupling capacitor for proper operation.
The LMH6586 has 16 video outputs each of which is buffered
through a programmable 1X or 2X gain output buffer. The
outputs are capable of driving 150Ω loads. The output signal
sync tip is set to 300 mV for a gain of 1X or 600 mV for a gain
of 2X (It is basically set to the V_CLAMP voltage level) Each
output can be individually placed in power save mode by
shutting down the respective output amplifier using the output
power save registers. When disabled the outputs are high
impedance, thus enabling multiple outputs to be connected
together for expanding the Crosspoint matrix. Output short
circuit protection is not provided.
30056959
FIGURE 4. Input Video Signal After DC Restore Clamp
The equivalent DC restore clamp circuit is shown below.
INPUT EXPANSION
The LMH6586 has the capability for creating larger switching
matrices. Depending on the number of input and output chan-
nels required, the number of IC’s required can be calculated.
To implement 128 X 16 non-blocking matrix arrange the build-
ing blocks in a grid. The inputs are connected in parallel while
the outputs are wired-or together. When using this configu-
ration care must be taken to ensure that only one of the four
outputs is active. The other three outputs should be placed in
power save mode by using the appropriate power save bit in
the power save registers. By doing so the loading effects from
the disabled outputs are minimized.
30056957
FIGURE 5. Clamp Circuit
Typically the clamp voltage is set to 300 mV. Thus during the
sync timing the clamp circuit amplifier sources current and the
coupling capacitor will not discharge. However, during the
active video amplifier will sink current and cause the coupling
capacitor to discharge through the 75Ω resistor. To limit this
discharge to an acceptable value we must choose an appro-
priate value of the coupling capacitor. The value of the DC
coupling capacitor for each input is calculated as follows:
The figure below shows the 128 input X 16 output switching
matrix using 4 LMH6586’s. To construct larger matrices use
the same technique with more devices.
Since the LMH6586 is two bit addressable up to 4 LMH6586’s
can be connected to a common I2C bus. For more devices
additional I2C buses will be required.
www.national.com
16
ration, the traces that are nearest each other will exhibit a
mutual inductance increasing the total inductance. This series
inductance causes the amplitude response to increase or
peak at higher frequencies, offsetting the roll off from the par-
asitic capacitance. Another solution is to add a small-value
inductor to the output.
THERMAL MANAGEMENT
The LMH6586 operates on a +5V supply and draws a load
current of approximately 300 mA. Thus it dissipates approxi-
mately 1.75W of power. In addition, each equivalent video
load (150Ω) connected to the outputs should be budgeted 30
mW of power.
The following calculations show the thermal resistance, θJA
,
required, to ensure safe operation and to prevent exceeding
the maximum junction temperature, given the maximum pow-
er dissipation.
30056945
PDMAX = (TJMAX – TAMAX)/θJA
FIGURE 6. 128 x 16 Crosspoint Array
DRIVING CAPACITIVE LOAD
Where:
•
•
•
TJMAX = Maximum junction temperature = 150°C
TAMAX = Maximum ambient temperature = +85°C
When many outputs are wired together as in the case of ex-
pansion each output buffer sees the normal load impedance
and the disabled impedance of all the other outputs. This
impedance has a resistive and a capacitive component. The
resistive components reduce the total effective load for the
driving output. Total capacitance is the sum of the capaci-
tance of all the outputs and depends on the size of the matrix.
As the size of the matrix increases, the length of the PC board
traces also increases, adding more capacitance. The output
buffers have been designed to drive more than 30 pF of ca-
pacitance while still maintaining a good AC response. If the
output capacitance exceeds this amount then the AC re-
sponse will be degraded. To prevent this, one option is to
reduce the number of output wired-or together by using more
LMH6586’s. The other option is to put a resistor in series with
the output before the capacitive load to limit excessive ringing
and oscillations.
θ
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
Where:
•
•
•
•
•
VS = Supply voltage = 5V
ISMAX = Maximum quiescent supply current = 300 mA
VOUT = Maximum output voltage of the application = 2.6V
RL = Load resistance tied to ground = 150Ω
n = 1 to 16 channels
A low pass filter is created from the series resistor and para-
sitic capacitance to ground. A single R-C does not affect the
performance at video frequencies, however, in large system,
there may be many such R-Cs cascaded in series. This may
result in high frequency roll off resulting in “softening of the
picture”. There are two solutions to improve performance in
this case. One way is to design the PC board traces with some
inductance. By routing the traces in a repeating “S” configu-
Calculating :
PDMAX = 2.2656
The required θJA to dissipate PDMAX is = (TJMAX – TAMAX)/
PDMAX
The table below shows the θJA values with airflow and differ-
ent heatsinks.
LMH6586VS 80-Pin TQFT
LMHXPT
0 LFPM @ 0 LFPM @
0 LFPM @ 0 LFPM @ 225 LFPM 500 LFPM
0.50 watt
1.0watt
2.0 watt
0.2.8 watt @ 2.8 watt @ 2.8 watt
Analog Video Crosspoint Board
NO Heat Sink
32.2
25.5
30.9
24.6
29.4
23.6
28.6
22.9
26.8
19.2
25.3
15.9
Small Tower
x y = 9.57x9.69 mm/ht. 6.28 mm
Aluminum 12 rail
x y = 9.82x10.73 mm/ht.10.07 mm
25.2
24.4
24.2
24.1
23.3
23.9
23.0
22.1
22.9
22.2
21.3
22.4
16.4
15.6
18.2
14.2
13.6
15.4
Anodized 9 rail
x y = 6.10x7.30 mm/ht. 13.67 mm
Round Tower
diameter = 14.35 mm/ht. 4.47 mm
17
www.national.com
REXT RESISTOR
power-up default Slave Device Address of the LMH6586 is
0x00, it can be programmed via pins 70 and 71 to accommo-
date up to four LMH6586 devices on a common I2C bus. With
the default Slave Device Address of “000 0011,” the address
byte of the LMH6586 for writing is 0x06 and the address for
reading is 0x07, since the first byte is composed of both the
7-bit address and the read/write bit. Figure 7 and Figure 8
show a write and read sequence on the I2C compatible inter-
face.
The REXT external resistor (Pin 67) establishes the internal
bias current and precise reference voltage for the LMH6586.
For optimal performance, REXT should be a 10 kΩ 1% pre-
cision resistor with a low temperature coefficient to ensure
proper operation over a wide temperature range. Using a
REXT resistor with less precision may result in reduced per-
formance against temperature, supply voltage, input signal,
or part-to-part variations.
WRITE SEQUENCE
SYNC SEPARATOR OUT (OUT 16)
The write sequence begins with a start condition, which con-
sists of the master pulling SDA low while SCL is held high.
Assuming that the default Slave Device Address is used, the
Write Address, 0x00, is sent next. Each byte that is sent is
followed by an acknowledge bit. When SCL is high the master
will release the SDA line. The slave must pull SDA low to ac-
knowledge. The register to be written to is next sent in two
bytes, the least significant byte being sent first. The master
can then send the data, which consists of one or more bytes.
Each data byte is followed by an acknowledge bit. If more than
one data byte is sent the data will increment to the next ad-
dress location. See Figure 7.
In addition to the 16 video outputs the LMH6586 has an ad-
ditional 17th output (OUT16). OUT16 only has a gain of 1
buffer at its output. This video signal output can be AC cou-
pled to an external sync separator such as the LMH1980 to
extract the timing information. The value of the coupling ca-
pacitor should be 0.1 µF. Refer to the LMH1980 datasheet for
more information.
LMH6586 I2C INTERFACE
The microcontroller interfaces to the LMH6586 preamp using
the I2C compatible interface. The protocol of the interface be-
gins with a Start Pulse followed by a byte comprised of a 7-
bit Slave Device Address and a Read/Write bit. Although the
30056903
FIGURE 7. I2C Compatible Write Sequence
www.national.com
18
READ SEQUENCE
followed by a byte containing the most significant address
byte, followed by its Acknowledge bit. Then a Stop bit indi-
cates the end of the address only write access. Next the read
data access will be performed beginning with the Start Pulse,
the Slave Device Read Address (0x07), and the Acknowledge
bit. The next 8 bits will be the read data driven out by the
LMH6586 preamp associated with the address indicated by
the two address bytes. Subsequent read data bytes will cor-
respond to the next increment address locations. Each data
byte is separated from the other data bytes by an Acknowl-
edge bit.
Read sequences are comprised of two I2C compatible trans-
fer sequences: The first is a write sequence that only transfers
the two byte address to be accessed. The second is a read
sequence that starts at the address transferred in the previous
address only write access and increments to the next address
upon every data byte read. This is shown in Figure 8. The
write sequence consists of the Start Pulse, the Slave Device
Write Address (0x06 for this example), and the Acknowledge
bit; the next byte is the least significant byte of the address to
be accessed, followed by its Acknowledge bit. This is then
30056904
FIGURE 8. I2C Compatible Read Sequence
REGISTER DESCRIPTIONS
responding to that input in the enable registers should be set
to 1. On setting the appropriate values for the video detect
invert and video and sync detect enable registers the FLAG
pin (pin 75) of the LMH6586 will function as described above.
LMH6586 Video and Sync Detection Output Registers
Registers 0x00 to 0x03 are sync detect out registers and reg-
isters 0x04 to 0x07 are video detect out registers. These are
read only registers and are used to detect sync and video on
each input. In the presence of sync or video, the respective
bit corresponding to each input in each register is 0. In the
absence of sync or video, that bit is 1. Thus these registers
can be used to detect the presence or loss of sync and video.
Video Detect Threshold Level Register
The video detect threshold level is set by programming the
appropriate value in register 0x1Ch. Table 1 shows the volt-
ages for the different levels.
Video Shutdown/Power save Registers
LMH6586 Video & Sync Detection Control Registers
Video Detect Invert Registers:
Each input channel and each output channel can be inde-
pendently placed in shutdown or power save mode. Registers
0x18 to 0x1B are the input power save registers and registers
0x1E and 0x1F are the output power save registers. To place
any channel in power save mode the respective bit in the cor-
responding to that channel is set to 1. To put the whole chip
in power save mode, the power save enable pin (Pin 70)
should be asserted high.
Registers 0X0C to 0X0 Fare video detect invert registers.
These registers are used to set the LMH6586 to either detect
the presence of video or the loss of video. If the respective
bits for each input are set to 1 then the LMH6586 detects the
presence of video on that input and if the bit is set to 0 then
the LMH6586 detects the loss of video on that input.
Video Input Selection Registers
Video/Sync Detect Enable Registers:
The registers 0x20 to 0x30 are used to control the routing of
the LMH6586 crosspoint switch. Each register is used to pro-
gram the routing for the corresponding output channels.
Registers 0x10 to 0x13 are sync detect enable registers and
registers 0x14 to 0x17 are video detect enable registers. To
enable video or sync detect for any input, the enable bit cor-
19
www.national.com
LMH6586 REGISTER MAP
TABLE 2. Video & Sync Detection Output Registers
Register
Address
R/W
Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYNC DETECT OUT
(CH 0-7)
0x00h
0x01h
0x02h
0x03h
0x04h
0x05h
0x06h
0x07h
R
SD_7 SD_6 SD_5 SD_4 SD_3 SD_2 SD_1 SD_0
SD_15 SD_14 SD_13 SD_12 SD_11 SD_10 SD_9 SD_8
SD_23 SD_22 SD_21 SD_20 SD_19 SD_18 SD_17 SD_16
SD_31 SD_30 SD_29 SD_28 SD_27 SD_26 SD_24 SD_24
VD_7 VD_6 VD_5 VD_4 VD_3 VD_2 VD_1 VD_0
VD_15 VD_14 VD_13 VD_12 VD_11 VD_10 VD_9 VD_8
VD_23 VD_22 VD_21 VD_20 VD_19 VD_18 VD_17 VD_16
VD_31 VD_30 VD_29 VD_28 VD_27 VD_26 VD_24 VD_24
SYNC DETECT OUT
(CH 8-15)
R
R
R
R
R
R
R
SYNC DETECT OUT
(CH 16-23)
SYNC DETECT OUT
(CH 24-31)
VIDEO DETECT OUT
(CH 0-7)
VIDEO DETECT OUT
(CH 8-15)
VIDEO DETECT OUT
(CH 16-23)
VIDEO DETECT OUT
(CH 24-31)
TABLE 3. LMH6586 Video & Sync Detection Control Registers
Register
Address
R/W
Default
0x00
Bit 7
RSV
VD_
Bit 6 Bit 5
Bit 4
RSV
VD_
Bit 3
RSV
VD_
Bit 2
RSV
VD_
Bit 1
RSV
VD_
Bit 0
RSV
VD_
RESERVED
0x08h 0x0Bh R/W
RSV
VD_
RSV
VD_
VIDEO DETECT INVERT
(CH 0-7)
0x0Ch
0x0Dh
R/W
R/W
0x00
INV_7 INV_6 INV_5 INV_4 INV_3 INV_2 INV_1 INV_0
VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_
INV_1 INV_1 INV_1 INV_1 INV_1 INV_1 INV_9 INV_8
VIDEO DETECT INVERT
(CH 8-15)
0x00
0x00
0x00
5
4
3
2
1
0
VIDEO DETECT INVERT
(CH 16-23)
0x0Eh
0x0Fh
R/W
R/W
VD_
VD_
VD_
VD_
VD_
VD_
VD_
VD_
INV_2 INV_2 INV_2 INV_2 INV_1 INV_1 INV_1 INV_1
3
2
1
0
9
8
7
6
VIDEO DETECT INVERT
(CH 24-31)
VD_
VD_
VD_
VD_
VD_
VD_
VD_
VD_
INV_3 INV_3 INV_2 INV_2 INV_2 INV_2 INV_2 INV_2
1
0
9
8
7
6
4
4
SYNC DETECT ENABLE
(CH 0-7)
0x10h
0x11h
R/W
R/W
0x00
0x00
SD_
SD_
SD_
SD_
SD_
SD_
SD_
SD_
EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
EN_15 EN_14 EN_1 EN_12 EN_11 EN_10 EN_9 EN_8
3
SYNC DETECT ENABLE
(CH 8-15)
SYNC DETECT ENABLE
(CH 16-23)
0x12h
0x13h
R/W
R/W
0x00
0x00
SD_
SD_
SD_
SD_
SD_
SD_
SD_
SD_
EN_23 EN_22 EN_2 EN_20 EN_19 EN_18 EN_17 EN_16
1
SYNC DETECT ENABLE
(CH 24-31)
SD_
SD_
SD_
SD_
SD_
SD_
SD_
SD_
EN_31 EN_30 EN_2 EN_28 EN_27 EN_26 EN_25 EN_24
9
VIDEO DETECT
ENABLE (CH 0-7)
0x14h
0x15h
R/W
R/W
0x00
0x00
VD_
EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_
VD_
VD_
VD_
VD_
VD_
VD_
VD_
VIDEO DETECT
ENABLE (CH 8-15)
EN_15 EN_14 EN_1 EN_12 EN_11 EN_10 EN_9 EN_8
3
www.national.com
20
Register
Address
R/W
Default
Bit 7
Bit 6 Bit 5
VD_ VD_
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VIDEO DETECT
0x16h
R/W
0x00
VD_
VD_
VD_
VD_
VD_
VD_
ENABLE (CH 16-23)
EN_23 EN_22 EN_2 EN_20 EN_19 EN_18 EN_17 EN_16
1
VIDEO DETECT
0x17h
R/W
0x00
VD_
VD_
VD_
VD_
VD_
VD_
VD_
SD_
ENABLE (CH 24-31)
EN_31 EN_30 EN_2 EN_28 EN_27 EN_26 EN_25 EN_24
9
TABLE 4. LMH6586 Video & Sync Detection Level Registers
Register
Address
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VIDEO DETECTION
THRESHOLD
0x1Dh
R/W
0x00
RSV
VDT_2 VDT_1 VDT_0
TABLE 5. LMH6586 Video Shutdown/Power Save Registers
Register
Address
R/W
Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INPUT SHUTDOWN
(CH 0-7)
0x18h
R/W
0x00
0x00
0x00
0x00
0x00
IN_
IN_
IN_
IN_
IN_
IN_
IN_
IN_
PS_0
PS_7 PS_6 PS_5
IN_ IN_ IN_
PS_15 PS_14 PS_13 PS_12 PS_11 PS_10 PS_9
IN_ IN_ IN_ IN_ IN_ IN_ IN_
PS_23 PS_22 PS_21 PS_20 PS_19 PS_18 PS_17 PS_16
IN_ IN_ IN_ IN_ IN_ IN_ IN_ IN_
PS_4 PS_3 PS_2 PS_1
INPUT SHUTDOWN
(CH 8-15)
0x19h
0x1Ah
0x1Bh
0x1Eh
R/W
R/W
R/W
R/W
IN_ IN_ IN_ IN_
IN_
PS_8
INPUT SHUTDOWN
(CH 16-23)
IN_
INPUT SHUTDOWN
(CH 24-31)
PS_31 PS_30 PS_29 PS_28 PS_27 PS_26 PS_25 PS_24
OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_
OUTPUT
SHUTDOWN
(CH 0-7)
PS_7 PS_6 PS_5
PS_4 PS_3 PS_2 PS_1
PS_0
OUTPUT
SHUTDOWN
(CH 8-15)
0x1Fh
R/W
0x00
OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_
PS_15 PS_14 PS_13 PS_12 PS_11 PS_10 PS_9 PS_8
TABLE 6. LMH6586 Video Input Selection Registers
Bit 7
Register
CH 0 OUTPUT
CH 1 OUTPUT
CH 2 OUTPUT
CH 3 OUTPUT
CH 4 OUTPUT
CH 5 OUTPUT
CH 6 OUTPUT
CH 7 OUTPUT
CH 8 OUTPUT
CH 9 OUTPUT
CH 10 OUTPUT
CH 11 OUTPUT
CH 12 OUTPUT
CH 13 OUTPUT
CH 14 OUTPUT
CH 15 OUTPUT
Address
0x20h
0x21h
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
0x29h
0x2Ah
0x2Bh
0x2Ch
0x2Dh
0x2Eh
0x2Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Bit 6
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
SELECTED INPUT CH[4:0]
CH 16 OUTPUT (FOR
SYNC SEP)
0x30h
R/W
0x00
RSV
SELECTED INPUT CH[4:0]
Note: At initial power-up, all 17 outputs are driven by input channel 0.
21
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
80-Pin TQFP
NS Package Number VHB80A
www.national.com
22
Notes
23
www.national.com
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
Products
www.national.com/amplifiers
Design Support
Amplifiers
WEBENCH
www.national.com/webench
www.national.com/AU
Audio
www.national.com/audio
www.national.com/timing
www.national.com/adc
Analog University
App Notes
Clock Conditioners
Data Converters
Displays
www.national.com/appnotes
www.national.com/contacts
www.national.com/quality/green
www.national.com/packaging
Distributors
www.national.com/displays
www.national.com/ethernet
www.national.com/interface
www.national.com/lvds
Green Compliance
Packaging
Ethernet
Interface
Quality and Reliability www.national.com/quality
LVDS
Reference Designs
Feedback
www.national.com/refdesigns
www.national.com/feedback
Power Management
Switching Regulators
LDOs
www.national.com/power
www.national.com/switchers
www.national.com/ldo
LED Lighting
PowerWise
www.national.com/led
www.national.com/powerwise
Serial Digital Interface (SDI) www.national.com/sdi
Temperature Sensors
Wireless (PLL/VCO)
www.national.com/tempsensors
www.national.com/wireless
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2008 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email: support@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
German Tel: +49 (0) 180 5010 771
English Tel: +44 (0) 870 850 4288
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
www.national.com
相关型号：
©2020 ICPDF网 联系我们和版权申明