DS90CR285 [NSC]
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz; + 3.3V上升沿数据选通LVDS 28位通道链接-66 MHz的
| 型号： | DS90CR285 |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz |
| 文件： | 总16页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
DS90CR285/DS90CR286
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-66 MHz
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, seven 4-bit nibbles or three 9-bit
(byte + parity) and 1 control.
General Description
The DS90CR285 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR286 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 66 MHz, 28 bits of TTL data are trans-
mitted at a rate of 462 Mbps per LVDS data channel. Using
a 66 MHz clock, the data throughput is 1.848 Gbit/s (231
Mbytes/s).
Features
n Single +3.3V supply
<
n Chipset (Tx + Rx) power consumption 250 mW (typ)
<
n Power-down mode ( 0.5 mW total)
n Up to 231 Megabytes/sec bandwidth
n Up to 1.848 Gbps data throughput
n Narrow bus reduces cable size
n 290 mV swing LVDS devices for low EMI
n +1V common mode range (around +1.2V)
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data and one clock, up to 58 conductors are required. With
the Channel Link chipset as few as 11 conductors (4 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
n Compatible with TIA/EIA-644 LVDS standard
>
n ESD Rating 7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagrams
DS90CR285
DS90CR286
DS012910-1
DS012910-27
Order Number DS90CR285MTD
See NS Package Number MTD56
Order Number DS90CR286MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS012910
www.national.com
Pin Diagrams
DS90CR285
DS90CR286
DS012910-21
DS012910-22
Typical Application
DS012910-23
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS90CR285
DS90CR286
1.63 W
1.61 W
Package Derating:
DS90CR285
12.5 mW/˚C above +25˚C
12.4 mW/˚C above +25˚C
DS90CR286
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
ESD Rating
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
>
(HBM, 1.5 kΩ, 100 pF)
7 kV
LVDS Receiver Input
Voltage
Recommended Operating
Conditions
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Min
Nom
Max
Units
Continuous
+150˚C
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0
3.3
3.6
V
Junction Temperature
Storage Temperature
Lead Temperature
−65˚C to +150˚C
−40
+25
+85
2.4
˚C
V
Receiver Input Range
0
(Soldering, 4 sec.)
+260˚C
Supply Noise Voltage (VCC
)
100 mVPP
@
Maximum Package Power Dissipation +25˚C
MTD56 (TSSOP) Package:
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
3.3
V
IOL = 2 mA
0.06
0.3
V
ICL = −18 mA
−0.79
−1.5
V
±
±
10
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
5.1
µA
mA
IOS
Output Short Circuit Current
−60
−120
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
290
450
35
mV
mV
∆VOD
Change in VOD between
Complimentary Output States
VOS
Offset Voltage (Note 4)
1.125
1.25
−3.5
1.375
35
V
∆VOS
Change in VOS between
Complimentary Output States
mV
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE® Current
VOUT = 0V, RL = 100Ω
PWR DWN = 0V,
−5
mA
µA
±
±
10
1
VOUT = 0V or VCC
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
VCM = +1.2V
+100
mV
mV
µA
−100
±
±
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
10
10
µA
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
31
Max
45
Units
mA
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case (with Loads)
RL = 100Ω,
CL = 5 pF,
Worst Case
Pattern
(Figures 1, 2),
TA = −10˚C to
+70˚C
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
32
50
mA
37
55
mA
RL = 100Ω,
CL = 5 pF,
Worst Case
Pattern
(Figures 1, 2),
TA = −40˚C to
+85˚C
38
51
mA
f = 66 MHz
42
10
55
55
mA
µA
ICCTZ
Transmitter Supply Current
Power Down
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current Worst
CL = 8 pF,
Worst Case
Pattern
(Figures 1, 3),
TA = −10˚C to
+70˚C
f = 32.5 MHz
49
53
78
55
65
70
mA
mA
mA
mA
Case
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
105
82
CL = 8 pF,
Worst Case
Pattern
(Figures 1, 3),
TA = −40˚C to
+85˚C
f = 66 MHz
78
10
105
55
mA
µA
ICCRZ
Receiver Supply Current Power
Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T = +25˚C.
A
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V and ∆V ).
OD
OD
Note 4:
V
previously referred as V .
CM
OS
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
LLHT
Parameter
Min
Typ
0.5
0.5
Max
1.5
1.5
5
Units
ns
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
LHLT
ns
TCIT
ns
TCCS
TPPos0
TxOUT Channel-to-Channel Skew (Figure 5)
250
0
ps
Transmitter Output Pulse Position for
Bit0 (Note 7) (Figure 16)
f = 40 MHz
−0.4
3.1
0.4
4.0
7.6
ns
TPPos1
TPPos2
Transmitter Output Pulse Position for
Bit1
3.3
6.8
ns
ns
Transmitter Output Pulse Position for
Bit2
6.5
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4
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
TPPos3
Transmitter Output Pulse Position for
Bit3
10.2
10.4
11.0
ns
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Transmitter Output Pulse Position for
Bit4
13.7
17.3
21.0
−0.4
1.8
13.9
17.6
21.2
0
14.6
18.2
21.8
0.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transmitter Output Pulse Position for
Bit5
Transmitter Output Pulse Position for
Bit6
Transmitter Output Pulse Position for
Bit0 (Note 6) (Figure 16)
f = 66 MHz
Transmitter Output Pulse Position for
Bit1
2.2
2.5
Transmitter Output Pulse Position for
Bit2
4.0
4.4
4.7
Transmitter Output Pulse Position for
Bit3
6.2
6.6
6.9
Transmitter Output Pulse Position for
Bit4
8.4
8.8
9.1
Transmitter Output Pulse Position for
Bit5
10.6
12.8
11.0
13.2
11.3
13.5
Transmitter Output Pulse Position for
Bit6
TCIP
TCIH
TCIL
TxCLK IN Period (Figure 6 )
15
0.35T
0.35T
2.5
T
50
ns
ns
ns
ns
ns
ns
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
TxIN Setup to TxCLK IN (Figure 6)
TxIN Hold to TxCLK IN (Figure 6)
0.5T
0.5T
0.65T
0.65T
TSTC
THTC
TCCD
0
@
TxCLK IN to TxCLK OUT Delay 25˚C,VCC=3.3V
3
3.7
5.5
(Figure 8)
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 14)
10
ms
ns
100
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17)
Receiver Input Strobe Position for Bit 1
Min
Typ
2.2
Max
Units
ns
5.0
5.0
CHLT
2.2
ns
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
f = 40 MHz
1.0
4.5
1.4
2.15
5.8
ns
5.0
ns
Receiver Input Strobe Position for Bit 2
8.1
8.5
9.15
12.6
16.3
19.9
23.6
ns
Receiver Input Strobe Position for Bit 3
11.6
15.1
18.8
22.5
11.9
15.6
19.2
22.9
ns
Receiver Input Strobe Position for Bit 4
ns
Receiver Input Strobe Position for Bit 5
ns
Receiver Input Strobe Position for Bit 6
ns
5
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Receiver Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Parameter
Receiver Input Strobe Position for Bit 0 (Note 6)(Figure 17)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 18)
Min
0.7
2.9
5.1
7.3
9.5
11.7
13.9
490
400
15
Typ
1.1
Max
1.4
Units
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
f = 66 MHz
3.3
3.6
5.5
5.8
7.7
8.0
9.9
10.2
12.4
14.6
12.1
14.3
f = 40 MHz
f = 66 MHz
RCOP
RCOH
RxCLK OUT Period (Figure 7)
T
50
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
6.0
4.0
10.0
6.0
6.5
2.5
6.0
2.5
4.0
5.0
10.0
6.1
RCOL
RSRC
RHRC
RCCD
RxCLK OUT Low Time (Figure 7)
13.0
7.8
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
RxCLK IN to RxCLK OUT Delay (Figure 9)
14.0
8.0
8.0
4.0
6.7
8.0
9.0
10
1
6.6
RPLLS
RPDD
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 15)
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and clock jitter less than 250 ps).
Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
AC Timing Diagrams
DS012910-2
FIGURE 1. “Worst Case” Test Pattern
DS012910-3
DS012910-4
FIGURE 2. DS90CR285 (Transmitter) LVDS Output Load and Transition Times
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6
AC Timing Diagrams (Continued)
DS012910-5
DS012910-6
FIGURE 3. DS90CR286 (Receiver) CMOS/TTL Output Load and Transition Times
DS012910-7
FIGURE 4. DS90CR285 (Transmitter) Input Clock Transition Time
DS012910-8
Note 8: Measurements at V
= 0V
Note 9: TCCS measured between earliest and latest LVDS edges.
DIFF
→
Note 10: TxCLK Differential Low High Edge
FIGURE 5. DS90CR285 (Transmitter) Channel-to-Channel Skew
DS012910-9
FIGURE 6. DS90CR285 (Transmitter) Setup/Hold and High/Low Times
7
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AC Timing Diagrams (Continued)
DS012910-10
FIGURE 7. DS90CR286 (Receiver) Setup/Hold and High/Low Times
DS012910-11
FIGURE 8. DS90CR285 (Transmitter) Clock In to Clock Out Delay
DS012910-12
FIGURE 9. DS90CR286 (Receiver) Clock In to Clock Out Delay
DS012910-13
FIGURE 10. DS90CR285 (Transmitter) Phase Lock Loop Set Time
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8
AC Timing Diagrams (Continued)
DS012910-14
FIGURE 11. DS90CR286 (Receiver) Phase Lock Loop Set Time
DS012910-15
FIGURE 12. Seven Bits of LVDS in Once Clock Cycle
DS012910-16
FIGURE 13. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs
9
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AC Timing Diagrams (Continued)
DS012910-17
FIGURE 14. Transmitter Powerdown DeIay
DS012910-18
FIGURE 15. Receiver Powerdown Delay
DS012910-19
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
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10
AC Timing Diagrams (Continued)
DS012910-28
FIGURE 17. Receiver LVDS Input Strobe Position
11
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AC Timing Diagrams (Continued)
DS012910-20
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 11) + ISI (Inter-symbol interference)(Note 12)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 11: Cycle-to-cycle jitter is less than 250 ps
Note 12: ISI is dependent on interconnect length; may be zero
FIGURE 18. Receiver LVDS Input Skew Margin
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
Applications Information
The DS90CR285 and DS90CR286 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR283, DS90CR284). To upgrade from a 5V to a 3.3V
system the following must be addressed:
3. The receiver powerdown feature when enabled will lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC
.
DS90CR285 Pin Description— Channel Link Transmitter
Pin Name
TxIN
I/O
I
No.
28
4
Description
TTL level input.
TxOUT+
O
O
I
Positive LVDS differential data output.
Negative LVDS differential data output.
TxOUT−
4
TxCLK IN
1
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
TxCLK OUT+
TxCLK OUT−
PWR DWN
O
O
I
1
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
VCC
I
I
I
I
I
I
4
5
1
2
1
3
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90CR286 Pin Description— Channel Link Receiver
Pin Name
RxIN+
I/O
No.
4
Description
I
I
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
RxIN−
4
RxOUT
O
I
28
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
Positive LVDS differential clock input.
Negative LVDS differential clock input.
I
1
O
1
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
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12
Applications Information (Continued)
DS90CR286 Pin Description— Channel Link Receiver (Continued)
Pin Name
PWR DWN
VCC
I/O
No.
Description
TTL level input.When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
I
I
I
I
I
I
I
1
4
GND
5
PLL VCC
PLL GND
LVDS VCC
LVDS GND
1
Power supply for PLL.
2
Ground pin for PLL.
1
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
3
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
<
lengths ( 2m), the media electrical performance is less criti-
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.848 Gbit/s. Additional
applications information can be found in the following Na-
tional Interface Application Notes:
AN = ####
AN-1041
AN-1035
Topic
Introduction to Channel Link
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
PCB Design Guidelines for LVDS and
Link Devices
AN-806
AN-905
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
AN-916
Cable Information
CABLES: A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The 21-
bit CHANNEL LINK chipset (DS90CR215/216) requires four
pairs of signal wires and the 28-bit CHANNEL LINK chipset
(DS90CR285/286) requires five pairs of signal wires. The
ideal cable/connector interface would have a constant 100Ω
differential impedance throughout the path. It is also recom-
mended that cable skew remain below 150 ps ( 66 MHz
clock rate) to maintain a sufficient data sampling window at
the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
plications include flat ribbon, flex, twisted pair and Twin-
Coax. All are available in a variety of configurations and op-
tions. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while Twin-
Coax is good for short and long applications. When using rib-
bon cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 19 shows an example. No additional pull-up or pull-
down resistors are necessary as with some other differential
technologies such as PECL. Surface mount resistors are
recommended to avoid the additional inductance that ac-
13
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ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 20. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
Applications Information (Continued)
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For
a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
DS012910-24
FIGURE 19. LVDS Serialized Link Termination
low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more im-
portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
±
Ground to +2.4V. This allows for a 1.0V shifting of the cen-
ter point due to ground potential differences and common
DS012910-25
mode noise.
FIGURE 20. CHANNEL LINK
Decoupling Configuration
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CNANNEL LINK transmitter remain in TRI-
STATE® until the power supply reaches 2V. Clock and data
outputs will begin to toggle 10 ms after VCC has reached 3V
and the Powerdown pin is above 1.5V. Either device may be
placed into a powerdown mode at any time by asserting the
Powerdown pin (active low). Total power dissipation for each
device will decrease to 5 µW (typical).
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
66 MHz clock has a period of 15 ns which results in a data bit
width of 2.16 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an-
other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each VCC to ground
will minimize the noise passed on to the PLL, thus creating a
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re-
ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re-
tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V
through an internal diode. Current is limited
CC
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
www.national.com
14
Applications Information (Continued)
DS012910-26
FIGURE 21. Single-Ended and Differential Waveforms
15
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS90CR285MTD or DS90CR286MTD
NS Package Number MTD56
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
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Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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