DS90CR286A [NSC]
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel LinkΑ66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel LinkΑ66 MHz; + 3.3V上升沿数据选通LVDS接收器28位通道LinkΑ66兆赫， + 3.3V上升沿频闪LVDS接收器21位通道LinkΑ66兆赫
| 型号： | DS90CR286A |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel LinkΑ66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel LinkΑ66 MHz |
| 文件： | 总12页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
DS90CR286A/DS90CR216A
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit
Channel Link—66 MHz, +3.3V Rising Edge Strobe
LVDS Receiver 21-Bit Channel Link—66 MHz
General Description
Features
n 20 to 66 MHz shift clock support
The DS90CR286A receiver converts the four LVDS data
streams (Up to 1.848 Gbps throughput or 231 Megabytes/
sec bandwidth) back into parallel 28 bits of CMOS/TTL data.
Also available is the DS90CR216A that converts the three
LVDS data streams (Up to 1.386 Gbps throughput or 173
Megabytes/sec bandwidth) back into parallel 21 bits of
CMOS/TTL data. Both Receivers’ outputs are Rising edge
strobe.
%
n 50 duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on RxOUTPUTs
n Rx power consumption 270 mW (typ) 66MHz Worst
Case
<
@
<
n Rx Power-down mode 200µW (max)
>
>
n ESD rating 7 kV (HBM), 700V (EIAJ)
n PLL requires no external components
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
n Operating Temperature: −40˚C to +85˚C
Block Diagrams
DS90CR286A
DS90CR216A
DS100873-31
Order Number DS90CR216AMTD
See NS Package Number MTD48
DS100873-30
Order Number DS90CR286AMTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS100873
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
DS90CR286A
12.4 mW/˚C above +25˚C
15 mW/˚C above +25˚C
DS90CR216A
ESD Rating
>
>
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
7 kV
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150˚C
700V
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Recommended Operating
Conditions
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)
Min Nom Max Units
+260˚C
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0
3.3
3.6
V
@
Maximum Package Power Dissipation Capacity 25˚C
MTD56 (TSSOP) Package:
−40
0
+25
+85
2.4
˚C
DS90CR286A
1.61 W
Receiver Input Range
V
MTD48 (TSSOP) Package:
DS90CR216A
Supply Noise Voltage (VCC
)
100
mVPP
1.89 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
VOUT = 0V
2.7
3.3
0.06
−60
V
V
0.3
−120
mA
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
I IN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
= +1.2V
+100
mV
mV
µA
CM
−100
±
±
V
V
= +2.4V, VCC = 3.6V
= 0V, VCC = 3.6V
10
10
IN
IN
µA
RECEIVER SUPPLY CURRENT
Receiver Supply Current Worst Case
ICCRW
ICCRW
ICCRW
ICCRW
ICCRZ
CL = 8 pF, Worst
Case Pattern,
DS90CR286A (Figures
1, 2 ), TA=−10˚C to
+70˚C
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
49
53
81
53
65
mA
mA
mA
mA
70
105
70
Receiver Supply Current Worst Case
Receiver Supply Current Worst Case
Receiver Supply Current Worst Case
CL = 8 pF, Worst
Case Pattern,
DS90CR286A (Figures
1, 2 ), TA=−40˚C to
+85˚C
f = 66 MHz
81
105
mA
CL = 8 pF, Worst
Case Pattern,
DS90CR216A (Figures
1, 2 ), TA=−10˚C to
+70˚C
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
49
53
78
53
55
60
90
60
mA
mA
mA
mA
CL = 8 pF, Worst
Case Pattern,
DS90CR216A (Figures
1, 2 ), TA=−40˚C to
+85˚C
f = 66 MHz
78
10
90
55
mA
µA
Receiver Supply Current
Power Down
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
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2
Electrical Characteristics (Continued)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V and ∆V ).
OD
OD
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
Min
Typ
2
Max
5
Units
ns
CMOS/TTL Low-to-High Transition Time (Figure 2 )
CMOS/TTL High-to-Low Transition Time (Figure 2 )
CHLT
1.8
1.4
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 9,
Figure 10)
f = 40 MHz
1.0
2.15
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
4.5
8.1
5.0
8.5
5.8
9.15
12.6
16.3
19.9
23.6
1.4
ns
ns
ns
ns
ns
ns
ns
11.6
15.1
18.8
22.5
0.7
11.9
15.6
19.2
22.9
1.1
Receiver Input Strobe Position for Bit 0 (Figure 9,
Figure 10)
f = 66 MHz
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 4) (Figure 11 )
2.9
5.1
3.3
5.5
3.6
5.8
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
7.3
7.7
8.0
9.5
9.9
10.2
12.4
14.6
11.7
13.9
490
400
15
12.1
14.3
f = 40 MHz
f = 66 MHz
RCOP
RCOH
RCOL
RSRC
RHRC
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RxCLK OUT Period (Figure 3)
T
50
RxCLK OUT High Time (Figure 3 )
RxCLK OUT Low Time (Figure 3)
RxOUT Setup to RxCLK OUT (Figure 3 )
RxOUT Hold to RxCLK OUT (Figure 3 )
RxCLK OUT High Time (Figure 3 )
RxCLK OUT Low Time (Figure 3)
RxOUT Setup to RxCLK OUT (Figure 3 )
RxOUT Hold to RxCLK OUT (Figure 3 )
f = 40 MHz
10.0
10.0
6.5
12.2
11.0
11.6
11.6
7.6
6.0
f = 66 MHz
5.0
5.0
6.3
4.5
7.3
4.0
6.3
RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Note 5)(Figure 4 )
Receiver Phase Lock Loop Set (Figure 5 )
3.5
5.0
7.5
10
1
Receiver Power Down Delay (Figure 8 )
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
=
*
for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2 T + RCCD), where T Clock period.
3
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AC Timing Diagrams
DS100873-2
FIGURE 1. “Worst Case” Test Pattern
DS100873-4
FIGURE 2. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times
DS100873-5
FIGURE 3. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times
DS100873-6
FIGURE 4. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay
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4
AC Timing Diagrams (Continued)
DS100873-7
FIGURE 5. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time
DS100873-9
FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A
DS100873-10
FIGURE 7. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A
5
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AC Timing Diagrams (Continued)
DS100873-8
FIGURE 8. DS90CR286A/DS90CR216A (Receiver) Power Down Delay
DS100873-25
FIGURE 9. DS90CR286A (Receiver) LVDS Input Strobe Position
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6
AC Timing Diagrams (Continued)
DS100873-26
FIGURE 10. DS90CR216A (Receiver) LVDS Input Strobe Position
7
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AC Timing Diagrams (Continued)
DS100873-11
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than TBD ps at 66 MHz.
Note 7: ISI is dependent on interconnect length; may be zero.
FIGURE 11. Receiver LVDS Input Skew Margin
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8
DS90CR286A Pin Description— 28-Bit Channel Link Receiver
Pin Name
RxIN+
I/O
No.
4
Description
Positive LVDS differentiaI data inputs.
I
I
RxIN−
4
Negative LVDS differential data inputs.
TTL level data outputs.
RxOUT
O
I
28
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
I
1
O
I
1
1
I
4
GND
I
5
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
1
Power supply for PLL.
I
2
Ground pin for PLL.
I
1
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
3
DS90CR216A Pin Description— 21-Bit Channel Link Receiver
Pin Name
RxIN+
I/O
No.
3
Description
Positive LVDS differentiaI data inputs. (Note 8)
Negative LVDS differential data inputs. (Note 8)
TTL level data outputs.
I
I
RxIN−
3
RxOUT
O
I
21
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
1
O
I
1
1
I
4
GND
I
5
Ground pins for TTL outputs.
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
1
Power supply for PLL.
I
2
Ground pin for PLL.
I
1
Power supply pin for LVDS inputs.
I
3
Ground pins for LVDS inputs.
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions re-
ceiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
9
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Pin Diagram
DS90CR286A
DS90CR216A
DS100873-13
DS100873-23
www.national.com
10
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CR286AMTD
NS Package Number MTD56
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CR216AMTD
NS Package Number MTD48
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whose failure to perform when properly used in
accordance with instructions for use provided in the
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significant injury to the user.
2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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