DS90CR285MTD/NOPB [TI]
DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz; DS90CR285 / DS90CR286 3.3V上升沿数据选通LVDS 28位通道链接-66 MHz的
| 型号： | DS90CR285MTD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz |
| 文件： | 总25页 (文件大小：1191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
Check for Samples: DS90CR285, DS90CR286
1
FEATURES
DESCRIPTION
The DS90CR285 transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR286 receiver converts the
LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency
of 66 MHz, 28 bits of TTL data are transmitted at a
rate of 462 Mbps per LVDS data channel. Using a 66
MHz clock, the data throughput is 1.848 Gbit/s (231
Mbytes/s).
2
•
Single +3.3V Supply
•
Chipset (Tx + Rx) Power Consumption <250
mW (typ)
•
•
•
•
•
•
•
•
Power-Down Mode (<0.5 mW total)
Up to 231 Megabytes/sec Bandwidth
Up to 1.848 Gbps Data Throughput
Narrow Bus Reduces Cable Size
290 mV Swing LVDS Devices for Low EMI
+1V Common Mode Range (Around +1.2V)
PLL Requires no External Components
Both Devices are Offered in a Low Profile 56-
Lead TSSOP Package
The multiplexing of the data lines provides
a
substantial cable reduction. Long distance parallel
single-ended buses typically require a ground wire
per active signal (and have very limited noise
rejection capability). Thus, for a 28-bit wide data and
one clock, up to 58 conductors are required. With the
Channel Link chipset as few as 11 conductors (4 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required
cable width, which provides a system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements due to the cables'
smaller form factor.
•
•
•
•
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
ESD Rating > 7 kV
Operating Temperature: −40°C to +85°C
The 28 LVCMOS/LVTTL inputs can support a variety
of signal combinations. For example, seven 4-bit
nibbles or three 9-bit (byte + parity) and 1 control.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Block Diagram
Figure 1. DS90CR285 - 56-Lead TSSOP
See Package Number DGG0056A
Figure 2. DS90CR285 - 56-Lead TSSOP
See Package Number DGG0056A
Pin Diagrams for TSSOP Packages
Figure 3. DS90CR285
See Package Number DGG (R-PDSO-G56)
Figure 4. DS90CR286
See Package Number DGG (R-PDSO-G56)
2
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Typical Application
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Continuous
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec.)
Solder Reflow Temperature
Maximum Package Power
Dissipation @ +25°C
DS90CR285MTD
DS90CR286MTD
DS90CR285MTD
DS90CR286MTD
1.63 W
1.61 W
Package Derating:
12.5 mW/°C above +25°C
12.4 mW/°C above +25°C
> 7 kV
ESD Rating (HBM, 1.5 kΩ, 100 pF)
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Recommended Operating Conditions
Min
3.0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
−40
+25
+85
2.4
°C
0
V
Supply Noise Voltage (VCC
)
100 mVPP
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
s
LVCMOS/LVTTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
3.3
0.06
−0.79
±5.1
−60
V
0.3
−1.5
±10
V
ICL = −18 mA
V
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
μA
mA
IOS
Output Short Circuit Current
−120
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
290
450
35
mV
mV
ΔVOD
Change in VOD between Complimentary Output
States
VOS
Offset Voltage(1)
1.125
1.25
1.375
35
V
ΔVOS
Change in VOS between Complimentary Output
States
mV
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE Current
VOUT = 0V, RL = 100Ω
PWR DWN = 0V,
−3.5
−5
mA
±1
±10
μA
VOUT = 0V or VCC
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
VCM = +1.2V
+100
mV
mV
μA
−100
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
±10
±10
μA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current Worst Case (with
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figure 5 Figure 6)
, TA = −10°C to +70°C
f = 32.5 MHz
31
32
37
45
50
55
mA
mA
mA
Loads)
f = 37.5 MHz
f = 66 MHz
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figure 5 Figure 6)
, TA = −40°C to +85°C
f = 40 MHz
f = 66 MHz
38
42
51
55
mA
mA
ICCTZ
Transmitter Supply Current Power Down
PWR DWN = Low
10
55
μA
Driver Outputs in TRI-STATE
under Powerdown Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current Worst Case
CL = 8 pF,
f = 32.5 MHz
49
53
78
55
78
65
70
mA
mA
mA
mA
mA
Worst Case Pattern
(Figure 5 Figure 7)
, TA = −10°C to +70°C
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
105
82
CL = 8 pF,
Worst Case Pattern
(Figure 5 Figure 7)
, TA = −40°C to +85°C
105
ICCRZ
Receiver Supply Current Power Down
PWR DWN = Low
10
55
μA
Receiver Outputs Stay Low during
Powerdown Mode
(1) VOS previously referred as VCM
.
4
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 6)
LVDS High-to-Low Transition Time (Figure 6)
TxCLK IN Transition Time (Figure 8)
Min
Typ
0.5
0.5
Max
1.5
1.5
5
Units
ns
LHLT
ns
TCIT
ns
TCCS
TPPos0
TxOUT Channel-to-Channel Skew (Figure 9)
250
0
ps
Transmitter Output Pulse Position for Bit0
(1)(Figure 20)
f = 40 MHz
−0.4
0.4
ns
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
3.1
6.5
3.3
6.8
4.0
7.6
ns
ns
ns
ns
ns
ns
ns
10.2
13.7
17.3
21.0
−0.4
10.4
13.9
17.6
21.2
0
11.0
14.6
18.2
21.8
0.3
Transmitter Output Pulse Position for Bit0
(2)(Figure 20)
f = 66 MHz
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure 10 )
1.8
4.0
2.2
4.4
2.5
4.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
6.2
6.6
6.9
8.4
8.8
9.1
10.6
12.8
15
11.0
13.2
T
11.3
13.5
50
TCIH
TxCLK IN High Time (Figure 10)
0.35T
0.35T
2.5
0.5T
0.5T
0.65T
0.65T
TCIL
TxCLK IN Low Time (Figure 10)
TSTC
TxIN Setup to TxCLK IN (Figure 10)
TxIN Hold to TxCLK IN (Figure 10)
THTC
0
TCCD
TPLLS
TPDD
TxCLK IN to TxCLK OUT Delay @ 25°C,VCC=3.3V (Figure 12)
Transmitter Phase Lock Loop Set (Figure 14)
3
3.7
5.5
10
Transmitter Powerdown Delay (Figure 18)
100
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 7)
CMOS/TTL High-to-Low Transition Time (Figure 7)
Receiver Input Strobe Position for Bit 0 (1)(Figure 21)
Receiver Input Strobe Position for Bit 1
Min
Typ
2.2
Max
5.0
Units
ns
CHLT
2.2
5.0
ns
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
f = 40 MHz
1.0
4.5
1.4
2.15
5.8
ns
5.0
ns
Receiver Input Strobe Position for Bit 2
8.1
8.5
9.15
12.6
16.3
19.9
23.6
ns
Receiver Input Strobe Position for Bit 3
11.6
15.1
18.8
22.5
11.9
15.6
19.2
22.9
ns
Receiver Input Strobe Position for Bit 4
ns
Receiver Input Strobe Position for Bit 5
ns
Receiver Input Strobe Position for Bit 6
ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
5
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Receiver Switching Characteristics (continued)
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
RSPos0
Parameter
Receiver Input Strobe Position for Bit 0 (2)(Figure 21)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (3)(Figure 22)
Min
0.7
2.9
5.1
7.3
9.5
11.7
13.9
490
400
15
Typ
1.1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
f = 66 MHz
1.4
3.6
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
3.3
5.5
5.8
7.7
8.0
9.9
10.2
12.4
14.6
12.1
14.3
f = 40 MHz
f = 66 MHz
RCOP
RCOH
RxCLK OUT Period (Figure 11)
T
50
RxCLK OUT High Time (Figure 11)
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
6.0
4.0
10.0
6.0
6.5
2.5
6.0
2.5
4.0
5.0
10.0
6.1
RCOL
RSRC
RHRC
RCCD
RxCLK OUT Low Time (Figure 11)
13.0
7.8
RxOUT Setup to RxCLK OUT (Figure 11)
RxOUT Hold to RxCLK OUT (Figure 11)
RxCLK IN to RxCLK OUT Delay (Figure 13)
14.0
8.0
8.0
4.0
6.7
8.0
9.0
10
1
6.6
RPLLS
RPDD
Receiver Phase Lock Loop Set (Figure 15)
Receiver Powerdown Delay (Figure 19)
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
(3) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS
interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter less than 250 ps).
AC TIMING DIAGRAMS
Figure 5. “Worst Case” Test Pattern
6
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Figure 6. DS90CR285 (Transmitter) LVDS Output Load and Transition Times
Figure 7. DS90CR286 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 8. DS90CR285 (Transmitter) Input Clock Transition Time
(1) Measurements at VDIFF = 0V
(2) TCCS measured between earliest and latest LVDS edges.
(3) TxCLK Differential Low→High Edge
Figure 9. DS90CR285 (Transmitter) Channel-to-Channel Skew
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Figure 10. DS90CR285 (Transmitter) Setup/Hold and High/Low Times
Figure 11. DS90CR286 (Receiver) Setup/Hold and High/Low Times
Figure 12. DS90CR285 (Transmitter) Clock In to Clock Out Delay
Figure 13. DS90CR286 (Receiver) Clock In to Clock Out Delay
8
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Figure 14. DS90CR285 (Transmitter) Phase Lock Loop Set Time
Figure 15. DS90CR286 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in Once Clock Cycle
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Figure 17. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs
Figure 18. Transmitter Powerdown DeIay
Figure 19. Receiver Powerdown Delay
10
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Figure 20. Transmitter LVDS Output Pulse Position Measurement
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Figure 21. Receiver LVDS Input Strobe Position
12
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 250 ps
(2) ISI is dependent on interconnect length; may be zero
Figure 22. Receiver LVDS Input Skew Margin
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
DS90CR285 DGG (TSSOP) Package Pin Description — Channel Link Transmitter
Pin Name
TxIN
I/O No.
Description
I
O
O
I
28 TTL level input.
TxOUT+
4
4
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential data output.
Negative LVDS differential data output.
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
VCC
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
Power supply pins for TTL inputs.
I
GND
I
Ground pins for TTL inputs.
PLL VCC
I
Power supply pin for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pins for PLL.
I
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
I
DS90CR286 DGG (TSSOP) Package Pin Description — Channel Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
I
28 TTL level data outputs.
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
VCC
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
I
O
I
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input.When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
GND
I
Ground pins for TTL outputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
14
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
APPLICATIONS INFORMATION
The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending
upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and
shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance
applications the media's performance becomes more critical. Certain cable constructions provide tighter skew
(matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at
distances as great as 5 meters and with the maximum data transfer of 1.848 Gbit/s. Additional applications
information can be found in the following Interface Application Notes:
AN = ####
AN-1041
Topic
Introduction to Channel Link
(SNLA218)
AN-1108
(SNLA008)
Channel Link PCB and Interconnect Design-In
Guidelines
AN-806
Transmission Line Theory
(SNLA026)
AN-905
Transmission Line Calculations and Differential
(SNSNLA035L Impedance
A008)
AN-916
Cable Information
(SNLA219)
CABLES
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21-bit
CHANNEL LINK chipset (DS90CR215/216) requires four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR285/286) requires five pairs of signal wires. The ideal cable/connector interface would have a
constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below
150 ps (@ 66 MHz clock rate) to maintain a sufficient data sampling window at the receiver.
In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one
additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance
ground provides a common mode return path for the two devices. Some of the more commonly used cable types
for point-to-point applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of
configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point
applications while Twin-Coax is good for short and long applications. When using ribbon cable, it is
recommended to place a ground line between each differential pair to act as a barrier to noise coupling between
adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All
extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless
of the cable type. This overall shield results in improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent
results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very
low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed
here and listed in the supplemental application notes provide the subsystem communications designer with many
useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to
arrive at a reliable and economical cable solution.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the
layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise canceling of the differential signals. The board designer
should also try to maintain equal length on signal traces for a given differential pair. As with any high speed
design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on
traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the
differential pair. Care should be taken to ensure that the differential trace impedance match the differential
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
impedance of the selected physical media (this impedance should also match the value of the termination
resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL
LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.
All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance
and EMI.
UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must be tied to ground. All unused outputs at the RxOUT
outputs of the receiver must then be left floating.
INPUTS
The TxIN and control inputs are compatible with LVCMOS and LVTTL levels. These pins are not 5V tolerant.
TERMINATION
Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK
chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination resistor should be selected to match the differential
mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 23 shows an example. No additional
pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface
mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These
resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively
terminate the differential lines.
DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01μF and 0.001 μF. An example is shown in Figure 24. The designer should employ wide traces for
power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS
VCC pins and finally the logic VCC pins.
Figure 23. LVDS Serialized Link Termination
16
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
Figure 24. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS
interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example,
a 66 MHz clock has a period of 15 ns which results in a data bit width of 2.16 ns. Differential skew (Δt within one
differential pair), interconnect skew (Δt of one differential pair to another) and clock jitter will all reduce the
available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input
to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-
to-channel skew and interconnect skew as a part of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN
The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100
mV threshold therefore providing approximately 200 mV of differential noise margin. Common mode protection is
of more importance to the system's operation due to the differential data transmission. LVDS supports an input
voltage range of Ground to +2.4V. This allows for a ±1.0V shifting of the center point due to ground potential
differences and common mode noise.
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the CNANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and
data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either
device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total
power dissipation for each device will decrease to 5 μW (typical).
The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs
(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the
receiver inputs are shorted to V
through an internal diode. Current is limited (5 mA per input) by the fixed
CC
current mode drivers, thus avoiding the potential for latchup when powering the device.
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
Figure 25. Single-Ended and Differential Waveforms
18
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
DS90CR285, DS90CR286
www.ti.com
SNLS130C –MARCH 1999–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS90CR285 DS90CR286
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DS90CR285MTD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DGG
56
56
56
56
56
56
56
34
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
CU SN
Call TI
DS90CR285MTD
>B
DS90CR285MTD/NOPB
DS90CR285MTDX
ACTIVE
ACTIVE
ACTIVE
NRND
DGG
DGG
DGG
DGG
DGG
DGG
34
1000
1000
34
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Call TI
-40 to 85
DS90CR285MTD
>B
TBD
-40 to 85
DS90CR285MTD
>B
DS90CR285MTDX/NOPB
DS90CR286MTD
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Call TI
-40 to 85
DS90CR285MTD
>B
TBD
DS90CR286MTD
>B
DS90CR286MTD/NOPB
DS90CR286MTDX/NOPB
NRND
34
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DS90CR286MTD
>B
NRND
1000
Green (RoHS
& no Sb/Br)
DS90CR286MTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR285MTDX
TSSOP
DGG
DGG
DGG
56
56
56
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
8.6
8.6
8.6
14.5
14.5
14.5
1.8
1.8
1.8
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
DS90CR285MTDX/NOPB TSSOP
DS90CR286MTDX/NOPB TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CR285MTDX
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
56
56
56
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
DS90CR285MTDX/NOPB
DS90CR286MTDX/NOPB
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
DS90CR285MTDX/NOPB
DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
TI
DS90CR286A
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel LinkΑ66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel LinkΑ66 MHz
NSC
DS90CR286AMTD
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel LinkΑ66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel LinkΑ66 MHz
NSC
©2020 ICPDF网 联系我们和版权申明