NJW4302 [NJRC]
THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC; 三相直流无刷电机控制IC
| 型号： | NJW4302 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC |
| 文件： | 总18页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4302
Preliminary
THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC
■ GENERAL DESCRIPTION
■ PACKEGE OUTLINE
pre-driver IC for precision applications.
control, FG(Frequency Generator) output, and voltage
velocity integration circuit.
for printer, FAX, and other DC motor control systems.
NJW4302FA1
■ FEATURES
Speed discriminator and PLL speed
■ PIN CONFIGRATION
•
H3 H3 H2 H2 H1
RF
VL
UL
VH
UH
WL
control circuit
•
Direct PWM driver
H1+
WH
•
•
•
•
•
•
CR oscillator
FGIN+
PVCC
VCC
Lock protection output
FGIN-
Break circuit (short circuit braking)
Start/stop switch Start/Stop Switch Circuit
Current limit circuit
FGOUT
VREG
DGND
AGND
FGSOUT
PGND
lockout circuit
NJW4302 QFP44
AGND
VSH
CR
•
•
•
•
FG output amplifier/Integrating circuit
Shunt regulator output : 5V
Bi-CMOS technology
N2
N1
CROCK
PACKAGE OUTLINE QFP44
SS
R
C
CLK
FILI
TOC
INT IN
DOUT
LD
POUT
FILO
BR FR
INTOUT
INTREF
■BLOCK DIAGRAM
FGO
CROCK
BR
BR
F/R
F/R
V+
FGSO
O
Dout
LD
INTREF
F
INTOUTS/S
INTIN
ROCK
OSC
LD
INTEGRATION
AMP
-
FGIN-
FGIN+
-
+
+
FG
SPEED
DISC RIMINATOR
H1+
H1
LOGIC
-
H2+
H2
H3+
H3
HALL
HYS
-
AMP
S/S
VREF
SPEED
PLL
-
Pout
Vreg
VSH
VREG
1
VCOOUT
PROTECTION
CIRCUIT
TSD / L VDS
CLK
ALTER NATIVE
PWM BLOCK
C OU NTER
CIR CUIT
PLL COUNTER
PRI- DRIVER
FILI
FILO
R
C
N1
N2 GND
CR RF TOC
UL VL WL UH VHWH
- 1 -
NJW4302
Preliminary
■PIN DESCRIPTION
SYMBOL
PIN No.
DESCRIPTION
H1+,H1-
H2+,H2-
H3+,H3-
UH
33, 34
35, 36
37, 38
41
Hall input pins
Positive input terminal is defined as IN+,Negative input terminal as IN- respectably.
Positive input is defined as IN+> IN as Negative.
-
VH
43
Output pins(for fixed current source )
WH
1
UL
40
Output pins(open collector sink outputs).
Duty control implement with PWM signal.
VL
42
WL
44
VPCC
VCC
VREG
2
3
Power-supply voltage pin
Connect a noise decouplingcapacitor between these pins and the ground.
Shunt regulator output pin
4
PGND.DGND
AGND
5,6
27,28
7
Ground pins
These pins are all connected internallyto the ground(GND).
VSH
Shunt regulator ON/OFF output pin
“H” or open:ON
“L”:OFF
CR
8
PWM oscillator frequency setting pin
Three blocks use the oscillator: motor constraint detection circuit, clock disconnection protection circuit
and others
CROCK
9
Reference clock signal oscillator pin
Connect a capacitor between this pin to the ground.This oscillator provides clock signal when motor is locked.
VCO oscillation frequency setting pin
R
C
10
11
Connect a resistor between this pin anhround.
VCO oscillation frequency setting pin
Connect a resister between this pin and ground.
Set the value of the capacitor so that the oscillator frequency does not exceed 1MHz.
FILI
13
VCO filter amplifier input pin
This pin is connected to VCO PLL output with 10KΩ resistor internally in the IC.
FILO
D OUT
P OUT
LD
12
18
19
20
VCO filter amplifier output pin
This pin is connected to VCO circuit internallin the IC.
Speed discriminator output pin
PLL output pin
Lock detection output pin
Open collector becomes“L”within the speed lock range(±6.25).
INT REF
INT IN
14
15
Integratinamplifier forward rotation input(a potential of 1/2V+
Negative input for Integration amplifier
INT OUT
TOC
Output for Integration amplifier
Torque command input pin
This pin is normally connected to the INT OUT pin. When the TOC voltage level falls,the UL,VL and Wl PWM duties are
changed to increase.
FG IN+
32
Input pin for FG amplifier forward rotation (a potential of 1/2V+)
Connect a noise decoupling capacitor between V+ terminal and the ground.
- 2 -
NJW4302
Preliminary
FGOUT
FGSOUT
31
29
FG amplifier reverse rotation input.
FG amplifier output.
FG amplifier output(after the schmitt)
Open collector output.
RF
SS
39
24
Output current detection
Connect a resistor between this pin and GND pin.The output limitation maximum current(IOUT)is set to be 0.5/Rf.
Start Stop control
“L”:Start
“H”or Open:Stop
FR
BR
22
21
23
Forward/reverse rotation control
“L”:Forward
“H”or Open:reverse
Brake control (short braking operation)
“L”:Start
“H”or Open:Brake
CLK
External clock signal input
10kHz max.
N1
N2
25
Speed discriminator count switching
- 3 -
NJW4302
Preliminary
■ FUNCTIONAL DESCRIPTION
1. VCO circuit
The variable range of PLL circuit is determined by two factors: VCO frequency determined by RC value connected
to Pin 15 and Pin 16 and VCO loop filter constants. VCO frequency range must be within 160kHZ to 1.0MHZ.
The typical external value is as follows:
R=20kΩ,C=100pF.
The filter constants are C=0.47µF,R=27kΩ.
2. Output drive circuit
The PWM control is made by upper side of external transistor.
3. Speed lock range
The speed lock range is ±6.25% of fixed speed. When the motor speed is within the lock range, the LD pin
(an open collector output)goes “L”. If the motor speed goes out of the lock range, the LD pin goes “H”.
Please be noted that the LD signal may go on during startup.
4. PWM frequency
The PWM frequency is determined by resistor and capacitor value connected to the CR pin.
The PWM frequency is given by expressed as:
fPWM=1/(0.48CR)
When C=1500pF,R=75KΩ,the PWM frequency goes about 19KHz.
5. Lock detection circuit(CLOCK)
Lock detection circuit protects the driver IC and the motor from fatal over current failure when the motor is
locked during startup. If the LD output remains “H” (motor lock state) for a certain period (Hold time),all phase of upper
side transistors are to be turned off.
The hold time can be programmed by capacitor value attached to the CLOCK pin by the following:
Set time(sec) =66×C(µF)
With C=0.068µF,the hold time can be programmed for approximately 4.5 sec.
Once Lock detection circuit is activated, the state remains unchanged unless it is turned off, or stopped.
This function can be disabled when the CLOCK pin is connected to the ground.
6. Forward / Reverse(F/R)Switching
The direction control can be made with the state of the F/R pin. The direction can be changed even during the
motor in motion.
- 4 -
NJW4302
Preliminary
7. Brake Switch
NJW4302 uses a short brake method that turns on all phase of upper side transistors for braking. During the
time, all lower side transistors are turned off.
8. VREG pin/VSH pin
NJW4302 includes a regulator to generate for +5V regulated IC supply when the motor drive circuit
is designed with a single power supply. The VREG pin and V+ pin compose a shunt regulator for 5V±5%
output with a external resistor and a transistor. To use the regulator, the VSH pin must be either “H”, or Open.
Otherwise, the VSH pin must be “L” and the VREG pin is to be opened.
9. Frequency Generator (FG) Amplifier
The internal FG amplifier with few passive components composes a filter amplifier shown in the
application. Circuit for noise rejection. The output voltage of the amplifier must be at least 250mA p-p since it feature
Schmitt comparator.
The capacitor connected between the FGIN+ pin and the ground is necessary for bias voltage
stabilization and initial reset pulse generation for the internal logic. The reset pulse is generated when the
FGIN+ pin goes from 0 to approximately 1.25V.
10. Integration Amplifier
The integration amplifier integrates the D-out and P-out and converts them to speed command voltage. During the
time, it also sets the control loop gain and frequency characteristics using external components.
11. Speed Control Circuit
NJW4302 features two speed control method; speed discriminator circuit with PLL circuit and phase
comparison circuit. The FG pulse frequency is controlled to be the same frequency with a clock frequency input to the CLK
pin. Therefore, the motor speed can be controlled by changing the clock frequency.
The motor speed (N) can be expressed as:
N=CLK (Hz)×(60/FGP)[RPM] ( FGP: Number of FG pulse per one rotation)
Given that the oscillation frequency range is 160kHz~1.0MHZ and the number of counts is 1024,the range of
clock frequency is 156HZ~960HZ , and therefore the motor speed can be changed from 260rpm to 1600rpm.
- 5 -
NJW4302
Preliminary
■ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
V+
TEST CONDITION
RATINGS
7
UNIT
V
Maximum supply voltage
Maximum input current
Output current
Ireg
Io
Vreg pin(5.6V)
UL,VL,WL
10
mA
mA
30
Operating temperature
Storage temperature
Power dissipation
Topr
Tstg
Pd
-40 85
-55 150
700
C
°
C
°
mW
■ALLOWABLE MAXIMUM RANGES/Ta=25°C
PARAMETER SYMBOL
Input current range
CONDITION
RATINGS
1.0~5.0
0~8
0~5
0~20
4.5~5.5
UNIT
mA
V
mA
mA
V
I
REG
FGSO
FGSO
LD
VREG pin=5.6V
FG Schmitt output applied voltage
FG Schmitt output current
Lock detection output current
Supply voltage
V
I
I
V+
- 6 -
NJW4302
Preliminary
■ELECTRICAL CHARACTERISTICS / Ta=25°C,V+=5.0V
PARAMETER SYMBOL CONDITION
Supply current 1
MIN.
TYP.
38
8
MAX.
55
18
UNIT
mA
mA
V
I
CC
1
-
-
-
Supply current 2
I
CC2
in stop mode
(sat) UL,VL and WL terminal Io=20mA
UH,VH and WH erminal Vout=1.4V
(leak) UL,VL,WL output
(off) UH,VH,WH output
Output saturation voltage
VO
0.2
0.7
t
Output current
Output leakage current
IO
-20
-
-
-16
-
-
-12
100
0.5
mA
µA
V
IO
Output off voltage
VO
•HALL AMPLIFIER
PARAMETER
SYMBOL TEST CONDITION
HB(HA)
MIN.
TYP.
MAX.
UNIT
µA
V
mVP-P
mV
mV
mV
Input bias current
Common mode input voltage range
Hall input sensitivity
I
-4
1.5
-
17
8
-1
-
60
32
16
-16
-
VICM
VCC-1.5
∆VIN(HA)
∆VIN(HA)
-
Hysteresis
60
30
-8
Input voltage Low → High
Input voltage High →Low
VSLH
VSHL
-30
•CR OSCILLATOR
PARAMETER
SYMBOL
OH(CR)
OL(CR)
f(CR)
V(CR)
TEST CONDITION
MIN.
TYP.
MAX.
3.0
1.9
-
UNIT
Output high level voltage
Output low level voltage
RC oscillation frequency
RC oscillation voltage
V
V
2.4
1.3
-
2.7
1.6
19
V
V
R=75kΩ,C=1500pF
kHz
VP-P
0.9
1.1
1.3
•CLOCK OSCILLATOR
PARAMETER
SYMBOL
TEST CONDITION
MIN.
2.7
0.1
-
-
-
TYP.
MAX.
UNIT
V
V
µA
µA
Hz
VP-P
Output high level voltage
Output low level voltage
External capacitor charge current
External capacitor discharge current
Clock oscillation frequency
V
V
I
I
OH(RK)
OL(RK)
CHG
CHG
(RK)
3.0
0.4
-10
10
35
2.6
3.3
0.7
-
-
-
1
2
f
C=0.068µF
RC oscillation voltage
V(RK)
2.4
2.8
•VCO OSCILLATOR (PLL COUNTER)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
1.15
0.9
TYP.
MAX.
1.35
1.1
1.0
0.6
UNIT
V
V
MHz
VP-P
C-terminal high-level output voltage
C-terminal low-level output voltage
VCO oscillation frequency
Amplitude
V
OH(C)
OL(C)
(C)
(C)
1.25
1.0
-
V
f
-
V
0.15
0.25
- 7 -
NJW4302
Preliminary
•CURRENT LIMITING OPERATION
PARAMETER
Limiter
•FG AMPLIFIER
PARAMETER
Input offset voltage
Input bias current
Output low-level voltage
Output high-level voltage
FG input sensitivity
Schmitt amplifier for next stage
Operating frequency range
Open loop gain
SYMBOL
TEST CONDITION
MIN.
0.47
TYP.
0.52
MAX.
0.57
UNIT
V
VRF
SYMBOL
TEST CONDITION
MIN.
TYP.
0
MAX.
10
1
-
1.5
-
250
-
UNIT
mV
µA
V
V
mV
mV
kHz
dB
V
IO(FG)
(FG)
OH(FG)
OL(FG)
∆VIN FG
-10
I
B
-1
0
V
V+-1.5 V+-1.0
V
-
1
3
180
16
51
(
)
GAIN =40dB
-
100
-
∆VSH(FG)
∆FG
AV(FG
)
f(FG)=2kHz
-
-
•FGSO OUTPUT
PARAMETER
SYMBOL
TEST CONDITION
O(FGS)=2mA
=V+
MIN.
TYP.
MAX.
0.5
10
UNIT
V
µA
Output saturation voltage
Output leak current
VO(FGSO)
I
V
-
-
0.1
-
IL(FGSO)
O
•SPEED DISCRIMINATOR OUTPUT (Dout)
PARAMETER
Output high-level voltage
Output low-level voltage
SYMBOL
TEST CONDITION
MIN.
V+-1.0
-
TYP.
V+-0.7
0.4
MAX.
UNIT
V
V
VOH(D)
-
-
VOL(D)
•SPEED CONTROL PLL OUTPUT (Pout)
PARAMETER
SYMBOL
TEST CONDITION
TEST CONDITION
MIN.
3.35
1.35
TYP.
3.65
1.65
MAX.
3.95
1.95
UNIT
V
V
Output high-level voltage
Output low-level voltage
VOH(P)
VOL(P)
•LOCK DETECTION (LD)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
0.5
10
UNIT
Output saturation voltage
Output leak current
Lock range
VOL(LD)
I
LD=10mA
=V+
Design target spec
-
-
0.1
-
-
V
µA
%
IL(LD)
V
O
-6.25
+6.25
∆LOCK
- 8 -
NJW4302
Preliminary
•INTEGRATER AMPLIFIER
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Input offset voltage
Input bias current
Output high-level voltage
Output low-level voltage
Open loop gain
Gain-band width product
Reference voltage
V
IO(INT)
(INT)
OH(INT)
OL(INT)
-10
-
-
10
mV
µA
V
IB
-0.4
0.4
V
V
V+-0.12
V+-0.8
0.8
60
-
1.2
-
-
-
-
-
V
AV(INT
GBW(INT
(INT)
)
dB
MHz
V
)
1.6
2.5
V
B
2.375
2.625
•FILTER AMPLIFIER (PLL COUNTER)
PARAMETER
Input bias current
Output high-level voltage
Output low-level voltage
Hysteresis
SYMBOL
TEST CONDITION
TEST CONDITION
TEST CONDITION
TEST CONDITION
MIN.
-
TYP.
0.4
MAX.
UNIT
µA
V
V
V
I
B(FIL)
OH(FIL)
OL(FIL)
B(FIL)
-
-
V
V
V+-1.2
-
V+-0.8
0.8
1.2
2.625
V
2.375
2.5
•S/S AMPLIFIER
PARAMETER
SYMBOL
MIN.
3.5
0
1.0
60
TYP.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(S/S)
IL(S/S)
∆VIN(S/S)
U(S/S)
V
Pull-Up resistance
R
•F/R AMPLIFIER
PARAMETER
SYMBOL
MIN.
3.5
0
1.0
60
TYP.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(F/R)
IL(F/R)
∆VIN(F/R)
U(F/R)
V
Pull-Up resistance
R
•BR AMPLIFIER
PARAMETER
SYMBOL
MIN.
3.5
0
1.0
60
TPY.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(BR)
IL(BR)
∆VIN(BR)
U(BR)
V
Pull-Up resistance
R
- 9 -
NJW4302
Preliminary
•CLK AMPLIFIER
PARAMETER
SYMBOL
TEST CONDITION
MIN.
3.5
0
1.0
60
-
TPY.
4.2
0.8
1.3
80
MAX.
UNIT
V
V
V
kΩ
kHz
Input high-level voltage
Input low-level voltage
Hysteresis
Pull-Up resistance
Input frequency
V
IH(CLK)
IL(CLK)
∆VIN(CLK)
U(CLK)
(CLK)
V+
1.0
1.6
100
-
V
R
f
16
•N1 AMPLIFIER
PARAMETER
SYMBOL
TEST CONDITION
TEST CONDITION
TEST CONDITION
MIN.
3.5
0
1.0
60
TYP.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(N1)
IL(N1)
∆VIN(N1)
U(N1)
V
Pull-Up resistance
R
•N2 AMPLIFIER
PARAMETER
SYMBOL
MIN.
3.5
0
1.0
60
TYP.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(N2)
IL(N2)
∆VIN(N2)
U(N2)
V
Pull-Up resistance
R
•UNDER VOLTAGE LOCKOUT
PARAMETER
Operating voltage
Release voltage
Hysteresis
SYMBOL
MIN.
TYP.
3.75
4.0
MAX.
UNIT
V
V
VSDL
-
-
-
-
VSDH
∆VSD
0.15
0.25
0.35
V
•SHUNT REGULATOR
PARAKMETER
SYMBOL
TEST CONDITION
TEST CONDITION
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
V
Output voltage
VO(VSH)
•VSH AMPLIFIER
PARAMETER
SYMBOL
MIN.
3.5
0
1.0
60
TYP.
4.2
0.8
1.3
80
MAX.
V+
1.0
1.6
100
UNIT
V
V
V
kΩ
Input high-level voltage
Input low-level voltage
Hysteresis
V
IH(VSH)
IL(VSH)
∆VIN(VSH)
U(VSH)
V
Pull-Up resistance
R
- 10 -
NJW4302
Preliminary
■ SPEED DISCRIMINATOR COUNT TABLE
N1
High or Open
High or Open
Low
N2
High or Open
Low
NUMBER OF COUNTS
128
512
High or Open
Low
256
Low
1024
■ THREE PHASE LOGIC TRUTH TABLE
F/R=L
F/R=H
OUTPUTS
H 1
H
H
H
L
H 2
L
H 3
H
L
H 1
L
H 2
H
H
L
H 3
L
Source
VH
Sink
UL
1
2
3
4
5
6
L
L
H
H
H
L
WH
WH
UH
UL
H
H
H
L
L
L
VL
L
H
H
H
L
VL
L
H
H
L
UH
WL
WL
L
H
L
VH
■ S/S TERMINAL
High or Open
Stop
Start
Low
■ BRAKE TERMINAL
High or Open
Brake
Low
Release
- 11 -
NJW4302
Preliminary
■ TYPICAL APPLICATION
VM
QVR
R12
R14
R13
R10
R11
R9
C10
0.1u
WH
PVCC
H1+
FGIN+
FGIN-
FGOUT
FGSOUT
PGND
C8
1000p
VCC
2k 0.47u
R8 C9
VREG
DGND
AGND
VSH
100k
CVR
47u
R7
FGS
NJW4302 QFP44
1
VSH
AGND
75k
C1
C2
R2
C3
CR
N2
N1
SS
CLK
1500p
0.047u
20k
CROCK
100p
220p
27k
R3
C4
R5 R6
C5
C7
C6
18k
2.4M
0.47u
0.1u
R4
0.22u
150k
- 12 -
NJW4302
Preliminary
■ TYPICAL CHARACTERISTICS
- 13 -
NJW4302
Preliminary
■ TYPICAL CHARACTERISTICS
(Ta=25degC,With standard device)
- 14 -
NJW4302
Preliminary
■ APPLICATION NOTE
•FG Amplifier
FG Amplifier consists of input differential amplifier and output Schmitt-trigger comparator. Input amplifier is
constructed as low-pass filter with external resistors and capacitors to reduce noise. The amplifier output level
should be over 250mVp-p to adjust gain by external resistors, due to hysteresis of Schmitt-trigger comparator.
FG+ input is biased internally to the half level of Vcc. This DC bias voltage is also used to RESET the internal logic
circuit. For stable RESET operation, It a capacitor, requires a 0.1 uF capacitor connected to FG+ terminal. RESET is
enable a during 0V to 1.25V of the voltage at the FG+.
FG Sensor Amplifier Application Circuit
1000p
100k
FGO
FGS
0.47u
2k
FG-
FG+
0.1u
for Internal logic
NJW4302
- 15 -
NJW4302
Preliminary
• FG interfac for logic output device
The circuit below is a FG interface for logic output device (i.e. Hall IC and optical encoder). Two external
resistors are required to adjust the input voltage within the common mode input voltage range,0 to Vcc-1.5V.
FG interface for logic level input
5 V
FGO
FG
1.5k
logic
FG -
FG +
3.5k
for Internal logic
0.1u
NJW4302
• Power supply generating from Vref
To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47
microfarad capacitor on V+ of NJW4302 for ripple filtering.
• Hall sensor biasing
Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity
of NJW4302.
• FG Input
Internal FG Amplifier is a differential amplifier which inputs and output are pin-outed. The DC gain of this
amplifier, AFG, is:
R7
AFG
=
R8
C8 is for noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. The inductor symbol
connected FGIN is FG sensing copper pattern on PC board.
• Power supply generating from Vref
To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47
microfarad capacitor on V+ of NJW4302 for ripple filtering.
• Hall sensor biasing
Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity
of NJW4302.
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NJW4302
Preliminary
• FG Input
Internal FG Amplifier is a differential amplifier and both inputs and output are connected to the pin. The DC gain
of this amplifier, AFG, is:
R7
AFG
=
R8
C8 is for compensation or noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. The
inductor symbol connected FGIN is FG sensing copper pattern on PC board.
• PWM Frequency
PWM clock generates by CR oscillator. The frequency is:
1
fPWM
=
0.48 R1 C1
In fig.x*, fPWM is about 19kHz. If fPWM is about 20kHz, it could reduce audible noise.
• Variable range of VCO frequency
VCO frequency in typical value is recommend 160kHz to 1MHz. External constants is:
R2 = 20k ohm, C3 = 100pF, R3 = 27k ohm, C4 = 0.47 uF
If it can not be settled into this range, change the division of speed discriminator.
• Detecting time of rock protection
Detecting time is settled by C2 as follow:
tROCK = 66 C2
In fig.x*, trock is about 3.1 sec.
• Integration Amplifier
Both speed discriminator output and PLL output should be mixed via two resistors before input to INTIN of
Integration Amplifier. Mixing resistor, Timing resistors and capacitors are necessary for good system operation.
C6 is need for non-polar type capacitor for good stability.
• Upper power transistor
To reduce ripple of power line, Upper output transistor is connect NJM4302 via common-base NPN transistors.
Minimum output current is 12mA, it is able to drive 1A class transistor. If more current is needed, change the
output transistor to Darlington type. Re-circulating diodes is needed on between collector and emitter of output
transistor.
• Lower power transistor
Lower output could drive external power transistor directly to about 1.5A. If more current is needed, change
the output transistor to Darlington type. The resistor connected between base and emitter of power transistor is
necessary on PWM operation for sharp cut-off of power transistor. When your system have any noise, attach a
capacitor in parallel the resistor.
Re-circulating diodes is needed on between collector and emitter of output transistor. R11 is a current sensing
resistor and settled by following:
VRE
R11=
IO
When VRF is sensing voltage, Io is sensing current. Take care of power dissipation of R11, also.
- 17 -
NJW4302
Preliminary
• Recirculation Diodes
Recirculation diodes are recommend to use Shottkey-burrier type. Forward voltage “VF” and reverse returning
time “trr” are contributed for power dissipation.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 18 -
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