NJW4351VC3 [NJRC]
Unipolar Stepper Motor Driver; 单极步进电机驱动器
| 型号： | NJW4351VC3 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Unipolar Stepper Motor Driver |
| 文件： | 总18页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4351
Unipolar Stepper Motor Driver
GENERAL DESCRIPTION
PACKAGE OUTLINE
The NJW4351 is a high efficiency DMOS unipolar stepper
motor driver IC. Compared to previous devices, it is more suitable
for low voltage operation, capable of handling 5.0V, 3.3V and the
like logic circuits. Drive Stage consists of DMOS which produces
high efficiency and low heat generation motor drive circuit.
The motor can be controlled by the STEP and DIR system.
Further more, to improve controllability of system, MO, ENABLE,
RESET and PD function are included, various applications are
possible.
NJW4351VC3
NJW4351D
FEATURES
• Supply Voltage
VDD=2.7 to 5.5V
VMM= to 55V
• Output Current
• Low Quiescent Current
Io=1.5A peak at VDD=5V
IDD=500µA typ.
• STEP&DIR Input Operation (Internal Translator)
• HALF/FULL Mode Generation
• TTL compatible Input With Schmitt-Comparator
• ENABLE Function
• RESET Function
• MO (Motor Origin Monitor) -Position-indication Output
• PD (Standby) Function
• Under Voltage Lock Out
• Thermal Shutdown Circuit
•Alarm Output Function (As the protection circuit operates)
• BCD Technology
• Package Outline
SSOP20-C3, DIP16
BLOCK DIAGRAM
VDD
NJW4351
POWER ON
RESET
OUT2B
OUT2A
OUT1B
OUT1A
HSM
STEP
DIR
GATE
DRIVE
TRANSLATOR
RESET
ENABLE
PD
Bias Circuit
MO
UNDER VOLTAGE
LOCK OUT
ALARM
SENSE1
SENSE2
THERMAL SHUT
DOWN
GND
‘Ver.2010-03-26
- 1 -
NJW4351
PIN CONNECTION
VDD
HSM
PD
PD
1
N.C.
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
VDD
HSM
2
3
OUT1A
SENSE1
OUT1B
OUT2B
SENSE2
OUT2A
GND
OUT1A
SENSE1
OUT1B
OUT2B
SENSE2
OUT2A
N.C.
STEP
DIR
STEP
DIR
4
5
RESET
ENABLE
MO
6
RESET
ENABLE
MO
7
8
ALARM
GND
9
10
N.C.
ALARM
SSOP20-C3
DIP16
PIN FUNCTION LIST
Pin#
SSOP20-C3
Terminal
Name
Function
Remark
DIP16
Power Saving State Setting
Input Terminal
Logic Voltage Supply Terminal
HALF/FULL Step Mode Setting
Input Terminal
L=Standby, H=Normal Operation
1
2
3
16
1
PD
Logic Voltage Supply
L=FULL, H=HALF
VDD
HSM
2
The Translator is triggered by positive edge of STEP
Pulse.
Stepping Pulse Input Terminal
4
3
STEP
Direction Setting Input Terminal
Reset Input Terminal
Phase Output Off Input Terminal L=ACTIVE, H=Normal Operation
L=FORWARD, H=REVERSE
L=The Translator is initialized, H=Normal Operation
5
6
7
8
4
5
6
7
DIR
RESET
ENABLE
MO
MO Output Terminal
When the Translator is in initial status, L level is to output.
Internal Protection Operation When the internal protection operation is detected, L level
9
8
ALARM
Detection Output Terminal
Logic Ground Terminal
No Connection
is to output.
Logic Ground
No Connection
10
11,12,19,20
13
9
-
10
GND
N.C.
OUT2A
2ch Output Terminal A
⎯
Current Detection Resistance
Connection Terminal 2
It connects resistance for the detection of the side of 2ch.
At the unused time, it connects with GND.
14
11
SENSE2
2ch Output Terminal B
1ch Output Terminal B
⎯
⎯
15
16
12
13
OUT2B
OUT1B
Current Detection Resistance
Connection Terminal 1
1ch Output Terminal A
It connects resistance for the detection of the side of 1ch.
At the unused time, it connects with GND.
⎯
17
18
14
15
SENSE1
OUT1A
Ver.2010-03-26
- 2 -
NJW4351
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
Logic Supply Voltage
Motor Output Voltage
SYMBOL
RATINGS
UNIT
V
V
VDD
VO
7
55
VDD PIN
OUT1A/1B/2A/2B PIN
STEP, DIR, HSM, RESET,
ENABLE, PD PIN
ALARM PIN
MO PIN
OUT1A/1B/2A/2B PIN
Logic Input Voltage
VIN
7
V
ALARM Output Voltage
MO Output Voltage
Output Current
VALARM
VMO
Io
7
7
1.5
V
V
A
ALARM Output Current
MO Output Current
Operating Temperature
Junction Temperature
Storage Temperature
Power Dissipation
(SSOP20-C3)
IALARM
IMO
Topr
Tj
20
20
mA ALARM PIN
mA MO PIN
°C
°C
°C
-40 to +85
-40 to +150
-50 to +150
1.0
-
-
-
Tstg
W
W
W
W
W
(*1) Mounted on 2Layers PCB
(*1) Mounted on 4Layers PCB
Device itself
(*1) Mounted on 2Layers PCB
(*1) Mounted on 4Layers PCB
PD
1.5
1.2
1.4
2.0
Power Dissipation
(DIP16)
PD
(*1): Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers/4Layers)
RECOMMENDED OPERATING CONDITIONS
(Ta=25°C)
TYP. MAX. UNIT
PARAMETER
Logic Supply Voltage
SYMBOL
VDD
TEST CONDITION
MIN.
2.7
-
-
3.3
500
-
5.5
-
500
V
mA
mA
VDD=5V
VDD=3.3V
Output Current
Io
- 3 -
NJW4351
ELECTRICAL CHARACTERISTICS
(VMM=24V, VDD=PD=3.3V, RL=1kΩ, RMO=3.3kΩ, RALARM=3.3kΩ, Ta=25°C)
PARAMETER
GENERAL
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX. UNIT
STEP,DIR,HSM,RESET,ENABLE=3.3V,
Except IIH
PD=0V, except IIH
Quiescent current
IDD
IPD
-
-
0.5
-
0.8
1.0
mA
uA
Quiescent current (Standby)
INPUT BLOCK1 (STEP)
H level input voltage1
L level input voltage1
Input hysteresis voltage1
H level input voltage2
L level input voltage2
Input hysteresis voltage2
H level input current
VIH1
VIL1
VIHYS1
VIH2
VIL2
VIHYS2
IIH
IIL
2.0
0
0.4
2.4
0
0.4
15
-
-
-
-
0.8
-
V
V
V
0.55
-
-
0.55
33
10
100
-
VDD=5V
VDD=5V
VDD=5V
-
V
0.8
-
V
V
STEP=3.3V
STEP=0V
45
20
-
uA
uA
kΩ
us
L level input current
Input pull down resistance
Input pulse widths
RDOWN
tp
-
2
-
INPUT BLOCK2 (PD/DIR/HSM/RESET/ENABLE)
H level input voltage1
L level input voltage1
Input hysteresis voltage1
H level input voltage2
L level input voltage2
Input hysteresis voltage2
VIH1
VIL1
VIHYS1
VIH2
VIL2
VIHYS2
2.0
0
-
2.4
0
-
-
-
0.8
-
-
0.8
-
V
V
V
V
V
V
-
0.13
-
VDD=5V
VDD=5V
VDD=5V
-
0.14
PD, DIR, HSM, RESET, ENABLE=3.3V,
per input
PD, DIR, HSM, RESET, ENABLE=0V,
per input
H level input current
L level input current
IIH
IIL
15
33
0
45
uA
nA
-200
+200
Input pull down resistance
Input pulse widths
Data setup time
RDOWN
tp
tDS
-
2
1
1
100
-
-
-
-
kΩ
us
us
us
-
-
-
Data hold time
tDH
MOTOR OUTPUT BLOCK (OUT1A/OUT1B/OUT2A/OUT2B)
Output ON resistance1
Output ON resistance2
Output leak current
RO1
RO2
IOLEAK
tDELAY
Io=500mA
-
-
-
-
-
1.2
0.9
1
0.3
-
1.45
1.25
5
-
1
Ω
Ω
uA
us
uA
VDD=5.0V,Io=500mA
ENABLE=0V,Vo=50V
Atturnon
Delay time
Sense terminal leak current
MO OUTPUT (MO)
L level output voltage
MO terminal leak current
MO OUTPUT (ALARM)
L level output voltage
ALARM terminal leak current
ISENSELEAK ENABLE=0V, VSENSE=1V(SENSE→GND)
VMO
IMOLEAK
IMO=10mA
VMO=5.5V
-
-
0.3
-
0.5
1
V
uA
VALARM
IALARMLEAK VALARM=5.5V
IALARM=10mA
-
-
0.3
-
0.5
1
V
uA
THERMAL SHUTDOWN BLOCK
Thermal shutdown operating
temperature
TTSD1
-
170
-
°C
Thermal shutdown recovery
temperature
Thermal shutdown hysteresis
TTSD2
-
-
140
30
-
-
°C
°C
∆TTSD
UNDER VOLTAGE LOCK OUT BLOCK
UVLO operating voltage
UVLO recovery voltage
UVLO hysteresis voltage
VUVLO1
VUVLO2
∆VUVLO
1.6
1.9
0.2
1.9
2.2
0.3
2.2
2.5
0.4
V
V
V
Ver.2010-03-26
- 4 -
NJW4351
PIN/ CIRCUIT OPERATIONAL DEFINITION
♦ Logic Input Pins Operational Voltage Definition
At VDD=3.3V
V
V
IN
5.0V
VDD
H level input voltage
H level input voltage
2.0V
2.0V
∆VHYS
0.8V
0V
0.8V
L level input voltage
H level L level
L level input voltage
L level
H level
L lebvel
0V
♦ Logic Input Pins Timing Definition
At VDD=3.3V
Master Pin
tp
tp
STEP
VIH=2.0V
VIL=0.8V
V
Slave Pins
HSM, DIR
RESET, PD
VIH=2.0V
tp
tp
VIL=0.8V
tDS1
tDH2
tDS2
tDH1
t
Data Setup Time and Data Hold Time are defined to positive edge of STEP.
tDS1,tDS2=Data Setup Time, tDH1,tDH2=Data Hold Time
t
DS1,tDH1=HSM,DIR,RESET, PD, tDS2,tDH2=HSM,DIR
- 5 -
NJW4351
♦ Thermal Shutdown Operational Definition
TSD Recovery TEMP
(Normal Operation)
Hysteresis
TEMP
TSD Operating TEMP
(Output Suspention)
-40°C
140°C 150°C 170°C
Tj
(Tj max)
♦ Under Voltage Protection Operational Definition
VDD
Recommended Operating Maximum Voltage
5.5V
Recommended Operating Minimum Voltage
2.7V
UVLO Recovery Voltage(Normal Operation)
Hysteresis Voltage
2.1V
1.9V
UVLO Operating Voltage(Output Suspention)
0V
Ver.2010-03-26
- 6 -
NJW4351
TERMINAL STATUS
STEP-Motor Stepping Pulse Input
MO-Motor Origin Position Output
STEP
Function
MO
Function
The translator is in noninitial
status
Negative Edge
-
H
Internal translator gose on
The translator is in initial
status
Positive Edge
OPEN
L
every this edge
-
HSM-HALF/FULL Step Mode Input
ALARM-Alarm Output
Function
HSM
H
Function
ALARM
H
HALF Step
Normal Operation
OUT terminals are OFF, as
the protection circuit
operates.
L
FULL Step
FULL Step
(Inside PULL DOWN)
L
OPEN
DIR-Direction Command Input
DIR
H
Function
REVERSE
L
FORWARD
FORWARD
(Inside PULL DOWN)
OPEN
ENABLE-Enable Input
ENABLE
H
Function
ACTIVE
OUT terminals are OFF , but
internal logic circuit is ON.
OUT terminals are OFF , but
internal logic circuit is ON.
(Inside PULL DOWN)
L
OPEN
RESET-Reset Input
RESET
Function
ACTIVE
H
L
RESET
RESET
(Inside PULL DOWN)
OPEN
PD-Power Down State Input
PD
H
Function
ACTIVE
L
RESET+POWER SAVING
RESET+POWER SAVING
(Inside PULL DOWN)
OPEN
- 7 -
NJW4351
TIMING CHART
POR
1
2
3
4
1
2
3
4
1
DIR
L
H
H
L
ENABLE
RESET
HSM
After
POR
OFF
ON
OFF
ON
STEP
1
2
3
4
STEP
L
OUT2B
OUT2A
OUT1B
OUT1A
MO
OFF ON
ON OFF OFF ON
ON ON OFF OFF
OFF OFF ON ON
OFF OFF OFF ON
ON OFF
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
ON
MO
ON
Fig.1 Full Step Mode / Forward Direction Sequence
POR
1
2
3
4
1
2
3
4
1
DIR
H
H
H
L
ENABLE
RESET
HSM
After
STEP
1
2
3
4
STEP
L
POR
OFF
ON
OFF
ON
OUT2B
OUT2A
OUT1B
OUT1A
MO
ON
ON OFF OFF
ON
ON OFF
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF OFF ON
OFF ON
ON OFF OFF ON
OFF OFF OFF ON
OFF
ON
ON
MO
ON
Fig.2 Full Step Mode / Reverse Direction Sequence
POR
1
2
3
4
5
6
7
8
1
DIR
L
H
H
H
L
ENABLE
RESET
HSM
After
STEP
1
2
3
4
5
6
7
8
STEP
POR
OFF
ON
OFF
ON
OUT2B
OUT2A
OUT1B
OUT1A
MO
OFF OFF OFF ON
ON
OFF ON
OFF OFF OFF OFF OFF ON
OFF OFF OFF OFF OFF OFF OFF ON
ON
ON OFF OFF
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
ON OFF OFF OFF OFF OFF ON
ON ON OFF OFF OFF OFF
ON ON
OFF
ON
ON
MO
ON
Fig.3 Half Step Mode / Forward Direction Sequence
POR
1
2
3
4
5
6
7
8
1
DIR
H
H
H
H
L
ENABLE
RESET
HSM
After
STEP
1
2
3
4
5
6
7
8
POR
OFF
ON
OFF
ON
STEP
OUT2B
OUT2A
OUT1B
OUT1A
MO
OFF ON
ON
ON OFF OFF OFF OFF
ON ON
ON OFF OFF
ON OFF OFF OFF OFF OFF ON
OFF OFF OFF OFF OFF OFF OFF ON
OFF OFF OFF OFF OFF ON
OFF OFF OFF ON ON
ON
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
ON
MO
ON
Fig.4 Half Step Mode / Reverse Direction Sequence
Ver.2010-03-26
- 8 -
NJW4351
POR
1
2
3
4
1
2
3
4
1
DIR
L
H
H
L
ENABLE
RESET
HSM
* When ENABLE is active OUT terminals are OFF,
STEP
L
but internal logic circuit is ON.
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.5 Full Step Mode / Enable Sequence
MO
ON
POR
POR
POR
1
1
1
2
2
2
3
4
5
6
1
1
7
2
2
8
3
3
1
4
4
DIR
L
H
H
H
L
ENABLE
RESET
HSM
* When ENABLE is active OUT terminals are OFF,
but internal logic circuit is ON.
STEP
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.6 Half Step Mode / Enable Sequence
MO
ON
*
*
*
DIR
L
H
H
L
ENABLE
RESET
HSM
* When RESET is active OUT terminals are OFF,
and internal logic circuit is to reset.
STEP
L
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.7 Full Step Mode / Reset Sequence
MO
ON
*
*
*
DIR
L
H
H
H
L
ENABLE
RESET
HSM
* When RESET is active OUT terminals are OFF,
and internal logic circuit is to reset.
STEP
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.8 Half Step Mode / Rest Sequence
MO
ON
- 9 -
NJW4351
POR
1
2
*
*
*
1
2
3
4
PD
H
L
DIR
ENABLE
RESET
HSM
H
H
L
* When PD is active it forces all settings to initialize
and be in stand-by mode, and MO is to be low.
STEP
L
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.9 Full Step Mode / PD Sequence
MO
ON
POR
1
2
1
2
3
4
*
*
*
PD
H
L
DIR
ENABLE
RESET
HSM
H
H
H
L
* When PD is active it forces all settings to initialize
and be in stand-by mode, and MO is to be low.
STEP
OUT2B
OUT2A
OUT1B
OUT1A
OFF
ON
OFF
ON
Fig.10 Full Step Mode / PD Sequence
MO
ON
Ver.2010-03-26
- 10 -
NJW4351
FUNCTION DESCRIPTION
The NJW4351 is designed for a high-performance constant-voltage unipolar stepper motor.
Using a general-purpose STEP&DIR motion controller, the device can easily control a stepper motor when
combined with a pulse generator.
The maximum value of the phase output is 55 V that keeps the voltage margin of the motor from exceeding the
limit, which is a common problem with unipolar winding systems. It simplifies the design of power control circuits
during phase turn-off.
LOGIC INPUT BLOCK
All inputs are LS-TTL compatible. Input Block1 (STEP) has Schmitt Comparator to keep the thresh voltage
unchanged even if logic supply voltage applied to it varies. It produces hesteresis voltage for noise immunity. Input
Block2 (PD, DIR, HSM, RESET, ENABLE) has Schmitt Inverter for the main purpose of noise immunity.
Inputs are internally connected to GND by pull-down resistances, being open, the device recognizes to be low.
• STEP – Stepping Pulse
The Translator starts counting on every positive edge of the STEP. In full step mode, the pulse turns the
stepper motor at the basic step angle. In half step mode, two pulses are required to turn the motor at the basic
step angle.
The DIR (direction) signal and HSM (half/full mode) are latched to the STEP positive edge and must therefore
be established before the start of the positive edge.
• DIR – Direction
The DIR signal determines the step direction. The direction of the stepper motor depends on how the
NJW4351 is connected to the motor. DIR can be modified anytime, it miss-steps when it is simultaneous with the
positive edge.
• HSM – Half/full Step Mode Switching
This signal determines whether the stepper motor runs at half step or full step mode. The Translator is set to
half step mode when HSM is low. Like DIR, HSM can be modified anytime but not when its simultaneous with
the positive edge.
• ENABLE – Phase Output Off
All phase outputs are turned off when ENABLE goes high reducing power consumption.
• RESET
A two-phase stepper motor repeats the same winding energizing sequence every angle that is a multiple of
four of the basic step. The Translator is repeated every four pulses in full step mode and every eight pulses in
half step mode.
When RESET is low, the Translator is initialized and the phase outputs turn-off.
When returning to high, the phase outputs are set to the initial energizing pattern output status.
• PD-Power Down
When PD goes low, it forces all settings to initialize and be in stand-by mode.
AND MO is to be low.
- 11 -
NJW4351
POR – Power On And Reset Function
The POR connected to VDD is to prevent miss-step under unstable condition of the inputting of logic supply
voltage VDD.
After inputting VDD, the phase outputs are set to the initial energizing pattern output status.
PHASE OUTPUT BLOCK
The phase output block consists of four open-drain DMOS FET capable of sinking max 1.5A.
MO – Motor Origin Monitor
In initialized position of the Translator, MO output low to indicate to external devices that it is the initial energizing
pattern output status.
Ver.2010-03-26
- 12 -
NJW4351
PRECAUTIONS
1. Never disconnect the device or PC-board when power is supplied.
2. Remember that excessive voltages might be generated by motor, even though clamping diodes are used.
3. Choose a motor that is proportional to the current you need to establish desired torque. A high supply voltage
will gain better stepping performance. If the motor is not specified for the VMM voltage, a current limiting
resistor will be necessary to connect in series with center tap. This changes the L/R time constant.
4. Avoid VMM and VDD power supplies with serial diodes (without filter capacitor) and common ground with
VDD.
5. To change actual motor rotation direction, exchange motor connections at OUT1A and OUT1B (OUT2A and
OUT2B).
6. Half-stepping
In the half-step mode, the power input to the motor alternates between one or two phase windings. In
half-step mode, motor resonances are reduced. In a two-phase motor, the electrical phase shift between the
windings is 90 degrees. The torque developed is the vector sum of two windings energized. Therefore, when
only one winding is energized, which is the case in half-step mode for every second step, the torque of the
motor is reduced by approximately 30%. This causes a torque ripple.
7. Drive Circuits
High-performance stepper motor operation requires windings to be energized immediately at phase turn-on
and quickly turned off when not in use.
8. Phase Turn-off Considerations
When the winding current is turned off, induced high voltage spike will damage the drive circuits if not
properly suppressed. Refer to the turn-off circuits described in Figures 11 to 14.
The voltage potential at the phase output terminal may sometimes become negative (GND or below) due to
the configuration of the turn-off circuit or the kickback voltage generated in it. In this condition there is a danger
of a malfunction occurring in the logic circuit inside the device.
8.1. Precautions against high voltage using the Zener-diode turn-off circuit
Refer the Zener-diode turn-off circuit (see Fig.15). Zener-diode voltage value is Vz and the forward voltage of
the diodes connected in series with the Zener-diode is Vd, the voltage VP of the phase output (OUT1A,
OUT1B, OUT2A, OUT2B) terminal when the turn-off operation have occurred is expressed by the following
equation. VP = VMM – (Vz + Vd)
The higher voltage, Vz, used, the shorter is the turn-off time of the winding current, thus producing high
speed operation of the stepper motor. Note, however, that depending on the Zener voltage, VZ, the voltage
potential at the phase output terminal may become negative, so design the turn-off circuit as indicated below.
8.1.1. When VP is a positive voltage: VMM > VZ + Vd
The circuit configuration is that of Fig.15.
Set the Zener voltage. For example, if VMM is 12 V, VZ + Vd is no higher than12V.
8.1.2 When VP is a negative voltage: VMM < VZ + Vd
The circuit configuration is that of Fig.16. In order to prevent a malfunction due to a negative voltage, be sure
to insert diodes in series with the phase output terminals.
- 13 -
NJW4351
R
i
i
VMM
VMM
Fig12 Resistor and turn off circuit.
Fig.11 Diode and turn off circuit.
VZ
i
VMM
i
VMM
VZ
Fig.14 Power regeneration and turn off circuit.
Fig.13 Zener diode and turn off circuit.
Negative voltage
prevention diode
Turn off circuit
(case of zener diode)
Turn off circuit
(case of zener diode)
VZ
VMM
VZ
VMM
Vd
Fig.16 Turn off negative voltage prevention circuit
by zener diode
Fig.15 Zener diode and turn off circuit 2.
Ver.2010-03-26
- 14 -
NJW4351
APPLICATION CIRCUIT
VMM
VDD
+
+
RMO
RAL AR M
VDD
NJW4351
POWER ON
RESET
OUT2B
OUT2A
OUT1B
OUT1A
Micro controller/
Microprocessor
output
HSM
STEP
output
output
output
GATE
DRIVE
DIR
TRANSLATOR
RESET
ENABLE
PD
output
output
Bias Circuit
MO
input
input
UNDER VOLTAGE
LOCK OUT
ALARM
SENSE1
SENSE2
THERMAL SHUT
DOWN
GND
- 15 -
NJW4351
TYPICAL CHARACTERISTICS
IDD - VDD
RON - VDD
Io=500mA, Ta=25oC
STEP=HSM=DIR=RESET=ENABLE=PD=VDD, Ta=25oC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
0
1
2
3
4
5
6
7
VDD [V]
VDD [V]
RON1 - Io
VDD=3.3V, Ta=25oC
RON2 - Io
VDD=5.0V, Ta=25oC
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
100
200
300
400
500
0
250
500
750
1000
1250
1500
Io [mA]
Io [mA]
Pd - Io
VDD=3.3V,Ta=25oC
Pd - Io
VDD=5.0V,Ta=25oC
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
9
8
7
6
5
4
3
2
1
0
Two channels on
Two channels on
One channel on
One channel on
0
100
200
300
400
500
0
250
500
750
1000
1250
1500
Io [mA]
Io [mA]
Ver.2010-03-26
- 16 -
NJW4351
TYPICAL CHARACTERISTICS
VOR - Io
VDD=3.3V, ENABLE=0V,Ta=25oC
VMO - IMO
VDD=3.3V, RESET=0V,Ta=25oC
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
5
10
15
20
0
250
500
750
1000
1250
1500
IMO [mA]
Io [mA]
RON1 - Tj
VDD=3.3V, Io=500mA
RON2 - Tj
VDD=5.0V, Io=500mA
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tj [deg.C]
Tj [deg.C]
VOR - Tj
VDD=3.3V,Io=500mA
IDD1 - Tj
VDD=3.3V
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-50
-25
0
25
50
Tj [deg.C]
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tj [deg.C]
- 17 -
NJW4351
TYPICAL CHARACTERISTICS
VMO - Tj
VDD=3.3V,IMO=10mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50
-25
0
25
50
75
100
125
150
Tj [deg.C]
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2010-03-26
- 18 -
相关型号：
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