NJW4350D [NJRC]
Stepper Motor Controller, 1.5A, DMOS, PDIP16, DIP-16;
| 型号： | NJW4350D |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Stepper Motor Controller, 1.5A, DMOS, PDIP16, DIP-16 电动机控制 光电二极管 |
| 文件： | 总10页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4350
UNIPOLAR STEPPER MOTOR DRIVER
♦ GENERAL DESCRIPTION
♦ PACKAGE OUTLINE
The NJW4350 is a high efficiency DMOS unipolar
stepper motor driver IC.
Low Ron DMOS driver realizes high power efficiency and
low heat generation of a stepper motor application.
The motor can be controlled by step and direction pulse
input which makes the programming task of a micro
controller simple and easy.
Enhanced control feature, Motor Origin output, INH and
RESET, make the NJW4350 applicable for a wide range of
stepper motor applications.
NJW4350D
NJW4350E2
♦ FEATURES
• Wide Voltage Range
5 to 50V
• Low RON=0.9Ω typ.@Io=±500mA(U&L)
• STEP & DIR input Operation
• Half / Full Step Operation
• RESET Function
• Output Power Save Function (INH)
• Motor Origin Monitor Output (MO)
• Thermal Shutdown Circuit
• BCD Process Technology
• Package Outline
DIP16, EMP16
♦ PIN CONNECTION
1
16
15
14
13
12
1.
PB1
16. VDD
15. MO
14. SGND
13. NC
12. RESET
11. INH
10. HSM
9. NC
2
3
4
5
6
7
8
PB2
PGND
PA2
DIR
11
10
STEP
NC
9
( DIP16 / EMP16 )
Fig.1 Pin Configuration
- 1 -
NJW4350
IDD
♦BLOCK DIAGLAM
VDD
NJW4350
VMM
POWER ON RESET
IPLEAK IO
PB1
PB2
PA1
PA2
IIH IIL
STEP
DIR
HSM
RESET
INH
PHASE LOGIC CIRCUIT
VP VDD
VIN
VDD
VIH
VIL
IMOLEAK
IMO
MO
Thermal Shut Down
VMO
SGND
PGND
Fig.2 Brock Diagram
♦PIN DESCRIPTION
Pin Pin name Description
1
2
3
4
5
6
7
B1 phase output with a maximum 1500 mA sinking open collector output
B2 phase output with a maximum 1500 mA sinking open collector output
Power ground terminal of motor supply VMM
A1 phase output with a maximum of 1500 mA sinking open collector
A2 phase output with a maximum of 1500 mA sinking open collector
Direction command input for determining motor turning direction
Motor stepping pulse input, phase logic operation triggered by negative
edge of STEP signal
PB1
PB2
PGND
PA1
PA2
DIR
STEP
8
9
Not connected
Not connected
NC
NC
10
Half/full step mode switching input
HSM
H level in full step mode and L level in half step mode
Phase output off input, all phase output is off at H level
External reset signal input terminal
11
12
13
14
15
16
INH
RESET
NC
SGND
MO
Not connected
Logic ground terminal of logic supply VDD
Phase output initial status detection output
Logic unit power supply voltage terminal
VDD
- 2 -
NJW4350
♦ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
NOTE
PARAMETER
RATINGS
SYMBOL (unit)
Maximum supply voltage
Logic supply voltage
Output current
55
7.0
Vmm (V)
VDD (V)
Io(A)
0.7
Peak output current
Logic Input Voltage
MO output current
Operating temperature
Storage temperature
1.5
Io(A)
-0.3 ~ VDD+0.3
-20
VID(V)
IMO(mA)
Topr (°C)
Tstg (°C)
-40 ~ +85
-50 ~ +150
1.6(DIP)
1.3(EMP)
Total power dissipation
PD (W)
♦RECOMMENDED OPERATING CONDITIONS
(Ta=25°C)
TYP. MAX. UNIT
PARAMETER
SYMBOL
TEST CONDITION
MIN.
Logic voltage range
VDD
4.5
5.0
-
5.5
50
125
0.5
-
V
V
Motor voltage
VMM
Tj
5
-40
-
Junction temperature range
Output current
-
°C
A
IO
-
Setup time
ts
-
0.5
1.0
µs
µs
Step pulse hold time
tp
-
-
- 3 -
NJW4350
♦ERECTRICAL CHARACTERISTICS
(Ta=25°C, VS=15V)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
-
TYP.
MAX. UNIT
♦GENERAL
STEP, DIR, HSM, RESET,
INH Terminal High-
Quiescent current
IDD
2.0
3.0
mA
Thermal shutdown
Thermal shutdown hysteresis
♦LOGIC
TSD
-
-
-
-
180
50
-
-
°C
°C
THYS
Input H voltage
VIH
VIL
-
-
3.5
-
-
V
V
Input L voltage
-
-
-
1.5
0.5
200
0.5
0.5
Input current (High)
Input current (Low)
MO output saturation voltgea
MO output leak current
♦OUTPUT
IIH
VIN=High
VIN=Low
IMO=10mA
VMO=7V
0.1
100
0.3
0.1
µA
µA
V
IIL
50
-
VMO
IMO LEAK
-
µA
Output resistance
Output leak current
Output turn ON time
Output turn OFF time
RONL
IP LEAK
TON
Io=500mA
-
-
-
0.9
1.0
-
5.0
-
Ω
µA
ns
ns
VP=50V
Io= 500mA,L=1mH
Io= 500mA,L=1mH
100
100
TOFF
HSM,DIR
VDD
GND
time
STEP,RESET
VDD
GND
time
time
tP
tS
PA1,PA2,PB1,PB2
IO
GND
tON /tOFF
Fig.3 Timing Chart
- 4 -
NJW4350
VM
≥
5V
C
10ƒΚF
-
R1
R2
VDD
OPTIONAL SENSOR
MO
CMOS
IO Device
STEP
STEP
DIR
MOTOR
CW/CCW
HALF/FULL
HSM
NJW4350
PB2
RESET
RESET
INH
PB1
PA1
PA2
NORMAL/INHBIT
GND
D1-D4
SGND
PGND
11DF2or31DF2
Nihon Inter Ele.
GND(VDD)
GND(VMM)
Fig.4 Application Circuit
♦Function description
The NJW4350 is a high-performance low-voltage driver system for driving stepping motors with unipolar
winding.
Employing a general-purpose STEP&DIR motion controller, it can easily control a stepping motor when
combined with a pulse generator.
The phase output is as high as 55 V max. This prevents the phase output voltage margin of the motor from
being exceeded, which is a common problem with unipolar winding systems and also simplifies the design of
power control circuits during phase turn off.
♦Logic input
All inputs are LS-TT compatible. When the logic input is open, the circuit recognizes any open logic inputs as H
level. The NJW4350 has built-in phase logic for optimum control of the stepping motor.
• STEP – Stepping pulse
The built-in phase logic sequencer goes UP on every negative edge of the STEP signal (pulse). In full step
mode, the pulse turns the stepping motor at the basic step angle. In half step mode, two pulses are required to
turn the motor at the basic step angle.
The DIR (direction) signal and HSM (half/full mode) are latched to the STEP negative edge and must
therefore be established before the start of the negative edge. Note the setup time ts in Figure 3.
• DIR – direction
The DIR signal determines the step direction. The direction of the stepping motor depends on how the
NJW4350 is connected to the motor. Although DIR can be modified this should be avoided since a misstep of
1 pulse increment may occur if it is set simultaneous with the negative edge. See the timing chart in Figure 3.
• HSM – half/full step mode switching
This signal determines whether the stepping motor turns at half step or full step mode. The built-in phase
logic is set to the half step mode when HSM is low level. Although HSM can be modified this should be
avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See
the timing chart in Figure 3.
- 5 -
NJW4350
• INH – phase output off
All phase output is turned off when INH goes high reducing power consumption (consumption current).
• RESET
A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of
four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every
eight pulses in the half step mode.
RESET forces to initialize the phase logic to sequence start mode.
When RESET is at L level, the phase logic is initialized and the phase output is turned off.
When RESET recovers to H level, the phase output resumes the energizing pattern output at sequence
start of phase logic. Refer to Figure 5 for a reset timing chart.
♦POR – power on and reset function
The internal power-on and reset circuit, which is connected to Vcc, resets the phase logic and turns off phase
output when the power is supplied to prevent missteps.
Each time the power is turned on, the energizing pattern of phase logic at sequence start is output.
♦Phase output unit
The phase output unit is composed of four open collector transistors that are directly connected to the stepping
motor as shown in Figure 4.
♦MO – origin monitor
At sequence start of the phase logic or after POR or external RESET, an L level output is made to indicate to
external devices that the energizing sequence is in initial status.
approx 3.0V∼ 4.0V
Vcc
STEP
RESET
PB1/PA1
PB2/PA
Normal
sequence
Normal
Phase
output OFF
sequence
After internal phase
logic initialize output
POR function
Fig.5 POR and external reset timing
- 6 -
NJW4350
POR
1
2
3
4
1
2
3
4
1
DIR
H
L
INH
HSM
STEP
H
H
STEP
After
RESAET
OFF
ON
OFF
1
2
3
4
PB1
PB2
PA1
PA2
OFF
ON
ON
ON
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
PB1 OFF
PB2 ON
PA1 OFF
PA2 ON
ON
OFF
OFF
MO ON
Fig.6 Full step mode / CW sequence
POR
1
2
3
4
1
2
3
4
1
DIR
L
L
INH
HSM
STEP
H
H
STEP
After
RESAET
OFF
ON
OFF
1
2
3
4
PB1
PB2
PA1
PA2
ON
OFF
OFF
ON
ON
OFF
ON
OFF
ON
ON
OFF
ON
OFF
ON
PB1 OFF
PB2 ON
PA1 OFF
PA2 ON
ON
OFF
OFF
Fig.7 Full step mode / CCW sequence
MO ON
POR
1
2
3
4
5
6
7
8
1
DIR
L
L
L
H
INH
STEP
After
RESAET
OFF
ON
OFF
1
2
3
4
5
6
7
8
HSM
STEP
PB1
PB2
PA1
PA2
OFF OFF OFF
ON ON
OFF ON
OFF OFF OFF OFF OFF
ON
ON
ON
OFF OFF
ON
OFF OFF OFF OFF
ON ON ON
OFF OFF OFF OFF OFF
ON ON
PB1 OFF
PB2 ON
PA1 OFF
PA2 ON
ON
Fig.8 Half step mode / CW sequence
MO ON
POR
1
2
3
4
5
6
7
8
1
DIR
L
L
L
H
INH
HSM
STEP
STEP
After
RESAET
OFF
ON
OFF
1
2
3
4
5
6
7
8
PB1
PB2
PA1
PA2
OFF ON
ON
ON
OFF OFF OFF OFF
PB1 OFF
PB2 ON
PA1 OFF
PA2 ON
OFF OFF OFF OFF OFF
OFF OFF OFF ON ON
ON ON
ON
ON
ON
OFF OFF
ON
ON
ON
OFF OFF OFF OFF OFF
Fig.9 Half step mode / CCW sequence
MO ON
POR
1
2
3
4
5
6
7
8
1
DIR
H
H
L
INH
HSM
STEP
H
PB1 OFF
PB2 OFF
PA1 OFF
PA2 OFF
Fig.10 Half step mode / INH sequence
MO
ON
- 7 -
NJW4350
♦ Application examples
• Logic input unit
The circuit handles an open state in the logic input unit as an H level input. Unused input units should be
fixed at Vdd level to maximize noise resistance characteristics.
•Phase output unit
The phase output unit is provided with a power sink to enable unipolar drive of stepping motor windings. The
resistor connected to the common line of the winding determines the maximum motor power.
To protect output transistors from kickback power, a high-speed free wheeling diode is required. A example
solution is shown in Figures 11 to 14.
♦I/O signal sequence in each drive mode
Timing charts for I/O signals in each drive mode are shown in Figures 6 to 10. The left side shows input and
output signals after POR.
♦Precautions
1. Do not remove ICs or PCBs when power is supplied.
2. Note that some stepping motors may generate excessive voltages even when free wheeling diode is used.
3. Select a stepping motor with the required power rating to obtain the required torque.
Generally, the higher the input voltage of the stepping motor, the higher rpm it will produce. When the supply
voltage is higher than stepping motor rated voltage, a current limit resistor must be used to connect the
common winding to the power supply. Use the L/R time constant of the resistor to obtain optimum high-speed
rpm characteristics from the stepping motor.
4. Do not use motor power supplies (without an output capacitor) with a serial diode. Nor use ground lines with
common impedance with Vcc, instead make a one point ground connection using the S ground terminal (pin
3) and S ground terminal (pin14) of the IC.
5. To reverse motor rotation, reverse PA and PA2 (or PB1 and PB2) stepping motor connections.
6. Drive circuit
High-performance stepping motor operation requires that the windings are energized speedily at phase turn
on, and that energizing is quickly turned off at turn off.
7. Phase turnoff problems
The drive circuit may be damaged if the kickback voltage induced when the energizing of the windings is
turned off (when winding current is turned off) is not adequately suppressed. Refer to the turn-off circuit
described in Figures 11 to 14.
The voltage potential at the phase output terminal may sometimes become negative (GND or below) due to the
configuration of the turn-off circuit or the kickback voltage generated in it. In this condition there is a danger of a
malfunction occurring in the logic circuit inside the IC.
[Precautions to be observed at the zener diode turn-off circuit]
In the zener diode turn-off circuit (see Fig.15), if the motor supply voltage is VMM, the zener voltage used is VZ,
and the forward voltage of the diodes connected in series with the zener diode is Vd, the voltage,VP, at the phase
output terminal when the turn-off operation takes place is expressed by the following equation. VP = VMM – (VZ +
Vd)
The higher the zener voltage, VZ, used, the shorter is the turn-off time of the winding current, thus realizing high
speed operation of the stepping motor. Note, however, that depending upon the zener voltage, VZ, the voltage
potential at the phase output terminal may become negative, so configure the turn-off circuit as indicated below.
(1) When VP is a positive voltage: VMM > VZ + Vd
The circuit configuration is that of Fig.15.
Set the zener voltage so that if VMM is 12 V, for example, VZ + Vd becomes no higher than 12 V.
- 8 -
NJW4350
(2) When VP is a negative voltage: VMM < VZ + Vd
The circuit configuration is that of Fig.16. In order to prevent a malfunction due to a negative voltage, be sure
to insert diodes in series with the phase output terminals.
• It is recommended that you use Schottky diodes that have a small forward voltage for these diodes.
R
i
i
VMM
VMM
VMM
VMM
Fig12 Resistor and turn off circuit.
Fig.11 Diode and turn off circuit.
VZ
i
VMM
i
VZ
Fig.14 Power regeneration and turn off circuit.
Fig.13 Zener diode and turn off circuit.
Negative voltage
prevention diode
Turn off circuit
Turn off circuit
(case of zener diode)
(case of zener diode)
VZ
VMM
VZ
Vd
Fig.16 Turn off negative voltage prevention circuit
by zener diode
Fig.15 Zener diode and turn off circuit 2.
- 9 -
NJW4350
♦ ELECTRICAL CHARACTERISTICS EXAMPLES
VDD VS. IDD1
VDD VS. IDD2
INPUT=L Ta=25[dg.C]
INPUT=H ta=25[dg.C]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
VCC[V]
VCC[V]
Iout VS. Vout
VDD=5V Ta=25[dg.C]
IMO VS. VMO
VDD=5V Ta=25[dg.C]
2.0
1.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
PB1
PB2
0.8
0.6
0.4
0.2
0.0
0
200 400 600 800 1000 1200 1400 1600
Iout[mA]
0
20
40
60
80
100
IMO[mA]
Iout VS. Vout
VDD=7V Ta=25[dg.C]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
0
200 400 600 800 1000 1200 1400 1600
Iout[mA]
- 10 -
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