MC68HC908EY16VFA_技术文档

68HC908EY16

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Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets and/or

specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for

each customer application by customer’s technical experts. Motorola does not convey

any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Motorola product could create a

situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall

indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and

are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc.

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List of Paragraphs

List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Section 1. General Description . . . . . . . . . . . . . . . . . . . .33

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .43

Section 3. Random Access Memory (RAM) . . . . . . . . . .57

Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .59

Section 5. Central Processor Unit (CPU) . . . . . . . . . . . .69

Section 6. System Integration Module (SIM) . . . . . . . . .87

Section 7. Internal Clock Generator (ICG) Module. . . .111

Section 8. Configuration Registers (CONFIG1 &

CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . .149

Section 9. Break Module (BRK) . . . . . . . . . . . . . . . . . . .157

Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .167

Section 11. Computer Operating Properly (COP) Module

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Section 12. Low-Voltage Inhibit (LVI) Module . . . . . . .187

Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . .193

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Section 14. Enhanced Serial Communications Interface

(ESCI) Module . . . . . . . . . . . . . . . . . . . . . . .201

Section 15. Serial Peripheral Interface (SPI) Module . .247

Section 16. Timer Interface A (TIMA) Module . . . . . . . .279

Section 17. Timer Interface B (TIMB) Module . . . . . . . .303

Section 18. BEMF Module . . . . . . . . . . . . . . . . . . . . . . .327

Section 19. Keyboard Interrupt (KBD) Module . . . . . . .329

Section 20. Timebase Module (TBM). . . . . . . . . . . . . . .337

Section 21. Analog-to-Digital Converter (ADC) Module

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

Section 22. Input/Output (I/O) Ports . . . . . . . . . . . . . . .363

Section 23. Preliminary Electrical Specifications . . . .381

Section 24. Mechanical Specifications . . . . . . . . . . . . .395

Section 25. Ordering Information . . . . . . . . . . . . . . . . .397

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

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Table of Contents

List of Paragraphs

Table of Contents

List of Figures

List of Tables

Section 1. General Description

1.1

1.2

1.3

1.4

1.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Pins (V_DDand V_SS). . . . . . . . . . . . . . . . . . . .39

Oscillator Pins (PTC4/OSC1 and PTC3/OSC2). . . . . . . . . .40

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .40

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

Analog Power Supply/Reference Pins (V_DDA, V_REFH, V_SSA

and V_REFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Port A I/O Pins (PTA6/SS, PTA5/SPSCK,

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

1.6.8

1.6.9

PTA4/KDB4–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port B I/O Pins (PTB7/AD7/TBCH1, PTB6/AD6/TBCH0,

PTB5/AD5–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port C I/O Pins (PTC4/OSC1, PTC3/OSC2, PTC2/MCLK,

PTC1/MOSI, PTC0/MISO) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port D I/O Pins (PTD1/TACH1–PTD0/TACH0) . . . . . . . . . .42

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1.6.10 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

Section 2. Memory Map

2.1

2.2

2.3

2.4

2.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .43

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Section 3. Random Access Memory (RAM)

3.1

3.2

3.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Section 4. FLASH Memory

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .62

FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .63

FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . . .64

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .67

4.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

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Section 5. Central Processor Unit (CPU)

5.1

5.2

5.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

5.4

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.5

Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.6

5.6.1

5.6.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.7

5.8

5.9

CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .78

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Section 6. System Integration Module (SIM)

6.1

6.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6.3

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .90

Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . .90

Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .91

6.3.1

6.3.2

6.3.3

6.4

6.4.1

6.4.2

6.4.2.1

6.4.2.2

6.4.2.3

Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .91

External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .93

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Computer Operating Properly (COP) Reset. . . . . . . . . . .95

Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

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6.4.2.4

6.4.2.5

6.4.2.6

Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Forced Monitor Mode Entry Reset (MENRST). . . . . . . . .96

Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . .96

6.5

SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .96

SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .97

SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .97

6.5.1

6.5.2

6.5.3

6.6

Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .101

6.6.1

6.6.1.1

6.6.1.2

6.6.2

6.6.3

6.6.4

6.7

6.7.1

6.7.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

6.8

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .106

SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .107

SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .109

6.8.1

6.8.2

6.8.3

Section 7. Internal Clock Generator (ICG) Module

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

7.1

7.2

7.3

7.4

7.4.1

7.4.2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Clock Enable Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . .116

7.4.2.1

7.4.2.2

7.4.2.3

7.4.2.4

7.4.3

Digitally Controlled Oscillator. . . . . . . . . . . . . . . . . . . . .117

Modulo N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Frequency Comparator . . . . . . . . . . . . . . . . . . . . . . . . .117

Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

External Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . .119

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7.4.3.1

7.4.3.2

7.4.4

7.4.4.1

7.4.4.2

7.4.4.3

7.4.5

External Oscillator Amplifier. . . . . . . . . . . . . . . . . . . . . .119

External Clock Input Path . . . . . . . . . . . . . . . . . . . . . . .120

Clock Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Clock Monitor Reference Generator . . . . . . . . . . . . . . .122

Internal Clock Activity Detector . . . . . . . . . . . . . . . . . . .123

External Clock Activity Detector. . . . . . . . . . . . . . . . . . .124

Clock Selection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Clock Selection Switches. . . . . . . . . . . . . . . . . . . . . . . .126

Clock Switching Circuit. . . . . . . . . . . . . . . . . . . . . . . . . .126

7.4.5.1

7.4.5.2

7.5

7.5.1

7.5.2

7.5.3

Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Switching Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . .128

Enabling the Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . .129

Using Clock Monitor Interrupts. . . . . . . . . . . . . . . . . . . . . .130

Quantization Error in DCO Output . . . . . . . . . . . . . . . . . . .131

Digitally Controlled Oscillator. . . . . . . . . . . . . . . . . . . . .131

Binary Weighted Divider . . . . . . . . . . . . . . . . . . . . . . . .132

Variable-Delay Ring Oscillator . . . . . . . . . . . . . . . . . . . .132

Ring Oscillator Fine-Adjust Circuit . . . . . . . . . . . . . . . . .133

Switching Internal Clock Frequencies . . . . . . . . . . . . . . . .133

Nominal Frequency Settling Time . . . . . . . . . . . . . . . . . . .134

Settling to Within 15 Percent . . . . . . . . . . . . . . . . . . . . .135

Settling to Within 5 Percent . . . . . . . . . . . . . . . . . . . . . .135

Total Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Trimming Frequency on the Internal Clock Generator . . . .137

7.5.4

7.5.4.1

7.5.4.2

7.5.4.3

7.5.4.4

7.5.5

7.5.6

7.5.6.1

7.5.6.2

7.5.6.3

7.5.7

7.6

7.6.1

7.6.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

7.7

CONFIG Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

External Clock Enable (EXTCLKEN) . . . . . . . . . . . . . . . . .139

External Crystal Enable (EXTXTALEN) . . . . . . . . . . . . . . .139

Slow External Clock (EXTSLOW) . . . . . . . . . . . . . . . . . . .140

Oscillator Enable In Stop (OSCENINSTOP) . . . . . . . . . . .140

7.7.1

7.7.2

7.7.3

7.7.4

7.8

Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . .141

ICG Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

ICG Multiplier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

ICG Trim Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

7.8.1

7.8.2

7.8.3

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7.8.4

7.8.5

ICG DCO Divider Register . . . . . . . . . . . . . . . . . . . . . . . . .147

ICG DCO Stage Register . . . . . . . . . . . . . . . . . . . . . . . . . .148

Section 8. Configuration Registers (CONFIG1 &

CONFIG2)

8.1

8.2

8.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Section 9. Break Module (BRK)

9.1

9.2

9.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

9.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Flag Protection During Break Interrupts. . . . . . . . . . . . . . .160

CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .160

TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .160

COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .160

9.4.1

9.4.2

9.4.3

9.4.4

9.5

9.5.1

9.5.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

9.6

Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Break Status and Control Register. . . . . . . . . . . . . . . . . . .162

Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .163

SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .163

SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .165

9.6.1

9.6.2

9.6.3

9.6.4

Section 10. Monitor ROM (MON)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

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10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

10.5 Monitor Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

10.5.1 Normal Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.5.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

10.6 Monitor Mode Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

10.7 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.8 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.9 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.9.1 Force Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

10.9.2 Normal Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

10.10 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

10.11 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Section 11. Computer Operating Properly (COP) Module

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

11.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.4.7 COPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.4.8 COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

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11.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

11.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . . . .186

Section 12. Low-Voltage Inhibit (LVI) Module

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

12.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

12.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .189

12.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .189

12.4.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

12.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

12.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

12.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Section 13. External Interrupt (IRQ)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .198

13.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .198

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Section 14. Enhanced Serial Communications Interface

(ESCI) Module

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

14.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

14.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

14.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

14.5.2.1

14.5.2.2

14.5.2.3

14.5.2.4

14.5.2.5

14.5.2.6

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .207

Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .211

Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .211

14.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

14.5.3.1

14.5.3.2

14.5.3.3

14.5.3.4

14.5.3.5

14.5.3.6

14.5.3.7

14.5.3.8

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .216

Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

14.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

14.7 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . .221

14.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

14.8.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .222

14.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .222

14.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

14.9.1 ESCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . .223

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14.9.2 ESCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .226

14.9.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . .229

14.9.4 ESCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

14.9.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

14.9.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

14.9.7 ESCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . .236

14.9.8 ESCI Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . .238

14.10 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

14.10.1 ESCI Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . .242

14.10.2 ESCI Arbiter Data Register . . . . . . . . . . . . . . . . . . . . . . . .244

14.10.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

14.10.4 Arbitration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Section 15. Serial Peripheral Interface (SPI) Module

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

15.4 Pin Name and Register Name Conventions. . . . . . . . . . . . . .249

15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

15.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

15.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

15.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

15.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .254

15.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .255

15.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .256

15.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .257

15.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

15.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

15.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

15.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

15.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .264

15.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

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15.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

15.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

15.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

15.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .267

15.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

15.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .268

15.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .269

15.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

15.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

15.13.5 V_SS(Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

15.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

15.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

15.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .274

15.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

Section 16. Timer Interface A (TIMA) Module

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

16.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .283

16.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

16.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

16.4.3.1

16.4.3.2

Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .285

Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .286

16.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .286

16.4.4.1

16.4.4.2

16.4.4.3

Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .287

Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .288

PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

16.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

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16.7 TIMA During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .291

16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

16.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . .293

16.9.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .295

16.9.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .296

16.9.4 TIMA Channel Status and Control Registers . . . . . . . . . . .297

16.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .301

Section 17. Timer Interface B (TIMB) Module

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

17.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .307

17.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

17.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

17.4.3.1

17.4.3.2

Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .309

Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .310

17.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .310

17.4.4.1

17.4.4.2

17.4.4.3

Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .312

Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .313

PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

17.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

17.7 TIMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .316

17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

17.8.1 TIMB Channel I/O Pins (PTB7/TBCH1–PTB6/TBCH0) . . .316

17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

17.9.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . .317

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17.9.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .320

17.9.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .321

17.9.4 TIMB Channel Status and Control Registers . . . . . . . . . . .322

17.9.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .326

Section 18. BEMF Module

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

18.4 BEMF Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

18.5 Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

18.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

Section 19. Keyboard Interrupt (KBD) Module

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330

19.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

19.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .334

19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

19.8.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .335

19.8.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .336

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Section 20. Timebase Module (TBM)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338

20.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

20.6 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

20.8 Timebase Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . .343

Section 21. Analog-to-Digital Converter (ADC) Module

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

21.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

21.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

21.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .349

21.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

21.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

21.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

21.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

21.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

21.7.1 ADC Analog Power Pin (V_DDA) . . . . . . . . . . . . . . . . . . . . .351

21.7.2 ADC Analog Ground Pin (V_SSA). . . . . . . . . . . . . . . . . . . . .352

21.7.3 ADC Voltage Reference Pin (V_REFH) . . . . . . . . . . . . . . . . .352

21.7.4 ADC Voltage Reference Low Pin (V_REFL) . . . . . . . . . . . . .352

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21.7.5 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . .352

21.7.6 ADC External Connections. . . . . . . . . . . . . . . . . . . . . . . . .352

21.7.6.1

21.7.6.2

21.7.6.3

V_REFHand V_REFL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

ANx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

21.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .354

21.8.2 ADC Data Register High (ADRH) and Data Register Low

(ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

21.8.2.1

21.8.2.2

21.8.2.3

21.8.2.4

Left Justified Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .358

Left Justified Signed Data Mode . . . . . . . . . . . . . . . . . .359

Eight Bit Truncation Mode . . . . . . . . . . . . . . . . . . . . . . .360

21.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

Section 22. Input/Output (I/O) Ports

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

22.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . .366

22.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368

22.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368

22.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .369

22.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

22.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

22.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .372

22.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

22.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

22.6.2 Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .375

22.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

22.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

22.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . .378

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Section 23. Preliminary Electrical Specifications

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .381

23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .383

23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

23.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .384

23.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386

23.8 Internal Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . .387

23.9 External Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . .387

23.10 Trimmed Accuracy of the Internal Clock Generator . . . . . . . .388

23.10.1 Trimmed Internal Clock Generator Characteristics . . . . . .388

23.11 Analog-to-Digital Converter (ADC) Characteristics. . . . . . . . .389

23.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

23.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

Section 24. Mechanical Specifications

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

24.3 32-Pin QFP (Case Number 873) . . . . . . . . . . . . . . . . . . . . . .396

Section 25. Ordering Information

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

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Revision History

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Changes from Rev 1.0 published on 17 April 2002 to Rev 2.0 pub-

lished in May 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Changes from Rev 0.4 published internally on 9 April 2002 to Rev

1.0 published on 17 April 2002 . . . . . . . . . . . . . . . . . . . . . . . .400

Changes from Rev 0.3 published on 6 September 2001 to Rev

0.4 published internally on 9 April 2002 . . . . . . . . . . . . . . . . .400

Changes from Rev 0.2 published on 1 August 2001 to Rev 0.3

published on 6 September 2001. . . . . . . . . . . . . . . . . . . . . . .401

Changes from Rev 0.0 published on 17 July 2001 to Rev 0.2 pub-

lished on 1 August 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

Glossary

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Figure

Title

Page

1-1

1-2

1-3

2-1

2-2

4-1

4-2

4-3

4-4

5-1

5-2

5-3

5-4

5-5

5-6

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .47

FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .60

FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .66

FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .67

FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .67

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .75

SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

System Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

6-10 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .100

6-11 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6-12 Wait Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .103

6-13 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .104

6-14 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

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6-15 Stop Mode Recovery from Interrupt . . . . . . . . . . . . . . . . . . . .105

6-16 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .106

6-17 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .107

6-18 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .109

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

ICG Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .114

Internal Clock Generator Block Diagram . . . . . . . . . . . . . . . .116

External Clock Generator Block Diagram. . . . . . . . . . . . . . . .119

Clock Monitor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .121

Internal Clock Activity Detector. . . . . . . . . . . . . . . . . . . . . . . .123

External Clock Activity Detector . . . . . . . . . . . . . . . . . . . . . . .124

Clock Selection Circuit Block Diagram . . . . . . . . . . . . . . . . . .125

Code Example for Switching Clock Sources . . . . . . . . . . . . .128

Code Example for Enabling the Clock Monitor. . . . . . . . . . . .129

7-10 ICG Module I/O Register Summary . . . . . . . . . . . . . . . . . . . .142

7-11 ICG Control Register (ICGCR) . . . . . . . . . . . . . . . . . . . . . . . .144

7-12 ICG Multiplier Register (ICGMR) . . . . . . . . . . . . . . . . . . . . . .146

7-13 ICG Trim Register (ICGTR) . . . . . . . . . . . . . . . . . . . . . . . . . .147

7-14 ICG DCO Divider Control Register (ICGDVR) . . . . . . . . . . . .147

7-15 ICG DCO Stage Control Register (ICGDSR) . . . . . . . . . . . . .148

8-1

8-2

9-1

9-2

9-3

9-4

9-5

9-6

Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .150

Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .150

Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .159

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Break Status and Control Register (BSCR) . . . . . . . . . . . . . .162

Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .163

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .163

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .165

10-1 Normal Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . .171

10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10-3 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

10-5 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

10-6 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .179

10-7 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .180

11-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

11-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .185

12-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .188

12-2 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .190

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13-1 IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

13-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

13-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .198

14-1 ESCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .205

14-2 ESCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .206

14-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

14-4 ESCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

14-5 ESCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .213

14-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

14-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

14-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

14-9 ESCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . .224

14-10 ESCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . . .227

14-11 ESCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . . .229

14-12 ESCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . .231

14-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14-14 ESCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . .235

14-15 ESCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . .236

14-16 ESCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . .236

14-17 ESCI Prescaler Register (SCPSC). . . . . . . . . . . . . . . . . . . . .238

14-18 ESCI Arbiter Control Register (SCIACTL) . . . . . . . . . . . . . . .242

14-19 ESCI Arbiter Data Register (SCIADAT) . . . . . . . . . . . . . . . . .244

14-20 Bit Time Measurement with ACLK = 0 . . . . . . . . . . . . . . . . . .245

14-21 Bit Time Measurement with ACLK = 1, Scenario A . . . . . . . .245

14-22 Bit Time Measurement with ACLK = 1, Scenario B . . . . . . . .245

15-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .251

15-2 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .252

15-3 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .255

15-4 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .256

15-5 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . .258

15-6 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .260

15-7 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .261

15-8 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .264

15-9 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .265

15-10 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

15-11 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .272

15-12 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .275

15-13 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .278

68HC908EY16 — Rev 2.0

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27

List of Figures

16-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

16-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .281

16-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .287

16-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .293

16-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . .295

16-6 TIMA Counter Modulo Registers (TMODH and TMODL) . . . .296

16-7 TIMA Channel Status and Control Registers (TASC0–TASC1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

16-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

16-9 TIMA Channel Registers (TACH0H/L–TACH1H/L) . . . . . . . .302

17-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

17-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .305

17-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .311

17-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .318

17-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . .320

17-6 TIMB Counter Modulo Registers (TMODH and TMODL) . . . .321

17-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

17-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325

17-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . .326

18-1 BEMF Register (BEMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

19-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .331

19-2 KBD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .331

19-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .335

19-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .336

20-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

20-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . .343

21-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

21-2 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . .350

21-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .354

21-4 ADC Data Register High (ADRH) and Low (ADRL) . . . . . . . .357

21-5 ADC Data Register High (ADRH) and Low (ADRL) . . . . . . . .358

21-6 ADC Data Register High (ADRH) and Low (ADRL) . . . . . . . .359

21-7 ADC Data Register High (ADRH) and Low (ADRL) . . . . . . . .360

21-8 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . .361

22-1 68HC908EY16 I/O Port Register Summary . . . . . . . . . . . . . .364

22-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .365

22-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .366

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22-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

22-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .368

22-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .369

22-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370

22-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .371

22-9 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .372

22-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

22-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .374

22-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .375

22-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375

22-14 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .377

22-15 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .378

22-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

23-1

23-2

SPI Master Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

SPI Slave Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

68HC908EY16 — Rev 2.0

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List of Figures

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MOTOROLA

Advance Information — 68HC908EY16

List of Tables

Table

Title

Page

2-1

4-1

5-1

5-2

6-1

6-2

6-3

7-1

7-2

7-3

7-4

8-1

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Protect Start Address Examples. . . . . . . . . . . . . . . . . . . . . . . .68

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Correction Sizes from DLF to DCO . . . . . . . . . . . . . . . . . . . .118

Quantization Error in ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Typical Settling Time Examples . . . . . . . . . . . . . . . . . . . . . . .136

ICG Module Register Bit Interaction Summary. . . . . . . . . . . .143

External Clock Option Settings. . . . . . . . . . . . . . . . . . . . . . . .152

10-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

10-2 Monitor Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10-3 Monitor Mode Vector Relocation . . . . . . . . . . . . . . . . . . . . . .172

10-4 Normal Monitor Mode Baud Rate Selection . . . . . . . . . . . . . .174

10-5 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .176

10-6 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .176

10-7 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .177

10-8 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .177

10-9 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .178

10-10 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .178

12-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

14-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

14-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

14-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

14-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

14-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .225

14-6 ESCI LIN Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

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List of Tables

14-7 ESCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . .237

14-8 ESCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .238

14-9 ESCI Prescaler Division Ratio . . . . . . . . . . . . . . . . . . . . . . . .239

14-10 ESCI Prescaler Divisor Fine Adjust . . . . . . . . . . . . . . . . . . . .239

14-11 ESCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . .241

14-12 ESCI Arbiter Selectable Modes . . . . . . . . . . . . . . . . . . . . . . .242

15-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

15-2 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

15-3 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .250

15-4 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

15-5 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

15-6 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .277

16-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

16-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .299

17-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

17-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .324

20-1 Timebase Divider Selection . . . . . . . . . . . . . . . . . . . . . . . . . .340

21-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

21-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

22-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

22-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370

22-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

22-4 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376

22-5 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

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Section 1. General Description

1.1 Contents

1.2

1.3

1.4

1.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Pins (V_DDand V_SS). . . . . . . . . . . . . . . . . . . .40

Oscillator Pins (PTC4/OSC1 and PTC3/OSC2). . . . . . . . . .40

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .40

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

Analog Power Supply/Reference Pins (V_DDA, V_REFH, V_SSA

and V_REFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Port A I/O Pins (PTA6/SS, PTA5/SPSCK,

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

1.6.8

1.6.9

PTA4/KBD4–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port B I/O Pins (PTB7/AD7/TBCH1, PTB6/AD6/TBCH0,

PTB5/AD5–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port C I/O Pins (PTC4/OSC1, PTC3/OSC2, PTC2/MCLK,

PTC1/MOSI, PTC0/MISO) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Port D I/O Pins (PTD1/TACH1–PTD0/TACH0) . . . . . . . . . .42

1.6.10 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

68HC908EY16 — Rev 2.0

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General Description

33

General Description

1.2 Introduction

The 68HC908EY16 is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the

family use the enhanced M68HC08 central processor unit (CPU08) and

are available with a variety of modules, memory sizes and types, and

package types.

1.3 Features

For convenience, features have been organized to reflect:

• Standard features of the 68HC908EY16

• Features of the CPU08

Standard features of the MC68HC908EY16 include:

• High-performance M68HC08 architecture optimized for

C-compilers

• Fully upward-compatible object code with M6805, M146805, and

M68HC05 Families

• 8-MHz internal bus frequency at 5V

• Internal oscillator requiring no external components:

– Software selectable bus frequencies

– 25 percent accuracy with trim capability to 2 percent

– Clock monitor

– Option to allow use of external clock source or external

crystal/ceramic resonator

• 15,872 bytes of on-chip FLASH memory with in-circuit

programming

• FLASH program memory security¹

• 512 bytes of on-chip random-access memory (RAM)

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.

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68HC908EY16 — Rev 2.0

General Description

MOTOROLA

General Description

Features

• Low voltage inhibit (LVI) module

• Internal clock generator module (ICG)

• Two 16-bit, 2-channel timer (TIMA and TIMB) interface modules

with selectable input capture, output compare, and pulse-width

modulation (PWM) capability on each channel

• 8-channel, 10-bit successive approximation analog-to-digital

converter (ADC)

• Enhanced serial communications interface module (ESCI) for

local interconnect network (LIN) connectivity

• Serial peripheral interface (SPI)

• Timebase Module (TBM)

• 5-bit keyboard interrupt (KBI) with wakeup feature

• 24 general-purpose input/output (I/O) pins

• External asynchronous interrupt pin with internal pullup (IRQ)

• System protection features:

– Optional computer operating properly (COP) reset

– Illegal opcode detection with reset

– Illegal address detection with reset

•

32-pin quad flat pack (QFP) package

• Low-power design; fully static with stop and wait modes

• Internal pullups on IRQ and RST to reduce customer system cost

• Standard low-power modes of operation:

– Wait mode

– Stop mode

• Master reset pin (RST) and power-on reset (POR)

• BREAK module (BRK) to allow single breakpoint setting during

in-circuit debugging

68HC908EY16 — Rev 2.0

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General Description

35

General Description

• Higher current source capability on nine port lines for LED drive

(PTA6/SS, PTA5/SPSCK, PTA4/KDB4, PTA3/KBD3,

PTA2/KBD2, PTA1/KBD1, PTA0/KBD0, PTC1/MOSI, and

PTC0/MISO)

Features of the CPU08 include:

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (eight more than the HC05)

• 16-bit index register and stack pointer

• Memory-to-memory data transfers

• Fast 8 × 8 multiply instruction

• Fast 16 ÷ 8 divide instruction

• Binary-coded decimal (BCD) instructions

• Optimization for controller applications

• Third party C language support

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908EY16.

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68HC908EY16 — Rev 2.0

MOTOROLA

General Description

1.5 Pin Assignments

Figure 1-2 shows the pin assignments for the MC68HC908EY16.

24

23

22

21

20

19

18

17

PTA2/KBD2

PTA1/KBD1

1

PTE1/RxD

PTE0/TxD

PTC0/MISO

PTC1/MOSI

PTA5/SPSCK

PTA6/SS

2

3

4

5

6

7

8

PTA0/KBD0

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTB0/AD0

IRQ

PTC2/MCLK

Figure 1-2. Pin Assignments

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General Description

Pin Functions

1.6 Pin Functions

Descriptions of the pin functions are provided here.

1.6.1 Power Supply Pins (V_DDand V_SS)

V_DDand V_SSare the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 1-3

shows. Place the C1 bypass capacitor as close to the MCU as possible.

Use a high-frequency-response ceramic capacitor for C1. C2 is an

optional bulk current bypass capacitor for use in applications that require

the port pins to source high current levels.

MCU

V

SS

DD

C1

0.1 µF

+

C2

V

DD

Note: Component values shown represent typical applications.

Figure 1-3. Power Supply Bypassing

68HC908EY16 — Rev 2.0

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MOTOROLA

General Description

1.6.2 Oscillator Pins (PTC4/OSC1 and PTC3/OSC2)

The OSC1 and OSC2 pins are available through programming options

in the configuration register. These pins then become the connections to

an external clock source or crystal/ceramic resonator.

When selecting PTC4 and PTC3 as I/O, OSC1 and OSC2 functions are

not available.

1.6.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. This pin contains an internal pullup

resistor that is always activated, even when the reset pin is pulled low.

See Section 6. System Integration Module (SIM).

1.6.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. This pin contains an

internal pullup resistor that is always activated, even when the IRQ pin

is pulled low. See Section 13. External Interrupt (IRQ).

1.6.5 Analog Power Supply/Reference Pins (V_DDA, V_REFH, V_SSAand V_REFL

)

V_DDAand V_SSAare the power supply pins for the analog-to-digital

converter (ADC). Decoupling of these pins should be as per the digital

supply.

NOTE: V_REFHis the high reference supply for the ADC. V_DDAshould be tied to

the same potential as V_DDvia separate traces.

V_REFLis the low reference supply for the ADC. V_SSAshould be tied to the

same potential as V_SSvia separate traces.

See Section 21. Analog-to-Digital Converter (ADC) Module.

Advance Information

40

68HC908EY16 — Rev 2.0

General Description

MOTOROLA

General Description

Pin Functions

1.6.6 Port A I/O Pins (PTA6/SS, PTA5/SPSCK, PTA4/KDB4–PTA0/KBD0)

Port A input/output (I/O) pins (PTA6/SS, PTA5/SPSCK, PTA4/KDB4,

PTA3/KBD3, PTA2/KBD2, PTA1/KBD1, and PTA0/KBD0) are special-

function, bidirectional I/O port pins. PTA5 and PTA6 are shared with the

serial peripheral interface (SPI). PTA4-PTA0 can be programmed to

serve as keyboard interrupt pins.

See Section 22. Input/Output (I/O) Ports and Section 13. External

Interrupt (IRQ).

1.6.7 Port B I/O Pins (PTB7/AD7/TBCH1, PTB6/AD6/TBCH0, PTB5/AD5–PTB0/AD0)

PTB7/AD7/TBCH1, PTB6/AD6/TBCH0, and PTB5/AD5–PTB0/AD0 are

special-function, bidirectional I/O port pins that can also be used for ADC

inputs. PTB7/AD7/TBCH1 and PTB6/AD6/TBCH0 are special function

bidirectional I/O port pins that can also be used for timer interface pins.

See Section 16. Timer Interface A (TIMA) Module and Section 21.

Analog-to-Digital Converter (ADC) Module.

1.6.8 Port C I/O Pins (PTC4/OSC1, PTC3/OSC2, PTC2/MCLK, PTC1/MOSI, PTC0/MISO)

PTC4/OSC1–PTC0/MISO are special-function, bidirectional I/O port

pins. See Section 22. Input/Output (I/O) Ports. PTC3/OSC2 and

PTC4/OSC1 are shared with the on-chip oscillator circuit through

configuration options. See Section 7. Internal Clock Generator (ICG)

Module.

When applications require:

• PTC3/OSC2 can be programmed to be OSC2

• PTC4/OSC1 can be programmed to be OSC1

PTC2/MCLK is software selectable to be MCLK, or bus clock out.

PTC1/MOSI can be programmed to be the MOSI signal for the SPI.

PTC0/MISO can be programmed to be the MISO signal for the SPI.

68HC908EY16 — Rev 2.0

Advance Information

41

MOTOROLA

General Description

1.6.9 Port D I/O Pins (PTD1/TACH1–PTD0/TACH0)

PTD1/TACH1–PTD0/TACH0 are special-function, bidirectional I/O port

pins that can also be programmed to be timer pins.

See Section 16. Timer Interface A (TIMA) Module and Section 22.

Input/Output (I/O) Ports.

1.6.10 Port E I/O Pins (PTE1/RxD–PTE0/TxD)

PTE1/RxD–PTE0/TxD are special-function, bidirectional I/O port pins

that can also be programmed to be enhanced serial communication

interface (ESCI) pins.

See Section 14. Enhanced Serial Communications Interface (ESCI)

Module and Section 22. Input/Output (I/O) Ports.

NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic

level (either V_DDor V_SS). Although the I/O ports of the 68HC908EY16 do

not require termination, termination is recommended to reduce the

possibility of electro-static discharge damage.

Advance Information

42

68HC908EY16 — Rev 2.0

General Description

MOTOROLA

Advance Information — 68HC908EY16

Section 2. Memory Map

2.1 Contents

2.2

2.3

2.4

2.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .43

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.2 Introduction

The M68HC08 central processor unit (CPU08) can address 64 Kbytes of

memory space. The memory map, shown in Figure 2-1, includes:

• 16 Kbytes of FLASH memory, 15, 872 bytes of user space

• 512 bytes of random-access memory (RAM)

• 36 bytes of user-defined vectors

• 310 bytes of monitor routines in read-only memory (ROM)

• 1024 bytes of integrated FLASH burn-in routines in ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address

reset. In the memory map (Figure 2-1) and in register figures in this

document, unimplemented locations are shaded.

68HC908EY16 — Rev 2.0

Advance Information

MOTOROLA

Memory Map

43

Memory Map

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on

microcontroller unit (MCU) operation. In the Figure 2-1 and in register

figures in this document, reserved locations are marked with the word

reserved or with the letter R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area

of $0000–$003F. Additional I/O registers have these addresses:

• $FE00; SIM break status register, SBSR

• $FE01; SIM reset status register, SRSR

• $FE03; SIM break flag control register, SBFCR

• $FE08; FLASH control register, FLCR

• $FE09; break address register high, BRKH

• $FE0A; break address register low, BRKL

• $FE0B; break status and control register, BRKSCR

• $FE0C; LVI status register, LVISR

• $FF7E; FLASH block protect register, FLBPR

Data registers are shown in Figure 2-2. and Table 2-1 is a list of vector

locations.

Advance Information

44

68HC908EY16 — Rev 2.0

Memory Map

MOTOROLA

Memory Map

Input/Output (I/O) Section

$0000

↓

I/O Registers

64 Bytes

$003F

$0040

↓

RAM

512 Bytes

$023F

$0240

↓

Unimplemented

3520 Bytes

$0FFF

$1000

↓

Reserved for Integrated FLASH Burn-in Routines

1024 Bytes

$13FF

$1400

↓

Unimplemented

44,032 Bytes

$BFFF

$C000

↓

FLASH Memory

15,872 Bytes

$FDFF

$FE00

$FE01

$FE02

$FE03

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

$FE0A

SIM Break Status Register (SBSR)

SIM Reset Status Register (SRSR)

Reserved

SIM Break Flag Control Register (SBFCR)

RESERVED

Reserved for FLASH Test Control Register (FLTCR)

FLASH Control Register (FLCR)

Break Address Register High (BRKH)

Break Address Register Low (BRKL)

Figure 2-1. Memory Map

68HC908EY16 — Rev 2.0

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45

MOTOROLA

Memory Map

$FE0B

$FE0C

$FE0D

↓

Break Status and Control Register (BRKSCR)

LVI Status Register (LVISR)

Reserved

3 Bytes

$FE0F

$FE10

↓

Reserved

16 Bytes

Reserved for Compatibility with Monitor Code

for A-Family Parts

$FE1F

$FE20

↓

Monitor ROM 310 Bytes

FF55

FF56

↓

Unimplemented

40 Bytes

FF7D

$FF7E

$FF7F

↓

FLASH Block Protect Register (FLBPR)

Unimplemented

93 Bytes

$FFDB

$FFDC

↓

FLASH Vectors

36 Bytes

$FFFF

Note: Locations $FFF6–$FFFD are reserved for eight security bytes.

Figure 2-1. Memory Map (Continued)

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46

68HC908EY16 — Rev 2.0

MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

0

Port A Data Register

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

(PTA) Write:

See 365.

Reset:

Read:

Unaffected by reset

PTB4 PTB3

Unaffected by reset

PTC4 PTC3

Unaffected by reset

Port B Data Register

PTB7

0

PTB6

0

PTB5

0

PTB2

PTB1

PTC1

PTD1

PTB0

PTC0

PTD0

(PTB) Write:

See 368.

Reset:

Read:

Port C Data Register

PTC2

0

(PTC) Write:

See 371.

Reset:

Read:

Write:

Reset:

Read:

0

Port D Data Register

(PTD)

See 374.

Unaffected by reset

Data Direction

Register A (DDRA) Write:

DDRA6

0

DDRA5

0

DDRA4

0

DDRA3

0

DDRA2

DDRA1

DDRA0

See 366.

Reset:

0

DDRB2

0

DDRB1

0

DDRB0

0

Read:

Data Direction

Register B (DDRB) Write:

DDRB7

0

DDRB6

DDRB5

DDRB4

0

DDRB3

0

See 369.

Reset:

0

Read:

Data Direction

Register C (DDRC) Write:

MCLKEN

DDRC4

DDRC3

DDRC2 DDRC1 DDRC0

See 372.

Reset:

0

Read:

Write:

Reset:

Read:

Data Direction

Register D (DDRD)

See 375.

DDRD1 DDRD0

0

Port E Data Register

PTE1

PTE0

(PTE) Write:

See 377.

Reset:

Unaffected by reset

R = Reserved

= Unimplemented

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)

68HC908EY16 — Rev 2.0

Advance Information

47

MOTOROLA

Memory Map

Addr. Register Name

Bit 7

6

5

4

3

2

1

Bit 0

$0009

Reserved

R

Read:

0

Data Direction

DDRE1

DDRE0

$000A

Register E (DDRE) Write:

See 378.

Reset:

0

Read: BEMF7

Write:

BEMF6

BEMF5

BEMF4

BEMF3

BEMF2

BEMF1

BEMF0

BEMF Register (BEMF)

See 328.

$000B

$000C

Reset:

0

Reserved

R

Read:

SPI Control Register

SPRIE

0

R

0

SPMSTR CPOL

CPHA

SPWOM

0

SPE

0

SPTIE

0

$000D

$000E

$000F

$0010

$0011

$0012

(SPCR) Write:

See 271.

Reset:

1

0

1

Read: SPRF

OVRF

MODF

SPTE

SPI Status and Control

ERRIE

MODFEN SPR1

SPR0

Register (SPSCR) Write:

See 274.

Reset:

0

1

0

Read:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SPI Data Register

(SPDR) Write:

See 277.

Reset:

Indeterminate after reset

Read:

ESCI Control Register 1

LOOPS

0

ENSCI

TXINV

M

0

WAKE

ILTY

0

PEN

0

PTY

0

(SCC1) Write:

See 224.

Reset:

0

TCIE

0

TE

0

Read:

ESCI Control Register 2

SCTIE

SCRIE

ILIE

0

RE

0

RWU

0

SBK

0

(SCC2) Write:

See 227.

Reset:

0

R

0

Read:

R8

ESCI Control Register 3

T8

0

R

ORIE

0

NEIE

0

FEIE

0

PEIE

0

(SCC3) Write:

See 229.

Reset:

U

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)

Advance Information

48

68HC908EY16 — Rev 2.0

Memory Map

MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read: SCTE

TC

SCRF

IDLE

OR

NF

FE

PE

ESCI Status Register 1

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

(SCS1) Write:

See 231.

Reset:

Read:

1

0

1

0

BKF

RPF

ESCI Status Register 2

(SCS2) Write:

See 235.

Reset:

0

Read:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

ESCI Data Register

(SCDR) Write:

See 236.

Reset:

Unaffected by reset

Read:

ESCI Baud Rate

R

0

LINR

0

SCP1

0

SCP0

0

R

0

SCR2

SCR1

SCR0

Register (SCBR) Write:

See 236.

Reset:

0

PSSB2

0

PSSB1

0

PSSB0

0

Read:

ESCI Prescale Register

PDS2

0

PDS1

PDS0

0

PSSB4

0

PSSB3

(SCPSC) Write:

See 238.

Reset:

0

Read:

Write:

Reset:

ALOST

AFIN

ARUN AROVFL ARD8

ESCII Arbiter Control

Register

AM1

AM0

ACLK

(SCIACTL)

See 242.

0

Read: ARD7

ARD6

ARD5

ARD4

ARD3

ARD2

ARD1

ARD0

ESCI Arbiter Data

Register (SCIACTL) Write:

See 244.

Reset:

0

Read:

Write:

Reset:

Read:

Write:

Reset:

KEYF

0

ACKK

0

Keyboard Status

and Control Register

(INTKBSCR)

IMASKK MODEK

See 335.

0

KBIE3

0

KBIE1

0

KBIE0

0

Keyboard Interrupt

Enable Register

(INTKBIER)

KBIE4

KBIE2

See 336.

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)

68HC908EY16 — Rev 2.0

Advance Information

49

MOTOROLA

Memory Map

Addr. Register Name

Bit 7

Read: TBIF

Write:

6

5

4

3

0

2

1

Bit 0

TBR2

TBR1

TBR0

TBIE

TBON

R

Timebase Control

TACK

$001C

$001D

$001E

$001F

Register (TBCR)

See 343.

Reset:

Read:

0

IRQF

0

ACK

0

IRQ Status and Control

IMASK

0

MODE

0

Register (INTSCR) Write:

See 198.

Reset:

0

Read:

ESCI

EXT-

CLKEN CLKSEL

TMB- OSCENIN- SSB-

R

Configuration Register 2

BDSRC XTALEN SLOW

STOP

PUENB

Write:

(CONFIG2)

See 150.

Reset:

0

1

Read:

Configuration Register 1

COPRS LVISTOP LVIRSTD LVIPWRD

SSREC

0

STOP

0

COPD

0

(CONFIG1) Write:

See 150.

Reset:

0

1. The LVI5OR3 bit is cleared only by a power-on reset (POR).

Read:

TOF

0

Timer A Status and

TOIE

TSTOP

R

PS2

PS1

PS0

$0020 Control Register (TASC) Write:

TRST

0

See 293.

Reset:

0

1

0

Read: BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

Timer A Counter

$0021 Register High (TACNTH) Write:

See 295.

Reset:

0

Read: BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Timer A Counter

$0022 Register Low (TACNTL) Write:

See 295.

Reset:

0

BIT 15

1

0

BIT 14

1

0

BIT 13

1

0

BIT 11

1

0

BIT 10

1

0

BIT 9

1

0

BIT 8

1

Read:

Write:

Reset:

Timer A Counter Modulo

Register High

(TAMODH)

BIT 12

$0023

See 296.

1

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)

Advance Information

50

68HC908EY16 — Rev 2.0

Memory Map

MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name

Bit 7

BIT 7

1

6

BIT 6

1

5

BIT 5

1

4

BIT 4

1

3

BIT 3

1

2

BIT 2

1

BIT 1

1

Bit 0

BIT 0

1

Read:

Timer A Counter Modulo

$0024 Register Low (TAMODL) Write:

See 296.

Reset:

Read: CH0F

Timer A Channel 0

Status and Control

Register (TASC0)

See 297.

CH0IE

0

MS0B

0

MS0A

0

ELS0B

0

ELS0A

0

TOV0

0

CH0MAX

0

$0025

Write:

Reset:

Read:

0

Timer A Channel 0

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

$0026 Register High (TACH0H) Write:

See 302.

Reset:

Indeterminate after reset

BIT 4 BIT 3

Indeterminate after reset

Read:

Timer A Channel 0

$0027 Register Low (TACH0L) Write:

BIT 7

BIT 6

BIT 5

BIT 2

BIT 1

BIT 0

See 302.

Reset:

Read: CH1F

0

R

0

Timer A Channel 1

Status and Control

Register (TASC1)

See 302.

CH1IE

0

MS1A

0

ELS1B

0

ELS1A

0

TOV1

0

CH1MAX

0

$0028

Write:

Reset:

Read:

0

Timer A Channel 1

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

$0029 Register High (TACH1H) Write:

See 302.

Reset:

Indeterminate after reset

BIT 4 BIT 3

Read:

Timer A Channel 1

$002A Register Low (TACH1L) Write:

BIT 7

BIT 6

TOIE

BIT 5

BIT 2

PS2

BIT 1

PS1

BIT 0

PS0

See 302.

Reset:

Indeterminate after reset

Read:

TOF

0

Timer B Status and

$002B Control Register (TBSC) Write:

TSTOP

R

TRST

See 318.

Reset:

0

1

0

Read: BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

Timer B Counter

$002C Register High (TBCNTH) Write:

See 320.

Reset:

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)

68HC908EY16 — Rev 2.0

Advance Information

51

MOTOROLA

Memory Map

Addr. Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read: BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Timer B Counter

$002D Register Low (TBCNTL) Write:

See 320.

Reset:

0

BIT 15

1

0

BIT 14

1

0

BIT 13

1

0

BIT 12

1

0

BIT 11

1

0

BIT 10

1

0

BIT 9

1

0

BIT 8

1

Read:

Write:

Reset:

Read:

Timer B Counter Modulo

Register High

(TBMODH)

$002E

See 321.

Timer B Counter Modulo

$002F Register Low (TBMODL) Write:

BIT 7

BIT 6

1

BIT 5

1

BIT 4

1

BIT 3

1

BIT 2

1

BIT 1

1

BIT 0

1

See 321.

Reset:

1

Read: CH0F

Timer B Channel 0

Status and Control

Register (TBSC0)

See 322.

CH0IE

0

MS0B

0

MS0A

0

ELS0B

0

ELS0A

0

TOV0

0

CH0MAX

0

$0030

Write:

Reset:

Read:

0

Timer B Channel 0

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

$0031 Register High (TBCH0H) Write:

See 326.

Reset:

Indeterminate after reset

BIT 4 BIT 3

Indeterminate after reset

Read:

Timer B Channel 0

$0032 Register Low (TBCH0L) Write:

BIT 7

BIT 6

BIT 5

BIT 2

BIT 1

BIT 0

See 326.

Reset:

Read: CH1F

0

R

0

Timer B Channel 1

Status and Control

Register (TBSC1)

See 322.

CH1IE

0

MS1A

0

ELS1B

0

ELS1A

0

TOV1

0

CH1MAX

0

$0033

Write:

Reset:

Read:

0

Timer B Channel 1

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

$0034 Register High (TBCH1H) Write:

See 326.

Reset:

Indeterminate after reset

BIT 4 BIT 3

Read:

Timer B Channel 1

$0035 Register Low (TBCH1L) Write:

BIT 7

BIT 6

BIT 5

BIT 2

BIT 1

BIT 0

See 326.

Reset:

Indeterminate after reset

R = Reserved

= Unimplemented

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)

Advance Information

52

68HC908EY16 — Rev 2.0

Memory Map

MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name

Bit 7

CMIE

0

6

CMF

0

5

4

CS

0

3

ICGON

1

2

1

ECGON

0

Bit 0

Read:

ICGS

ECGS

ICG Control Register

CMON

$0036

$0037

$0038

$0039

(ICGCR) Write:

See 144.

Reset:

0

N5

0

N2

0

N0

Read:

ICG Multiplier Register

N6

N4

1

N3

N1

(ICGMR) Write:

See 146.

Reset:

0

TRIM7

1

0

TRIM6

0

1

0

1

Read:

ICG Trim Register

TRIM5

0

TRIM4

0

TRIM3

TRIM2

TRIM1

TRIM0

(ICGTR) Write:

See 147.

Reset:

0

Read:

Write:

Reset:

DDIV3

DDIV2

DDIV1

DDIV0

ICG Divider Control

Register

(ICGDVR)

See 147.

0

DSTG6

R

0

DSTG5

R

0

U

DSTG1

R

U

DSTG0

R

Read: DSTG7

DSTG4 DDSTG3 DSTG2

ICG DCO Stage Control

$003A

$003B

Register (ICGDSR) Write:

R

U

R

U

R

U

R

U

R

See 148.

Reset:

U

Reserved

R

Read:

Write:

Reset:

Read:

Analog-to-Digital Status

and Control Register

(ADSCR)

COCO

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

$003C

See 354.

0

1

0

1

0

1

0

1

ADCH9

ADCH8

Analog-to-Digital Data

$003D Register High (ADRH) Write:

See 357.

Reset:

Unaffected by reset

AD4 AD3

Read:

AD7

AD6

AD5

AD2

AD1

AD0

Analog-to-Digital Data

$003E

Register Low (ADRL) Write:

See 361.

Reset:

Unaffected by reset

R = Reserved

= Unimplemented

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)

68HC908EY16 — Rev 2.0

Advance Information

53

MOTOROLA

Memory Map

Addr. Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

0

Analog-to-Digital Clock

ADIV2

ADIV1

ADIV0

ADICLK MODE1

MODE0

R

$003F

$FE00

Register (ADCLK) Write:

See 361.

Reset:

0

R

0

R

0

R

0

R

0

R

0

1

R

0

R

0

Read:

SBSW

NOTE

0

SIM Break Status

Write:

Register (SBSR)

Reset:

Note: Writing a logic 0 clears SBSW.

Read: POR

0

COP

0

ILOP

0

ILAD

0

MENRST

0

LVI

0

SIM Reset Status

$FE01

Register (SRSR) Write:

See 107.

POR:

1

$FE02

Reserved

BCFE

R

SIM Break Flag Control

$FE03

Register (SBFCR)

$FE04

↓

Reserved

$FE07

Reserved

Read:

0

FLASH Control Register

HVEN

MASS

0

ERASE

PGM

0

$FE08

$FE09

$FE0A

(FLCR) Write:

See 60.

Reset:

0

BIT 15

0

BIT 14

0

BIT 13

0

BIT 12

0

BIT 11

0

BIT 9

0

Read:

Break Address Register

BIT 10

0

BIT 8

0

High (BRKH) Write:

See 163.

Reset:

Read:

Break Address Register

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

BIT 3

0

BIT 2

0

BIT 1

0

BIT 0

0

Low (BRKL) Write:

See 163.

Reset:

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)

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68HC908EY16 — Rev 2.0

Memory Map

MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name

Bit 7

BRKE

0

6

5

4

3

2

1

Bit 0

Read:

0

Break Status and Control

BRKA

$FE0B

$FE0C

$FF7E

Register (BRKSCR) Write:

See 162.

Reset:

0

Read: LVIOUT

LVI Status Register

(LVISR) Write:

See 190.

Reset:

Read:

Write:

Reset:

0

FLASH Block Protect

Register (FLBPR)

BPR7

BPR6

BPR5

BPR4

BPR3

BPR2

BPR1

BPR0

(1)

See 67.

Unaffected by reset

1. Non-volatile FLASH register

COP Control Register

Read:

Low byte of reset vector

$FFFF

(COPCTL) Write:

Writing clears COP counter (any value)

Unaffected by reset

See 185.

Reset:

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)

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55

MOTOROLA

Memory Map

Table 2-1. Vector Addresses

Vector Priority Vector Address

Lowest

Vector

$FFDC

$FFDD

$FFDE

$FFDF

$FFE0

$FFE1

$FFE2

$FFE3

$FFE4

$FFE5

$FFE6

$FFE7

$FFE8

$FFE9

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

$FFFF

Timebase interrupt vector (high)

Timebase interrupt vector (low)

SPI transmit vector (high)

SPI transmit vector (low)

SPI receive vector (high)

SPI receive vector (low)

ADC conversion complete vector (high)

ADC conversion complete vector (low)

Keyboard vector (high)

IF15

IF14

IF13

IF12

IF11

IF10

IF9

Keyboard vector (low)

ESCI error vector (high)

ESCI error vector (low)

ESCI transmit vector (high)

ESCI transmit vector (low)

ESCI receive vector (high)

ESCI receive vector (low)

TIMB overflow vector (high)

TIMB overflow vector (low)

TIMB channel 1 vector (high)

TIMB channel 1 vector (low)

TIMB channel 0 vector (high)

TIMB channel 0 vector (low)

TIMA overflow vector (high)

TIMA overflow vector (low)

TIMA channel 1 vector (high)

TIMA channel 1 vector (low)

TIMA channel 0 vector (high)

TIMA channel 0 vector (low)

CMIREQ (high)

IF8

IF7

IF6

IF5

IF4

IF3

IF2

CMIREQ (low)

IRQ vector (high)

IF1

IRQ vector (low)

SWI vector (high)

—

SWI vector (low)

Reset vector (high)

—

Highest

Reset vector (low)

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MOTOROLA

Advance Information — 68HC908EY16

Section 3. Random Access Memory (RAM)

3.1 Contents

3.2

3.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2 Introduction

This section describes the 512 bytes of random-access memory (RAM).

3.3 Functional Description

Addresses $0040–$00FF and $0100–$023F are RAM locations. The

location of the stack RAM is programmable with the reset stack pointer

instruction (RSP). The 16-bit stack pointer allows the stack RAM to be

anywhere in the 64K-byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM

locations.

Within page zero are 192 bytes of RAM. Because the location of the

stack RAM is programmable, all page zero RAM locations can be used

for input/output (I/O) control and user data or code. When the stack

pointer is moved from its reset location at $00FF, direct addressing

mode instructions can access all page zero RAM locations efficiently.

Page zero RAM, therefore, provides ideal locations for frequently

accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to

save the contents of the central processor unit (CPU) registers.

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57

Random Access Memory (RAM)

NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not

stacked.

During a subroutine call, the CPU uses two bytes of the stack to store

the return address. The stack pointer decrements during pushes and

increments during pulls.

NOTE: Be careful when using nested subroutines. The CPU could overwrite

data in the RAM during a subroutine or during the interrupt stacking

operation.

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Random Access Memory (RAM)

MOTOROLA

Advance Information — 68HC908EY16

Section 4. FLASH Memory

4.1 Contents