MC68HC908GP20 [FREESCALE]
M68HC08 Microcontrollers; M68HC08微控制器
| 型号： | MC68HC908GP20 |
| 厂家： | 
Freescale |
| 描述： | M68HC08 Microcontrollers |
| 文件： | 总406页 (文件大小：3942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908GP20
Advance Information
M68HC08
Microcontrollers
Rev. 2.1
MC68HC908GP20/D
08/2005
freescale.com
Advance Information — MC68HC908GP20
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 31
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 3. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . 57
Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 69
Section 5. Analog-to-Digital Converter (ADC) . . . . . . . 87
Section 6. Break Module (BRK). . . . . . . . . . . . . . . . . . . . 99
Section 7. Clock Generator Module (CGMC) . . . . . . 107
Section 8. Configuration Register (CONFIG). . . . . . . . 139
Section 9. Computer Operating Properly (COP) . . . . 145
Section 10. Central Processor Unit (CPU) . . . . . . . . . . 151
Section 11. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . 169
Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . 185
Section 13. Keyboard Interrupt Module (KBI) . . . . . . . 191
Section 14. Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . 199
Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . 205
Section 16. Input/Output (I/O) Ports . . . . . . . . . . . . . . 221
Section 17. Random-Access Memory (RAM). . . . . . . 245
Section 18. Serial Communications
Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . 247
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
3
List of Sections
Section 19. System Integration Module (SIM). . . . . . . 287
Section 20. Serial Peripheral Interface
Module (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Section 21. Timebase Module (TBM) . . . . . . . . . . . . . . 345
Section 22. Timer Interface Module (TIM) . . . . . . . . . . 351
Section 23. Preliminary Electrical Specifications . . . . 377
Section 24. Mechanical Specifications. . . . . . . . . . . . 399
Section 25. Ordering Information. . . . . . . . . . . . . . . . . 403
Advance Information
4
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Table of Contents
Section 1. General Description
1.1
1.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.3
1.3.1
1.3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Standard Features of the MC68HC908GP20 . . . . . . . . . . .32
Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.4
1.5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
1.6.11
1.6.12
1.6.13
1.6.14
Power Supply Pins (V and V ) . . . . . . . . . . . . . . . . . . .37
DD SS
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .38
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .38
External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . .39
CGM Power Supply Pins (V
and V
). . . . . . . . . . . . .39
SSA
DDA
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .39
Analog Power Supply Pins (V and V ) . . . . . . . . .39
DDAD
SSAD
ADC Voltage Reference High Pin (V
) . . . . . . . . . . . . .39
REFH
ADC Voltage Reference Low Pin (V
). . . . . . . . . . . . . .39
REFL
Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) .40
Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .40
Port C I/O Pins (PTC6–PTC0). . . . . . . . . . . . . . . . . . . . . . .40
Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . .40
Port E I/O Pins (PTE1/RxD–PTE0/TxD) . . . . . . . . . . . . . . .41
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
5
Section 2. Memory Map
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .43
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 3. Low-Power Modes
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.2
3.2.1
3.2.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3
3.3.1
3.3.2
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.4
3.4.1
3.4.2
Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.5
3.5.1
3.5.2
Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.6
3.6.1
3.6.2
Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.7
3.7.1
3.7.2
Computer Operating Properly Module (COP). . . . . . . . . . . . . .61
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.8
3.8.1
3.8.2
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.9
3.9.1
3.9.2
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Advance Information
6
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63
3.10.1
3.10.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .63
3.11.1
3.11.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .64
3.12.1
3.12.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .64
3.13.1
3.13.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.14.1
3.14.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4. Resets and Interrupts
4.1
4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.4
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
External Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
COP Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . .74
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
7
4.4
4.4.1
4.4.2
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
CGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TIM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
KBD0–KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
4.4.2.6
4.4.2.7
4.4.2.8
4.4.2.9
4.4.2.10
4.4.2.11
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
ADC (Analog-to-Digital Converter). . . . . . . . . . . . . . . . . .83
TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . .83
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .84
Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .86
Section 5. Analog-to-Digital Converter (ADC)
5.1
5.2
5.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Voltage Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .90
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.6
5.6.1
5.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Advance Information
8
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
5.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.7.1
ADC Analog Power Pin (V
Reference High Pin (V
)/ADC Voltage
) . . . . . . . . . . . . . . . . . . . . .92
DDAD
REFH
5.7.2
ADC Analog Ground Pin (V
)/ADC Voltage
SSAD
Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . . .92
REFL
5.7.3
ADC Voltage In (ADV ) . . . . . . . . . . . . . . . . . . . . . . . . . . .92
IN
5.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . .93
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
5.8.1
5.8.2
5.8.3
Section 6. Break Module (BRK)
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Flag Protection During Break Interrupts . . . . . . . . . . . . . .102
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .102
TIMI and TIM2 During Break Interrupts. . . . . . . . . . . . . . .102
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .102
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
6.6
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Break Status and Control Register . . . . . . . . . . . . . . . . . .103
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .104
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .106
6.6.1
6.6.2
6.6.3
6.6.4
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
9
Section 7. Clock Generator Module (CGMC)
7.1
7.2
7.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .111
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .111
PLL Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .113
Manual and Automatic PLL Bandwidth Modes . . . . . . . . .113
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Special Programming Exceptions . . . . . . . . . . . . . . . . . . .119
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . .119
CGMC External Connections . . . . . . . . . . . . . . . . . . . . . .120
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . .121
Crystal Amplifier Output Pin (OSC2). . . . . . . . . . . . . . . . .121
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . .122
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
PLL Analog Power Pin (V
) . . . . . . . . . . . . . . . . . . . . .122
DDA
PLL Analog Ground Pin (V
). . . . . . . . . . . . . . . . . . . . .122
SSA
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . .122
Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . .122
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .123
CGMC Base Clock Output (CGMOUT). . . . . . . . . . . . . . .123
CGMC CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . .123
7.6
CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . .127
PLL Multiplier Select Register High. . . . . . . . . . . . . . . . . .129
PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . .130
PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . .131
PLL Reference Divider Select Register. . . . . . . . . . . . . . .132
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Advance Information
10
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . .134
7.8.1
7.8.2
7.8.3
7.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .135
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .135
Parametric Influences on Reaction Time . . . . . . . . . . . . .136
Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.9.1
7.9.2
7.9.3
Section 8. Configuration Register (CONFIG)
8.1
8.2
8.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Section 9. Computer Operating Properly (COP)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.1
9.2
9.3
9.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .148
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.5
9.6
9.7
COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
11
9.8
9.8.1
9.8.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .150
Section 10. Central Processor Unit (CPU)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .158
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
10.6.1
10.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .159
10.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Section 11. FLASH Memory
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
11.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
11.5.1
11.5.2
FLASH Charge Pump Frequency Control. . . . . . . . . . . . .173
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Advance Information
12
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
11.6 FLASH Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
11.7 FLASH Program/Margin Read Operation. . . . . . . . . . . . . . . .177
11.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . .181
11.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Section 12. External Interrupt (IRQ)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
12.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
12.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .189
12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .189
Section 13. Keyboard Interrupt Module (KBI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
13.6.1
13.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .196
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
13.8.1
13.8.2
Keyboard Status and Control Register . . . . . . . . . . . . . . .197
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .198
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
13
Section 14. Low-Voltage Inhibit (LVI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
14.4.1
14.4.2
14.4.3
14.4.4
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . .202
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .202
LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
14.7.1
14.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Section 15. Monitor ROM (MON)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Advance Information
14
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Section 16. Input/Output (I/O) Ports
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.3.1
16.3.2
16.3.3
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .226
Port A Input Pullup Enable Register . . . . . . . . . . . . . . . . .228
16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
16.4.1
16.4.2
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .230
16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
16.5.1
16.5.2
16.5.3
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .233
Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . .235
16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
16.6.1
16.6.2
16.6.3
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .238
Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . .240
16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
16.7.1
16.7.2
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .242
Section 17. Random-Access Memory (RAM)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
15
Section 18. Serial Communications
Interface Module (SCI)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.5.1
18.5.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .255
Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .257
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .257
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .262
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18.5.2.1
18.5.2.2
18.5.2.3
18.5.2.4
18.5.2.5
18.5.2.6
18.5.3
18.5.3.1
18.5.3.2
18.5.3.3
18.5.3.4
18.5.3.5
18.5.3.6
18.5.3.7
18.5.3.8
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
18.6.1
18.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .268
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.8.1
18.8.2
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .268
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .269
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
18.9.1
18.9.2
18.9.3
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .269
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .272
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Advance Information
16
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
18.9.4
18.9.5
18.9.6
18.9.7
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .284
Section 19. System Integration
Module (SIM)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .291
19.3.1
19.3.2
19.3.3
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . .292
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .292
19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .292
19.4.1
19.4.2
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Active Resets from Internal Sources. . . . . . . . . . . . . . . . .294
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
Computer Operating Properly (COP) Reset. . . . . . . . . .296
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .297
Monitor Mode Entry Module Reset (MODRST) . . . . . . .297
19.4.2.1
19.4.2.2
19.4.2.3
19.4.2.4
19.4.2.5
19.4.2.6
19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
19.5.1
19.5.2
19.5.3
SIM Counter During Power-On Reset. . . . . . . . . . . . . . . .297
SIM Counter During Stop Mode Recovery . . . . . . . . . . . .298
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .298
19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
19.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .302
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .305
19.6.1.1
19.6.1.2
19.6.1.3
19.6.2
19.6.3
19.6.4
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
17
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
19.7.1
19.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
19.8.1
19.8.2
19.8.3
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .308
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .310
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . .311
Section 20. Serial Peripheral Interface
Module (SPI)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.4 Pin Name Conventions and I/O Register Addresses . . . . . . .315
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
20.5.1
20.5.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
20.6.1
20.6.2
20.6.3
20.6.4
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .319
Transmission Format When CPHA = 0. . . . . . . . . . . . . . .320
Transmission Format When CPHA = 1. . . . . . . . . . . . . . .322
Transmission Initiation Latency. . . . . . . . . . . . . . . . . . . . .323
20.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .325
20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
20.8.1
20.8.2
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.11.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .334
Advance Information
18
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .335
20.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .335
20.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
20.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
20.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . .337
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .340
20.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
Section 21. Timebase Module (TBM)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .347
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
21.7.1
21.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Section 22. Timer Interface Module (TIM)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.5.1
22.5.2
22.5.3
22.5.4
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . .358
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
19
22.5.5
22.5.6
22.5.7
22.5.8
22.5.9
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . .359
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .359
Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . .360
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . .361
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.7.1
22.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
22.10.1 TIM Status and Control Register. . . . . . . . . . . . . . . . . . . .366
22.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .368
22.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .369
22.10.4 TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .370
22.10.5 TIM Channel Status and Control Registers. . . . . . . . . . . .371
22.10.6 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .375
Section 23. Preliminary Electrical Specifications
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .379
23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .380
23.7 3.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .382
23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
23.9 3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
23.10 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .386
23.11 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . .387
23.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
Advance Information
20
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
23.14 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
23.15 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .396
23.17 Clock Generation Module Characteristics . . . . . . . . . . . . . . .396
23.17.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .396
23.17.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .397
23.18 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
Section 24. Mechanical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
24.3 40-Pin Plastic Dual In-Line Package (DIP). . . . . . . . . . . . . . .400
24.4 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .401
Section 25. Ordering Information
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
21
Advance Information
22
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . .47
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . .72
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . .74
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . .77
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 3 (INT3) . . . . . . . . . . . . . . . . . . . .86
5-1
5-2
5-3
5-4
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
ADC Status and Control Register (ADSCR). . . . . . . . . . . . .93
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . .95
ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . .96
6-1
6-2
6-3
6-4
6-5
6-6
6-7
Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .101
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Break Status and Control Register (BRKSCR) . . . . . . . . .103
Break Address Register High (BRKH) . . . . . . . . . . . . . . . .104
Break Address Register Low (BRKL). . . . . . . . . . . . . . . . .104
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .105
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .106
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
23
List of Figures
Figure
Title
Page
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . .121
CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . .124
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . .125
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .128
PLL Multiplier Select Register High (PMSH) . . . . . . . . . . .129
PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . .130
PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . .131
PLL Reference Divider Select Register (PMDS) . . . . . . . .132
PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
8-1
8-2
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . .140
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . .140
9-1
9-2
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .149
10-1
10-2
10-3
10-4
10-5
10-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . .156
11-1
11-2
11-3
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . .171
Smart Programming Algorithm. . . . . . . . . . . . . . . . . . . . . .179
FLASH Block Protect Register (FLBPR) . . . . . . . . . . . . . .181
12-1
12-2
12-3
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .187
IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .187
IRQ Status and Control Register (INTSCR). . . . . . . . . . . .190
13-1
13-2
13-3
13-4
Keyboard Module Block Diagram. . . . . . . . . . . . . . . . . . . .193
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Keyboard Status and Control Register (INTKBSCR) . . . . .197
Keyboard Interrupt Enable Register (INTKBIER). . . . . . . .198
Advance Information
24
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
List of Figures
Figure
Title
Page
14-1
14-2
14-3
LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .201
LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .201
LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . .203
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Low-Voltage Monitor Mode Entry Flowchart . . . . . . . . . . .211
Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . .218
Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . .219
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .222
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .225
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .226
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Port A Input Pullup Enable Register (PTAPUE). . . . . . . . .228
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .229
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .230
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .232
Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .233
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Port C Input Pullup Enable Register (PTCPUE). . . . . . . . .235
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .236
Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .238
Port D I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
Port D Input Pullup Enable Register (PTDPUE). . . . . . . . .240
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .241
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . .242
Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
18-1
18-2
18-3
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .251
SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .252
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
25
List of Figures
Figure
Title
Page
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .259
Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .260
Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .270
SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .273
SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .275
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .278
Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .281
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .282
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .283
SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . .284
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
SIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .290
CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . .294
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . .299
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . .301
Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . .303
Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . .303
Interrupt Status Register 3 (INT3) . . . . . . . . . . . . . . . . . . .304
Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .306
Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . .306
Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . .306
Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .307
Stop Mode Recovery from Interrupt or Break. . . . . . . . . . .308
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .308
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . .310
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .311
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
Advance Information
26
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
List of Figures
Figure
Title
Page
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .315
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .316
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .317
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .321
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .322
Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . .324
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .325
Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . .327
Clearing SPRF When OVRF Interrupt Is Not Enabled. . . .328
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .331
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .338
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .340
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .343
20-9
20-10
20-11
20-12
20-13
20-14
20-15
21-1
21-2
22-1
22-2
22-3
22-4
22-5
22-6
Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .346
Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . .347
TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .355
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .360
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .366
TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . .368
TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . .368
TIM Counter Modulo Register High (TMODH) . . . . . . . . . .369
TIM Counter Modulo Register Low (TMODL). . . . . . . . . . .369
TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . .370
TIM Counter Register Low (TCNTL) . . . . . . . . . . . . . . . . .370
TIM Channel 0 Status and Control Register (TSC0) . . . . .371
TIM Channel 1Status and Control Register (TSC1). . . . . .371
CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . .376
TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . .376
TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . .376
TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . .376
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
22-15
22-16
22-17
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
27
List of Figures
Figure
Title
Page
23-1
Typical High-Side Driver Characteristics –
Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 4.5 Vdc). . . . . .386
DD
23-2
23-3
23-4
23-5
23-6
Typical High-Side Driver Characteristics –
Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc). . . . . .386
DD
Typical Low-Side Driver Characteristics –
Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 4.5 Vdc). . . . . .387
DD
Typical Low-Side Driver Characteristics –
Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc). . . . . .387
DD
Typical Low-Side Driver Characteristics
for Higher Current Drive – Ports PTC4–PTC0
(V = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
DD
Typical Low-Side Driver Characteristics
for Higher Current Drive – Ports PTC4–PTC0
(V = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
DD
23-7
23-8
23-9
Typical Operating I with All Modules
DD
Turned On (–40 °C to 85 °C). . . . . . . . . . . . . . . . . . . . .389
Typical Wait Mode I with TBM Enabled,
DD
LVI Disabled, and PLL Disabled (–40 °C to 85 °C) . . . .389
Typical Wait Mode I , with LVI and TBM Enabled,
DD
PLL Disabled (–40 °C to 85 °C). . . . . . . . . . . . . . . . . . .390
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
23-10
23-11
Advance Information
28
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
List of Tables
Table
Title
Page
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4-1
4-2
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5-1
5-2
Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7-1
7-2
7-3
Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . .127
VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . .127
10-1
10-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
11-1
11-2
Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . .173
Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
14-1
LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
Monitor Mode Signal Requirements and Options. . . . . . . . .209
Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .213
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . .215
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . .215
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . .216
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . .216
READSP (Read Stack Pointer) Command. . . . . . . . . . . . . .217
RUN (Run User Program) Command. . . . . . . . . . . . . . . . . .217
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
29
List of Tables
Table
Title
Page
16-1
16-2
16-3
16-4
16-5
16-6
Port Control Register Bits Summary . . . . . . . . . . . . . . . . . .224
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . .272
SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . .284
SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .285
SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . .286
19-1
19-2
19-3
19-4
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .289
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
20-1
20-2
20-3
20-4
Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . .343
21-1
Timebase Rate Selection for OSC1 = 32.768 kHz. . . . . . . .347
22-1
22-2
22-3
Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . .374
25-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
Advance Information
30
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 1. General Description
1.1 Contents
1.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.3
1.3.1
1.3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Standard Features of the MC68HC908GP20 . . . . . . . . . . .32
Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.4
1.5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
Power Supply Pins (V and V ) . . . . . . . . . . . . . . . . . . .37
DD SS
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .38
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .38
External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . .39
CGM Power Supply Pins (V
and V
). . . . . . . . . . . . .39
SSA
DDA
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .39
Analog Power Supply Pins (V and V ) . . . . . . . . .39
DDAD
SSAD
ADC Voltage Reference High Pin (V
) . . . . . . . . . . . . .39
REFH
ADC Voltage Reference Low Pin (V
Port A Input/Output (I/O) Pins
). . . . . . . . . . . . . .39
REFL
(PTA7/KBD7–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . .40
Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .40
Port C I/O Pins (PTC6–PTC0). . . . . . . . . . . . . . . . . . . . . . .40
Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . .40
Port E I/O Pins (PTE1/RxD–PTE0/TxD) . . . . . . . . . . . . . . .41
1.6.11
1.6.12
1.6.13
1.6.14
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
31
1.2 Introduction
The MC68HC908GP20 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
1.3 Features
For convenience, features have been organized to reflect:
• Standard features of the MC68HC908GP20
• Features of the CPU08
1.3.1 Standard Features of the MC68HC908GP20
• High-performance M68HC08 architecture optimized for
C-compilers
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
• 8-MHz internal bus frequency
1
• FLASH program memory security
• On-chip programming firmware for use with host personal
computer which does not require high voltage for entry
• In-system programming
• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip
points for 3.0-V and 5.0-V operation
– Illegal opcode detection with reset
– Illegal address detection with reset
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Advance Information
32
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Low-power design; fully static with stop and wait modes
• Standard low-power modes of operation:
– Wait mode
– Stop mode
• Master reset pin and power-on reset (POR)
• 20 Kbytes of on-chip FLASH memory with in-circuit programming
capabilities of FLASH program memory
• 512 bytes of on-chip random-access memory (RAM)
• Serial peripheral interface module (SPI)
• Serial communications interface module (SCI)
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel
• 8-channel, 8-bit successive approximation analog-to-digital
converter (ADC)
• BREAK module (BRK) to allow single breakpoint setting during
in-circuit debugging
• Internal pullups on IRQ and RST to reduce customer system cost
• Clock generator module with on-chip 32-kHz crystal compatible
PLL (phase-lock loop)
• Up to 33 general-purpose input/output (I/O) pins, including:
– 26 shared-function I/O pins
– Five or seven dedicated I/O pins, depending on package
choice
• Selectable pullups on inputs only on ports A, C, and D. Selection
is on an individual port bit basis. During output mode, pullups are
disengaged.
• High current 10-mA sink/10-mA source capability on all port pins
• Higher current 15-mA sink/source capability on PTC0–PTC4
• Timebase module with clock prescaler circuitry for eight user
selectable periodic real-time interrupts with optional active clock
source during stop mode for periodic wakeup from stop using an
external 32-kHz crystal
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
33
• Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG
register to allow user selection of having the oscillator enabled or
disabled during stop mode
• 8-bit keyboard wakeup port
• 5-mA maximum current injection on all port pins to maintain input
protection
• 40-pin plastic dual-in-line package (DIP) or 44-pin quad flat pack
(QFP)
• Specific features of the MC68HC908GP20 in 40-pin DIP are:
– Port C is only 5 bits: PTC0–PTC4
– Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM
module
1.3.2 Features of the CPU08
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GP20. Text in
parentheses within a module block indicates the module name. Text in
parentheses next to a signal indicates the module which uses the signal.
Advance Information
34
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
INTERNAL BUS
M68HC08 CPU
PTA7/KBD7–PTA0/KBD0 †
PROGR. TIMEBASE
MODULE
CPU
ARITHMETIC/LOGIC
UNIT (ALU)
REGISTERS
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
SINGLE BRKPT BREAK
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 19968 BYTES
DUAL V. LOW-VOLTAGE INHIBIT
MODULE
USER RAM — 512 BYTES
8-BIT KEYBOARD
INTERRUPT MODULE
MONITOR ROM — 307 BYTES
PTC6 †
PTC5 †
2-CHANNEL TIMER INTERFACE
MODULE 1
USER FLASH VECTOR SPACE — 36 BYTES
CLOCK GENERATOR MODULE
PTC4 † ‡
PTC3 † ‡
PTC2 † ‡
PTC1 † ‡
PTC0 † ‡
2-CHANNEL TIMER INTERFACE
MODULE 2
32-kHz OSCILLATOR
OSC1
OSC2
SERIAL COMMUNICATIONS
INTERFACE MODULE
PHASE-LOCKED LOOP
PTD7/T2CH1 †
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTD3/SPSCK †
PTD2/MOSI †
PTD1/MISO †
PTD0/SS †
CGMXFC
COMPUTER OPERATING
PROPERLY MODULE
24 INTR SYSTEM INTEGRATION
MODULE
* RST
* IRQ
SERIAL PERIPHERAL
INTERFACE MODULE
SINGLE EXTERNAL IRQ
MODULE
MONITOR MODULE
VDDAD / VREFH
VSSAD / VREFL
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
DATA BUS SWITCH
MODULE
PTE1/RxD
PTE0/TxD
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
VDD
VSS
VDDA
SECURITY
MASK OPTION REGISTER1
MODULE
POWER
MODULE
VSSA
MONITOR MODE ENTRY
MODULE
MASK OPTION REGISTER2
MODULE
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
1.5 Pin Assignments
VDDA (PLL)
VSSA (PLL)
PTA7/KBD7
PTA6/KBD6
PTA5/KBD5
PTA4/KBD4
PTA3/KBD3
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
CGMXFC(PLL)
OSC2
3
4
OSC1
RST
5
PTA2/KBD2
6
PTC0
PTA1/KBD1
7
PTC1
PTA0/KBD0
8
VSSAD/VREFL (ADC)
VDDAD/VREFH (ADC)
PTC2
9
PTC3
10
11
12
13
14
15
16
17
18
19
20
PTC4
PTB7/AD7
PTE0/TxD/FLSPMGN
PTE1/RxD
IRQ/VPP/FLSEPMGN
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
VSS
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
PTD5/T1CH1
PTD4/T1CH0
VDD
Note: PTC5, PTC6, PTD6, and PTD7 were removed for this package.
Figure 1-2. DIP Pin Assignments
Advance Information
36
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
RST
PTC0
PTA1/KBD1
PTA0/KBD0
1
33
2
32
31
30
29
28
27
26
25
24
PTC1
VSSAD/VREFL
VDDAD/VREFH
PTB7/AD7
3
PTC2
4
PTC3
5
PTC4
PTB6/AD6
6
PTB5/AD5
PTC5
7
PTC6
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
8
PTE0/TxD
PTE1/RxD
IRQ
9
10
11
23
Figure 1-3. QFP Pin Assignments
1.6 Pin Functions
Descriptions of the pin functions are provided here.
1.6.1 Power Supply Pins (V and V )
DD
SS
V
and V are the power supply and ground pins. The MCU operates
SS
DD
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
37
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
NOTE: Component values shown
represent typical applications.
Figure 1-4. Power Supply Bypassing
1.6.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 7. Clock Generator Module (CGMC).
1.6.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor. See Section 19. System Integration Module (SIM).
Advance Information
38
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
1.6.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor. See Section 12. External Interrupt (IRQ).
1.6.5 CGM Power Supply Pins (V
and V
)
DDA
SSA
V
and V
are the power supply pins for the analog portion of the
SSA
DDA
clock generator module (CGM). Decoupling of these pins should be as
per the digital supply. See Section 7. Clock Generator Module
(CGMC).
1.6.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Section 7. Clock Generator Module (CGMC).
1.6.7 Analog Power Supply Pins (V
and V
)
SSAD
DDAD
V
and V
are the power supply pins for the analog-to-digital
DDAD
SSAD
converter. Decoupling of these pins should be as per the digital supply.
See Section 5. Analog-to-Digital Converter (ADC).
1.6.8 ADC Voltage Reference High Pin (V
)
REFH
V
is the high reference supply for the ADC. Connect the V
pin
REFH
REFH
to the same voltage potential as V
. See Section 5. Analog-to-
DDAD
Digital Converter (ADC).
1.6.9 ADC Voltage Reference Low Pin (V
)
REFL
V
is the low reference supply for the ADC. Connect the V
pin to
REFL
REFL
the same voltage potential as V
. See Section 5. Analog-to-Digital
SSAD
Converter (ADC).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
39
1.6.10 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0)
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all
of the port A pins can be programmed to serve as keyboard interrupt
pins. See Section 16. Input/Output (I/O) Ports and Section 13.
Keyboard Interrupt Module (KBI).
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
1.6.11 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can
also be used for analog-to-digital converter (ADC) inputs. See Section
16. Input/Output (I/O) Ports and Section 5. Analog-to-Digital
Converter (ADC).
1.6.12 Port C I/O Pins (PTC6–PTC0)
PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See
Section 16. Input/Output (I/O) Ports. PTC5 and PTC6 are only
available on 44-pin QFP packages.
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
1.6.13 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins.
PTD0–PTD3 can be programmed to be serial peripheral interface (SPI)
pins, while PTD4–PTD7 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Section 22. Timer
Interface Module (TIM), Section 20. Serial Peripheral Interface
Module (SPI), and Section 16. Input/Output (I/O) Ports. PTD6 and
PTD7 are only available on 44-pin QFP packages.
Advance Information
40
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
1.6.14 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins
can also be programmed to be serial communications interface (SCI)
pins. See Section 18. Serial Communications Interface Module (SCI)
and Section 16. Input/Output (I/O) Ports.
NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V or V ). Although the I/O ports of the
DD
SS
MC68HC908GP20 do not require termination, termination is
recommended to reduce the possibility of static damage.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
41
Advance Information
42
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 2. Memory Map
2.1 Contents
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .43
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
• 20 Kbytes of FLASH memory, 19,968 bytes of user space
• 512 bytes of random-access memory (RAM)
• 36 bytes of user-defined vectors
• 307 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map
(Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
43
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area
of $0000–$003F. Additional I/O registers have these addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE02; reserved, SUBAR
• $FE03; SIM break flag control register, SBFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
• $FE07; reserved, FLTCR
• $FE08; FLASH control register, FLCR
• $FE09; break address register high, BRKH
• $FE0A; break address register low, BRKL
• $FE0B; break status and control register, BRKSCR
• $FE0C; LVI status register, LVISR
• $FF80; FLASH block protect register, FLBPR
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector
locations.
Advance Information
44
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
$0000
↓
I/O Registers
64 Bytes
$003F
$0040
↓
RAM
512 Bytes
$023F
$0240
↓
Unimplemented
44,480 Bytes
$AFFF
$B000
↓
FLASH Memory
19,968 Bytes
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
↓
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved (SUBAR)
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Interrupt Status Register 3 (INT3)
Reserved (FLTCR)
FLASH Control Register (FLCR)
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
LVI Status Register (LVISR)
Unimplemented
3 Bytes
$FE0F
Figure 2-1. Memory Map
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
45
$FE10
↓
Unimplemented
16 Bytes
Reserved for Compatibility with Monitor Code
for A-Family Parts
$FE1F
$FE20
↓
Monitor ROM
307 Bytes
$FF52
$FF53
↓
Unimplemented
45 Bytes
$FF7F
$FF80
$FF81
↓
FLASH Block Protect Register (FLBPR)
Unimplemented
91 Bytes
$FFDB
$FFDC
↓
Note: $FFF6–$FFFD
reserved for
8 security bytes
FLASH Vectors
36 Bytes
$FFFF
Figure 2-1. Memory Map (Continued)
Advance Information
46
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
0
PTB6
PTC6
PTD6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Port C Data Register
(PTC)
PTD7
Port D Data Register
(PTD)
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
DDRB1
0
0
DDRB0
0
DDRB7
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
Data Direction Register B
(DDRB)
0
0
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Data Direction Register C
(DDRC)
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
Unimplemented Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
47
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
$000A
Unimplemented Write:
Reset:
Read:
0
0
0
0
0
0
0
0
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
Unimplemented Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRE1
0
0
DDRE0
0
Read:
Data Direction Register E
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
(DDRE)
0
0
0
0
0
0
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Port A Input Pullup Enable
Register (PTAPUE)
0
0
0
0
0
0
0
0
0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Port C Input Pullup Enable
Register (PTCPUE)
0
0
0
0
0
0
0
0
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Port D Input Pullup Enable
Register (PTDPUE)
0
SPRIE
0
0
0
0
0
0
0
SPE
0
0
DMAS
SPMSTR
CPOL
CPHA
SPWOM
0
SPTIE
0
SPI Control Register
(SPCR)
0
1
0
1
Read: SPRF
Write:
OVRF
MODF
SPTE
ERRIE
MODFEN
SPR1
SPR0
SPI Status and Control
Register (SPSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
1
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by reset
LOOPS
0
ENSCI
0
TXINV
0
M
WAKE
0
ILTY
0
PEN
0
PTY
0
SCI Control Register 1
(SCC1)
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
Advance Information
48
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
Read:
Write:
Reset:
SCTIE
SCI Control Register 2
(SCC2)
$0014
0
0
R8
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
SCI Control Register 3
(SCC3)
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
U
U
0
0
0
0
0
0
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
PE
SCI Status Register 1
(SCS1)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
1
1
0
0
0
0
0
0
BKF
RPF
SCI Status Register 2
(SCS2)
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register
(SCDR)
Unaffected by reset
SCP1
SCP0
R
SCR2
SCR1
0
SCR0
0
SCI Baud Rate Register
(SCBR)
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status
IMASKK MODEK
and Control Register Write:
(INTKBSCR)
Reset:
0
KBIE7
0
0
0
0
0
0
KBIE1
0
0
Read:
KBIE6
0
KBIE5
0
KBIE4
0
KBIE3
KBIE2
0
KBIE0
Keyboard Interrupt Enable
Write:
Register (INTKBIER)
Reset:
0
0
0
R
0
Read: TBIF
Write:
TBR2
TBR1
TBR0
TBIE
TBON
0
Time Base Module Control
Register (TBCR)
TACK
0
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
IRQF1
0
IMASK1 MODE1
IRQ Status and Control
Register (INTSCR)
ACK1
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
49
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
PMPSGV- OSC-
LVEN STOPENB
SCIBD-
SRC
Configuration Register 2
$001E
(CONFIG2)† Write:
Reset:
0
0
0
0
0
0
0
STOP
0
0
COPD
0
Read:
†
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
Configuration Register 1
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Write:
Reset:
Read:
Write:
Reset:
†
(CONFIG1)
0
TOF
0
0
0
0
0
0
0
0
TOIE
TSTOP
PS2
PS1
PS0
Timer 1 Status and Control
Register (T1SC)
TRST
0
0
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
Timer 1 Counter Register
High (T1CNTH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 1 Counter Register
Low (T1CNTL)
0
Bit 15
1
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Timer 1 Counter Modulo
Register High (T1MODH)
1
1
1
1
1
1
1
Bit 0
1
Bit 7
1
6
1
5
1
4
1
3
2
1
Timer 1 Counter Modulo
Register Low (T1MODL)
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read: CH0F
Timer 1 Channel 0 Status
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
and Control Register Write:
0
0
(T1SC0)
Reset:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 1 Channel 0
Write:
Register High (T1CH0H)
Reset:
Read:
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
Timer 1 Channel 0
Register Low (T1CH0L)
Write:
Reset:
Indeterminate after reset
† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Advance Information
50
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
CH1IE
0
5
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
0
Timer 1 Channel 1 Status
$0028
and Control Register Write:
0
0
(T1SC1)
Reset:
0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 1 Channel 1
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
Write:
Register High (T1CH1H)
Reset:
Read:
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
PS0
Timer 1 Channel 1
Register Low (T1CH1L)
Write:
Reset:
Read:
Indeterminate after reset
TOF
0
TRST
0
0
TOIE
TSTOP
PS2
PS1
Timer 2 Status and Control
Write:
0
0
Register (T2SC)
Reset:
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
Timer 2 Counter Register
High (T2CNTH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 2 Counter Register
Low (T2CNTL)
0
Bit 15
1
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Timer 2 Counter Modulo
Register High (T2MODH)
1
1
1
1
1
1
1
Bit 0
1
Bit 7
1
6
1
5
1
4
1
3
2
1
Timer 2 Counter Modulo
Register Low (T2MODL)
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read: CH0F
Timer 2 Channel 0 Status
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
and Control Register Write:
0
0
(T2SC0)
Reset:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 2 Channel 0
Register High (T2CH0H)
Write:
Reset:
Indeterminate after reset
R = Reserved
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
51
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Timer 2 Channel 0
Register Low (T2CH0L)
$0032
Indeterminate after reset
Read: CH1F
0
Timer 2 Channel 1 Status
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
and Control Register Write:
0
0
(T2SC1)
Reset:
0
0
0
0
0
9
0
Read:
Bit 15
14
13
12
11
10
Bit 8
Timer 2 Channel 1
Register High (T2CH1H)
Write:
Reset:
Read:
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
Timer 2 Channel 1
Register Low (T2CH1L)
Write:
Reset:
Read:
Indeterminate after reset
PLLF
PLLIE
0
PLLON
1
BCS
PRE1
PRE0
VPR1
VPR0
PLL Control Register
Write:
(PCTL)
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
LOCK
AUTO
ACQ
R
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
0
0
0
0
0
0
0
0
0
MUL11
0
0
MUL10
0
0
MUL9
0
0
MUL8
0
PLL Multiplier Select High
Write:
Register (PMSH)
Reset:
Read:
0
0
0
0
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
MUL2
0
MUL1
0
MUL0
0
PLL Multiplier Select Low
Write:
Register (PMSL)
Reset:
Read:
VRS7
VRS6
VRS5
VRS4
VRS3
0
VRS2
0
VRS1
0
VRS0
0
PLL VCO Select Range
Write:
Register (PMRS)
Reset:
Read:
0
0
1
0
0
0
0
0
RDS3
0
RDS2
0
RDS1
0
RDS0
1
PLL Reference Divider
Select Register (PMDS)
Write:
Reset:
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
Advance Information
52
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: COCO
Analog-to-Digital Status
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
$003C
and Control Register Write:
R
0
(ADSCR)
Reset:
0
AD6
R
0
AD5
R
1
AD4
R
1
AD3
R
1
AD2
R
1
AD1
R
1
AD0
R
Read:
AD7
R
Analog-to-Digital Data
$003D
$003E
$003F
$FE00
Write:
Register (ADR)
Reset:
Read:
Indeterminate after reset
0
0
R
0
0
R
0
0
R
0
ADIV2
0
ADIV1
0
ADIV0
0
ADICLK
R
Analog-to-Digital Input
Clock Register (ADCLK)
Write:
Reset:
Read:
0
0
Unimplemented Write:
Reset:
Read:
SBSW
NOTE
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SIM Break Status Register
Write:
(SBSR)
Reset:
Note: Writing a logic 0 clears SBSW.
Read: POR
Write:
PIN
COP
ILOP
ILAD
MODRST
LVI
0
SIM Reset Status Register
$FE01
(SRSR)
POR:
Read:
Write:
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
SIM Upper Byte Address
$FE02
Register (SUBAR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
$FE04
$FE05
0
IF6
R
IF5
R
IF4
R
IF3
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
R
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
R
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
53
Addr.
Register Name
Bit 7
6
0
5
0
4
0
3
0
2
0
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
R
0
Interrupt Status Register 3
(INT3)
$FE06
R
0
R
0
R
0
R
0
R
0
0
0
R
R
R
0
R
0
R
R
0
R
0
R
0
FLASH Test Control
Register (FLTCR)
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FF80
$FFFF
0
FDIV1
0
0
0
FDIV0
BLK1
0
BLK0
0
HVEN
MARGIN ERASE
PGM
0
FLASH Control Register
(FLCR)
0
0
11
0
0
10
0
0
9
0
1
Bit 15
0
14
13
0
12
0
Bit 8
0
Break Address Register
High (BRKH)
0
Bit 7
0
6
0
5
4
3
2
Bit 0
Break Address Register
Low (BRKL)
0
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
BRKA
Break Status and Control
Register (BRKSCR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: LVIOUT
Write:
LVI Status Register
(LVISR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
Bit 7
U
0
6
0
5
0
Bit 4
U
0
BPR3
U
0
BPR2
U
0
BPR1
U
0
BPR0
U
FLASH Block Protect
Register (FLBPR)
†
U
U
Low byte of reset vector
COP Control Register
(COPCTL)
Writing clears COP counter (any value)
Unaffected by reset
† Non-volatile FLASH register
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
Advance Information
54
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
.
Table 2-1. Vector Addresses
Vector Priority Vector Address
Lowest
Vector
Timebase Vector (High)
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
Timebase Vector (Low)
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIM2 Overflow Vector (High)
TIM2 Overflow Vector (Low)
TIM2 Channel 1 Vector (High)
TIM2 Channel 1 Vector (Low)
TIM2 Channel 0 Vector (High)
TIM2 Channel 0 Vector (Low)
TIM1 Overflow Vector (High)
TIM1 Overflow Vector (Low)
TIM1 Channel 1 Vector (High)
TIM1 Channel 1 Vector (Low)
TIM1 Channel 0 Vector (High)
TIM1 Channel 0 Vector (Low)
PLL Vector (High)
IF8
IF7
IF6
IF5
IF4
IF3
IF2
PLL Vector (Low)
IRQ Vector (High)
IF1
IRQ Vector (Low)
SWI Vector (High)
—
SWI Vector (Low)
Reset Vector (High)
—
Highest
Reset Vector (Low)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
55
Advance Information
56
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 3. Low-Power Modes
3.1 Contents
3.2
3.2.1
3.2.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3
3.3.1
3.3.2
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.4
3.4.1
3.4.2
Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.5
3.5.1
3.5.2
Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.6
3.6.1
3.6.2
Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.7
3.7.1
3.7.2
Computer Operating Properly Module (COP). . . . . . . . . . . . . .61
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.8
3.8.1
3.8.2
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.9
3.9.1
3.9.2
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63
3.10.1
3.10.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
57
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .63
3.11.1
3.11.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .64
3.12.1
3.12.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .64
3.13.1
3.13.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.14.1
3.14.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.2 Introduction
The MCU may enter two low-power modes: wait mode and stop mode.
They are common to all HC08 MCUs and are entered through instruction
execution. This section describes how each module acts in the low-
power modes.
3.2.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in
which the CPU clock is disabled but the bus clock continues to run.
Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See
Section 8. Configuration Register (CONFIG).)
Advance Information
58
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
3.2.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU
clock is disabled and the bus clock is disabled if the OSCSTOPENB bit
in the CONFIG register is at a logic 0. (See Section 8. Configuration
Register (CONFIG).)
3.3 Analog-to-Digital Converter (ADC)
3.3.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.
3.3.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
3.4 Break Module (BRK)
3.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if the BW
bit in the break status register is set.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
59
3.4.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the BW bit in the break status register. The
STOP instruction does not affect break module register states.
3.5 Central Processor Unit (CPU)
3.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
3.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
3.6 Clock Generator Module (CGM)
3.6.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
Advance Information
60
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
3.6.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.
3.7 Computer Operating Properly Module (COP)
3.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
3.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
61
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
3.8 External Interrupt Module (IRQ)
3.8.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of wait mode.
3.8.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of stop mode.
3.9 Keyboard Interrupt Module (KBI)
3.9.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
3.9.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
Advance Information
62
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
3.10 Low-Voltage Inhibit Module (LVI)
3.10.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.
3.10.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of stop mode.
3.11 Serial Communications Interface Module (SCI)
3.11.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
3.11.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
63
3.12 Serial Peripheral Interface Module (SPI)
3.12.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
3.12.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
3.13 Timer Interface Module (TIM1 and TIM2)
3.13.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
3.13.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.
Advance Information
64
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
3.14 Timebase Module (TBM)
3.14.1 Wait Mode
The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.
If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.
3.14.2 Stop Mode
The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.
If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during stop mode. In stop mode, the
timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.
3.15 Exiting Wait Mode
These events restart the CPU clock and load the program counter with
the reset vector or with an interrupt vector:
• External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
65
• External interrupt — A high-to-low transition on an external
interrupt pin (IRQ pin) loads the program counter with the contents
of locations: $FFFA and $FFFB; IRQ pin.
• Break interrupt — A break interrupt loads the program counter
with the contents of $FFFC and $FFFD.
• Computer operating properly module (COP) reset — A timeout of
the COP counter resets the MCU and loads the program counter
with the contents of $FFFE and $FFFF.
• Low-voltage inhibit module (LVI) reset — A power supply voltage
below the V
voltage resets the MCU and loads the program
tripf
counter with the contents of locations $FFFE and $FFFF.
• Clock generator module (CGM) interrupt — A CPU interrupt
request from the phase-locked loop (PLL) loads the program
counter with the contents of $FFF8 and $FFF9.
• Keyboard module (KBI) interrupt — A CPU interrupt request from
the KBI module loads the program counter with the contents of
$FFE0 and $FFE1.
• Timer 1 interface module (TIM1) interrupt — A CPU interrupt
request from the TIM1 loads the program counter with the
contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
• Timer 2 interface module (TIM2) interrupt — A CPU interrupt
request from the TIM2 loads the program counter with the
contents of:
– $FFEC and $FFED; TIM2 overflow
– $FFEE and $FFEF; TIM2 channel 1
– $FFF0 and $FFF1; TIM2 channel 0
• Serial peripheral interface module (SPI) interrupt — A CPU
interrupt request from the SPI loads the program counter with the
contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
Advance Information
66
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Serial communications interface module (SCI) interrupt — A CPU
interrupt request from the SCI loads the program counter with the
contents of:
– $FFE2 and $FFE3; SCI transmitter
– $FFE4 and $FFE5; SCI receiver
– $FFE6 and $FFE7; SCI receiver error
• Analog-to-digital converter module (ADC) interrupt — A CPU
interrupt request from the ADC loads the program counter with the
contents of: $FFDE and $FFDF; ADC conversion complete.
• Timebase module (TBM) interrupt — A CPU interrupt request from
the TBM loads the program counter with the contents of: $FFDC
and $FFDD; TBM interrupt.
3.16 Exiting Stop Mode
These events restart the system clocks and load the program counter
with the reset vector or with an interrupt vector:
• External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
• External interrupt — A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:
– $FFFA and $FFFB; IRQ pin
– $FFE0 and $FFE1; keyboard interrupt pins
• Low-voltage inhibit (LVI) reset — A power supply voltage below
the LVI
voltage resets the MCU and loads the program counter
tripf
with the contents of locations $FFFE and $FFFF.
• Break interrupt — A break interrupt loads the program counter
with the contents of locations $FFFC and $FFFD.
• Timebase module (TBM) interrupt — A TBM interrupt loads the
program counter with the contents of locations $FFDC and $FFDD
when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
67
Upon exit from stop mode, the system clocks begin running after an
oscillator stabilization delay. A 12-bit stop recovery counter inhibits the
system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register
controls the oscillator stabilization delay during stop recovery. Setting
SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE: Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
Advance Information
68
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 4. Resets and Interrupts
4.1 Contents
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.4
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
External Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
COP Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . .74
4.4
4.4.1
4.4.2
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
CGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TIM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
KBD0–KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
4.4.2.6
4.4.2.7
4.4.2.8
4.4.2.9
4.4.2.10
4.4.2.11
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
ADC (Analog-to-Digital Converter). . . . . . . . . . . . . . . . . .83
TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . .83
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .84
Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .86
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
69
4.2 Introduction
Resets and interrupts are responses to exceptional events during
program execution. A reset re-initializes the MCU to its startup condition.
An interrupt vectors the program counter to a service routine.
4.3 Resets
A reset immediately returns the MCU to a known startup condition and
begins program execution from a user-defined memory location.
4.3.1 Effects
A reset:
• Immediately stops the operation of the instruction being executed
• Initializes certain control and status bits
• Loads the program counter with a user-defined reset vector
address from locations $FFFE and $FFFF
• Selects CGMXCLK divided by four as the bus clock
4.3.2 External Reset
A logic 0 applied to the RST pin for a time, t , generates an external
IRL
reset. An external reset sets the PIN bit in the SIM reset status register.
Advance Information
70
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
4.3.3 Internal Reset
Sources:
• Power-on reset (POR)
• Computer operating properly (COP)
• Low-power reset circuits
• Illegal opcode
• Illegal address
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles
to allow resetting of external devices. The MCU is held in reset for an
additional 32 CGMXCLK cycles after releasing the RST pin.
PULLED LOW BY MCU
RST PIN
32 CYCLES
32 CYCLES
CGMXCLK
INTERNAL
RESET
Figure 4-1. Internal Reset Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
71
4.3.3.1 Power-On Reset
A power-on reset (POR) is an internal reset caused by a positive
transition on the V pin. V at the POR must go completely to 0 V to
DD
DD
reset the MCU. This distinguishes between a reset and a POR. The POR
is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay
• Sets the POR and LP bits in the SIM reset status register and
clears all other bits in the register
OSC1
PORRST(1)
4096
32
32
CYCLES CYCLES CYCLES
CGMXCLK
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
Advance Information
72
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
4.3.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
4.3.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI voltage.
tripf
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI
voltage
tripr
• Drives the RST pin low for as long as V is below the LVI
DD
tripr
voltage and during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
• Sets the LVI bit in the SIM reset status register
4.3.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
73
4.3.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
4.3.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits
are automatically cleared following a read of the register. Reset service
can read the SIM reset status register to clear the register after power-
on reset and to determine the source of any subsequent reset.
The register is initialized on powerup as shown with the POR bit set and
all other bits cleared. During a POR or any other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32 XCLK
cycles later. If the pin is not above a VIH at that time, then the PIN bit in
the SRSR may be set in addition to whatever other bits are set.
NOTE: Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.
Address: $FE01
Bit 7
POR
6
5
4
3
2
0
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 4-3. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
Advance Information
74
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.4 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.
4.4.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.
• Sets the interrupt mask (I bit) to prevent additional interrupts.
Once an interrupt is latched, no other interrupt can take
precedence, regardless of its priority.
• Loads the program counter with a user-defined vector address
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
75
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
5
4
3
2
1
1
2
3
4
5
INDEX REGISTER (LOW BYTE)*
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
UNSTACKING
ORDER
•
•
•
$00FF DEFAULT ADDRESS ON RESET
*High byte of index register is not stacked.
Figure 4-4. Interrupt Stacking Order
After every instruction, the CPU checks all pending interrupts if the I bit
is not set. If more than one interrupt is pending when an instruction is
done, the highest priority interrupt is serviced first. In the example shown
in Figure 4-5, if an interrupt is pending upon exit from the interrupt
service routine, the pending interrupt is serviced before the LDA
instruction is executed.
Advance Information
76
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 4-5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the
H register and then restore it prior to exiting the routine.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
77
FROM RESET
YES
BREAK
INTERRUPT
?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT
?
NO
CGM
INTERRUPT
?
NO
OTHER
INTERRUPTS
?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
YES
INSTRUCTION
?
NO
RTI
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
INSTRUCTION
?
NO
Figure 4-6. Interrupt Processing
Advance Information
78
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
4.4.2 Sources
The sources in Table 4-1 can generate CPU interrupt requests.
Table 4-1. Interrupt Sources
Reset
None
None
IRQF
PLLF
CH0F
CH1F
TOF
None
None
None
None
IF1
0
0
1
2
3
4
5
6
7
8
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
$FFEC–$FFED
SWI instruction
IRQ pin
IMASK1
PLLIE
CH0IE
CH1IE
TOIE
CGM (PLL)
IF2
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receiver full
SPI overflow
IF3
IF4
IF5
CH0F
CH1F
TOF
CH0IE
CH1IE
TOIE
IF6
IF7
IF8
SPRF
OVRF
MODF
SPTE
OR
SPRIE
ERRIE
ERRIE
SPTIE
ORIE
IF9
9
$FFEA–$FFEB
$FFE8–$FFE9
SPI mode fault
SPI transmitter empty
SCI receiver overrun
SCI noise fag
IF10
10
NF
NEIE
IF11
11
$FFE6–$FFE7
SCI framing error
SCI parity error
SCI receiver full
SCI input idle
FE
FEIE
PE
PEIE
SCRF
IDLE
SCTE
TC
SCRIE
ILIE
IF12
IF13
12
13
$FFE4–$FFE5
$FFE2–$FFE3
SCI transmitter empty
SCI transmission complete
Keyboard pin
SCTIE
TCIE
KEYF
COCO
TBIF
IMASKK
AIEN
IF14
IF15
IF16
14
15
$FFE0–$FFE1
$FFDE–$FFDF
ADC conversion complete
Timebase
TBIE
16 $FFDC–$FFDD
Note:
1. The I bit in the condition code register is a global mask for all interrupt sources except the
SWI instruction.
2. 0 = highest priority
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
79
4.4.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
NOTE: A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
4.4.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
4.4.2.3 IRQ Pin
4.4.2.4 CGM
A logic 0 on the IRQ1 pin latches an external interrupt request.
The CGM can generate a CPU interrupt request every time the phase-
locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
4.4.2.5 TIM1
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x
status and control register.
Advance Information
80
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
4.4.2.6 TIM2
TIM2 CPU interrupt sources:
• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2
counter value rolls over to $0000 after matching the value in the
TIM2 counter modulo registers. The TIM2 overflow interrupt
enable bit, TOIE, enables TIM2 overflow CPU interrupt requests.
TOF and TOIE are in the TIM2 status and control register.
• TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM2 CPU
interrupt requests. CHxF and CHxIE are in the TIM2 channel x
status and control register.
4.4.2.7 SPI
SPI CPU interrupt sources:
• SPI receiver full bit (SPRF) — The SPRF bit is set every time a
byte transfers from the shift register to the receive data register.
The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register
and SPRIE is in the SPI control register.
• SPI transmitter empty (SPTE) — The SPTE bit is set every time a
byte transfers from the transmit data register to the shift register.
The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register
and SPTIE is in the SPI control register.
• Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the
SS pin goes high during a transmission with the mode fault enable
bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS
pin goes low at any time with the MODFEN bit set. The error
interrupt enable bit, ERRIE, enables MODF CPU interrupt
requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
81
• Overflow bit (OVRF) — The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.
4.4.2.8 SCI
SCI CPU interrupt sources:
• SCI transmitter empty bit (SCTE) — SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.
• Transmission complete bit (TC) — TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.
• SCI receiver full bit (SCRF) — SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.
• Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
• Receiver overrun bit (OR) — OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.
Advance Information
82
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Noise flag (NF) — NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.
• Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
• Parity error bit (PE) — PE is set when the SCI detects a parity error
in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
4.4.2.9 KBD0–KBD7 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
4.4.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not
used as a conversion complete flag when interrupts are enabled.
4.4.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2–TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
83
4.4.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 4-2 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 4-2. Interrupt Source Flags
Interrupt Status
Interrupt Source
Register Flag
Reset
—
—
SWI instruction
IRQ pin
IF1
CGM (PLL)
IF2
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receive
IF3
IF4
IF5
IF6
IF7
IF8
IF9
SPI transmit
SCI error
IF10
IF11
IF12
IF13
IF14
IF15
IF16
SCI receive
SCI transmit
Keyboard
ADC conversion complete
Timebase
Advance Information
84
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
4.4.3.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
IF5
R
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF6
R
R
0
R
0
0
0
0
0
0
0
R = Reserved
Figure 4-7. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 and Bit 0 — Always read 0
4.4.3.2 Interrupt Status Register 2
Address: $FE05
Bit 7
6
IF13
R
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF14
R
0
0
0
0
0
0
0
0
R = Reserved
Figure 4-8. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
85
4.4.3.3 Interrupt Status Register 3
Address: $FE06
Bit 7
6
0
5
0
4
0
3
0
2
0
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
0
R
0
R
0
R
0
R
0
0
0
0
R = Reserved
Figure 4-9. Interrupt Status Register 3 (INT3)
IF16–IF15 — Interrupt Flags 16–15
This flag indicates the presence of an interrupt request from the source
shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bits 7–2 — Always read 0
Advance Information
86
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 5. Analog-to-Digital Converter (ADC)
5.1 Contents
5.2
5.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Voltage Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .90
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.6
5.6.1
5.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.7.1
ADC Analog Power Pin (V
)/ADC Voltage
DDAD
Reference High Pin (V
) . . . . . . . . . . . . . . . . . . . . .92
REFH
5.7.2
5.7.3
ADC Analog Ground Pin (V
)/ADC Voltage
) . . . . . . . . . . . . . . . . . . . . . .92
SSAD
Reference Low Pin (V
REFL
ADC Voltage In (ADV ) . . . . . . . . . . . . . . . . . . . . . . . . . . .92
IN
5.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . .93
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
5.8.1
5.8.2
5.8.3
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
87
5.2 Introduction
5.3 Features
This section describes the 8-bit analog-to-digital converter (ADC).
Features of the ADC module include:
• Eight channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
5.4 Functional Description
The ADC provides eight pins for sampling external sources at pins
PTB7/AD7–PTB0/AD0. An analog multiplexer allows the single ADC
converter to select one of eight ADC channels as ADC voltage in
(ADCV ). ADCV is converted by the successive approximation
IN
IN
register-based analog-to-digital converter. When the conversion is
completed, ADC places the result in the ADC data register and sets a
flag or generates an interrupt. (See Figure 5-1.)
NOTE: References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. If the MCU has no DMA,
any DMA-related register bits should be left in their reset state for
expected MCU operation.
Advance Information
88
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
DISABLE
DDRBx
PTBx
RESET
WRITE PTB
PTB/Dx
ADC CHANNEL x
READ PTB
DISABLE
ADC DATA REGISTER
ADC
VOLTAGE IN
(ADVIN
CONVERSION
COMPLETE
ADCH4–ADCH0
)
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
ADC CLOCK
AIEN
COCO
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0
ADICLK
Figure 5-1. ADC Block Diagram
5.4.1 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins
that share with the ADC channels. The channel select bits define which
ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
Read of a port pin in use by the ADC will return a logic 0.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
89
5.4.2 Voltage Conversion
When the input voltage to the ADC equals V
, the ADC converts the
REFH
signal to $FF (full scale). If the input voltage equals V
, the ADC
SSAD
converts it to $00. Input voltages between V
and V
are a
REFH
SSAD
straight-line linear conversion. All other input voltages will result in $FF,
if greater than V
.
REFH
NOTE: Input voltage should not exceed the analog supply voltages.
5.4.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits
should be set to provide a 1-MHz ADC clock frequency.
16-17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time x bus frequency
5.4.4 Conversion
In continuous conversion mode, the ADC data register will be filled with
new data after each conversion. Data from the previous conversion will
be overwritten whether that data has been read or not. Conversions will
continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after
the first conversion and will stay set until the next write of the ADC status
and control register or the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the
ADSCR. Only one conversion occurs between writes to the ADSCR.
5.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
Advance Information
90
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
5.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU
interrupts after each ADC conversion. A CPU interrupt is generated if the
COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt
is generated. The COCO/IDMAS bit is not used as a conversion
complete flag when interrupts are enabled.
5.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power-
consumption standby modes.
5.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.
5.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
5.7 I/O Signals
The ADC module has eight pins shared with port B,
PTB7/AD7–PTB0/AD0.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
91
5.7.1 ADC Analog Power Pin (V
)/ADC Voltage Reference High Pin (V
)
DDAD
REFH
The ADC analog portion uses V
as its power pin. Connect the
DDAD
V
pin to the same voltage potential as V . External filtering may
DDAD
DD
be necessary to ensure clean V
for good results.
DDAD
NOTE:
For maximum noise immunity, route V
carefully and place bypass
DDAD
capacitors as close as possible to the package.
5.7.2 ADC Analog Ground Pin (V
)/ADC Voltage Reference Low Pin (V
)
SSAD
REFL
The ADC analog portion uses V
as its ground pin. Connect the
SSAD
V
pin to the same voltage potential as V .
SS
SSAD
NOTE: Route V
cleanly to avoid any offset errors.
SSAD
5.7.3 ADC Voltage In (ADV )
IN
ADV is the input voltage signal from one of the eight ADC channels to
IN
the ADC module.
5.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
Advance Information
92
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
5.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described
here.
Address: $0003C
Bit 7
6
AIEN
0
5
ADCO
0
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Read:
COCO/
IDMAS
Write:
Reset:
0
Figure 5-2. ADC Status and Control Register (ADSCR)
COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit
When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADSCR is written or whenever the
ADR is read.
If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request. Reset
clears this bit.
1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
CAUTION: Because the MC68HC908GP20 does NOT have a DMA module, the
IDMAS bit should NEVER be set when AIEN is set. Doing so will mask
ADC interrupts and cause unwanted results.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
93
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16
ADC channels. Only eight channels, AD7–AD0, are available on this
MCU. The channels are detailed in Table 5-1. Care should be taken
when using a port pin as both an analog and digital input
simultaneously to prevent switching noise from corrupting the analog
signal. (See Table 5-1.)
The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not being used.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
The voltage levels supplied from internal reference nodes, as specified
in Table 5-1, are used to verify the operation of the ADC converter both
in production test and for user applications.
Advance Information
94
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 5-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
PTB0/AD0
PTB1/AD1
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
↓
1
1
1
1
1
0
0
0
0
0
0
0
0
↓
1
1
1
1
1
0
0
0
0
1
1
1
1
↓
0
1
1
1
1
0
0
1
1
0
0
1
1
↓
1
0
0
1
1
0
1
0
1
0
1
0
1
↓
1
0
1
0
1
V
V
REFH
SSAD
ADC power off
NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown
or reserved.
5.8.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address: $0003D
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
95
5.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
Address: $0003E
Bit 7
6
ADIV1
0
5
ADIV0
0
4
ADICLK
0
3
0
2
0
1
0
Bit 0
0
Read:
ADIV2
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock. Table 5-2 shows the
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 5-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
X = don’t care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
Advance Information
96
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If CGMXCLK
is less than 1 MHz, use the PLL-generated bus clock as the clock
source. As long as the internal ADC clock is at approximately 1 MHz,
correct operation can be guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
----------------------------------------------------------------------- = 1 M H z
ADIV2–ADIV0
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
97
Advance Information
98
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 6. Break Module (BRK)
6.1 Contents
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Flag Protection During Break Interrupts . . . . . . . . . . . . . .102
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .102
TIMI and TIM2 During Break Interrupts. . . . . . . . . . . . . . .102
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .102
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
6.6
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Break Status and Control Register . . . . . . . . . . . . . . . . . .103
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .104
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .106
6.6.1
6.6.2
6.6.3
6.6.4
6.2 Introduction
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
99
6.3 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
6.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 6-1 shows the structure of the break module.
Advance Information
100
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 6-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
0
5
0
4
1
3
0
2
1
BW
NOTE
0
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
R
0
0
R
0
0
R
0
SIM Break Status Register
(SBSR)
$FE00
R
0
R
0
R
1
R
0
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
$FE09
$FE0A
$FE0B
0
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
Break Address Register
High (BRKH)
0
Bit 7
0
6
5
4
3
2
Bit 0
Break Address Register
Low (BRKL)
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
Break Status and Control
Register (BRKSCR)
0
0
0
0
0
0
Note: Writing a logic 0 clears BW.
= Unimplemented
R
= Reserved
Figure 6-2. I/O Register Summary
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
101
6.4.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
6.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
6.4.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
6.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
the RST pin.
is present on
TST
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
6.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set. See Section 3. Low-Power Modes. Clear the BW bit by writing
logic 0 to it.
Advance Information
102
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
6.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register.
6.6 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM break status register (SBSR)
• SIM break flag control register (SBFCR)
6.6.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module
enable and status bits.
Address: $FE0B
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 6-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
103
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
6.6.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
$FE09
Address:
Bit 7
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Bit 15
0
Figure 6-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 6-5. Break Address Register Low (BRKL)
Advance Information
104
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
6.6.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break
caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Address: $FE00
Bit 7
0
6
0
5
0
4
3
0
2
0
1
BW
NOTE
0
Bit 0
0
Read:
Write:
Reset:
1
R
R
0
R
0
R
R
0
R
0
R
0
1
0
Note: Writing a logic 0 clears BW.
R
= Reserved
Figure 6-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The following
code is an example.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not BW, do RTI
BRCLR BW,BSR, RETURN ; See if wait mode or stop mode
; was exited by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
105
6.6.4 Break Flag Control Register
The break flag control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 6-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Advance Information
106
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 7. Clock Generator Module (CGMC)
7.1 Contents
7.2
7.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .111
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .111
PLL Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .113
Manual and Automatic PLL Bandwidth Modes . . . . . . . . .113
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Special Programming Exceptions . . . . . . . . . . . . . . . . . . .119
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . .119
CGMC External Connections . . . . . . . . . . . . . . . . . . . . . .120
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . .121
Crystal Amplifier Output Pin (OSC2). . . . . . . . . . . . . . . . .121
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . .122
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
PLL Analog Power Pin (V
) . . . . . . . . . . . . . . . . . . . . .122
DDA
PLL Analog Ground Pin (V
). . . . . . . . . . . . . . . . . . . . .122
SSA
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . .122
Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . .122
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .123
CGMC Base Clock Output (CGMOUT). . . . . . . . . . . . . . .123
CGMC CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . .123
7.6
CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . .127
PLL Multiplier Select Register High. . . . . . . . . . . . . . . . . .129
PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . .130
7.6.1
7.6.2
7.6.3
7.6.4
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
107
7.6.5
7.6.6
PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . .131
PLL Reference Divider Select Register. . . . . . . . . . . . . . .132
7.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
7.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . .134
7.8.1
7.8.2
7.8.3
7.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .135
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .135
Parametric Influences on Reaction Time . . . . . . . . . . . . .136
Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.9.1
7.9.2
7.9.3
7.2 Introduction
This section describes the clock generator module. The CGMC
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In
user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL
is a fully functional frequency generator designed for use with crystals or
ceramic resonators. The PLL can generate an 8-MHz bus frequency
using a 32-kHz crystal.
Advance Information
108
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.3 Features
Features of the CGMC include:
• Phase-locked loop with output frequency in integer multiples of an
integer dividend of the crystal reference
• Low-frequency crystal operation with low-power operation and
high-output frequency resolution
• Programmable prescaler for power-of-two increases in frequency
• Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop
mode
7.4 Functional Description
The CGMC consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock, CGMVCLK.
• Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.
Figure 7-1 shows the structure of the CGMC.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
109
OSCILLATOR (OSC)
OSC2
CGMXCLK
(TO: SIM, TIMTB15A, ADC)
OSC1
SIMOSCEN (FROM SIM)
OSCSTOPENB
(FROM CONFIG)
PHASE-LOCKED LOOP (PLL)
CGMRDV
CGMRCLK
CGMXFC
REFERENCE
DIVIDER
CGMOUT
A
B
CLOCK
SELECT
CIRCUIT
÷
2
BCS
(TO SIM)
S*
SIMDIV2
*WHEN S = 1,
CGMOUT = B
RDS3–RDS0
VDDA
VSSA
(FROM SIM)
VPR1–VPR0
VRS7–VRS0
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
CGMVCLK
PLL ANALOG
PLLIREQ
(TO SIM)
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL11–MUL0
PRE1–PRE0
CGMVDV
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER
Figure 7-1. CGMC Block Diagram
Advance Information
110
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable
the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the
OSC1 pin of the crystal oscillator circuit. Connect the external clock to
the OSC1 pin and let the OSC2 pin float.
7.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
7.4.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency prescaler
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
111
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGM/XFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
.
VRS
Modulating the voltage on the CGM/XFC pin changes the frequency
within this range. By design, f is equal to the nominal center-of-range
VRS
frequency, f
factor, E, or (L × 2 )f
, (38.4 kHz) times a linear factor, L, and a power-of-two
NOM
E
.
NOM
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f , and is fed to the PLL through a
RCLK
programmable modulo reference divider, which divides f
by a
RCLK
factor, R. The divider’s output is the final reference clock, CGMRDV,
running at a frequency, f = f /R. With an external crystal
RDV
RCLK
(30 kHz–100 kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
, is
VCLK
fed back through a programmable prescale divider and a programmable
modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N.
The dividers’ output is the VCO feedback clock, CGMVDV, running at a
P
frequency, f
= f
/(N × 2 ). (See 7.4.6 Programming the PLL for
VDV
VCLK
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in 7.4.4 Acquisition and Tracking Modes. The value of the
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
Advance Information
112
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
frequency, f
. The circuit determines the mode of the PLL and the lock
RDV
condition based on this comparison.
7.4.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
• Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See 7.6.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See 7.4.8 Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
7.4.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. Automatic mode is recommended for most
users.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See 7.6.2 PLL Bandwidth Control Register.) If PLL
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
113
to use as the source for the base clock. (See 7.4.8 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See 7.7 Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit (See 7.6.2 PLL Bandwidth Control Register.) is a
read-only indicator of the mode of the filter. (See 7.4.4
Acquisition and Tracking Modes.)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 7.9 Acquisition/Lock Time
Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 7.9 Acquisition/Lock Time
Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 7.6.1 PLL
Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below
f
.
BUSMAX
Advance Information
114
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t
(See 7.9 Acquisition/Lock Time
ACQ
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
• Software must wait a given time, t , after entering tracking mode
AL
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGMC are disabled.
7.4.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
.
BUSDES
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f
= 4 × f
VCLKDES
BUSDES
3. Choose a practical PLL (crystal) reference frequency, f
, and
RCLK
the reference clock divider, R. Typically, the reference crystal is
32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
/R. For
RCLK
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency, f
, and the
VCLK
reference frequency, f
, is
RCLK
P
2 N
= ----------- (f
f
)
RCLK
VCLK
R
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
115
P, the power of two multiplier, and N, the range multiplier, are
integers.
In cases where desired bus frequency has some tolerance,
choose f
to a value determined either by other module
RCLK
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
allows. See Section 23. Preliminary Electrical Specifications.
Choose the reference divider, R = 1. After choosing N and P, the
actual bus frequency can be determined using equation in 2
above.
When the tolerance on the bus frequency is tight, choose f
to
RCLK
an integer divisor of f
, and R = 1. If f
cannot meet this
BUSDES
RCLK
requirement, use the following equation to solve for R with
practical choices of f
lowest R.
, and choose the f
that gives the
RCLK
RCLK
f
f
VCLKDES
VCLKDES
-------------------------
-------------------------
R = round R
×
– integer
MAX
f
f
RCLK
RCLK
4. Select a VCO frequency multiplier, N.
R × f
VCLKDES
------------------------------------
N = round
f
RCLK
Reduce N/R to the lowest possible R.
5. If N is < N
, use P = 0. If N > N
, choose P using this table:
max
max
Current N Value
P
0
1
2
3
0 < N ≤ N
max
N
< N ≤ N
× 2
max
max
N
N
× 2 < N ≤ N
× 4 < N ≤ N
× 4
× 8
max
max
max
max
Advance Information
116
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Then recalculate N:
R × f
VCLKDES
------------------------------------
N = round
P
f
× 2
RCLK
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
117
6. Calculate and verify the adequacy of the VCO and bus
frequencies f
and f
.
VCLK
f
BUS
P
= (2 × N ⁄ R) × f
VCLK
RCLK
f
= (f
) ⁄ 4
VCLK
BUS
7. Select the VCO’s power-of-two range multiplier E, according to
this table:
Frequency Range
0 < fVCLK < 9,830,400
E
0
1
2
9,830,400 ≤ fVCLK < 19,660,800
19,660,800 ≤ fVCLK < 39,321,600
NOTE: Do not program E to a value of 3.
8. Select a VCO linear range multiplier, L, where f
= 38.4 kHz
NOM
f
VCLK
--------------------------
L = round
E
2 × f
NOM
9. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency, f . The center-of-range frequency is
VRS
the midpoint between the minimum and maximum frequencies
attainable by the PLL.
E
f
= (L × 2 )f
VRS
NOM
For proper operation,
E
f
× 2
NOM
f
– f
≤ --------------------------
VRS
VCLK
2
10. Verify the choice of P, R, N, E, and L by comparing f
to f
VRS
VCLK
and f
. For proper operation, f
must be within the
VCLKDES
VCLK
application’s tolerance of f
, and f
must be as close as
VCLKDES
VRS
possible to f
.
VCLK
NOTE: Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
Advance Information
118
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program
the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program
the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
d. In the PLL VCO range select register (PMRS), program the
binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program
the binary coded equivalent of R.
Table 7-1 provides numeric examples (numbers are in hexadecimal
notation):
Table 7-1. Numeric Example
f
f
RCLK
R
1
1
1
1
1
1
1
1
N
P
0
0
0
0
0
0
0
0
E
0
1
1
1
2
2
2
2
L
BUS
2.0 MHz
2.4576 MHz
2.5 MHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
F5
D1
80
83
D1
80
82
C0
D0
12C
132
1E9
258
263
384
3D1
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
119
7.4.7 Special Programming Exceptions
The programming method described in 7.4.6 Programming the PLL
does not account for three possible exceptions. A value of 0 for R, N, or
L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See 7.4.8 Base Clock Selector Circuit.)
7.4.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
Advance Information
120
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.4.9 CGMC External Connections
In its typical configuration, the CGMC requires up to nine external
components. Five of these are for the crystal oscillator and two or four
are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 7-2. Figure 7-2 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X
1
• Fixed capacitor, C
1
• Tuning capacitor, C (can also be a fixed capacitor)
2
• Feedback resistor, R
B
• Series resistor, R
S
The series resistor (R ) is included in the diagram to follow strict Pierce
S
oscillator guidelines. Refer to the crystal manufacturer’s data for more
information regarding values for C1 and C2.
Figure 7-2 also shows the external components for the PLL:
• Bypass capacitor, C
• Filter network
BYP
Routing should be done with great care to minimize signal cross talk and
noise.
See 23.17.1 CGM Component Specifications for capacitor and
resistor values.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
121
SIMOSCEN
OSCSTOPENB
(FROM CONFIG)
CGMXCLK
CGMXFC
VSSA
OSC1
OSC2
VDDA
VDD
RB
10 k
CBYP
0.1 µF
0.01 µF
RS
0.47 µF
X1
C1
C2
Note: Filter network in box can be replaced with a 0.47 µF capacitor, but will degrade stability.
Figure 7-2. CGMC External Connections
7.5 I/O Signals
The following paragraphs describe the CGMC I/O signals.
7.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
Advance Information
122
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. An external filter network is connected to this pin. (See
Figure 7-2.)
NOTE: To prevent noise problems, the filter network should be placed as close
to the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
7.5.4 PLL Analog Power Pin (V
)
DDA
V
V
is a power pin used by the analog portions of the PLL. Connect the
DDA
DDA
pin to the same voltage potential as the V pin.
DD
NOTE: Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
7.5.5 PLL Analog Ground Pin (V
)
SSA
V
is a ground pin used by the analog portions of the PLL. Connect
SSA
the V
pin to the same voltage potential as the V pin.
SSA
SS
NOTE: Route V
carefully for maximum noise immunity and place bypass
SSA
capacitors as close as possible to the package.
7.5.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)
OSCSTOPENB is a bit in the CONFIG register that enables the oscillator
to continue operating during stop mode. If this bit is set, the Oscillator
continues running during stop mode. If this bit is not set (default), the
oscillator is controlled by the SIMOSCEN signal which will disable the
oscillator during stop mode.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
123
7.5.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f ) and comes directly from the crystal oscillator circuit.
XCLK
Figure 7-2 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
7.5.9 CGMC Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGMC. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.
7.5.10 CGMC CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
7.6 CGMC Registers
These registers control and monitor operation of the CGMC:
• PLL control register (PCTL)
(See 7.6.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 7.6.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See 7.6.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See 7.6.4 PLL Multiplier Select Register Low.)
Advance Information
124
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• PLL VCO range select register (PMRS)
(See 7.6.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 7.6.6 PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr.
Register Name
Bit 7
PLLIE
0
6
5
PLLON
1
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PLLF
BCS
PRE1
PRE0
VPR1
VPR0
PLL Control Register
(PCTL)
$0036
0
0
0
0
0
0
0
0
0
0
LOCK
AUTO
ACQ
R
PLL Bandwidth Control
Register (PBWC)
$0037
$0038
0
0
0
0
0
0
0
0
0
MUL11
0
0
MUL10
0
0
MUL9
0
0
MUL8
0
PLL Multiplier Select High
Register (PMSH)
0
0
0
0
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
MUL2
0
MUL1
0
MUL0
0
PLL Multiplier Select Low
Register (PMSL)
$0039
VRS7
VRS6
VRS5
VRS4
VRS3
0
VRS2
0
VRS1
0
VRS0
0
PLL VCO Select Range
Register (PMRS)
$003A
$003B
NOTES:
0
0
1
0
0
0
0
0
RDS3
RDS2
0
RDS1
0
RDS0
1
PLL Reference Divider
Select Register (PMDS)
0
0
0
0
0
= Unimplemented
R
= Reserved
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
125
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
Address: $0036
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
PRE1
0
2
PRE0
0
1
VPR1
0
Bit 0
VPR0
0
Read:
Write:
Reset:
PLLF
0
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF always
reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control
register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Advance Information
126
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See 7.4.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGMC
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See 7.4.8
Base Clock Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE: PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See 7.4.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier, P. (See 7.4.3 PLL Circuits and 7.4.6
Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE: The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
127
Table 7-2. PRE 1 and PRE0 Programming
PRE1 and PRE0
P
0
1
2
3
Prescaler Multiplier
00
01
10
11
1
2
4
8
VPR1 and 0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range
multiplier E that, in conjunction with L (See 7.4.3 PLL Circuits, 7.4.6
Programming the PLL, and 7.6.5 PLL VCO Range Select Register.)
controls the hardware center-of-range frequency, f
. VPR1:VPR0
VRS
cannot be written when the PLLON bit is set. Reset clears these bits.
Table 7-3. VPR1 and VPR0 Programming
VCO Power-of-Two
Range Multiplier
VPR1 and VPR0
E
00
0
1
1
2
4
8
01
10
2
(1)
11
3
1. Do not program E to a value of 3.
7.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Address: $0037
Advance Information
128
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Bit 7
AUTO
0
6
5
ACQ
0
4
0
3
0
2
0
1
0
Bit 0
R
Read:
Write:
Reset:
LOCK
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 7-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. The write one function of this bit is
reserved for test, so this bit must always be written a 0. Reset clears
the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL
is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
129
7.6.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the
programming information for the high byte of the modulo feedback
divider.
Address: $0038
Bit 7
0
6
0
5
0
4
0
3
MUL11
0
2
MUL10
0
1
MUL9
0
Bit 0
MUL8
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback
divider that selects the VCO frequency multiplier N. (See 7.4.3 PLL
Circuits and 7.4.6 Programming the PLL.) A value of $0000 in the
multiplier select registers configures the modulo feedback divider the
same as a value of $0001. Reset initializes the registers to $0040 for
a default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as logic 0s.
Advance Information
130
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.6.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address: $0038
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
0
4
MUL4
0
3
MUL3
0
2
MUL2
0
1
MUL1
0
Bit 0
MUL0
0
Read:
Write:
Reset:
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See 7.4.3 PLL
Circuits and 7.4.6 Programming the PLL.) MUL7–MUL0 cannot be
written when the PLLON bit in the PCTL is set. A value of $0000 in the
multiplier select registers configures the modulo feedback divider the
same as a value of $0001. Reset initializes the register to $40 for a
default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
131
7.6.5 PLL VCO Range Select Register
NOTE: PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.
Address: $003A
Bit 7
VRS7
0
6
VRS6
1
5
VRS5
0
4
VRS4
0
3
VRS3
0
2
VRS2
0
1
VRS1
0
Bit 0
VRS0
0
Read:
Write:
Reset:
Figure 7-8. PLL VCO Range Select Register (PMRS)
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (See 7.4.3 PLL Circuits, 7.4.6
Programming the PLL, and 7.6.1 PLL Control Register.), controls
the hardware center-of-range frequency, f
. VRS7–VRS0 cannot
VRS
be written when the PLLON bit in the PCTL is set. (See 7.4.7 Special
Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control
register (PCTL). (See 7.4.8 Base Clock Selector Circuit and 7.4.7
Special Programming Exceptions.). Reset initializes the register to
$40 for a default range multiply value of 64.
NOTE: The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
Advance Information
132
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.6.6 PLL Reference Divider Select Register
NOTE: PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
Address: $003B
Bit 7
0
6
0
5
0
4
0
3
RDS3
0
2
RDS2
0
1
RDS1
0
Bit 0
RDS0
1
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 7-9. PLL Reference Divider Select Register (PMDS)
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See 7.4.3 PLL Circuits and 7.4.6
Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See 7.4.7 Special Programming Exceptions.) Reset initializes
the register to $01 for a default divide value of 1.
NOTE: The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE: The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
133
7.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
7.8 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby
modes.
7.8.1 Wait Mode
The WAIT instruction does not affect the CGMC. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL) to save power. Less
power-sensitive applications can disengage the PLL without turning it
off, so that the PLL clock is immediately available at WAIT exit. This
would be the case also when the PLL is to wake the MCU from wait
Advance Information
134
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
mode, such as when the PLL is first enabled and waiting for LOCK or
LOCK is lost.
7.8.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default),
then the STOP instruction disables the CGMC (oscillator and phase
locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.
7.8.3 CGMC During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 19.8.3 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
135
7.9 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
7.9.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5 percent acquisition time tolerance.
If a command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
Advance Information
136
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f
. This frequency is the input to the phase
RDV
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is under user control via the choice of crystal
frequency f
and the R value programmed in the reference divider.
XCLK
(See 7.4.3 PLL Circuits, 7.4.6 Programming the PLL, and 7.6.6 PLL
Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is
proportional to the capacitance. The size of the capacitor also is related
to the stability of the PLL. If the capacitor is too small, the PLL cannot
make small enough adjustments to the voltage and the system cannot
lock. If the capacitor is too large, the PLL may not be able to adjust the
voltage in a reasonable time. (See 7.9.3 Choosing a Filter.)
Also important is the operating voltage potential applied to V
. The
DDA
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
137
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
7.9.3 Choosing a Filter
As described in 7.9.2 Parametric Influences on Reaction Time, the
external filter network is critical to the stability and reaction time of the
PLL. The PLL is also dependent on reference frequency and supply
voltage.
Either of the filter networks in Figure 7-10 is recommended when using
a 32.768-kHz reference crystal. Figure 7-10 (a) is used for applications
requiring better stability. Figure 7-10 (b) is used in low-cost applications
where stability is not critical.
CGMXFC
CGMXFC
10 k
0.01 µF
0.47 µF
0.47 µF
VSSA
VSSA
(a)
(b)
Figure 7-10. PLL Filter
Advance Information
138
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 8. Configuration Register (CONFIG)
8.1 Contents
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
8.2 Introduction
This section describes the configuration registers, CONFIG1 and
CONFIG2. The configuration registers enable or disable these options:
• Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
18
4
13
4
• COP timeout period (2 – 2 or 2 – 2 CGMXCLK cycles)
• STOP instruction
• Computer operating properly module (COP)
• Low-voltage inhibit (LVI) module control and voltage trip point
selection
• Enable/disable the oscillator (OSC) during stop mode
8.3 Functional Description
The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001E and $001F. The configuration register
may be read at anytime.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
139
NOTE: On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by
the user only after each POR (power-on reset). The CONFIG registers
are not in the FLASH memory but are special registers containing one-
time writeable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in Figure 8-1 and
Figure 8-2.
Address: $001E
Bit 7
0
6
0
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
PMPSGV- OSC-
LVEN STOPENB
SCIBD-
SRC
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-1. Configuration Register 2 (CONFIG2)
Address: $001F
Bit 7
6
5
4
3
2
1
STOP
0
Bit 0
COPD
0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
Write:
Reset:
0
0
0
0
See Note
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 8-2. Configuration Register 1 (CONFIG1)
PMPSGVLVEN — FLASH Charge Pump Select Gate Voltage
Low-Voltage Enable Bit
PMPSGVLVEN enables low-voltage mode in the charge pump voltage
regulator circuit. Setting this bit turns the voltage regulator off to
conserve power (Recommended for voltage operation below 3.6 V
where voltage regulation is not needed). Clearing this bit turns the
regulator on (default setting) for operation above 3.6 V.
1 = Voltage regulator turned off (V < 3.6 V)
DD
0 = Voltage regulator turned on (V > 3.6 V) (default)
DD
Advance Information
140
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: For V > 3.6 V:
DD
The voltage regular must always be enabled. The charge pump must
have the voltage regulator on to provide the proper voltage to the
FLASH memory.
For V < 3.6 V:
DD
The voltage regulator may be disabled to conserve power. The charge
pump does not use the voltage regulator when V is less than 3.6 V,
DD
so the voltage regulator can be turned off.
Leaving the voltage regulator enabled will not cuase any harm. The
chip will merely consume more power than necessary.
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during
stop mode. Setting the OSCSTOPENB bit allows the oscillator to
operate continuously even during stop mode. This is useful for driving
the timebase module to allow it to generate periodic wakeup while in
stop mode. (See 3.6 Clock Generator Module (CGM) subsection
3.6.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 9. Computer Operating Properly (COP).)
13
4
1 = COP timeout period = 2 – 2 CGMXCLK cycles
18
4
0 = COP timeout period = 2 – 2 CGMXCLK cycles
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
141
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
3.6.2 Stop Mode.)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Section
14. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 14. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. (See
Section 14. Low-Voltage Inhibit (LVI).) The voltage mode selected
for the LVI should match the operating V . See Section 23.
DD
Preliminary Electrical Specifications for the LVI’s voltage trip points
for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
Advance Information
142
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a
delay longer than the enable time for the LVI. There is no period where
the MCU is not protected from a low power condition. However, when
using the short stop recovery configuration option, the 32-CGMXCLK
delay is less than the LVI’s turn-on time and there exists a period in
startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 9. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
143
Advance Information
144
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 9. Computer Operating Properly (COP)
9.1 Contents
9.1
9.2
9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .148
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.5
9.6
9.7
COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.8
9.8.1
9.8.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .150
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
145
9.2 Introduction
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG register.
9.3 Functional Description
Figure 9-1 shows the structure of the COP module.
RESET CIRCUIT
12-BIT COP PRESCALER
CGMXCLK
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SEL
(FROM CONFIG)
Figure 9-1. COP Block Diagram
Advance Information
146
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
18
4
13
4
and generates an asynchronous reset after 2 – 2 or 2 – 2
CGMXCLK cycles, depending on the state of the COP rate select bit,
13
4
COPRS, in the configuration register. With a 2 – 2 CGMXCLK cycle
overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V
. During the break state, V
on the RST pin disables the COP.
TST
TST
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
9.4 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1.
9.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
9.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
147
9.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 9.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
9.4.4 Power-On Reset
9.4.5 Internal Reset
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.
An internal reset clears the COP prescaler and the COP counter.
9.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
9.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. (See Section 8. Configuration Register
(CONFIG).)
9.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register. (See Section 8. Configuration Register
(CONFIG).)
Advance Information
148
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
9.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 9-2. COP Control Register (COPCTL)
9.6 Interrupts
The COP does not generate CPU interrupt requests.
9.7 Monitor Mode
When monitor mode is entered with V
on the IRQ pin, the COP is
TST
disabled as long as V
remains on the IRQ pin or the RST pin. When
TST
monitor mode is entered by having blank reset vectors and not having
on the IRQ pin, the COP is automatically disabled until a POR
V
TST
occurs.
9.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
149
9.8.1 Wait Mode
9.8.2 Stop Mode
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a
configuration option is available that disables the STOP instruction.
When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an
illegal opcode reset.
9.9 COP Module During Break Mode
The COP is disabled during a break interrupt when V
is present on
TST
the RST pin.
Advance Information
150
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 10. Central Processor Unit (CPU)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .158
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
10.6.1
10.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .159
10.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
10.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
151
10.3 Features
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
10.4 CPU Registers
Figure 10-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Advance Information
152
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
V
0
C
1
1
H
I
N
Z
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 10-1. CPU Registers
10.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 10-2. Accumulator (A)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
153
10.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 10-3. Index Register (H:X)
10.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Advance Information
154
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Bit
15
Bit
0
14 13 12 11 10
9
0
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
1
Read:
Write:
Reset:
0
0
0
0
0
0
1
Figure 10-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
10.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 10-5. Program Counter (PC)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
155
10.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
H
X
3
I
2
N
X
1
Z
X
Bit 0
C
Read:
Write:
Reset:
X
1
X
X = Indeterminate
Figure 10-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Advance Information
156
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
157
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
10.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
10.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
10.6.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
Advance Information
158
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
10.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
10.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
159
10.8 Instruction Set Summary
Table 10-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
2
3
4
4
3
2
4
5
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
FB
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
AND #opr
AND opr
IMM
DIR
EXT
IX2
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND
A ← (A) & (M)
0
–
–
–
↕ ↕ –
IX1
IX
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
58
↕ –
↕ –
↕ ↕ ↕
↕ ↕ ↕
C
0
68 ff
78
b7
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37 dd
47
4
1
1
4
3
5
57
C
Arithmetic Shift Right
–
–
67 ff
77
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
– REL
24 rr
3
Advance Information
160
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
3
3
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
IX2
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
IX1
IX
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
–
–
–
–
–
– REL
93 rr
3
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
3
3
3
3
3
3
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
161
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
26 rr
2A rr
20 rr
3
3
3
BPL rel
BRA rel
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↕
BRN rel
Branch Never
PC ← (PC) + 2
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
INH
5F
CLRH
Clear
0
–
–
0
1
– INH
IX1
IX
SP1
8C
CLR opr,X
CLR ,X
6F ff
7F
CLR opr,SP
9E6F ff
Advance Information
162
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
CMP #opr
IMM
DIR
EXT
IX2
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Compare A with M
(A) – (M)
↕ –
–
↕ ↕ ↕
IX1
IX
SP1
SP2
F1
CMP opr,SP
CMP opr,SP
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
4
1
1
4
3
5
COMX
53
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
↕ ↕ 1
COM opr,X
COM ,X
COM opr,SP
63 ff
73
9E63 ff
SP1
CPHX #opr
CPHX opr
IMM
DIR
65 ii ii+1
75 dd
3
4
(H:X) – (M:M + 1)
↕ –
↕ ↕ ↕
CPX #opr
CPX opr
IMM
DIR
EXT
IX2
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
CPX opr
CPX ,X
Compare X with M
(X) – (M)
↕ –
–
↕ ↕ ↕
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IX1
IX
SP1
SP2
F3
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
(A)10
U –
–
–
↕ ↕ ↕ INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
3B dd rr
4B rr
Decrement and Branch if Not Zero
–
–
–
–
– INH
IX1
5B rr
6B ff rr
7B rr
IX
SP1
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
3A dd
4A
4
1
1
4
3
5
DECX
5A
Decrement
Divide
↕ –
–
–
↕ ↕ –
DEC opr,X
DEC ,X
DEC opr,SP
IX1
IX
6A ff
7A
9E6A ff
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
0
–
–
–
↕ ↕ INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
Exclusive OR M with A
A ← (A ⊕ M)
–
↕ ↕ –
F8
9EE8 ff
9ED8 ee ff
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
163
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
INC opr
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
4
1
1
4
3
5
INCA
INCX
5C
Increment
Jump
↕ –
–
↕ ↕ –
INC opr,X
INC ,X
6C ff
7C
9E6C ff
INC opr,SP
SP1
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
IX2
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
IX1
IX
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45 ii jj
55 dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
LSL opr
LSLA
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
58
C
0
↕ –
↕ –
–
–
↕ ↕ ↕
LSL opr,X
LSL ,X
LSL opr,SP
68 ff
78
9E68 ff
b7
b0
SP1
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34 dd
44
4
1
1
4
3
5
54
0
C
Logical Shift Right
0 ↕ ↕
64 ff
74
b7
b0
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
MUL
Unsigned multiply
X:A ← (X) × (A)
–
–
0 INH
42
5
Advance Information
164
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
NEG opr
DIR
INH
INH
IX1
IX
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGA
NEGX
50
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
NEG opr,X
NEG ,X
60 ff
70
9E60 ff
NEG opr,SP
SP1
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
IX2
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
DIR
INH
INH
39 dd
49
4
1
1
4
3
5
ROLX
59
C
Rotate Left through Carry
Rotate Right through Carry
↕ –
↕ –
–
↕ ↕ ↕
↕ ↕ ↕
ROL opr,X
ROL ,X
ROL opr,SP
IX1
IX
69 ff
79
9E69 ff
b7
b0
SP1
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
DIR
INH
INH
IX1
IX
36 dd
46
4
1
1
4
3
5
56
C
–
–
66 ff
76
b7
b0
SP1
9E66 ff
RSP
RTI
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
– INH
9C
80
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
–
–
–
–
–
– INH
81
4
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
165
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
SBC #opr
IMM
DIR
EXT
IX2
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract with Carry
A ← (A) – (M) – (C)
↕ –
–
↕ ↕ ↕
IX1
IX
SP1
SP2
F2
SBC opr,SP
SBC opr,SP
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
F7
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
↕ ↕ – DIR
35 dd
8E
4
1
STOP
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
– INH
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
↕ ↕ – IX1
IX
SP1
SP2
FF
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
↕ ↕ ↕
IX1
Subtract
A ← (A) – (M)
↕ –
IX
SP1
SP2
F0
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
– INH
– INH
Transfer CCR to A
A ← (CCR)
Advance Information
166
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 10-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
TST opr
DIR
INH
INH
IX1
IX
3D dd
4D
3
1
1
3
2
4
TSTA
TSTX
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
↕ ↕ –
TST opr,X
TST ,X
6D ff
7D
9E6D ff
TST opr,SP
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
A
C
Accumulator
Carry/borrow bit
n
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD Direct to direct addressing mode
DIR Direct addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
Undefined
Overflow bit
Index register low byte
Zero bit
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
&
|
⊕
( )
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
IMD Immediate source to direct destination addressing mode
IMM Immediate addressing mode
INH Inherent addressing mode
IX
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
«
←
?
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
↕
—
Concatenated with
Set or cleared
Not affected
10.9 Opcode Map
See Table 10-2.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
167
Table 10-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
IX
RTI
INH
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
IX
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
3
BRN
REL 3 DIR
3
BHI
REL
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
3
BEQ
1
1
2
IX1 3 SP1
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2
1
1
1
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
CMP
EXT 3 IX2
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
4
4
4
4
4
4
4
4
4
4
4
4
SP2
5
CMP
SP2
5
SBC
SP2
5
CPX
SP2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
3
CMP
IX1
3
SBC
IX1
3
CPX
IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1
4
CMP
SP1
4
SBC
SP1
4
CPX
SP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
4
4
6
4
CBEQ
IX+
2
DAA
INH
3
COM
IX
3
LSR
IX
4
CPHX
DIR
3
ROR
IX
3
ASR
IX
3
LSL
IX
3
ROL
IX
3
DEC
IX
4
DBNZ
IX
3
INC
IX
4
2
3
4
2
CMP
IX
2
SBC
IX
2
CPX
IX
2
AND
IX
2
BIT
IX
2
LDA
IX
2
STA
IX
2
EOR
IX
2
ADC
IX
2
ORA
IX
2
ADD
IX
2
JMP
IX
4
JSR
IX
2
LDX
IX
2
STX
IX
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
RTS
BLT
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
IMM 3 IMM 3 IX1+
4
SP1
INH
REL 2 IMM 2 DIR
5
7
3
3
BGT
2
SBC
3
SBC
4
SBC
BRSET1 BSET1
MUL
INH
DIV
INH
NSA
3
DIR
5
2
DIR
4
1
1
1
2
2
3
2
2
2
2
2
INH
REL 2 IMM 2 DIR
3
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
2
CPX
3
CPX
4
CPX
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
SWI
BLE
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
4
LSR
1
LSRA
INH
1
LSRX
INH
5
LSR
SP1
2
2
2
AND
IMM 2 DIR
2
BIT
IMM 2 DIR
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
3
AND
4
AND
5
3
4
4
BRSET2 BSET2
TAP
TXS
AND
AND
AND
3
DIR
5
2
DIR
4
1
3
1
INH
INH
2
2
2
2
2
2
2
2
SP2
IX1
SP1
4
3
4
1
2
3
BIT
4
BIT
5
BIT
SP2
5
LDA
SP2
5
STA
SP2
5
EOR
3
BIT
IX1
3
LDA
IX1
4
BIT
SP1
4
LDA
SP1
4
STA
SP1
4
EOR
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
TPA
TSX
3
DIR
5
2
DIR
4
IMM 2 DIR
INH
INH
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
3
LDA
4
LDA
6
BRSET3 BSET3
RORA
RORX
ROR
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
SP1
5
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
1
3
STA
4
STA
3
7
BRCLR3 BCLR3
ASR
TAX
STA
3
DIR
5
2
DIR
4
REL 2 DIR
3
1
1
1
1
1
1
1
1
SP1
5
1
1
1
1
1
1
1
INH
IX1
4
LSL
1
CLC
INH
1
3
EOR
4
EOR
3
EOR
8
BRSET4 BSET4 BHCC
LSL
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
SP1
5
SP2
5
ADC
SP2
IX1
3
SP1
4
ADC
SP1
4
ROL
3
ADC
4
ADC
9
BRCLR4 BCLR4 BHCS
ROL
SEC
INH
2
CLI
INH
2
SEI
INH
1
RSP
INH
ADC
IX1
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
3
BMC
REL 2 DIR
3
BMS
REL 2 DIR
3
BIL
SP1
5
4
DEC
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
ORA
4
ORA
5
3
4
A
B
C
D
E
F
BRSET5 BSET5
DEC
ORA
ORA
ORA
3
DIR
5
2
DIR
4
SP1
6
SP2
IX1
SP1
5
3
3
5
3
ADD
4
ADD
5
3
ADD
IX1
3
JMP
IX1
4
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
ADD
ADD
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
INC
IX1
3
TST
IX1
4
MOV
IMD
3
CLR
IX1
SP1
5
SP2
SP1
4
INC
2
JMP
DIR
4
JSR
4
JMP
BRSET6 BSET6
INCA
INCX
INC
3
DIR
5
2
DIR
4
INH
1
TSTA
INH
5
MOV
DD
1
CLRA
INH
INH
1
TSTX
INH
4
MOV
DIX+
1
CLRX
INH
SP1
4
2
3
TST
2
TST
IX
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
5
JSR
BRCLR6 BCLR6
TST
SP1
NOP
3
DIR
5
2
DIR
4
INH
2
2
2
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
IX1
3
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
4
BRSET7 BSET7
MOV
IX+D
LDX
LDX
IX1
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
BIH
1
1
4
4
SP2
3
3
SP1
3
CLR
4
2
CLR
IX
3
STX
4
STX
5
STX
SP2
3
4
STX
SP1
BRCLR7 BCLR7
DIR DIR
CLR
SP1
STX
3
2
REL 2 DIR
3
1
IX1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
Advance Information — MC68HC908GP20
Section 11. FLASH Memory
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
11.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
11.5.1
11.5.2
FLASH Charge Pump Frequency Control. . . . . . . . . . . . .173
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
11.6 FLASH Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
11.7 FLASH Program/Margin Read Operation. . . . . . . . . . . . . . . .177
11.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . .181
11.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
11.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program, erase, and read operations are enabled
through the use of an internal charge pump.
11.3 Functional Description
The FLASH memory is an array of 19,968 bytes with an additional 36
bytes of user vectors and one byte of block protection. An erased bit
reads as logic 0 and a programmed bit reads as a logic 1. Program and
erase operations are facilitated through control bits in a memory mapped
register. Details for these operations appear later in this section. Memory
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
169
in the FLASH array is organized into pages within rows. There are eight
pages of memory per row with eight bytes per page. The minimum erase
block size is a single row, 64 bytes. Programming is performed on a per
page basis; eight bytes at a time. The address ranges for the user
memory and vectors are:
• $B000–$FDFF; user memory
• $FF80; block protect register
• $FE08; FLASH control register
• $FFDC–$FFFF; These locations are reserved for user-defined
interrupt and reset vectors.
When programming the FLASH, just enough program time must be used
to program a page. Too much program time can result in a program
disturb condition, in which case an erased bit on the row being
programmed becomes unintentionally programmed. Program disturb is
avoided by using an iterative program and margin read technique known
as the smart page programming algorithm. The smart programming
algorithm is required whenever programming the array (see 11.7 FLASH
Program/Margin Read Operation).
To avoid the program disturb issue, each row should not be programmed
more than eight times before it is erased. The eight program cycle
maximum per row aligns with the architecture’s eight pages of storage
per row. The margin read step of the smart programming algorithm is
used to ensure programmed bits are programmed to sufficient margin for
data retention over the device lifetime.
Row architecture for this array is:
• $B000-$B03F; row0
• $B040-$B07F; row1
• $B080-$B0BF; row2
• ----------------------------
• $FFC0-$FFFF; row 319
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
Advance Information
170
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
1
NOTE: A security feature prevents viewing of the FLASH contents.
11.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program, erase,
and margin read operations.
Address: $FE08
Bit 7
FDIV1
0
6
FDIV0
0
5
BLK1
0
4
BLK0
0
3
HVEN
0
2
1
Bit 0
PGM
0
Read:
Write:
Reset:
MARGIN ERASE
0
0
Figure 11-1. FLASH Control Register (FLCR)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
BLK1— Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
171
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for
program/margin read or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MARGIN — Margin Read Control Bit
This read/write bit configures the memory for margin read operation.
MARGIN cannot be set if the HVEN = 1. MARGIN will return to unset
automatically if asserted when HVEN is set.
1 = Margin read operation selected
0 = Margin read operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE
is interlocked with the PGM bit such that both bits cannot be equal to
1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM
is interlocked with the ERASE bit such that both bits cannot be equal
to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
Advance Information
172
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
11.5 Charge Pump
The internal FLASH charge pump is an analog circuit that provides the
proper voltage to the FLASH memory when reading, programming, and
erasing the memory arrays.
11.5.1 FLASH Charge Pump Frequency Control
The internal charge pump required for program, margin read, and erase
operations is designed to operate most efficiently with a 2 MHz clock.
The charge pump clock is derived from the bus clock. Table 11-1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program and erase operations cannot be
performed if the bus clock frequency is below 2 MHz.
.
Table 11-1. Charge Pump Clock Frequency
FDIV1
FDIV0
Pump Clock Frequency
Bus frequency ÷ 1
Bus frequency ÷ 2
Bus frequency ÷ 2
Bus frequency ÷ 4
Bus Clock Frequency
1.8 to 2.5 MHz
0
0
1
1
0
1
0
1
3.6 to 5.0 MHz
3.6 to 5.0 MHz
7.2 to 10.0 MHz
11.5.2 Voltage Regulator
The PMPSGVLVEN bit in the configuration register (CONFIG) enables
or disables the voltage regulator in the internal charge pump. For V
DD
greater than 3.6 V, the supply regulator must be enabled at all times for
the charge pump to supply the proper voltage to the FLASH memory.
For V less than 3.6 V, the voltage regulator may be disabled to
DD
conserve power. The charge pump no longer needs the voltage
regulator and can supply the proper voltage to the FLASH memory
without it. Leaving the voltage regulator enabled will not cause any harm.
The chip will merely consume more power than necessary. See
Section 8. Configuration Register (CONFIG).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
173
11.6 FLASH Erase Operation
Use this step-by-step procedure to erase a block of FLASH memory to
read as logic 0:
1. If operating voltage is below 3.6 V, set the PMPSGVLVEN bit in
the CONFIG2 register. (See 8.3 Functional Description.)
2. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the
FLASH control register. See Table 11-1 for FDIV settings. See
Table 11-2 for block sizes.
3. To ensure target portion of array is unprotected, read the FLASH
block protect register. (See 11.8 FLASH Block Protection.)
4. Write to any FLASH address with any data within the block
address range desired.
5. Set the HVEN bit.
6. Wait for a time, t
.
Erase
7. Clear the HVEN bit.
8. Wait for a time, t , for the high voltages to dissipate.
Kill
9. Clear the ERASE bit.
10. After a time, t
mode.
, the memory can be accessed again in read
HVD
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Do not exceed t
maximum.
Erase
Table 11-2 shows the various block sizes which can be erased in one
erase operation. A write to a particular address will erase varying block
sizes. The first column of the table shows a particular address bit and
the second column shows the address value of that bit which will select
a particular desired erase address array (fifth column) when selected
with the appropriate BLK1 (third column) and BLK0 (fourth column) bits.
The corresponding array size that will be erased is shown in the last
column of the table as well as the critical address bits which are affected.
Advance Information
174
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 11-2. Erase Block Sizes
Write to
Address
Bit
Array Size
(Critical
Address Bits)
Address
Value
BLK1 BLK0
Desired Erase Address Range
Any
FLASH
address
Full array: 20 KBytes
(A14–A0,
Any FLASH Address)
Any
0
0
$B000–$FDFF and $FFDC–$FFFF
4/5 array: 16 Kbytes
(A14 = 1)
A14
A14
1
0
0
0
1
1
$C000–$FDFF and $FFDC–$FFFF
$B000–$BFFF
1/5 array: 4 Kbytes
(A14 = 0)
Address range determined by value
of A15–A10, while A9 = 1:
$<A15–A12><A11,A10,10><0000><0000>
–$<A15–A12><A11,A10,11><1111><1111>
Eight rows:
512 bytes
(A14–A9, A9 = 1)
A9
A9
A6
A6
1
0
1
0
1
1
1
1
0
0
1
1
Address range determined by value
of A15–A10, while A9 = 0:
$<A15–A12><A11,A10,00><0000><0000>
–$<A15–A12><A11,A10,01><1111><1111>
Eight rows:
512 bytes
(A14–A9, A9 = 0)
Address range determined by value
of A15–A7, while A6 = 1:
$<A15–A12><A11:A8><A7,100><0000>
–$<A15–A12><A11:A8><A7,111><1111>
Single row: 64 bytes
(A14–A6, A6 = 1)
Address range determined by value
of A15–A7, while A6 = 0:
$<A15–A12><A11:A8><A7,000><0000>
–$<A15–A12><A11:A8><A7,011><1111>
Single row: 64 bytes
(A14–A6, A6 = 0)
In step 4 of the erase operation, the desired erase addresses are latched
and used to determine the location of the block to be erased. For the full
array (BLK1 = BLK0 = 0), the only requirement is that the FLASH
memory be selected. Writing to any address in the range $B000 to
$FDFF or the vectors in the address range $FFDC to $FFFF will enable
the full array erase. This case is shown in Table 11-2.
In the 4/5 array case in Table 11-2 (A14 = 1, BLK1 = 0, BLK0 = 1), the
state of A14 = 1 determines that the range from $C000 to $FDFF and
$FFDC to $FFFF is erased. For example, writing to address $D123
(A14 = 1, BLK1 = 0, BLK0 = 1) will erase the range $C000 to $FDFF and
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
175
$FFDC to $FFFF. This block erase can also be accomplished by writing
to any FLASH address in which A14 = 1 while BLK1 = 0 and BLK0 = 1.
In the 1/5 array case (A14 = 0, BLK1 = 0, BLK0 = 1) the state of
A14 = 0 determines that the range from $B000 to $BFFF is erased. For
example, writing to address $B123 (A14 = 0, BLK1 = 0, BLK0 = 1) will
erase the range $B000 to $BFFF. This block erase can also be
accomplished by writing to any FLASH address in which A14 = 0 while
BLK1 = 0 and BLK0 = 1.
In the 8 row case (A9 = 1, BLK1 = 1, BLK0 = 0), the state of A9=1
determines that the range from
$<A15:A12><A11,A10,10><0000><0000> to
$<A15:A12><A11,A10,11><1111><1111> is erased. Address bits
A15–A10 indicate arbitrary address bit values defined in the desired
erase address range while the remaining lower bits A9–A0 are fixed as
shown. For example, writing to address $FB10 (1111 1011 0001 0000
binary) (A9 = 1, BLK1 = 1, BLK0 = 0) will erase the range $FA00
(1111 1010 0000 0000 binary) to $FBFF (1111 1011 1111 1111 binary).
In the other 8 row case (A9 = 0, BLK1 = 1, BLK0 = 0), the state of
A9 = 0 determines that the range from
$<A15:A12><A11,A10,00><0000><0000> to
$<A15:A12><A11,A10,01><1111><1111> is erased. Address bits
A15–A10 indicate arbitrary address bit values defined in the desired
erase address range while the remaining lower bits A9–A0 are fixed as
shown. For example, writing to address $FD10 (1111 1101 0001 0000
binary) (A9 = 0, BLK1 = 1, BLK0 = 0) will erase the range $FC00 (1111
1100 0000 0000 binary) to $FDFF (1111 1101 1111 1111 binary).
In the single row case (A6 = 1, BLK1 = 1, BLK0 = 1), the state of
A6 = 1 determines that the range from
$<A15:A12><A11:A8><A7,100><0000> to
$<A15:A12><A11:A8><A7,111><1111> is erased. Address bits
A15–A7 indicate arbitrary address bit values defined in the desired erase
address range while the remaining lower bits A6–A0 are fixed as shown.
For example, writing to address $BC60 (1011 1100 0110 0000 binary)
(A6 = 1, BLK1 = 1, BLK0 = 1) will erase the range $BC40 (1011 1100
0100 0000 binary) to $BC7F (1011 1100 0111 1111 binary).
Advance Information
176
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
In the other “single row case” (A6 = 0, BLK1 = 1, BLK0 = 1), the state of
A6 = 0 determines that the range from
$<A15:A12><A11:A8><A7,000><0000> to
$<A15:A12><A11:A8><A7,011><1111> is erased. Address bits
A15–A7 indicate arbitrary address bit values defined in the desired erase
address range while the remaining lower bits A6–A0 are fixed as shown.
For example, writing to address $BC87 (1011 1100 1000 0111 binary)
(A6 = 0, BLK1 = 1, BLK0 = 1) will erase the range $BC80 (1011 1100
1000 0000 binary) to $BCBF (1011 1100 1011 1111 binary).
11.7 FLASH Program/Margin Read Operation
NOTE: After a total of eight program operations have been applied to a row, the
row must be erased before further programming to avoid program
disturb. An erased byte will read $00.
Programming of the FLASH memory is done on a page basis. A page
consists of eight consecutive bytes starting from address $XXX0 or
$XXX8. The purpose of the margin read mode is to ensure that data has
been programmed with sufficient margin for long-term data retention.
During margin read, the control gates of the selected memory bits are
held at a slightly negative voltage by an internal charge pump. While
performing a margin read, the operation is the same as for ordinary read
mode except that a built-in counter stretches the data access for an
additional eight cycles to allow sensing of the lower cell current. Margin
read mode imposes a more stringent read condition on the bitcell to
ensure the bitcell is programmed with enough margin for long-term data
retention. During these eight cycles the COP counter continues to run.
The user must account for these extra cycles within COP feed loops. A
margin read cycle can only follow a program operation.
NOTE: To overwrite a memory location, it must first be erased to 0s then
programmed to the new value. For instance, if a location previously has
been programmed to $AA (1010 1010 binary) and the value should be
changed to $55 (0101 0101 binary), it is necessary to erase $AA to $00
FIRST before programming to $55. If the erase operation in this
example is not performed and $AA is simply re-programmed to $55, then
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
177
the location will be read as $FF (1111 1111 binary). (0s cannot be
programmed. 0s only result from the erase operation.)
To program and margin read the FLASH memory, use this procedure:
1. If operating voltage is below 3.6 V, set the PMPSGVLVEN bit in
the CONFIG2 register. (See 8.3 Functional Description.)
2. Set the PGM, FDIV1, and FDIV0 bits in the FLASH control
register. This configures the memory for program operation and
enables the latching of address and data for programming.
3. Read from the FLASH block protect register.
4. Write data to the eight bytes of the page being programmed. This
requires eight separate write operations.
5. Set the HVEN bit.
6. Wait for a time, t
.
PROG
7. Clear the HVEN bit.
8. Wait for a time, t
.
HVTV
9. Set the MARGIN bit.
10. Wait for a time, t
.
VTP
11. Clear the PGM bit.
12. Wait for a time, t
.
HVD
13. Read back data in margin read mode. This is done in eight
separate read operations which are each stretched by eight
cycles.
14. Clear the MARGIN bit.
15. Repeat steps 2 through 14 for each page until the data verifies.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
This program/margin read sequence is repeated throughout the memory
until all data is programmed. For minimum overall programming time and
least program disturb effect, the smart programming algorithm in Figure
11-2 should be followed.
Advance Information
178
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Smart Programming Algorithm
PROGRAM FLASH
Page Program/Margin Read Procedure
Note: This algorithm is mandatory for programming the FLASH.
INITIALIZE ATTEMPT
COUNTER TO 0
Note: This page program algorithm assumes the page/s
to be programmed are initially erased.
SET PGM BIT AND FDIV BITS
READ FLASH BLOCK
PROTECT REGISTER
WRITE DATA TO SELECTED PAGE
SET HVEN BIT
WAIT tPROG
CLEAR HVEN BIT
WAIT tHVTV
SET MARGIN BIT
WAIT tVTP
CLEAR PGM BIT
WAIT tHVD
MARGIN READ PAGE OF DATA
CLEAR MARGIN BIT
INCREMENT ATTEMPT COUNTER
N
N
ATTEMPT COUNT
MARGIN READ DATA
EQUAL TO
EQUAL TO
FLSPULSES?
WRITE DATA?
Y
Y
PROGRAMMING OPERATION
FAILED
PROGRAMMING OPERATION
COMPLETE
Figure 11-2. Smart Programming Algorithm
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
179
11.8 FLASH Block Protection
NOTE: In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by reserving a location in the
memory for block protect information and requiring that this location be
read to enable setting of the HVEN bit. When the block protect register
is read, its contents are latched by the FLASH control logic. If the
address range for an erase or program operation includes a protected
block, the PGM or ERASE bit is cleared which prevents the HVEN bit in
the FLASH control register from being set so that no high voltage is
allowed in the array.
When the block protect register is erased (all 0s), the entire memory is
accessible for program and erase. When bits within the register are
programmed, they lock blocks of memory address ranges as shown in
11.9 FLASH Block Protect Register. The block protect register itself
can be erased or programmed only with an external voltage, V
,
TST
present on the IRQ pin. This voltage also allows entry from reset into the
monitor mode.
Advance Information
180
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
11.9 FLASH Block Protect Register
The block protect register (FLBPR) is implemented as a byte within the
FLASH memory. Each bit, when programmed, protects a range of
addresses in the FLASH.
Address: $FF80
Bit 7
Bit 7
U
6
Bit 6
U
5
Bit 5
U
4
Bit 4
U
3
BPR3
U
2
BPR2
U
1
BPR1
U
Bit 0
BPR0
U
Read:
Write:
Reset:
U = Unaffected by reset. Initial value from factory is 0.
Figure 11-3. FLASH Block Protect Register (FLBPR)
BPR3 — Block Protect Register Bit 3
This bit protects the memory contents in the address range $C000 to
$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block Protect Register Bit 2
In a larger memory, this bit would protect the memory contents in the
address range $A000 to $FFFF. It is redundant in this implementation.
Setting this bit locks everything from $B000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block Protect Register Bit 1
In a larger memory, this bit would protect the memory contents in the
address range $9000 to $FFFF. It is redundant in this implementation.
Setting this bit locks everything from $B000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
181
BPR0 — Block Protect Register Bit 0
In a larger memory, this bit would protect the memory contents in the
address range $8000 to $FFFF. It is redundant in this implementation.
Setting this bit locks everything from $B000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
Bit 7, Bit 6, Bit 5, and Bit 4
These bits do not affect FLASH block protection. They are extra bits
that can be used by the user as readable/writeable bits.
1 = Bit is set
0 = Bit is cleared
By programming the block protect bits, a portion of the memory will be
locked so that no further erase or program operations may be
performed. Programming more than one bit at a time is redundant. If
both BPR3 and BPR2 are set, for instance, the address range $B000
through $FFFF is locked. If all bits are erased, then all of the memory is
available for erase and program. The presence of a voltage V
on the
TST
IRQ pin will bypass the block protection so that all of the memory,
including the block protect register, is open for program and erase
operations.
11.10 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. When the MCU is put into
wait mode, the charge pump for the FLASH is disabled so that either a
program or erase operation will not continue. If the memory is in either
program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1,
HVEN = 1), then it will remain in that mode during wait. Exit from wait
must now be done with a reset rather than an interrupt because if exiting
wait with an interrupt, the memory will not be in read mode and the
interrupt vector cannot be read from the memory.
Advance Information
182
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
11.11 Stop Mode
When the MCU is put into stop mode, if the FLASH is in read mode, it
will be put into low-power standby. Exit from stop is possible with an
external interrupt, such as IRQ, keyboard interrupt, or reset.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH. When the MCU is put into
stop mode, the charge pump for the FLASH is disabled so that either a
program or erase operation will not continue. If the memory is in either
program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1,
HEVEN = 1), then it will remain in that mode during stop. In this case,
exit from stop must be done with a reset rather than an interrupt because
if exiting stop with an interrupt, the memory will not be in read mode and
the interrupt vector cannot be read from the memory.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
183
Advance Information
184
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 12. External Interrupt (IRQ)
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
12.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
12.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .189
12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .189
12.2 Introduction
12.3 Features
The IRQ (external interrupt) module provides a maskable interrupt input.
Features of the IRQ module include:
• A dedicated external interrupt pin (IRQ)
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup resistor
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
185
12.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 12-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (INTSCR). Writing a logic 1 to the ACK bit clears
the IRQ latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level-
triggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt remains set
until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
Advance Information
186
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
ACK
RESET
TO CPU FOR
VECTOR
BIL/BIH
FETCH
INSTRUCTIONS
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
IRQ
CK
IRQ
FF
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
0
1
IMASK
0
Bit 0
Read:
Write:
Reset:
0
0
0
0
IRQF
MODE
0
IRQ Status and Control
Register (INTSCR)
$001D
ACK
0
0
0
0
0
0
= Unimplemented
Figure 12-2. IRQ I/O Register Summary
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
187
12.5 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-
level-sensitive. With MODE set, both of the following actions must occur
to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ pin. A falling edge that occurs after writing
to the ACK bit another interrupt request. If the IRQ mask bit,
IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
Advance Information
188
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
12.6 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Section 6. Break
Module (BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
12.7 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
189
Address: $001D
Bit 7
Read:
6
0
5
0
4
0
3
2
0
1
IMASK
0
Bit 0
MODE
0
IRQF
Write:
ACK
0
Reset:
0
0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Advance Information
190
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 13. Keyboard Interrupt Module (KBI)
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
13.6.1
13.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .196
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
13.8.1
13.8.2
Keyboard Status and Control Register . . . . . . . . . . . . . . .197
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .198
13.2 Introduction
The keyboard interrupt module (KBI) provides eight independently
maskable external interrupts.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
191
13.3 Features
• Eight keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask
• Hysteresis buffers
• Programmable edge-only or edge- and level- interrupt sensitivity
• Exit from low-power modes
• I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)
13.4 Functional Description
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port A pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin also enables its internal
pullup device. A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low-level sensitive, an
interrupt request is present as long as any keyboard interrupt pin
is low and the pin is keyboard interrupt enabled.
Advance Information
192
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
INTERNAL BUS
VECTOR FETCH
DECODER
KBD0
ACKK
VDD
KEYF
RESET
CLR
.
.
.
D
Q
TO PULLUP ENABLE
SYNCHRONIZER
CK
KB0IE
KEYBOARD
INTERRUPT
REQUEST
KEYBOARD
INTERRUPT FF
IMASKK
KBD7
MODEK
TO PULLUP ENABLE
KB7IE
Figure 13-1. Keyboard Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status
IMASKK MODEK
$001A
and Control Register Write:
(INTKBSCR)
Reset:
0
KBIE7
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Read:
KBIE2
0
Keyboard Interrupt Enable
$001B
Write:
Register (INTKBIER)
Reset:
= Unimplemented
Figure 13-2. I/O Register Summary
If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low-level sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (INTKBSCR). The ACKK bit is useful in applications that
poll the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFE0 and
$FFE1.
• Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
Advance Information
194
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
13.5 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
13.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
195
13.6.1 Wait Mode
13.6.2 Stop Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
13.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear status
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect. (See 13.8.1 Keyboard Status and
Control Register.)
Advance Information
196
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
13.8 I/O Registers
These registers control and monitor operation of the keyboard module:
• Keyboard status and control register (INTKBSCR)
• Keyboard interrupt enable register (INTKBIER)
13.8.1 Keyboard Status and Control Register
The keyboard status and control register:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
KEYF
0
ACKK
0
IMASKK MODEK
0
0
0
0
0
0
0
= Unimplemented
Figure 13-3. Keyboard Status and Control Register (INTKBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
197
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
13.8.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A
pin to operate as a keyboard interrupt pin.
Address: $001B
Bit 7
KBIE7
0
6
KBIE6
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin
Advance Information
198
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 14. Low-Voltage Inhibit (LVI)
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
14.4.1
14.4.2
14.4.3
14.4.4
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . .202
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .202
LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
14.7.1
14.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
14.2 Introduction
14.3 Features
This section describes the low-voltage inhibit (LVI) module, which
monitors the voltage on the V pin and can force a reset when the V
DD
DD
voltage falls below the LVI trip falling voltage, V
.
TRIPF
Features of the LVI module include:
• Programmable LVI reset
• Selectable LVI trip voltage
• Programmable stop mode operation
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
199
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V voltage. Clearing the LVI reset disable bit, LVIRSTD,
DD
enables the LVI module to generate a reset when V falls below a
DD
voltage, V
. Setting the LVI enable in stop mode bit, LVISTOP,
TRIPF
enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip
point bit, LVI5OR3, enables the trip point voltage,V , to be
TRIPF
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip
point voltage, V , to be configured for 3-V operation. The actual trip
TRIPF
points are shown in Section 23. Preliminary Electrical Specifications.
NOTE: After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5-V system is used, the user must set the LVI5OR3 bit to raise the
trip point to 5-V operation. Note that this must be done after every power-
on reset since the default will revert back to 3-V mode after each power-
on reset. If the V supply is below the 5-V mode trip voltage but above
DD
the 3-V mode trip voltage when POR is released, the part will operate
because V
defaults to 3-V mode after a POR. So, in a 5-V system
TRIPF
care must be taken to ensure that V is above the 5-V mode trip voltage
DD
after POR is released.
NOTE: If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the V supply is not above the V
for 5-V mode, the
DD
TRIPR
MCU will immediately go into reset. The LVI in this case will hold the part
in reset until either V goes above the rising 5-V trip point, V
,
TRIPR
DD
which will release reset or V decreases to approximately 0 V which will
DD
re-trigger the power-on reset and reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (MOR1). See 8.3 Functional Description for details of the LVI’s
configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V rises above a voltage, V
, which causes the MCU to exit
DD
TRIPR
reset. See 19.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of the
interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
Advance Information
200
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
VDD > LVITrip = 0
DD ≤ LVITrip = 1
LVI RESET
LOW VDD
DETECTOR
V
LVIOUT
LVI5OR3
FROM CONFIG
Figure 14-1. LVI Module Block Diagram
Addr.
Register Name
Bit 7
Read: LVIOUT
Write:
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LVI Status Register
(LVISR)
$FE0C
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
14.4.1 Polled LVI Operation
In applications that can operate at V levels below the V
level,
DD
TRIPF
software can monitor V by polling the LVIOUT bit. In the configuration
DD
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
201
14.4.2 Forced Reset Operation
In applications that require V to remain above the V
level,
TRIPF
DD
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls below the V
level. In the configuration register, the LVIPWRD
TRIPF
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
14.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V fall below V
), the LVI
TRIPF
DD
will maintain a reset condition until V rises above the rising trip point
DD
voltage, V
. This prevents a condition in which the MCU is
TRIPR
continually entering and exiting reset if V is approximately equal to
DD
V
. V
is greater than V
by the hysteresis voltage, V
.
TRIPF
TRIPR
TRIPF
HYS
14.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5-V or 3-V protection.
NOTE: The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (V
[5 V] or V
[3 V]) may be lower than
TRIPF
TRIPF
this. (See Section 23. Preliminary Electrical Specifications for the
actual trip point voltages.)
Advance Information
202
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
14.5 LVI Status Register
The LVI status register (LVISR) indicates if the V voltage was
DD
detected below the V
level.
TRIPF
Address: $FE0C
Bit 7
Read: LVIOUT
Write:
6
0
5
4
0
3
0
2
0
1
0
Bit 0
0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V voltage falls below the
DD
V
trip voltage. (See Table 14-1.) Reset clears the LVIOUT bit.
TRIPF
Table 14-1. LVIOUT Bit Indication
V
LVIOUT
DD
V
> V
0
DD
TRIPR
TRIPF
V
< V
1
DD
V
< V < V
TRIPR
Previous value
TRIPF
DD
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
203
14.6 LVI Interrupts
The LVI module does not generate interrupt requests.
14.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
14.7.1 Wait Mode
14.7.2 Stop Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.
If enabled in stop mode (LVISTOP set), the LVI module remains active
in stop mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of stop mode.
Advance Information
204
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 15. Monitor ROM (MON)
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
15.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode
entry methods. The monitor ROM allows complete testing of the MCU
through a single-wire interface with a host computer. Monitor mode entry
can be achieved without use of the higher test voltage, V
, as long as
TST
vector addresses $FFFE and $FFFF are blank, thus reducing the
hardware requirements for in-circuit programming.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
205
15.3 Features
Features of the monitor ROM include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM
and host computer
• Standard mark/space non-return-to-zero (NRZ) communication
with host computer
• Execution of code in RAM or FLASH
1
• FLASH memory security feature
• FLASH memory programming interface
• Enhanced PLL (phase-locked loop) option to allow use of external
32.768-kHz crystal to generate internal frequency of 2.4576 MHz
• 307 bytes monitor ROM code size ($FE20 to $FF52)
• Monitor mode entry without high voltage, V
blank ($FFFE and $FFFF contain $00)
, if reset vector is
TST
• Standard monitor mode entry if high voltage, V
IRQ
, is applied to
TST
15.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 15-1 shows an example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute code downloaded into RAM by a host
computer while most MCU pins retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Advance Information
206
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
68HC08
RST
0.1 µF
V
TST
RESET VECTORS
$FFFE
(SEE NOTE 3)
10 kΩ
$FFFF
(SEE NOTES 2
AND 3)
C
SW2
IRQ
C
D
V
DDA
V
DDA
CGMXFC
10 k
0.47 µF
SW3
(SEE NOTE 2)
C
C
OSC1
6–30 pF
1
20
MC145407
D
+
+
+
+
OSC2
PTA7
10
10
µ
F
F
10 µF
SW4
(SEE NOTE 2)
3
4
18
17
V
V
V
SS
32.768 kHz XTAL
V
/V
SSAD REFL
330 k
Ω
D
SSA
6–30 pF
DD
10 µF
µ
2
19
DB-25
2
V
5
6
16
15
DD
V
3
7
DD
V
/V
DDAD REFH
0.1 µF
V
DD
V
DD
1
2
6
4
14
3
MC74HC125
10 k
Ω
PTA0
PTC3
5
V
DD
V
DD
7
A
PTC0
PTC1
SW1
(SEE NOTE 1)
B
Notes:
1. For monitor mode entry when IRQ = VTST
:
SW1: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
SW1: Position B — Bus clock = CGMXCLK ÷ 2
2. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator.
SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL.
3. See Table 15-1 for IRQ voltage level requirements.
Figure 15-1. Monitor Mode Circuit
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
207
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the
monitor code to allow enabling the PLL to generate the internal clock,
provided the reset vector is blank, when the device is being clocked by
a low-frequency crystal. This addition, which is enabled when IRQ is
held low out of rest, is intended to support serial communication/
programming at 9600 baud in monitor mode by stepping up the external
frequency (assumed to be 32.768 kHz) by a fixed amount to generate
the desired internal frequency (2.4576 MHz). Since this feature is
enabled only when IRQ is held low out of reset, it cannot be used when
the reset vector is non-zero because entry into monitor mode in this case
requires V
on IRQ.
TST
15.4.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If $FFFE and $FFFF contain non-zero values:
– The external clock is 4.9152 MHz with PTC3 low or
9.8304 MHz with PTC3 high
– IRQ = V
(PLL off)
TST
2. If $FFFE and $FFFF contain zero values:
– The external clock is 9.8304 MHz
– IRQ = V (this can be implemented through the internal IRQ
DD
pullup; PLL off)
3. If $FFFE and $FFFF contain zero values:
– The external clock is 32.768 kHz (crystal)
– IRQ = V (this setting initiates the PLL to boost the external
SS
32.768 kHz to an internal bus frequency of 2.4576 MHz)
If V
is applied to IRQ and PTC3 is low upon monitor mode entry
TST
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC3 is high with V applied to IRQ upon monitor mode entry,
TST
the bus frequency will be a divide-by-four of the input clock. Holding the
Advance Information
208
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 15-1. Monitor Mode Signal Requirements and Options
For Serial
Communication
External
Clock(1)
$FFFE/
$FFFF
Bus
Frequency
IRQ
RESET
PLL PTC0 PTC1 PTC3
CGMOUT
COP
Comment
Baud
PTA0 PTA7
Rate(2) (3)
X
GND
X
X
X
X
1
X
0
X
0
X
0
0
Disabled
Disabled
X
X
0
No operation until
reset goes high
VTST
VDD
or
VTST
OFF
4.9152
MHz
4.9152
MHz
2.4576
MHz
1
0
1
9600
DNA
PTC0 and PTC
voltages only
required if
X
IRQ = VTST
;
PTC3 determines
frequency divider
VTST
VDD
or
VTST
X
OFF
1
0
1
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
0
1
9600
DNA
PTC0 and PTC1
voltages only
required if
X
IRQ = VTST
;
PTC3 determines
frequency divider
VDD
VDD
$0000
$0000
OFF
ON
X
X
X
X
X
X
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
Disabled
1
X
1
0
1
0
1
9600
DNA
9600
DNA
External frequency
always divided by 4
GND
VDD
32.768
kHz
4.9152
MHz
2.4576
MHz
PLL enabled
(BCS set)
in monitor code
X
VDD
or
GND
VTST
$0000
OFF
X
X
X
X
X
X
X
—
—
Enabled
Enabled
X
X
X
—
Enters user
mode — will
encounter an illegal
address reset
VDD
or
VDD
or
Non-zero OFF
X
—
—
X
—
Enters user mode
GND
VTST
Notes:
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA7 = 0 → serial, PTA7 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
PTC3 pin low when entering monitor mode causes a bypass of a divide-
by-two stage at the oscillator only if V is applied to IRQ. In this event,
TST
the CGMOUT frequency is equal to the CGMXCLK frequency, and the
OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is either V or V ), then all port C pin
DD
SS
requirements and conditions, including the PTC3 frequency divisor
selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
NOTE: If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V
IRQ must be used to enter monitor mode.
, to
TST
The COP module is disabled in monitor mode based on these
conditions:
• If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ or RST.
• If monitor mode was entered with V
on IRQ (condition set 1),
TST
then the COP is disabled as long as V
or RST.
is applied to either IRQ
TST
The second condition states that as long as V
is maintained on the
TST
IRQ pin after entering monitor mode, or if V
is applied to RST after
TST
the initial reset to get into monitor mode (when V
was applied to IRQ),
TST
then the COP will be disabled. In the latter situation, after V
is applied
TST
to the RST pin, V
can be removed from the IRQ pin in the interest of
TST
freeing the IRQ for normal functionality in monitor mode.
Figure 15-2 shows a simplified diagram of the monitor mode entry when
the reset vector is blank and just 1 x V voltage is applied to the IRQ
DD
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.
Advance Information
210
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
POR RESET
NO
IS VECTOR
BLANK?
NORMAL USER
MODE
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
NO
POR
TRIGGERED?
YES
Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with pin configuration shown in Figure 15-1 by
pulling RST low and then high. The rising edge of RST latches monitor
mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See 15.5 Security.) After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
NOTE: The PTA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.
In monitor mode, the MCU uses different vectors for reset, SWI
(software interrupt), and break interrupt than those for user mode. The
alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE: Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST low will not exit
monitor mode in this situation.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
211
Table 15-2 summarizes the differences between user mode and monitor
mode.
Table 15-2. Mode Differences
Functions
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
Modes
User
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
Monitor
15.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
NEXT
START
BIT
START
BIT
BIT 6
STOP
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
BIT 7
Figure 15-3. Monitor Data Format
15.4.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-4. Break Transaction
Advance Information
212
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
15.4.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and
the state of the PTC3 pin (when IRQ is set to V ) upon entry into
TST
monitor mode. When PTC3 is high, the divide by ratio is 1024. If the
PTC3 pin is at logic 0 upon entry into monitor mode, the divide by ratio
is 512.
If monitor mode was entered with V on IRQ, then the divide by ratio is
DD
set at 1024, regardless of PTC3. If monitor mode was entered with V
SS
on IRQ, then the internal PLL steps up the external frequency, presumed
to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor
mode entry require that the reset vector is blank.
Table 15-3 lists external frequencies required to achieve a standard
baud rate of 9600 BPS. Other standard baud rates can be accomplished
using proportionally higher or lower frequency generators. If using a
crystal as the clock source, be aware of the upper frequency limit that the
internal clock module can handle. See 23.8 5.0-V Control Timing and
23.9 3.0-V Control Timing for this limit.
Table 15-3. Monitor Baud Rate Selection
External
Frequency
Internal
Frequency
Baud Rate
(BPS)
IRQ
PTC3
4.9152 MHz
9.8304 MHz
9.8304 MHz
32.768 kHz
V
0
1
2.4576 MHz
2.4576 MHz
2.4576 MHz
2.4576 MHz
9600
9600
9600
9600
TST
V
TST
V
X
X
DD
V
SS
15.4.5 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
213
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0
pin for error checking. An 11-bit delay at the end of each command
allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ,
IREAD, or READSP data is returned. The data returned by a read
command appears after the echo of the last byte of the command.
NOTE: Wait one bit time after each echo before sending the next byte.
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
4
4
1
1
4
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-5. Read Transaction
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
WRITE
3
3
1
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-6. Write Transaction
Advance Information
214
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
A brief description of each monitor mode command is given in
Table 15-4 through Table 15-9.
Table 15-4. READ (Read Memory) Command
Description Read byte from memory
Operand
2-byte address in high-byte:low-byte order
Returns contents of specified address
Data
Returned
Opcode
$4A
Command Sequence
SENT TO
MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
Table 15-5. WRITE (Write Memory) Command
Description Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by
data byte
Operand
Data
Returned
None
Opcode
$49
FROM
HOST
Command Sequence
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
ECHO
WRITE
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
215
Table 15-6. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand
2-byte address in high byte:low byte order
Returns contents of next two addresses
Data
Returned
Opcode
$1A
Command Sequence
FROM
HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
Table 15-7. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand
Single data byte
Data
Returned
None
$19
Opcode
Command Sequence
FROM
HOST
DATA
DATA
IWRITE
IWRITE
ECHO
Advance Information
216
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Table 15-8. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand
None
Data
Returned
Returns incremented stack pointer value (SP + 1) in high-byte:low-
byte order
Opcode
$0C
Command Sequence
FROM
HOST
SP
HIGH
SP
LOW
READSP
READSP
ECHO
RETURN
Table 15-9. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand
None
None
$28
Data
Returned
Opcode
Command Sequence
FROM
HOST
RUN
RUN
ECHO
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
217
The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER SP + 1
CONDITION CODE REGISTER
ACCUMULATOR
SP + 2
SP + 3
SP + 4
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER SP + 5
LOW BYTE OF PROGRAM COUNTER SP + 6
SP + 7
Figure 15-7. Stack Pointer at Monitor Mode Entry
15.5 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-
defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTA0. If the received
bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See Figure 15-8.)
Advance Information
218
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
VDD
RST
PA7
4096 + 32 CGMXCLK CYCLES
24 BUS CYCLES
256 BUS CYCLES (MINIMUM)
FROM HOST
FROM MCU
PA0
1
1
4
1
4
2
1
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-8. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
219
If the security sequence fails, the device can be reset and brought up in
monitor mode to attempt another entry. After failing the security
sequence, the FLASH mode can also be bulk erased by executing an
erase routine that was downloaded into internal RAM. The bulk erase
operation clears the security code locations so that all eight security
bytes become $00.
Advance Information
220
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 16. Input/Output (I/O) Ports
16.1 Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.3.1
16.3.2
16.3.3
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .226
Port A Input Pullup Enable Register . . . . . . . . . . . . . . . . .228
16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
16.4.1
16.4.2
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .230
16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
16.5.1
16.5.2
16.5.3
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .233
Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . .235
16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
16.6.1
16.6.2
16.6.3
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .238
Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . .240
16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
16.7.1
16.7.2
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .242
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
221
16.2 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel
ports. All I/O pins are programmable as inputs or outputs. All individual
bits within port A, port C, and port D are software configurable with pullup
devices if configured as input port bits. The pullup devices are
automatically and dynamically disabled when a port bit is switched to
output mode.
NOTE: Connect any unused I/O pins to an appropriate logic level, either V or
DD
V . Although the I/O ports do not require termination for proper
SS
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
0
PTB6
PTC6
PTD6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
Port C Data Register
(PTC)
PTD7
Port D Data Register
(PTD)
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Data Direction Register A
(DDRA)
= Unimplemented
Figure 16-1. I/O Port Register Summary
Advance Information
222
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DDRB7
Data Direction Register B
(DDRB)
$0005
0
0
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Data Direction Register C
(DDRC)
$0006
$0007
$0008
$000C
$000D
$000E
$000F
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
0
0
0
0
0
0
0
0
0
0
DDRE1
0
DDRE0
0
Data Direction Register E
(DDRE)
0
0
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Port A Input Pullup Enable
Register (PTAPUE)
0
0
0
0
0
0
0
0
0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Port C Input Pullup Enable
Register (PTCPUE)
0
0
0
0
0
0
0
0
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Port D Input Pullup Enable
Register (PTDPUE)
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-1. I/O Port Register Summary (Continued)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
223
Table 16-1. Port Control Register Bits Summary
Port
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
DDR
Module Control
KBIE0
Pin
DDRA0
DDRA1
DDRA2
DDRA3
DDRA4
DDRA5
DDRA6
DDRA7
DDRB0
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
DDRB6
DDRB7
DDRC0
DDRC1
DDRC2
DDRC3
DDRC4
DDRC5
DDRC6
DDRD0
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRD7
DDRE0
DDRE1
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTA5/KBD5
PTA6/KBD6
PTA7/KBD7
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD6
PTB7/ATD7
PTC0
KBIE1
KBIE2
KBIE3
KBIE4
KBIE5
KBIE6
KBIE7
CH0
A
KBD
CH1
CH2
CH3
B
ADC
CH4
CH5
CH6
CH7
PTC1
PTC2
C
PTC3
PTC4
PTC5
PTC6
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
PTD7/T2CH1
PTE0/TxD
PTE1/RxD
SPI
D
E
TIM1
TIM2
SCI
Advance Information
224
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
16.3 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with
the keyboard interrupt (KBI) module. Port A also has software
configurable pullup devices if configured as an input port.
16.3.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight
port A pins.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTA7
Write:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by reset
KBD4 KBD3
Alternate
KBD7
KBD6
KBD5
KBD2
KBD1
KBD0
Function:
Figure 16-2. Port A Data Register (PTA)
PTA7–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
KBD7–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard
interrupt control register (KBICR) enable the port A pins as external
interrupt pins. See Section 13. Keyboard Interrupt Module (KBI).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
225
16.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address: $0004
Bit 7
DDRA7
0
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
Figure 16-3. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA7–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 16-4 shows the port A I/O logic.
Advance Information
226
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
PTAx
RESET
WRITE PTA ($0000)
PTAx
V
DD
PTAPUEx
INTERNAL
PULLUP
DEVICE
READ PTA ($0000)
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes
the operation of the port A pins.
Table 16-2. Port A Pin Functions
Accesses
Accesses to PTA
to DDRA
PTAPUE Bit
DDRA Bit PTA Bit
I/O Pin Mode
Read/Write
Read
Pin
Write
(1)
(4)
(3)
(3)
1
0
0
1
X
Input, V
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
PTA7–PTA0
PTA7–PTA0
DD
(2)
0
X
X
Input, Hi-Z
Output
Pin
X
PTA7–PTA0
PTA7–PTA0
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
227
16.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software
configurable pullup device for each of the eight port A pins. Each bit is
individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRA is configured for output
mode.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
0
Figure 16-5. Port A Input Pullup Enable Register (PTAPUE)
PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
Advance Information
228
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
16.4 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with
the analog-to-digital converter (ADC) module.
16.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight
port pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTB7
Write:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by reset
AD4 AD3
Alternate
AD7
AD6
AD5
AD2
AD1
AD0
Function:
Figure 16-6. Port B Data Register (PTB)
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
AD7–AD0 — Analog-to-Digital Input Bits
AD7–AD0 are pins used for the input channels to the analog-to-digital
converter module. The channel select bits in the ADC status and
control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as
the input to the analog circuitry.
NOTE: Care must be taken when reading port B while applying analog voltages
to AD7–AD0 pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTBx/ADx pin, while PTB is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
229
16.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address: $0005
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
Figure 16-7. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB7–DDRB0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 16-8 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 16-8. Port B I/O Circuit
Advance Information
230
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-3 summarizes
the operation of the port B pins.
Table 16-3. Port B Pin Functions
Accesses
to DDRB
Accesses to PTB
DDRB Bit
PTB Bit
I/O Pin Mode
Read/Write
Read
Pin
Write
(1)
(2)
(3)
0
1
X
Input, Hi-Z
Output
DDRB7–DDRB0
DDRB7–DDRB0
PTB7–PTB0
X
PTB7–PTB0
PTB7–PTB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
231
16.5 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has
software configurable pullup devices if configured as an input port.
16.5.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the
seven port C pins.
Address: $0002
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Unaffected by reset
= Unimplemented
Figure 16-9. Port C Data Register (PTC)
PTC6–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
Advance Information
232
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
16.5.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is
an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address: $0006
Bit 7
0
6
DDRC6
0
5
DDRC5
0
4
DDRC4
0
3
DDRC3
0
2
DDRC2
0
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 16-10. Data Direction Register C (DDRC)
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC6–DDRC0, configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 16-11 shows the port C I/O logic.
NOTE: For those devices packaged in a 40-pin dual in-line package, set DDRC6
and DDRC5 to a 1 to configure PTC5 and PTC6 as outputs.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
233
READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
PTCx
RESET
WRITE PTC ($0002)
PTCx
V
DD
PTCPUEx
INTERNAL
PULLUP
DEVICE
READ PTC ($0002)
Figure 16-11. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-4 summarizes
the operation of the port C pins.
Table 16-4. Port C Pin Functions
Accesses to DDRC
Read/Write
Accesses to PTC
PTCPUE Bit DDRC Bit PTC Bit I/O Pin Mode
Read
Write
(1)
(4)
(2)
(3)
(3)
1
0
0
0
1
X
Input, V
DDRC6–DDRC0
DDRC6–DDRC0
DDRC6–DDRC0
Pin
Pin
PTC6–PTC0
PTC6–PTC0
DD
X
Input, Hi-Z
Output
X
X
PTC6–PTC0
PTC6–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
Advance Information
234
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
16.5.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software
configurable pullup device for each of the seven port C pins. Each bit is
individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRC is configured for output
mode.
Address: $000E
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
235
16.6 Port D
Port D is an 8-bit special-function port that shares four of its pins with the
serial peripheral interface (SPI) module and four of its pins with two timer
interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
16.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
NOTE: Bit 7 and bit 6 of PTD are not available in a 40-pin dual in-line
package.
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset
T1CH0 SPSCK
Alternate
Function:
T2CH1
T2CH0
T1CH1
MOSI
MISO
SS
Figure 16-13. Port D Data Register (PTD)
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD7/T2CH1–PTD6/T2CH0 pins are the TIM2 input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0
pins are timer channel I/O pins or general-purpose I/O pins. See
Section 22. Timer Interface Module (TIM).
Advance Information
236
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input
capture/output compare pins. The edge/level select bits, ELSxB and
ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are
timer channel I/O pins or general-purpose I/O pins. See Section 22.
Timer Interface Module (TIM).
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module.
When the SPE bit is clear, the PTD3/SPSCK pin is available for
general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTD2/MOSI pin is available for
general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the SPI module. However, the
DDRD bits always determine whether reading port D returns the states
of the latches or the states of the pins. See Table 16-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTD0/SS pin is available for general-purpose I/O. When the SPI is
enabled, the DDRB0 bit in data direction register B (DDRB) has no
effect on the PTD0/SS pin.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
237
16.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address: $0007
Bit 7
DDRD7
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Read:
Write:
Reset:
Figure 16-14. Data Direction Register D (DDRD)
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD7–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-15 shows the port D I/O logic.
NOTE: For those devices packaged in a 40-pin dual in-line package, set DDRC7
and DDRC6 to a 1 to configure PTD6 and PTD7 as outputs.
Advance Information
238
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
PTDx
RESET
WRITE PTD ($0003)
PTDx
VDD
PTDPUEx
INTERNAL
PULLUP
DEVICE
READ PTD ($0003)
Figure 16-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-5 summarizes
the operation of the port D pins.
Table 16-5. Port D Pin Functions
Accesses to DDRD
Read/Write
Accesses to PTD
PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode
Read
Write
(1)
(4)
(2)
(3)
(3)
1
0
0
0
1
X
Input, V
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
Pin
Pin
PTD7–PTD0
PTD7–PTD0
DD
X
Input, Hi-Z
Output
X
X
PTD7–PTD0
PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
239
16.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software
configurable pullup device for each of the eight port D pins. Each bit is
individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRD is configured for output
mode.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
0
0
0
0
0
0
0
0
Figure 16-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
16.7 Port E
Port E is a 2-bit special-function port that shares two of its pins with the
serial communications interface (SCI) module.
Advance Information
240
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
16.7.1 Port E Data Register
The port E data register contains a data latch for each of the two port E
pins.
Address: $0008
Bit 7
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
0
PTE1
PTE0
Unaffected by reset
Alternate
Function:
RxD
TxD
= Unimplemented
Figure 16-17. Port E Data Register (PTE)
PTE1 and PTE0 — Port E Data Bits
PTE1 and PTE0 are read/write, software programmable bits. Data
direction of each port E pin is under the control of the corresponding
bit in data direction register E.
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 16-6.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See Section
18. Serial Communications Interface Module (SCI).
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See
Section 18. Serial Communications Interface Module (SCI).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
241
16.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address: $000C
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
DDRE1
0
Bit 0
DDRE0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-18. Data Direction Register E (DDRE)
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE1 and DDRE0, configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16-19 shows the port E I/O logic.
Advance Information
242
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
READ DDRE ($000C)
WRITE DDRE ($000C)
DDREx
PTEx
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
Figure 16-19. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-6 summarizes
the operation of the port E pins.
Table 16-6. Port E Pin Functions
Accesses to DDRE
Read/Write
Accesses to PTE
DDRE Bit
PTE Bit
I/O Pin Mode
Read
Write
(1)
(2)
(3)
0
1
X
Input, Hi-Z
DDRE1–DDRE0
DDRE1–DDRE0]
Pin
PTE1–PTE0
X
Output
PTE1–PTE0
PTE1–PTE0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
243
Advance Information
244
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 17. Random-Access Memory (RAM)
17.1 Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.2 Introduction
This section describes the 512 bytes of RAM (random-access memory).
17.3 Functional Description
Addresses $0040 through $023F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
245
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Advance Information
246
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 18. Serial Communications Interface Module
(SCI)
18.1 Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.5.1
18.5.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .255
Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .257
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .257
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .262
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18.5.2.1
18.5.2.2
18.5.2.3
18.5.2.4
18.5.2.5
18.5.2.6
18.5.3
18.5.3.1
18.5.3.2
18.5.3.3
18.5.3.4
18.5.3.5
18.5.3.6
18.5.3.7
18.5.3.8
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
18.6.1
18.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .268
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.8.1
18.8.2
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .268
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .269
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
247
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
18.9.1
18.9.2
18.9.3
18.9.4
18.9.5
18.9.6
18.9.7
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .269
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .272
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .275
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.2 Introduction
This section describes the serial communications interface (SCI)
module, which allows high-speed asynchronous communications with
peripheral devices and other MCUs.
NOTE: References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. This MCU does not have
the DMA function. Any DMA-related register bits should be left in their
reset state for normal MCU operation.
18.3 Features
Features of the SCI module include:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter CPU interrupt requests
• Programmable transmitter output polarity
Advance Information
248
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• Configuration register bit, SCIBDSRC, to allow selection of baud
rate clock source
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
249
18.4 Pin Name Conventions
The generic names of the SCI I/O pins are:
• RxD (receive data)
• TxD (transmit data)
SCI I/O (input/output) lines are implemented by sharing parallel I/O port
pins. The full name of an SCI input or output reflects the name of the
shared port pin. Table 18-1 shows the full names and the generic names
of the SCI I/O pins.
The generic pin names appear in the text of this section.
Table 18-1. Pin Name Conventions
Generic Pin Names:
Full Pin Names:
RxD
TxD
PTE1/RxD
PTE0/TxD
18.5 Functional Description
Figure 18-1 shows the structure of the SCI module. The SCI allows full-
duplex, asynchronous, NRZ serial communication among the MCU and
remote devices, including other MCUs. The transmitter and receiver of
the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
The baud rate clock source for the SCI can be selected via the
configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source
selection values are shown in Figure 18-1.
Advance Information
250
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
INTERNAL BUS
SCI DATA
REGISTER
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
TRANSMIT
SHIFT REGISTER
PTE1/RxD
PTE0/TxD
TXINV
SCTIE
TCIE
SCRIE
ILIE
R8
T8
DMARE
DMATE
TE
SCTE
TC
RE
RWU
SBK
SCRF
IDLE
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
LOOPS
ENSCI
LOOPS
RECEIVE
CONTROL
FLAG
CONTROL
TRANSMIT
CONTROL
WAKEUP
CONTROL
SCIBDSRC
FROM
M
BKF
RPF
ENSCI
CONFIG
WAKE
ILTY
PEN
PTY
SL
A
PRE-
BAUD
CGMXCLK
IT12
÷ 4
X
SCALER
DIVIDER
B
SL = 0 => X = A
SL = 1 => X = B
DATA SELECTION
CONTROL
³ ÷ 16
Figure 18-1. SCI Module Block Diagram
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
251
Addr.
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
TXINV
0
4
M
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
SCI Control Register 1
(SCC1)
$0013
0
SCTIE
TCIE
0
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2
(SCC2)
$0014
$0015
$0016
$0017
$0018
$0019
0
0
R8
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
SCI Control Register 3
(SCC3)
U
U
0
0
0
0
0
0
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
PE
SCI Status Register 1
(SCS1)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
1
1
0
0
0
0
0
0
BKF
RPF
SCI Status Register 2
(SCS2)
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register
(SCDR)
Unaffected by reset
SCP1
0
SCP0
R
0
SCR2
0
SCR1
0
SCR0
0
SCI Baud Rate Register
(SCBR)
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 18-2. SCI I/O Register Summary
Advance Information
252
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
18.5.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 18-3.
8-BIT DATA FORMAT
PARITY
BIT M IN SCC1 CLEAR
NEXT
START
BIT
BIT
START
BIT
STOP
BIT
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCC1 SET
PARITY
BIT
BIT 8
NEXT
START
BIT
START
BIT
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
Figure 18-3. SCI Data Formats
18.5.2 Transmitter
Figure 18-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI can be selected via the
configuration bit, SCIBDSRC. Source selection values are shown in
Figure 18-4.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
253
SCIBDSRC
FROM
CONFIG2
SL
A
CGMXCLK
IT12
X
B
SL = 0 => X = A
SL = 1 => X = B
INTERNAL BUS
PRE-
BAUD
÷ 16
÷ 4
SCI DATA REGISTER
SCALER DIVIDER
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
PTE0/TxD
TXINV
M
PEN
PTY
PARITY
GENERATION
T8
DMATE
TRANSMITTER
CONTROL LOGIC
DMATE
SCTIE
SCTE
SCTE
SBK
DMATE
SCTE
SCTIE
LOOPS
ENSCI
TE
SCTIE
TC
TC
TCIE
TCIE
Figure 18-4. SCI Transmitter
Advance Information
254
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
18.5.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
18.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character
out to the PTE0/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the
PTE0/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
255
18.5.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
18.5.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes
idle after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
Advance Information
256
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NOTE: When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit
becomes set and just before writing the next byte to the SCDR.
18.5.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See 18.9.1 SCI Control Register 1.)
18.5.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
257
18.5.3 Receiver
Figure 18-5 shows the structure of the SCI receiver.
18.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
18.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
Advance Information
258
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
INTERNAL BUS
SCIBDSRC
FROM
SCR1
SCR2
SCR0
SCP1
SCP0
CONFIG2
SCI DATA REGISTER
SL
A
CGMXCLK
IT12
PRE-
BAUD
X
÷ 4
÷ 16
B
SCALER DIVIDER
11-BIT
SL = 0 => X = A
RECEIVE SHIFT REGISTER
SL = 1 => X = B
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
PTE1/RxD
ALL 0s
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
DMARE
ILIE
SCRF
SCRIE
DMARE
SCRIE
SCRF
SCRIE
DMARE
DMARE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 18-5. SCI Receiver Block Diagram
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
259
18.5.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see Figure 18-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
PTE1/RxD
SAMPLES
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 18-6. Receiver Data Sampling
Advance Information
260
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 18-2 summarizes the results of
the start bit verification samples.
Table 18-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
001
010
011
100
101
110
111
Yes
Yes
Yes
No
0
1
1
0
1
0
0
0
Yes
No
No
No
Start bit verification is not successful if any two of the three verification
samples are logic 1s. If start bit verification is not successful, the RT
clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 18-3 summarizes the
results of the data bit samples.
Table 18-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
261
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 18-4 summarizes the results of the stop bit
samples.
Table 18-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
001
010
011
100
101
110
111
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
18.5.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
18.5.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
Advance Information
262
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
tolerance is much more than the degree of misalignment that is likely to
occur.
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
Figure 18-7 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 18-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-7, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147
× 100 = 4.54%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
263
With the misaligned character shown in Figure 18-7, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163
× 100 = 4.12%
-------------------------
170
Fast Data Tolerance
Figure 18-8 shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast stop
bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 18-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
·
154 – 160
× 100 = 3.90%
-------------------------
154
Advance Information
264
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176
× 100 = 3.53%
-------------------------
170
18.5.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PTE1/RxD pin can bring the receiver out of the standby
state:
• Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
• Idle input line condition — When the WAKE bit is clear, an idle
character on the PTE1/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
265
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
18.5.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI
receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTE1/RxD pin. The idle
line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
18.5.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
• Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
Advance Information
266
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
18.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
Refer to Section 3. Low-Power Modes for information on exiting wait
mode.
18.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
267
Refer to Section 3. Low-Power Modes for information on exiting stop
mode.
18.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
18.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
18.8.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the
PTE0/TxD pin is an output regardless of the state of the DDRE2 bit in
data direction register E (DDRE).
Advance Information
268
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
18.8.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTE1/RxD pin with port E. When the SCI is enabled, the
PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
18.9 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
18.9.1 SCI Control Register 1
SCI control register 1:
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
269
Address: $0013
Bit 7
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
LOOPS
Write:
Reset:
0
Figure 18-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
PTE1/RxD pin is disconnected from the SCI, and the transmitter
output goes into the receiver input. Both the transmitter and the
receiver must be enabled to use loop mode. Reset clears the LOOPS
bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and
disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
Advance Information
270
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 18-5.) The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PTE1/RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as
idle character bits. The counting begins either after the start bit or after
the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 18-5.)
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Figure 18-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
271
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 18-5.) Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 18-5. Character Format Selection
Control Bits
PEN and
Character Format
Start
Bits
Data
Bits
Stop
Parity
Character
Length
M
PTY
0X
0X
10
Bits
0
1
0
0
1
1
1
1
1
1
1
1
8
9
7
7
8
8
None
None
Even
Odd
1
1
1
1
1
1
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
11
10
Even
Odd
11
18.9.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
Advance Information
272
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address: $0014
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
SCTIE
0
Figure 18-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU
interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
273
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PTE0/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTE0/TxD returns to the idle
condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
Advance Information
274
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character
followed by a logic 1. The logic 1 after the break character guarantees
recognition of a valid start bit. If SBK remains set, the transmitter
continuously transmits break characters with no logic 1s between
them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
18.9.3 SCI Control Register 3
SCI control register 3:
• Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
• Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
• Parity error interrupts
Address: $0015
Bit 7
R8
6
T8
U
5
4
3
ORIE
0
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
DMARE DMATE
U
0
0
= Unimplemented
U = Unaffected
Figure 18-11. SCI Control Register 3 (SCC3)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
275
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth
bit (bit 8) of the transmitted character. T8 is loaded into the transmit
shift register at the same time that the SCDR is loaded into the transmit
shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
DMATE — DMA Transfer Enable Bit
CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt
requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt
requests enabled
Advance Information
276
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated
by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated
by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated
by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt
requests generated by the parity error bit, PE. (See 18.9.4 SCI Status
Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
277
18.9.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
PE
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
Figure 18-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Advance Information
278
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
279
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 18-13 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next flag-clearing
sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-
clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
Advance Information
280
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 18-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the PEIE
bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set
and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
281
18.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
0
3
0
2
0
1
Bit 0
RPF
Read:
Write:
Reset:
BKF
0
0
0
0
0
= Unimplemented
Figure 18-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI module
or entering stop mode can show whether a reception is in progress.
1 = Reception in progress
0 = No reception in progress
Advance Information
282
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
18.9.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus
and the receive and transmit shift registers. Reset has no effect on data
in the SCI data register.
Address: $0018
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by reset
Figure 18-15. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
NOTE: Do not use read/modify/write instructions on the SCI data register.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
283
18.9.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver
and the transmitter.
Address: $0019
Bit 7
0
6
5
SCP1
0
4
SCP0
0
3
2
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
R
SCR2
0
0
0
= Unimplemented
R
= Reserved
Figure 18-16. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 18-6. Reset clears SCP1 and SCP0.
Table 18-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 18-7. Reset clears SCR2–SCR0.
Advance Information
284
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 18-7. SCI Baud Rate Selection
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
000
001
010
011
100
101
110
111
1
2
4
8
16
32
64
128
Use this formula to calculate the SCI baud rate:
f
BUS
baud rate = ------------------------------------
64 × PD × BD
where:
f
= bus frequency
BUS
PD = prescaler divisor
BD = baud rate divisor
SCI_BDSRC is an input to the SCI. Normally it will be tied off low at the
top level to select the bus clock as the clock source. This makes the
formula:
f
BUS
baud rate = ------------------------------------
64 × PD × BD
Table 18-8 shows the SCI baud rates that can be generated with a
4.9152-MHz bus clock.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
285
Table 18-8. SCI Baud Rate Selection Examples
Baud Rate
SCP1 and
SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
(f
= 4.9152 MHz)
BUS
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
1
2
76,800
38,400
19,200
9600
4800
2400
1200
600
1
4
1
8
1
16
32
64
128
1
1
1
1
3
25,600
12,800
6400
3200
1600
800
3
2
3
4
3
8
3
16
32
64
128
1
3
3
400
3
200
4
19,200
9600
4800
2400
1200
600
4
2
4
4
4
8
4
16
32
64
128
1
4
4
300
4
150
13
13
13
13
13
13
13
13
5908
2954
1477
739
2
4
8
16
32
64
128
369
185
92
46
Advance Information
286
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 19. System Integration Module (SIM)
19.1 Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .291
19.3.1
19.3.2
19.3.3
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . .292
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .292
19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .292
19.4.1
19.4.2
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Active Resets from Internal Sources. . . . . . . . . . . . . . . . .294
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
Computer Operating Properly (COP) Reset. . . . . . . . . .296
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .297
Monitor Mode Entry Module Reset (MODRST) . . . . . . .297
19.4.2.1
19.4.2.2
19.4.2.3
19.4.2.4
19.4.2.5
19.4.2.6
19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
19.5.1
19.5.2
19.5.3
SIM Counter During Power-On Reset. . . . . . . . . . . . . . . .297
SIM Counter During Stop Mode Recovery . . . . . . . . . . . .298
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .298
19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
19.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .302
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .305
19.6.1.1
19.6.1.2
19.6.1.3
19.6.2
19.6.3
19.6.4
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
19.7.1
19.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
287
19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
19.8.1
19.8.2
19.8.3
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .308
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .310
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . .311
19.2 Introduction
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in Figure 19-1. Table 19-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 19-1 shows the internal signal names used in this section.
Advance Information
288
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷ 2
CLOCK
CONTROL
VDD
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULLUP
DEVICE
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
MASTER
RESET
CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET PIN CONTROL
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 19-1. SIM Block Diagram
Table 19-1. Signal Name Conventions
Signal Name
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
CGMXCLK
CGMVCLK
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
CGMOUT
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
289
Addr.
Register Name
Bit 7
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
Read:
Write:
Reset:
SBSW
NOTE
0
R
0
R
0
SIM Break Status Register
(SBSR)
$FE00
Note: Writing a logic 0 clears SBSW.
Read: POR
Write:
PIN
COP
ILOP
ILAD
MODRST
LVI
0
SIM Reset Status Register
$FE01
(SRSR)
POR:
Read:
Write:
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
SIM Upper Byte Address
$FE02
Register (SUBAR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
$FE04
$FE05
$FE06
0
IF6
R
IF5
R
IF4
R
IF3
R
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IF16
R
IF15
R
Interrupt Status Register 3
(INT3)
R
R
R
R
R
R
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-2. SIM I/O Register Summary
Advance Information
290
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 19-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See
Section 7. Clock Generator Module (CGMC).)
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
TO TIMTB15A, ADC
SIM
SIMOSCEN
OSCSTOPENB
FROM
CONFIG
SIM COUNTER
IT12
TO REST
OF CHIP
CGMRCLK
CGMOUT
SIMDIV2
BUS CLOCK
GENERATORS
IT23
÷ 2
TO REST
OF CHIP
PHASE-LOCKED LOOP (PLL)
PTC3
MONITOR MODE
USER MODE
Figure 19-3. CGM Clock Signals
19.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Section 12. External Interrupt (IRQ).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
291
19.3.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
19.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 19.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
19.4 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
Advance Information
292
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
An internal reset clears the SIM counter (see 19.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 19.8 SIM Registers.)
19.4.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor
the LVI was the source of the reset. See Table 19-2 for details. Figure
19-4 shows the relative timing.
Table 19-2. PIN Bit Set Timing
Reset Type
POR/LVI
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
CGMOUT
RST
VECT H VECT L
IAB
PC
Figure 19-4. External Reset Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
293
19.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See Figure
19-5. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. (See Figure 19-6.)
NOTE: For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in Figure
19-5.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 19-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 19-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
Advance Information
294
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 19-7. POR Recovery
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
295
19.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 4
of the SIM counter. The SIM counter output, which occurs at least every
13
4
2 – 2 CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
V
+ V while the MCU is in monitor mode. The COP module can be
HI
DD
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
V
+ V on the RST pin disables the COP module.
HI
DD
19.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
19.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
Advance Information
296
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V voltage falls to the LVI voltage. The LVI bit in the SIM reset
DD
TRIPF
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
19.4.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to
the SIM when monitor mode is entered in the condition where the reset
vectors are blank ($00). (See 15.4.1 Entering Monitor Mode.) When
MODRST gets asserted, an internal reset occurs. The SIM actively pulls
down the RST pin for all internal reset sources.
19.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
19.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
297
19.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
19.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 19.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
19.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
19.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
19.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
Advance Information
298
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
processing can resume. Figure 19-8 shows interrupt entry timing.
Figure 19-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). (See Figure
19-10.)
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY
PC–1[7:0]
PC–1[15:8]
X
A
CCR
V DATA H V DATA L
OPCODE
R/W
Figure 19-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1 [7:0] PC–1[15:8] OPCODE OPERAND
R/W
Figure 19-9. Interrupt Recovery Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
299
FROM RESET
BREAK
YES
INTERRUPT?
NO
YES
I BIT SET?
NO
IRQ0
INTERRUPT?
YES
YES
NO
IRQ
INTERRUPT?
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 19-10. Interrupt Processing
Advance Information
300
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 19-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
LDA #$FF
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 19-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
301
19.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
19.6.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 19-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 19-3. Interrupt Sources
Interrupt Status
Register Flag
Priority
Highest
Interrupt Source
Reset
SWI instruction
IRQ pin
—
—
I1
PLL
I2
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receiver full
SPI transmitter empty
SCI receive error
SCI receive
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
SCI transmit
Keyboard
ADC conversion complete
Timebase module
Lowest
Advance Information
302
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Interrupt Status
Register 1
Address: $FE04
Bit 7
6
5
I4
R
0
4
I3
R
0
3
I2
R
0
2
I1
R
0
1
0
Bit 0
0
Read:
Write:
Reset:
I6
R
0
I5
R
R
0
R
0
0
R
= Reserved
Figure 19-12. Interrupt Status Register 1 (INT1)
I6–I1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the
sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
Interrupt Status
Register 2
Address: $FE05
Bit 7
I14
R
6
5
I12
R
4
I11
R
3
I10
R
2
I9
R
0
1
I8
R
0
Bit 0
I7
Read:
Write:
Reset:
I13
R
R
0
0
0
0
0
0
R
= Reserved
Figure 19-13. Interrupt Status Register 2 (INT2)
I14–I7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the
sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
303
Interrupt Status
Register 3
Address: $FE06
Bit 7
6
5
0
4
0
3
0
2
0
1
I16
R
Bit 0
I15
R
Read:
Write:
Reset:
0
R
0
0
R
R
0
R
0
R
0
R
0
0
0
0
R
= Reserved
Figure 19-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
I16–I15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the
source shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
19.6.2 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
19.6.3 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. (See
Section 22. Timer Interface Module (TIM).) The SIM puts the CPU into
the break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
Advance Information
304
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
19.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described in
the following subsections. Both STOP and WAIT clear the interrupt mask
(I) in the condition code register, allowing interrupts to occur.
19.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 19-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
305
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 19-15. Wait Mode Entry Timing
Figure 19-16 and Figure 19-17 show the timing for WAIT recovery.
IAB
IDB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 19-16. Wait Recovery from Interrupt or Break
32
CYCLES
32
CYCLES
IAB
$6E0B
$A6
RST VCT H RST VCT L
IDB $A6
RST
$A6
CGMXCLK
Figure 19-17. Wait Recovery from Internal Reset
Advance Information
306
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
19.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 19-18 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
Figure 19-18. Stop Mode Entry Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
307
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 19-19. Stop Mode Recovery from Interrupt or Break
19.8 SIM Registers
The SIM has three memory-mapped registers. Table 19-4 shows the
mapping of these registers.
Table 19-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
SBSR
Access Mode
User
SRSR
User
SBFCR
User
19.8.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop mode or wait mode.
Address: $FE00
Bit 7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
R
Read:
Write:
Reset:
SBSW
R
R
(1)
Note
0
0
0
0
R
= Reserved
Note: 1. Writing a logic 0 clears SBSW.
Figure 19-20. SIM Break Status Register (SBSR)
Advance Information
308
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit clears it.
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE
LOBYTE
EQU
EQU
5
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN
PULH
RTI
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
309
19.8.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset
provided all previous reset status bits have been cleared. Clear the SIM
reset status register by reading it. A power-on reset sets the POR bit and
clears all other bits in the register.
Address: $FE01
Bit 7
POR
6
5
4
3
2
1
Bit 0
0
Read:
Write:
Reset:
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 19-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
Advance Information
310
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $00 after POR while IRQ = V
0 = POR or read of SRSR
DD
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
19.8.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 19-22. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
311
Advance Information
312
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 20. Serial Peripheral Interface Module (SPI)
20.1 Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.4 Pin Name Conventions and I/O Register Addresses . . . . . . .315
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
20.5.1
20.5.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
20.6.1
20.6.2
20.6.3
20.6.4
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .319
Transmission Format When CPHA = 0. . . . . . . . . . . . . . .320
Transmission Format When CPHA = 1. . . . . . . . . . . . . . .322
Transmission Initiation Latency. . . . . . . . . . . . . . . . . . . . .323
20.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .325
20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
20.8.1
20.8.2
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.11.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .335
20.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .335
20.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
20.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
20.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . .337
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
313
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .340
20.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
20.2 Introduction
20.3 Features
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
Features of the SPI module include:
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive
registers
• Four master mode frequencies (maximum = bus frequency ÷ 2)
• Maximum slave mode frequency = bus frequency
• Serial clock with programmable polarity and phase
• Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
• Mode fault error flag with CPU interrupt capability
• Overflow error flag with CPU interrupt capability
• Programmable wired-OR mode
2
• I C (inter-integrated circuit) compatibility
• I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)
Advance Information
314
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
20.4 Pin Name Conventions and I/O Register Addresses
The text that follows describes the SPI. The SPI I/O pin names are SS
(slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI
(master out slave in), and MISO (master in/slave out). The SPI shares
four I/O pins with four parallel I/O ports.
The full names of the SPI I/O pins are shown in Table 20-1. The generic
pin names appear in the text that follows.
Table 20-1. Pin Name Conventions
SPI Generic
Pin Names:
MISO
MOSI
SS
SPSCK
CGND
Full SPI
Pin Names:
SPI PTD1/MISO PTD2/MOSI PTD0/SS PTD3/SPSCK
V
SS
20.5 Functional Description
Figure 20-1 summarizes the SPI I/O registers and Figure 20-2 shows
the structure of the SPI module.
Addr.
Register Name
Bit 7
SPRIE
0
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
Write:
Reset:
DMAS
SPMSTR
CPOL
CPHA
SPWOM
0
SPI Control Register
(SPCR)
$0010
0
1
0
1
Read: SPRF
Write:
OVRF
MODF
SPTE
ERRIE
MODFEN
SPR1
SPR0
SPI Status and Control
Register (SPSCR)
$0011
$0012
Reset:
Read:
Write:
Reset:
0
0
0
0
1
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by reset
= Unimplemented
Figure 20-1. SPI I/O Register Summary
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
315
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
CGMOUT ÷ 2
FROM SIM
MISO
MOSI
7
6
5
4
3
2
1
0
÷ 2
÷ 8
÷ 32
CLOCK
DIVIDER
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SPSCK
SS
SPMSTR SPE
SELECT
M
CLOCK
LOGIC
S
SPR1
SPR0
SPMSTR CPHA
CPOL
RESERVED
MODFEN
ERRIE
SPTIE
SPRIE
DMAS
SPE
SPWOM
TRANSMITTER CPU INTERRUPT REQUEST
RESERVED
SPI
CONTROL
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRF
SPTE
OVRF
MODF
Figure 20-2. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be interrupt-
driven.
Advance Information
316
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
If a port bit is configured for input, then an internal pullup device may be
enabled for that port bit. (See 16.5.3 Port C Input Pullup Enable
Register.)
The following paragraphs describe the operation of the SPI module.
20.5.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is
set.
NOTE: Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. (See 20.14.1 SPI Control
Register.)
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the transmit
data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte
begins shifting out on the MOSI pin under the control of the serial clock.
(See Figure 20-3.)
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
VDD
Figure 20-3. Full-Duplex Master-Slave Connections
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
317
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See 20.14.2 SPI Status and Control
Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF, becomes set. At the same time that SPRF
becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register with
SPRF set and then reading the SPI data register. Writing to the SPI data
register clears the SPTE bit.
20.5.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode, the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is
complete. (See 20.8.2 Mode Fault Error.)
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software then
must read the receive data register before another full byte enters the
shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI
baud rate. The baud rate only controls the speed of the SPSCK
generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency
less than or equal to the bus speed.
Advance Information
318
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise,
the byte already in the slave shift register shifts out on the MISO pin.
Data written to the slave shift register during a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See 20.6 Transmission Formats.)
NOTE: SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
20.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock synchronizes
shifting and sampling on the two serial data lines. A slave select line
allows selection of an individual slave SPI device; slave devices that are
not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be used to indicate multiple-
master bus contention.
20.6.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK)
phase and polarity using two bits in the SPI control register (SPCR). The
clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission
format.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
319
The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE) .
20.6.2 Transmission Format When CPHA = 0
Figure 20-4 shows an SPI transmission in which CPHA is logic 0. The
figure should not be used as a replacement for data sheet parametric
information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another
for CPOL = 1. The diagram may be interpreted as a master or slave
timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 20.8.2 Mode Fault Error.) When CPHA = 0, the first SPSCK
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the slave data transmission. The slave’s SS pin must be
toggled back to high and then low again between each byte transmitted
as shown in Figure 20-5.
Advance Information
320
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
LSB
FROM MASTER
MISO
FROM SLAVE
MSB
SS; TO SLAVE
CAPTURE STROBE
Figure 20-4. Transmission Format (CPHA = 0)
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
321
20.6.3 Transmission Format When CPHA = 1
Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The
figure should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 20.8.2 Mode Fault Error.) When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
MSB
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
FROM MASTER
MISO
LSB
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
Figure 20-6. Transmission Format (CPHA = 1)
Advance Information
322
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
20.6.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the
SPDR starts a transmission. CPHA has no effect on the delay to the start
of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first
half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle
begins with an edge on the SPSCK line from its inactive to its active
level. The SPI clock rate (selected by SPR1:SPR0) affects the delay
from the write to SPDR and the start of the SPI transmission. (See
Figure 20-7.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. To conserve power, it is enabled
only when both the SPE and SPMSTR bits are set. SPSCK edges occur
halfway through the low time of the internal MCU clock. Since the SPI
clock is free-running, it is uncertain where the write to the SPDR occurs
relative to the slower SPSCK. This uncertainty causes the variation in
the initiation delay shown in Figure 20-7. This delay is no longer than a
single SPI bit time. That is, the maximum delay is two MCU bus cycles
for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32,
and 128 MCU bus cycles for DIV128.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
323
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 8;
LATEST
LATEST
LATEST
8 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 20-7. Transmission Start Delay (Master)
Advance Information
324
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
20.7 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high. Figure 20-8 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
1
3
8
WRITE TO SPDR
SPTE
5
10
2
SPSCK
CPHA:CPOL = 1:0
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
BYTE 1
BYTE 2
BYTE 3
4
9
SPRF
READ SPSCR
READ SPDR
6
11
7
12
1
2
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
7
8
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
BYTE 1 TRANSFERS FROM TRANSMIT DATA
3 AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
3
4
10
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
CPU READS SPDR, CLEARING SPRF BIT.
11
12
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
Figure 20-8. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
325
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
20.8 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before
the next full byte enters the shift register sets the OVRF bit. The
new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control
register.
• Mode fault error (MODF) — The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode
of the SPI. MODF is in the SPI status and control register.
20.8.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still
has unread data from a previous transmission when the capture strobe
of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs
in the middle of SPSCK cycle 7. (See Figure 20-4 and Figure 20-6.) If
an overflow occurs, all data received after the overflow and before the
OVRF bit is cleared does not transfer to the receive data register and
does not set the SPI receiver full bit (SPRF). The unread data that
transferred to the receive data register before the overflow occurred can
still be read. Therefore, an overflow error always indicates the loss of
data. Clear the overflow flag by reading the SPI status and control
register and then reading the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
Advance Information
326
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
interrupts share the same CPU interrupt vector. (See Figure 20-11.) It
is not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 20-9 shows how it is possible to
miss an overflow. The first part of Figure 20-9 shows how it is possible
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ
2
5
5
SPSCR
READ
SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
7
3
4
CPU READS BYTE 1 IN SPDR,
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
8
Figure 20-9. Missed Read of Overflow Condition
In this case, an overflow can be missed easily. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit. Figure 20-10 illustrates this process. Generally, to
avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
327
BYTE 1
1
BYTE 2
5
BYTE 3
7
BYTE 4
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
READ
2
4
6
9
12
14
SPSCR
READ
SPDR
3
8
10
13
1
2
8
9
BYTE 1 SETS SPRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11
12
13
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
5
6
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
20.8.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the
SPSCK and MOSI pins as outputs and the MISO pin as an input.
Clearing SPMSTR selects slave mode and configures the SPSCK and
MOSI pins as inputs and the MISO pin as an output. The mode fault bit,
MODF, becomes set any time the state of the slave select pin, SS, is
inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault
error occurs if:
• The SS pin of a slave SPI goes high during a transmission
• The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
Advance Information
328
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
interrupts share the same CPU interrupt vector. (See Figure 20-11.) It is
not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of
port drivers.
NOTE: To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O port
before enabling the SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK goes back to its
idle level following the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
idle level following the shift of the last data bit. (See 20.6 Transmission
Formats.)
NOTE: Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = 0. Reading SPMSTR when MODF = 1
shows the difference between a MODF occurring when the SPI is a
master and when it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
329
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
20.9 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests.
Table 20-2. SPI Interrupts
Flag
Request
SPTE
Transmitter empty
SPI transmitter CPU interrupt request
(DMAS = 0, SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver CPU interrupt request
(DMAS = 0, SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
MODF
Mode fault
Advance Information
330
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. (See Figure 20-11.)
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
NOT AVAILABLE
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
DMAS
NOT AVAILABLE
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 20-11. SPI Interrupt Request Generation
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
331
The following sources in the SPI status and control register can generate
CPU interrupt requests:
• SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.
20.10 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new
complete transmission.
• All the SPI port logic is defaulted back to being general-purpose
I/O.
These items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to set all control bits again when
SPE is set back high for the next transmission.
Advance Information
332
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled
by a mode fault occuring in an SPI that was configured as a master with
the MODFEN bit set.
20.11 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
20.11.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction.
In wait mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See 20.9 Interrupts.)
20.11.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after an external interrupt. If stop mode is exited by reset, any
transfer in progress is aborted, and the SPI is reset.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
333
20.12 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See Section 19. System Integration
Module (SIM).)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
20.13 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel
I/O port. They are:
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• CGND — Clock ground (internally connected to V )
SS
Advance Information
334
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
2
The SPI has limited inter-integrated circuit (I C) capability (requiring
software support) as a master in a single-master environment. To
2
communicate with I C peripherals, MOSI becomes an open-drain output
2
when the SPWOM bit in the SPI control register is set. In I C
communication, the MOSI and MISO pins are connected to a
2
bidirectional pin from the I C peripheral and through a pullup resistor to
V .
DD
20.13.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-
slave system, a logic 1 on the SS pin puts the MISO pin in a high-
impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
20.13.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
335
20.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full-duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
20.13.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
20.6 Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 20-12.
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-12. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See 20.14.2
SPI Status and Control Register.)
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
Advance Information
336
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See 20.8.2 Mode Fault Error.) For the state of the
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. (See
Table 20-3.)
Table 20-3. SPI Configuration
SPE SPMSTR
MODFEN
SPI Configuration
Not enabled
State of SS Logic
General-purpose I/O;
SS ignored by SPI
(1)
0
1
1
1
X
X
X
0
0
Slave
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
1
1
Master without MODF
Master with MODF
1
Input-only to SPI
Note 1. X = Don’t care
20.13.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. It is internally connected to V as
SS
shown in Table 20-1.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
337
20.14 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
20.14.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
SPMSTR
1
4
CPOL
0
3
CPHA
1
2
SPWOM
0
1
SPE
0
Bit 0
SPTIE
0
Read:
Write:
Reset:
DMAS
SPRIE
0
0
= Unimplemented
Figure 20-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests
0 = SPRF CPU interrupt requests
Advance Information
338
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
DMAS —DMA Select Bit
This read only bit has no effect on this version of the SPI. This bit
always reads as a 0.
0 = SPRF DMA and SPTE DMA service requests disabled
(SPRF CPU and SPTE CPU interrupt requests enabled)
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 20-4 and Figure 20-6.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 20-4 and Figure 20-6.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. (See Figure 20-12.) Reset sets
the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See 20.10 Resetting the SPI.) Reset clears
the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
339
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
20.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Bit 7
Read: SPRF
Write:
6
ERRIE
0
5
4
3
2
1
Bit 0
SPR0
0
OVRF
MODF
SPTE
MODFEN SPR1
Reset:
0
0
0
1
0
0
= Unimplemented
Figure 20-14. SPI Status and Control Register (SPSCR)
Advance Information
340
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the
shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the SPI
data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU
interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
341
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
NOTE: Do not write to the SPI data register unless the SPTE bit is high.
During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing
to the transmit data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If the
MODF flag is set, clearing the MODFEN does not clear the MODF flag.
If the SPI is enabled as a master and the MODFEN bit is low, then the
SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general-
purpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. (See 20.13.4 SS (Slave Select).)
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See 20.8.2 Mode Fault Error.)
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as
shown in Table 20-4. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
Advance Information
342
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Table 20-4. SPI Master Baud Rate Selection
SPR1 and SPR0
Baud Rate Divisor (BD)
00
01
10
11
2
8
32
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Baud rate = --------------------------
2 × BD
where:
CGMOUT = base clock output of the clock generator module (CGM)
BD = baud rate divisor
20.14.3 SPI Data Register
The SPI data register consists of the read-only receive data register and
the write-only transmit data register. Writing to the SPI data register
writes data into the transmit data register. Reading the SPI data register
reads data from the receive data register. The transmit data and receive
data registers are separate registers that can contain different values.
(See Figure 20-2.)
Address: $0012
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Indeterminate after reset
Figure 20-15. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE: Do not use read-modify-write instructions on the SPI data register since
the register read is not the same as the register written.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
343
Advance Information
344
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 21. Timebase Module (TBM)
21.1 Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .347
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
21.7.1
21.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
21.2 Introduction
21.3 Features
This section describes the timebase module (TBM). The TBM will
generate periodic interrupts at user selectable rates using a counter
clocked by the external crystal clock. This TBM version uses 15 divider
stages, eight of which are user selectable.
Features of the TBM module include:
• Software programmable 1-Hz, 4-Hz, 16-Hz, 256-Hz, 512-Hz,
1024-Hz, 2048-Hz, and 4096-Hz periodic interrupt using external
32.768-kHz crystal
• User selectable oscillator clock source enable during stop mode to
allow periodic wakeup from stop
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
345
21.4 Functional Description
NOTE: This module is designed for a 32.768-kHz oscillator.
This module can generate a periodic interrupt by dividing the crystal
frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit
is cleared. The counter, shown in Figure 21-1, starts counting when the
TBON bit is set. When the counter overflows at the tap selected by
TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt
request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the
TACK bit. The first time the TBIF flag is set after enabling the timebase
module, the interrupt is generated at approximately half of the overflow
period. Subsequent events occur at the exact period.
TBON
÷2
÷2
÷2
÷2
÷2
÷2
÷2
CGMXCLK
TBMINT
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
TBIF
TBIE
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
Figure 21-1. Timebase Block Diagram
Advance Information
346
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
21.5 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the
timebase interrupts and set the rate.
Address: $001C
Bit 7
TBIF
6
TBR2
0
5
TBR1
0
4
TBR0
0
3
0
2
TBIE
0
1
TBON
0
Bit 0
TBTST*
0
Read:
Write:
Reset:
TACK
0
0
= Unimplemented
* PTM test mode
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts
as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz
Timebase Interrupt Rate
TBR2
TBR1
TBR0
Divider
Hz
1
ms
1000
250
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32,768
8192
2048
128
64
4
16
62.5
~ 3.9
~2
256
512
1024
2048
4096
32
~1
16
~0.5
~0.24
8
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
347
NOTE: Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK— Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic
1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic
0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit
becomes set. Reset clears the TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off
to reduce power consumption when its function is not necessary. The
counter can be initialized by clearing and then setting this bit. Reset
clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
21.6 Interrupts
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2:TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
Advance Information
348
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
21.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
21.7.1 Wait Mode
The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.
If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.
21.7.2 Stop Mode
The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.
If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during STOP mode. In stop mode the
timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
349
Advance Information
350
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 22. Timer Interface Module (TIM)
22.1 Contents
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.5.1
22.5.2
22.5.3
22.5.4
22.5.5
22.5.6
22.5.7
22.5.8
22.5.9
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . .358
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . .359
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .359
Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . .360
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . .361
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.7.1
22.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .364
22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
22.10.1 TIM Status and Control Register. . . . . . . . . . . . . . . . . . . .366
22.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .368
22.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .369
22.10.4 TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .370
22.10.5 TIM Channel Status and Control Registers. . . . . . . . . . . .371
22.10.6 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .375
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
351
22.2 Introduction
This section describes the timer interface (TIM) module. The TIM is a 2-
channel timer that provides a timing reference with input capture, output
compare, and pulse-width-modulation functions. Figure 22-1 is a block
diagram of the TIM. This particular MCU has two timer interface modules
which are denoted as TIM1 and TIM2.
22.3 Features
Features of the TIM include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width-modulation (PWM) signal
generation
• Programmable TIM clock input with 7-frequency internal bus clock
prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
• DMA (direct-memory access) service request generation
(optional, not available on this MCU)
• Modular architecture expandable to eight channels
• I/O port bit(s) software configurable with pullup device(s) if
configured as input port bit(s)
Advance Information
352
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
22.4 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM
input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and
T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four port
D I/O port pins. The full names of the TIM I/O pins are listed in
Table 22-1. The generic pin names appear in the text that follows.
Table 22-1. Pin Name Conventions
TIM Generic Pin Names:
T[1,2]CH0
PTD4/T1CH0
PTD6/T2CH0
T[1,2]CH1
PTD5/T1CH1
PTD7/T2CH1
TIM1
Full TIM
Pin Names:
TIM2
NOTE: References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TCH0 may refer generically
to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
22.5 Functional Description
NOTE: References to DMA and associated functions are only valid if the MCU
has a DMA module. This MCU does not have the DMA function. Any
DMA-related register bits should be left in their reset state for expected
MCU operation.
NOTE: References to TCLK and external TIM clock input are only valid if the
MCU has an external TCLK pin. If the MCU has no external TCLK pin,
the TIM module must use the internal bus clock prescaler selections.
Figure 22-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
353
The two TIM channels (per timer) are programmable independently as
input capture or output compare channels. If a channel is configured as
input capture, then an internal pullup device may be enabled for that
channel. (See 16.5.3 Port C Input Pullup Enable Register.)
INTERNAL
TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
T[1,2]CH0
CH0F
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA0S
CH0IE
MS0A
MS0B
CH1F
TOV1
ELS1B ELS1A
PORT
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
T[1,2]CH1
LOGIC
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA1S
CH1IE
MS1A
Figure 22-1. TIM Block Diagram
Figure 22-2 summarizes the timer registers.
NOTE: References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer
to both T1SC and T2SC.
Advance Information
354
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
TOIE
TSTOP
PS2
PS1
PS0
Timer 1 Status and Control
Register (T1SC)
$0020
TRST
0
0
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
Timer 1 Counter Register
High (T1CNTH)
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 1 Counter Register
Low (T1CNTL)
0
Bit 15
1
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Timer 1 Counter Modulo
Register High (T1MODH)
1
1
1
1
1
1
1
Bit 0
1
Bit 7
1
6
1
5
1
4
1
3
2
1
Timer 1 Counter Modulo
Register Low (T1MODL)
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read: CH0F
Timer 1 Channel 0 Status
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
and Control Register Write:
0
0
(T1SC0)
Reset:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 1 Channel 0
Register High (T1CH0H)
Write:
Reset:
Read:
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
Timer 1 Channel 0
Register Low (T1CH0L)
Write:
Reset:
Indeterminate after reset
Read: CH1F
0
0
Timer 1 Channel 1 Status
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
0
and Control Register Write:
0
0
(T1SC1)
Reset:
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 1 of 3)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
355
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 1 Channel 1
$0029
Register High (T1CH1H)
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
PS0
Timer 1 Channel 1
Register Low (T1CH1L)
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
Indeterminate after reset
TOF
0
TRST
0
0
TOIE
TSTOP
PS2
PS1
Timer 2 Status and Control
Register (T2SC)
0
0
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
Timer 2 Counter Register
High (T2CNTH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 2 Counter Register
Low (T2CNTL)
0
Bit 15
1
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Timer 2 Counter Modulo
Register High (T2MODH)
1
1
1
1
1
1
1
Bit 0
1
Bit 7
6
1
5
1
4
1
3
2
1
Timer 2 Counter Modulo
Register Low (T2MODL)
1
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read: CH0F
Timer 2 Channel 0 Status
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
and Control Register Write:
0
0
(T2SC0)
Reset:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Timer 2 Channel 0
Register High (T2CH0H)
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 2 of 3)
Advance Information
356
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Timer 2 Channel 0
Register Low (T2CH0L)
$0032
Indeterminate after reset
Read: CH1F
0
Timer 2 Channel 1 Status
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
$0033
$0034
$0035
and Control Register Write:
0
0
(T2SC1)
Reset:
0
0
0
0
0
9
0
Read:
Bit 15
14
13
12
11
10
Bit 8
Timer 2 Channel 1
Register High (T2CH1H)
Write:
Reset:
Read:
Indeterminate after reset
Bit 7
6
5
4
3
2
1
Bit 0
Timer 2 Channel 1
Register Low (T2CH1L)
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 3 of 3)
22.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.
22.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
357
22.5.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
22.5.4 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 22.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable channel
x TIM overflow interrupts and write the new value in the TIM
overflow interrupt routine. The TIM overflow interrupt occurs at the
end of the current counter overflow period. Writing a larger value
in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same
counter overflow period.
Advance Information
358
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
22.5.5 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
22.5.6 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 22-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
359
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See 22.10.1 TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
22.5.7 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 22.5.6 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
Advance Information
360
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
22.5.8 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
361
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
22.5.9 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. See Table 22-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 22-3.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Advance Information
362
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 22.10.5 TIM
Channel Status and Control Registers.)
22.6 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE, and the
channel x DMA select bit, DMAxS. Channel x TIM CPU interrupt
requests are enabled when CHxIE:DMAxS = 1:0. Channel x
TIM DMA service requests are enabled when
CHxIE:DMAxS = 1:1. CHxF and CHxIE are in the TIM channel x
status and control register. DMAxS is in the TIM DMA select
register.
CAUTION: Because this chip does NOT have a DMA module, CHxIE bit should
NEVER be set when DMAxS is set. Doing so will mask TIM CPU
interrupt request and cause unwanted results.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
363
22.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
22.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
The DMA can service the TIM without exiting wait mode.
22.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
22.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 19.8.3 SIM Break Flag Control
Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
Advance Information
364
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
22.9 I/O Signals
Port D shares four of its pins with the TIM. (There is an optional TCLK
which can be used as an external clock input to the TIM prescaler, but is
not available on this MCU.) The four TIM channel I/O pins are T1CH0,
T1CH1, T2CH0, and T2CH1 as described in 22.4 Pin Name
Conventions.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
22.10 I/O Registers
NOTE: References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer
to both T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
365
22.10.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 22-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then writing
logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot
be lost due to inadvertent clearing of TOF. Reset clears the TOF bit.
Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
Advance Information
366
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers. Counting
resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST
bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS2–PS0 — Prescaler Select Bits
These read/write bits select either the TCLK pin or one of the seven
prescaler outputs as the input to the TIM counter as Table 22-2 shows.
Reset clears the PS[2:0] bits.
Table 22-2. Prescaler Selection
PS2–PS0
000
TIM Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
001
010
011
100
101
110
111
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
367
22.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T1CNTH, $002C
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T1CNTL, $002D
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-6. TIM Counter Registers Low (TCNTL)
Advance Information
368
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
22.10.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T1MODH, $002E
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
1
1
1
1
1
1
1
1
= Unimplemented
Figure 22-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
1
1
1
1
1
1
1
1
= Unimplemented
Figure 22-8. TIM Counter Modulo Register Low (TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
369
22.10.4 TIMA Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T1CNTH, $002C
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-9. TIM Counter Register High (TCNTH)
Address: T1CNTL, $0022 and T1CNTL, $002D
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-10. TIM Counter Register Low (TCNTL)
Advance Information
370
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
22.10.5 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
6
CH0IE
1
5
MS0B
1
4
MS0A
1
3
ELS0B
1
2
ELS0A
1
1
TOV0
1
Bit 0
CH0MAX
1
Read: CH0F
Write:
0
1
Reset:
Figure 22-11. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
6
CH1IE
0
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
Write:
0
0
Reset:
0
Figure 22-12. TIM Channel 1Status and Control Register (TSC1)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
371
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE:DMAxS = 1:0),
clear CHxF by reading TIM channel x status and control register with
CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts and TIM DMA service
requests on channel x. The DMAxS bit in the TIM DMA select register
selects channel x TIM DMA service requests or TIM CPU interrupt
requests.
NOTE: TIM DMA service requests cannot be used in buffered PWM mode. In
buffered PWM mode, disable TIM DMA service requests by clearing the
DMAxS bit in the TIM DMA select register.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests and DMA service requests
enabled
0 = Channel x CPU interrupt requests and DMA service requests
disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and
control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Advance Information
372
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See Table
22-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. See Table 22-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to
port D, and pin PTDx/TCHx is available as a general-purpose I/O pin.
Table 22-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
373
Table 22-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under port control;
initial output level high
X0
X1
00
00
Output preset
Pin under port control;
initial output level low
00
00
01
10
Capture on rising edge only
Capture on falling edge only
Input capture
Capture on rising or
falling edge
00
11
01
01
01
1X
1X
1X
01
10
11
01
10
11
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Output
compare or
PWM
Buffered
output
compare or
buffered PWM
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
Advance Information
374
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty
cycle of buffered and unbuffered PWM signals to 100%. As Figure 22-
13 shows, the CHxMAX bit takes effect in the cycle after it is set or
cleared. The output stays at the 100% duty cycle level until the cycle
after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-13. CHxMAX Latency
22.10.6 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
375
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
Indeterminate after reset
Figure 22-14. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
Indeterminate after reset
Figure 22-15. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
Indeterminate after reset
Figure 22-16. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035
Bit 7
6
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
Indeterminate after reset
Figure 22-17. TIM Channel 1 Register Low (TCH1L)
Advance Information
376
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 23. Preliminary Electrical Specifications
23.1 Contents
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .379
23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .380
23.7 3.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .382
23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
23.9 3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
23.10 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .386
23.11 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . .387
23.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
23.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
23.14 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
23.15 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .396
23.17 Clock Generation Module Characteristics . . . . . . . . . . . . . . .396
23.17.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .396
23.17.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .397
23.18 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
377
23.2 Introduction
This section contains electrical and timing specifications. These values
are design targets and have not yet been fully tested.
23.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 23.6 5.0-V DC Electrical Characteristics for
guaranteed operating conditions.
(1)
Symbol
Value
Unit
V
Characteristic
Supply voltage
V
–0.3 to + 6.0
DD
Input voltage
V
V
– 0.3 to V + 0.3
V
In
SS
DD
Maximum current per pin
excluding V , V
and PTC0–PTC4
I
± 15
± 25
mA
mA
DD SS,
Maximum current for pins
PTC0–PTC4
I
PTC0–PTC4
Maximum current into V
I
150
150
mA
mA
°C
DD
mvdd
Maximum current out of V
Storage temperature
Note:
I
SS
mvss
T
–55 to +150
stg
1. Voltages referenced to VSS
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that V and V
be constrained to the
Out
In
range V ≤ (V or V ) ≤ V . Reliability of operation is enhanced if
SS
In
Out
DD
unused inputs are connected to an appropriate logic voltage level (for
example, either V or V ).
SS
DD
Advance Information
378
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.4 Functional Operating Range
Characteristic
Symbol
Value
Unit
Operating temperature range
T
–40 to +85
°C
A
3.0 ±10%
5.0 ±10%
Operating voltage range
V
V
DD
23.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
°C/W
W
Thermal resistance
PDIP (40-pin)
QFP (44-pin)
θ
60
95
JA
I/O pin power dissipation
P
User-Determined
I/O
P = (I × V ) + P
I/O
D
DD
DD
(1)
Power dissipation
P
=
W
D
K/(T + 273 °C)
J
P x (T + 273 °C)
(2)
J
A
Constant
K
W/°C
2
+ P × θ
D
JA
Average junction temperature
Maximum junction temperature
Notes:
T
T + (P × θ )
°C
°C
J
A
D
JA
T
125
JM
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known T and measured
A
P . With this value of K, P and T can be determined for any value of T .
D
D
J
A
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
379
23.6 5.0-V DC Electrical Characteristics
(2)
(1)
Symbol
Min
Max
Unit
Typ
Characteristic
Output high voltage
(I
(I
(I
= –2.0 mA) all I/O pins
= –10.0 mA) all I/O pins
= –10.0 mA) pins PTC0–PTC4 only
V
V
V
V
V
V
– 0.8
– 1.5
– 0.8
—
—
—
—
—
—
—
50
V
V
V
OH
OH
DD
DD
DD
Load
Load
Load
OH
Maximum combined I for port C, port E,
I
—
mA
OH
OH1
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
I
—
—
—
—
50
mA
mA
OH
OH2
OHT
port A, port B
Maximum total I for all port pins
I
100
OH
Output low voltage
(I
(I
(I
= 1.6 mA) all I/O pins
= 10 mA) all I/O pins
= 15 mA) pins PTC0–PTC4 only
V
V
V
—
—
—
—
—
—
—
—
0.4
1.5
1.0
50
V
V
V
OL
OL
Load
Load
Load
OL
Maximum combined I for port C, port E,
I
mA
OL
OL1
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
I
—
—
—
—
50
mA
mA
OL
OL2
port A, port B
Maximum total I for all port pins
I
100
OL
OLT
Input high voltage
All ports, IRQs, RESET, OSC1
V
0.7 x V
—
—
V
DD
V
V
IH
DD
Input low voltage
All ports, IRQs, RESET, OSC1
V
V
0.2 x V
DD
IL
SS
V
supply current
DD
(3)
Run
Wait
—
—
—
—
30
12
mA
mA
(4)
(5)
Stop
I
DD
25 °C
—
—
—
—
—
5
20
300
50
500
—
—
—
—
—
µA
µA
µA
µA
µA
(6)
25 °C with TBM enabled
25 °C with LVI and TBM enabled
–40 °C to 85 °C with TBM enabled
–40 °C to 85 °C with LVI and TBM enabled
(6)
(6)
(6)
(7)
I/O ports Hi-Z leakage current
Input current
I
I
—
—
—
—
±10
µA
µA
IL
±1
In
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
R
20
33
50
kΩ
PU
Capacitance
Ports (as input or output)
C
V
—
—
—
—
12
8
Out
In
pF
V
C
Monitor mode entry voltage
V
+2.5
DD
—
9
TST
Advance Information
380
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
(2)
(1)
Symbol
Min
Max
Unit
Typ
Characteristic
Low-voltage inhibit, trip falling voltage – target
Low-voltage inhibit, trip rising voltage – target
Low-voltage inhibit reset/recover hysteresis – target
V
4.13
4.23
4.3
4.4
4.35
4.45
V
V
TRIPF
V
TRIPR
V
—
100
—
mV
HYS
(V
+ V
= V
)
TRIPF
HYS
TRIPR
(8)
POR rearm voltage
V
0
0
—
700
—
100
800
—
mV
mV
POR
(9)
POR reset voltage
V
PORRST
(10)
POR rise time ramp rate
R
0.035
V/ms
POR
Notes:
1. V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , unless otherwise noted
SS A L H
DD
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (f = 32.8 MHz). All inputs 0.2 V from rail. No
DD
osc
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run I . Measured with all modules enabled.
DD
4. Wait I measured using external square wave clock source (f
= 32.8 MHz). All inputs 0.2 V from rail. No dc loads. Less
osc
DD
than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
L
I
. Measured with PLL and LVI enabled.
DD
5. Stop I
is measured with OSC1 = V
.
DD
SS
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 23.13 ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
V
is reached.
DD
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
381
23.7 3.0-V DC Electrical Characteristics
(2)
(1)
Symbol
Min
Max
Unit
Typ
Characteristic
Output high voltage
(I
(I
(I
= –0.6 mA) all I/O pins
= –4.0 mA) all I/O pins
= –4.0 mA) pins PTC0–PTC4 only
V
V
V
V
V
V
– 0.3
– 1.0
– 0.5
—
—
—
—
—
—
—
30
V
V
V
OH
OH
DD
DD
DD
Load
Load
Load
OH
Maximum combined I for port C, port E,
I
—
mA
OH
OH1
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
I
—
—
—
—
30
60
mA
mA
OH
OH2
OHT
port A, port B
Maximum total I for all port pins
I
OH
Output low voltage
(I
(I
(I
= 0.5 mA) all I/O pins
= 6.0 mA) all I/O pins
= 10.0 mA) pins PTC0–PTC4 only
V
V
V
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
V
V
V
OL
OL
Load
Load
Load
OL
Maximum combined I for port C, port E,
I
mA
OL
OL1
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
I
—
—
—
—
30
60
mA
mA
OL
OL2
port A, port B
Maximum total I for all port pins
I
OLT
OL
Input high voltage
All ports, IRQs, RESET, OSC1
V
0.7 x V
—
—
V
DD
V
V
IH
DD
Input low voltage
All ports, IRQs, RESET, OSC1
V
V
0.3 x V
DD
IL
SS
V
supply current
DD
(3)
Run
Wait
—
—
—
—
10
6
mA
mA
(4)
(5)
Stop
I
DD
25 °C
—
—
—
—
—
3
12
200
30
300
—
—
—
—
—
µA
µA
µA
µA
µA
(6)
25 °C with TBM enabled
25 °C with LVI and TBM enabled
–40 °C to 85 °C with TBM enabled
–40 °C to 85 °C with LVI and TBM enabled
(6)
(6)
(6)
(7)
I/O ports Hi-Z leakage current
Input current
I
I
—
—
—
—
±10
µA
µA
IL
±1
In
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
R
20
33
50
kΩ
PU
Capacitance
Ports (as input or output)
C
V
—
—
—
—
12
8
Out
In
pF
V
C
Monitor mode entry voltage
V
+2.5
DD
—
9
TST
Advance Information
382
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
(2)
(1)
Symbol
Min
Max
Unit
Typ
Characteristic
Low-voltage inhibit, trip falling voltage – target
Low-voltage inhibit, trip rising voltage – target
Low-voltage inhibit reset/recover hysteresis – target
V
2.5
2.6
2.6
2.63
2.73
V
V
TRIPF
V
2.66
TRIPR
V
—
60
—
mV
HYS
(V
+ V
= V
)
TRIPF
HYS
TRIPR
(8)
POR rearm voltage
V
0
0
—
700
—
100
800
—
mV
mV
POR
(9)
POR reset voltage
V
PORRST
(10)
POR rise time ramp rate
R
0.02
V/ms
POR
Notes:
1. V
= 3.0 Vdc ± 10%, V = 0 Vdc, T = T to T , unless otherwise noted
SS A L H
DD
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (f = 16.4 MHz). All inputs 0.2 V from rail. No
DD
osc
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run I . Measured with all modules enabled.
DD
4. Wait I measured using external square wave clock source (f
= 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
osc
DD
than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
L
I
. Measured with PLL and LVI enabled.
DD
5. Stop I
is measured with OSC1 = V
.
DD
SS
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
V
is reached.
DD
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
383
23.8 5.0-V Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
(2)
Frequency of operation
Crystal option
External clock option
f
32
dc
100
32.8
kHz
MHz
osc
(3)
(4)
Internal operating frequency
Internal clock period (1/f
f
—
122
50
8.2
—
MHz
ns
op
)
t
OP
cyc
IRL
(5)
(6)
RESET input pulse width low
t
—
ns
IRQ interrupt pulse width low
(edge-triggered)
t
50
—
—
ns
ILIH
IRQ interrupt pulse period
t
TBD Note 8
t
cyc
ILIL
(7)
16-bit timer
Input capture pulse width
Input capture period
t
t
TBD
Note 8
—
—
ns
TH, TL
t
t
TLTL
cyc
Notes:
1. V = 0 Vdc; timing shown with respect to 20% V
and 70% V unless otherwise noted
SS
SS
DD
2. See 23.17 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to
execute the interrrupt service routine plus tcyc
.
Advance Information
384
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.9 3.0-V Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
(2)
Frequency of operation
Crystal option
External clock option
f
32
dc
100
16.4
kHz
MHz
osc
(3)
(4)
Internal operating frequency
Internal clock period (1/f
f
—
4.1
—
MHz
ns
op
)
t
244
125
OP
cyc
IRL
(5)
(6)
RESET input pulse width low
t
—
ns
IRQ interrupt pulse width low
(edge-triggered)
t
125
—
—
ns
ILIH
IRQ interrupt pulse period
t
TBD Note 8
t
cyc
ILIL
(7)
16-bit timer
Input capture pulse width
Input capture period
t
t
TBD
Note 8
—
—
ns
TH, TL
t
t
TLTL
cyc
Notes:
1. V = 0 Vdc; timing shown with respect to 20% V
and 70% V unless otherwise noted
SS
SS
DD
2. See 23.17 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to
execute the interrrupt service routine plus tCYC
.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
385
23.10 Output High-Voltage Characteristics
0
–5
–40
25
–10
–15
–20
–25
–30
–35
85
3
3.5
4
4.5
V
OH (V)
VOH < VDD –0.8 V @ IOH = –2.0 mA
VOH < VDD –1.5 V @ IOH = –10.0 mA
Figure 23-1. Typical High-Side Driver
Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 4.5 Vdc)
DD
0
–5
–10
–15
–20
–25
–40
25
85
1
1.2
1.4
1.6
VOH (V)
OH < VDD –0.3 V @ IOH = –0.6 mA
VOH < VDD –1.0 V @ IOH = –4.0 mA
1.8
2
2.2
2.4
V
Figure 23-2 .Typical High-Side Driver
Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc)
DD
Advance Information
386
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.11 Output Low-Voltage Characteristics
35
30
25
20
15
10
5
–40
25
85
0
0
0.2
0.4
0.6
0.8
OL(V)
1
1.2
1.4
V
VOL < 0.4 V @ IOL = 1.6 mA
OL < 1.5 V @ IOL = 10.0 mA
V
Figure 23-3. Typical Low-Side Driver
Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 4.5 Vdc)
DD
20
18
16
14
12
10
8
–40
25
85
6
4
2
0
0
0.2
0.4
0.6
V
0.8
OL (V)
1
1.2
1.4
VOL < 0.3 V @ IOL = 0.5 mA
OL < 1.0V @ IOL = 6.0 mA
V
Figure 23-4. Typical Low-Side Driver
Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc)
DD
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
387
70
60
50
40
30
20
10
0
–40
25
85
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VOL (V)
VOL < 1.0 V @ IOL = 15 mA
Figure 23-5. Typical Low-Side Driver Characteristics
for Higher Current Drive – Ports PTC4–PTC0 (V = 4.5 Vdc)
DD
40
35
30
25
20
15
10
5
-40
25
85
0
0
0.2
0.4
0.6
V
0.8
OL (V)
1
1.2
1.4
VOL < 0.8 V @ IOL = 10 mA
Figure 23-6. Typical Low-Side Driver Characteristics
for Higher Current Drive – Ports PTC4–PTC0 (V = 2.7 Vdc)
DD
Advance Information
388
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.12 Typical Supply Currents
30
25
20
15
10
5
5.5 V
3.3 V
0
0
1
2
3
4
5
6
7
8
9
f
bus (MHz)
Figure 23-7. Typical Operating I with All Modules
DD
Turned On (–40 °C to 85 °C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5 V
3.3 V
0
1
2
3
4
5
6
7
8
fbus (MHz)
Figure 23-8. Typical Wait Mode I with TBM Enabled,
DD
LVI Disabled, and PLL Disabled (–40 °C to 85 °C)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
389
6
5
4
3
2
1
0
5.5 V
3.3 V
0
1
2
3
4
5
6
7
8
9
f
bus (MHz)
Figure 23-9. Typical Wait Mode I , with LVI and TBM Enabled,
DD
PLL Disabled (–40 °C to 85 °C)
Advance Information
390
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.13 ADC Characteristics
(1)
Symbol
Min
Max
Unit
Comments
should be tied
Characteristic
V
DDAD
2.7
5.5
to the same potential
Supply voltage
V
(V
(V
V
DDAD
DD
DD
as V via separate
DD
min)
max)
traces.
V
0
1.5
V
ADIN
DDAD
V
DDAD
Input voltages
V
V
<= V
ADIN REFH
V
REFH
Resolution
B
8
8
Bits
AD
AD
Absolute accuracy
(V
= 0 V, VDDAD = V
=
REFH
A
± 1/2
± 1
LSB
Includes quantization
REFL
5 V ± 10%)
t
= 1/f
only at 1 MHz
, tested
ADIC
AIC
ADC internal clock
f
0.5
1.048
MHz
V
ADIC
Conversion range
Power-up time
R
V
V
V
REFL
= V
AD
REFL
REFH
SS
t
16
t
t
cycles
ADPU
AIC
AIC
Conversion time
t
16
5
17
—
cycles
ADC
t
(2)
AIC
Sample time
t
ADS
cycles
Hex
Hex
pF
(3)
Zero input reading
Z
00
FE
—
01
FF
V
= V
= V
ADI
IN
REFL
(3)
Full-scale reading
Input capacitance
F
V
ADI
IN
REFH
C
(20) 8
Not tested
ADI
(4)
Input leakage
—
—
± 1
µA
Port B
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc ± 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc ± 10%, VREFL = 0
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
391
23.14 5.0-V SPI Characteristics
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
Operating frequency
(1)
Number
Master
Slave
f
f
f
/128
DC
f /2
OP
MHz
MHz
OP(M)
OP
f
OP(S)
OP
Cycle time
Master
Slave
1
t
t
2
1
128
—
t
t
CYC(M)
cyc
cyc
CYC(S)
2
3
Enable lead time
Enable lag time
t
1
1
—
—
t
Lead(S)
cyc
cyc
t
t
Lag(S)
Clock (SPSCK) high time
4
5
6
7
Master
Slave
t
t
t
–25
64 t
—
ns
ns
SCKH(M)
cyc
cyc
1/2 t –25
SCKH(S)
cyc
Clock (SPSCK) low time
Master
Slave
t
t
t
–25
64 t
ns
ns
SCKL(M)
cyc
cyc
1/2 t –25
—
SCKL(S)
cyc
Data setup time (inputs)
Master
Slave
t
30
30
—
—
ns
ns
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
30
30
—
—
ns
ns
H(M)
t
H(S)
(3)
Access time, slave
8
9
CPHA = 0
CPHA = 1
t
t
0
0
40
40
ns
ns
A(CP0)
A(CP1)
(4)
Disable time, slave
t
—
40
ns
DIS(S)
Data valid time, after enable edge
Master
Slave
10
t
t
—
—
50
50
ns
ns
V(M)
(5)
V(S)
Data hold time, outputs, after enable edge
11
Master
Slave
t
t
0
0
—
—
ns
ns
HO(M)
HO(S)
Notes:
1. Numbers refer to dimensions in Figure 23-10 and Figure 23-11.
2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins.
DD
DD
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
Advance Information
392
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.15 3.0-V SPI Characteristics
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
(1)
Number
Operating frequency
Master
Slave
f
f
f
/128
DC
f
/2
MHz
MHz
OP(M)
OP
OP
f
OP(S)
OP
Cycle time
Master
Slave
1
t
t
2
1
128
—
t
t
CYC(M)
cyc
cyc
CYC(S)
2
3
Enable lead time
Enable lag time
t
1
1
—
—
t
Lead(s)
cyc
cyc
t
t
Lag(s)
Clock (SPSCK) high time
4
5
6
7
Master
Slave
t
t
t
–35
64 t
—
ns
ns
SCKH(M)
cyc
cyc
1/2 t –35
SCKH(S)
cyc
Clock (SPSCK) low time
Master
Slave
±
t
t
t
–35
64 t
ns
ns
SCKL(M)
cyc
cyc
1/2 t –35
—
SCKL(S)
cyc
Data setup time (inputs)
Master
Slave
t
40
40
—
—
ns
ns
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
40
40
—
—
ns
ns
H(M)
t
H(S)
(3)
Access time, slave
8
9
CPHA = 0
CPHA = 1
t
t
0
0
50
50
ns
ns
A(CP0)
A(CP1)
(4)
Disable time, slave
t
—
50
ns
DIS(S)
Data valid time, after enable edge
Master
Slave
10
t
t
—
—
60
60
ns
ns
V(M)
(5)
V(S)
Data hold time, outputs, after enable edge
11
Master
Slave
t
t
0
0
—
—
ns
ns
HO(M)
HO(S)
Notes:
1. Numbers refer to dimensions in Figure 23-10 and Figure 23-11.
2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins.
DD
DD
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
393
SS
SS PIN OF MASTER HELD HIGH
INPUT
1
5
4
SPSCK OUTPUT
CPOL = 0
NOTE
4
5
SPSCK OUTPUT
CPOL = 1
NOTE
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
INPUT
11
MASTER MSB OUT
10
11
MOSI
MASTER LSB OUT
OUTPUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS
SS PIN OF MASTER HELD HIGH
1
INPUT
SPSCK OUTPUT
CPOL = 0
5
NOTE
NOTE
4
SPSCK OUTPUT
CPOL = 1
5
4
6
7
MISO
MSB IN
11
BITS 6–1
BITS 6–1
LSB IN
INPUT
10
10
MOSI
MASTER MSB OUT
MASTER LSB OUT
OUTPUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 23-10. SPI Master Timing
Advance Information
394
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
SS
INPUT
3
1
SPSCK INPUT
CPOL = 0
5
4
4
5
2
SPSCK INPUT
CPOL = 1
9
8
MISO
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
INPUT
11
6
7
10
MOSI
MSB IN
LSB IN
OUTPUT
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SPSCK INPUT
CPOL = 0
5
4
5
2
3
SPSCK INPUT
CPOL = 1
4
10
9
8
MISO
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
OUTPUT
11
6
7
10
MOSI
MSB IN
LSB IN
INPUT
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 23-11. SPI Slave Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
395
23.16 Timer Interface Module Characteristics
Characteristic
Symbol
, t
Min
Max
Unit
Input capture pulse width
t
1
—
t
cyc
TIH TIL
23.17 Clock Generation Module Characteristics
23.17.1 CGM Component Specifications
Characteristic
Symbol
Min
30
—
Typ
Max
Unit
kHz
pF
(1)
Crystal reference frequency
f
32.768
—
100
—
XCLK
(2)
Crystal load capacitance
C
C
C
L
1
2
B
S
(2)
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
Series resistor
6
2 × C
2 × C
10
40
pF
L
L
(2)
6
40
pF
R
R
10
330
22
MΩ
kΩ
330
470
Notes:
1. Fundamental mode crystals only
2. Consult crystal manufacturer’s data.
Advance Information
396
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
23.17.2 CGM Electrical Specifications
Description
Operating voltage
Symbol
Min
2.7
–40
30
Typ
—
Max
5.5
Unit
V
V
DD
o
Operating temperature
T
25
32.768
38.4
—
130
100
—
C
Crystal reference frequency
Range nominal multiplier
f
kHz
kHz
Hz
RCLK
f
—
NOM
(1)
VCO center-of-range frequency
f
38.4 k
38.4 k
1
40.0 M
40.0 M
255
4
VRS
VRS
L
(2)
f
Medium-voltage VCO center-of-range frequency
VCO range linear range multiplier
VCO power-of-two range multiplier
VCO multiply factor
—
Hz
—
E
2
1
—
N
1
—
4095
8
P
VCO prescale multiplier
2
1
1
Reference divider factor
R
1
1
15
VCO operating frequency
f
38.4 k
—
—
40.0 M
8.2
Hz
MHz
MHz
ms
VCLK
(1)
Bus operating frequency
f
f
—
BUS
BUS
Lock
Lock
(2)
Bus frequency @ medium voltage
—
—
4.1
Manual acquisition time
Automatic lock time
t
t
—
—
50
—
—
50
ms
f
x
RCLK
(3)
PLL jitter
f
0
—
0.025%
x 2 N/4
Hz
J
P
External clock input frequency
PLL disabled
f
f
dc
—
—
32.8 M
1.5 M
Hz
Hz
OSC
External clock input frequency
PLL enabled
30 k
OSC
Notes:
1. 5.0 V ± 10% VDD
2. 3.0 V ± 10% VDD
3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
397
23.18 Memory Characteristics
Characteristic
RAM data retention voltage
FLASH pages per row
Symbol
Min
1.3
8
Typ
—
Max
—
Unit
V
V
RDR
—
—
8
Pages
Bytes
Hz
FLASH bytes per page
—
8
—
8
(1)
FLASH read bus clock frequency
f
32 k
—
8.4 M
Read
FLASH charge pump clock frequency
(See 11.5.1 FLASH Charge Pump Frequency
Control.)
(2)
f
1.8
—
2.5
MHz
Pump
FLASH block/bulk erase time
FLASH high-voltage kill time
FLASH return to read time
FLASH page program pulses
FLASH page program step size
t
100
200
50
—
—
—
20
—
—
—
ms
µs
Erase
t
Kill
t
—
µs
HVD
(3)
fls
1
TBD
1.2
Pulses
ms
Pulses
(4)
t
1.0
PROG
FLASH cumulative program time per row between
erase cycles
(5)
Row
t
—
—
TBD
ms
FLASH HVEN low to MARGIN high time
FLASH MARGIN high to PGM low time
t
50
150
100
100
10
—
—
—
—
—
—
—
—
—
—
µs
HVTV
t
µs
VTP
(6)
FLASH row erase endurance
—
Cycles
Cycles
Years
(7)
FLASH row program endurance
—
—
(8)
FLASH data retention time
Notes:
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. fPump is defined as the charge pump clock frequency required for program, erase, and margin read operations.
3. flsPulses is defined as the number of pulses used to program the FLASH using the required smart program algorithm.
4. tPROG is defined as the amount of time during one page program cycle that HVEN is held high.
5. tRow is defined as the cumulative time a row can see the program voltage before the row must be erased before further
programming.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire temperature range for at least the minimum time specified.
Advance Information
398
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 24. Mechanical Specifications
24.1 Contents
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
24.3 40-Pin Plastic Dual In-Line Package (DIP). . . . . . . . . . . . . . .400
24.4 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .401
24.2 Introduction
This section gives the dimensions for:
• 40-pin plastic dual in-line package (case 711-03)
• 44-pin plastic quad flat pack (case 824E-02)
The following figures show the latest package drawings at the time of this
publication. To make sure that you have the latest package
specifications, please visit the Freescale website at http://freescale.com.
Follow Worldwide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
399
24.3 40-Pin Plastic Dual In-Line Package (DIP)
NOTES:
1. POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
40
1
21
20
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
A
B
C
D
F
G
H
J
K
L
M
N
51.69
13.72
3.94
0.36
1.02
52.45
14.22
5.08
0.56
1.52
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
L
A
C
N
2.54 BSC
0.100 BSC
1.65
0.20
2.92
15.24 BSC
0°
2.16
0.38
3.43
0.065
0.008
0.115
0.600 BSC
0°
0.085
0.015
0.135
J
K
M
H
G
F
D
SEATING
PLANE
1°
1.02
1°
0.040
0.51
0.020
Advance Information
400
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
24.4 44-Pin Plastic Quad Flat Pack (QFP)
S
M
S
S
S
S
0.20 (0.008)
T L-M
N
N
-L-, -M-, -N-
A
M
0.20 (0.008)
H L-M
PIN 1
0.05 (0.002) L-M
IDENT
J1
J1
G
44
34
33
1
VIEW Y
3 PL
-L-
-M-
F
PLATING
BASE METAL
J
B1
VIEW Y
D
M
S
S
N
0.20 (0.008)
T L-M
11
23
G 40X
12
22
SECTION J1-J1
44 PL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-N-
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT
DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
M
VIEW P
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE D DIMENSION TO EXCEED 0.530
(0.021).
E
DATUM
C
-H-
PLANE
0.01 (0.004)
W
-T-
Y
MILLIMETERS
INCHES
MIN MAX
0.390 0.398
0.390 0.398
0.079 0.087
DIM
A
MIN
9.90
9.90
2.00
0.30
2.00
0.30
MAX
10.10
10.10
2.21
B
C
q1
D
0.45 0.0118 0.0177
E
2.10
0.40
0.80 BSC
0.079 0.083
0.012 0.016
0.031 BSC
F
R R1
G
J
0.13
0.65
5°
0.23
0.95
10°
0.005 0.009
0.026 0.037
DATUM
PLANE
-H-
K
R R2
M
S
5°
10°
12.95
12.95
0.000
5°
13.45
13.45
0.210
10°
0.510 0.530
0.510 0.530
0.000 0.008
V
W
Y
K
5°
10°
q2
A1
A1
0.450 REF
0.018 REF
0.005 0.007
0.063 REF
B1 0.130
0.170
C1
C1
R1
1.600 REF
0.130
0.300
0.300
10°
0.005
0.012
R2 0.130
0.005 0.012
VIEW P
q1
q2
5°
0°
5°
0°
10°
7°
7°
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
401
Advance Information
402
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information — MC68HC908GP20
Section 25. Ordering Information
25.1 Contents
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
25.2 Introduction
This section contains ordering numbers for the MC68HC908GP20.
25.3 MC Order Numbers
Table 25-1. MC Order Numbers
Operating
MC order number(1)
MC68HC908GP20CP
temperature range
–40 °C to +85 °C
–40 °C to +85 °C
MC68HC908GP20CFB
1. P = Plastic dual in-line package
FB = Plastic quad flat pack
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
403
Advance Information
404
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
How to Reach Us:
Home Page:
www.freescale.com
For information on Freescale.s Environmental Products program, go to
http://www.freescale.com/epp.
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Semiconductor was negligent regarding the design or manufacture of the part.
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. The ARM
POWERED logo is a registered trademark of ARM Limited. ARM7TDMI-S is a
trademark of ARM Limited. Java and all other Java-based marks are trademarks or
registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The
Bluetooth trademarks are owned by their proprietor and used by Freescale
Semiconductor, Inc. under license.
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
© Freescale Semiconductor, Inc. 2005. All rights reserved.
LDCForFreescaleSemiconductor@hibbertgroup.com
Rev. 2.1
MC68HC908GP20/D
08/2005
相关型号：
MC68HC908GP20CFB
Microcontroller, 8-Bit, FLASH, 68HC08 CPU, 8.2MHz, HCMOS, PQFP44, PLASTIC, QFP-44
MOTOROLA
©2020 ICPDF网 联系我们和版权申明