MC68HC908GP32_技术文档

Freescale Semiconductor, Inc.

MC68HC908GP32

MC68HC08GP32

Technical Data

M68HC08

Microcontrollers

MC68HC908GP32/H

Rev. 6, 8/2002

MOTOROLA.COM/SEMICONDUCTORS

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MC68HC908GP32

MC68HC08GP32

Technical Data

Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets and/or

specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for

each customer application by customer's technical experts. Motorola does not convey

any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Motorola product could create a

situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall

indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and the Stylized M logo are registered trademarks of Motorola, Inc.

digital dna is a trademark of Motorola, Inc.

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Revision History

To provide the most up-to-date information, the revision of our

documents on the World Wide Web will be the most current. Your printed

copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://motorola.com/semiconductors

The following revision history table summarizes changes contained in

this document. For your convenience, the page number designators

have been linked to the appropriate location.

Revision History

Revision

Level

Page

Date

Description

Number(s)

Section 22. Timer Interface Module (TIM) — Timer

341

discrepancies corrected throughout this section.

August, 2002

6

Section 24. Mechanical Specifications — Replaced incorrect

393

44-pin QFP drawing, case 824E to case 824A.

In Table 15-1, second cell in "Comment" column, corrected PTC

to PTC1.

199

In Figure 21-2, Timebase control register, bit 0 is a reserved bit.

337

387

397

July, 2001

5

Updated crystal oscillator component values in 23.17.1 CGM

Component Specifications.

Added appendix A: MC68HC08GP32 — ROM part.

Technical Data

2

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . .31

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .43

Section 3. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .57

Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . .69

Section 5. Analog-to-Digital Converter (ADC) . . . . . . . .87

Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . .97

Section 7. Clock Generator Module (CGMC) . . . . . . . .105

Section 8. Configuration Register (CONFIG) . . . . . . . .137

Section 9. Computer Operating Properly (COP) . . . . .141

Section 10. Central Processor Unit (CPU) . . . . . . . . . .147

Section 11. FLASH Memory . . . . . . . . . . . . . . . . . . . . . .165

Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . .175

Section 13. Keyboard Interrupt Module (KBI). . . . . . . .181

Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .189

Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .195

Section 16. Input/Output (I/O) Ports . . . . . . . . . . . . . . .211

Section 17. Random-Access Memory (RAM) . . . . . . . .235

Section 18. Serial Communications Interface

Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .237

Section 19. System Integration Module (SIM) . . . . . . .277

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

3

List of Sections

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Sections

Section 20. Serial Peripheral Interface Module (SPI). .303

Section 21. Timebase Module (TBM). . . . . . . . . . . . . . .335

Section 22. Timer Interface Module (TIM) . . . . . . . . . . .341

Section 23. Electrical Specifications. . . . . . . . . . . . . . .365

Section 24. Mechanical Specifications . . . . . . . . . . . . .391

Section 25. Ordering Information . . . . . . . . . . . . . . . . .395

Appendix A. MC68HC08GP32 . . . . . . . . . . . . . . . . . . . .397

Technical Data

4

MC68HC908GP32•MC68HC08GP32 — Rev. 6

List of Sections

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

Table of Contents

Section 1. General Description

1.1

1.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3

1.3.1

1.3.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Standard Features of the MC68HC908GP32. . . . . . . . . . . .32

Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.4

1.5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Pins (V_DDand V_SS). . . . . . . . . . . . . . . . . . . .39

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .40

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

CGM Power Supply Pins (V_DDAand V_SSA) . . . . . . . . . . . . .41

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .41

ADC Power Supply/Reference Pins

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

(V_DDAD/V_REFHand V_SSAD/V_REFL) . . . . . . . . . . . . . . . . . .41

Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) .41

Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .41

1.6.8

1.6.9

1.6.10 Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . .42

1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . .42

1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

5

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 2. Memory Map

2.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .43

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.2

2.3

2.4

2.5

Section 3. Low-Power Modes

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2

3.2.1

3.2.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3

3.3.1

3.3.2

Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4

3.4.1

3.4.2

Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5

3.5.1

3.5.2

Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6

3.6.1

3.6.2

Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7

3.7.1

3.7.2

Computer Operating Properly Module (COP). . . . . . . . . . . . . .61

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.8

3.8.1

3.8.2

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9

Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62

Technical Data

6

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

3.9.1

3.9.2

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63

3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .63

3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .64

3.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .64

3.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Section 4. Resets and Interrupts

4.1

4.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3

4.3.1

4.3.2

4.3.3

4.3.3.1

4.3.3.2

4.3.3.3

4.3.3.4

4.3.3.5

4.3.4

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

COP Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . .73

Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .74

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

7

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

4.4

4.4.1

4.4.2

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

CGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

TIM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

KBD0–KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.2.1

4.4.2.2

4.4.2.3

4.4.2.4

4.4.2.5

4.4.2.6

4.4.2.7

4.4.2.8

4.4.2.9

4.4.2.10

4.4.2.11

4.4.3

4.4.3.1

4.4.3.2

4.4.3.3

ADC (Analog-to-Digital Converter). . . . . . . . . . . . . . . . . .83

TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . .83

Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .84

Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .85

Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .85

Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .86

Section 5. Analog-to-Digital Converter (ADC)

5.1

5.2

5.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.5

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6

5.6.1

5.6.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.7

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Technical Data

8

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

5.7.1

ADC Analog Power Pin (V_DDAD)/

ADC Voltage Reference High Pin (V_REFH) . . . . . . . . . . .92

ADC Analog Ground Pin (V_SSAD)/

ADC Voltage Reference Low Pin (V_REFL). . . . . . . . . . . .92

ADC Voltage In (V_ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

5.7.2

5.7.3

5.8

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . .93

ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

5.8.1

5.8.2

5.8.3

Section 6. Break Module (BRK)

6.1

6.2

6.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

6.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Flag Protection During Break Interrupts. . . . . . . . . . . . . . .100

CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .100

COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.5.1

6.5.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

6.6

Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Break Status and Control Register. . . . . . . . . . . . . . . . . . .101

Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .102

Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . .104

6.6.1

6.6.2

6.6.3

6.6.4

Section 7. Clock Generator Module (CGMC)

7.1

7.2

7.3

7.4

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

9

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

7.4.1

Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . .109

Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .109

PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .111

Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .111

Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Special Programming Exceptions . . . . . . . . . . . . . . . . . . .117

Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .117

CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . .118

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

7.5

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .119

Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .119

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .120

PLL Analog Power Pin (V_DDA) . . . . . . . . . . . . . . . . . . . . . .120

PLL Analog Ground Pin (V_SSA) . . . . . . . . . . . . . . . . . . . . .120

Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .120

Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . .120

Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .121

CGMC Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .121

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

7.5.9

7.5.10 CGMC CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . .121

7.6

CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .125

PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . .127

PLL Multiplier Select Register Low. . . . . . . . . . . . . . . . . . .128

PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .129

PLL Reference Divider Select Register . . . . . . . . . . . . . . .130

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

7.8

Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . .132

7.8.1

7.8.2

7.8.3

7.9

Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .133

Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .133

Parametric Influences on Reaction Time . . . . . . . . . . . . . .134

Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

7.9.1

7.9.2

7.9.3

Technical Data

10

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 8. Configuration Register (CONFIG)

8.1

8.2

8.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Section 9. Computer Operating Properly (COP)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

9.1

9.2

9.3

9.4

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.5

9.6

9.7

COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9.8

9.8.1

9.8.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.9

COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .146

Section 10. Central Processor Unit (CPU)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

11

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

10.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

10.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

10.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .155

10.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Section 11. FLASH Memory

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .167

11.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .168

11.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .169

11.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . .172

11.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

11.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Technical Data

12

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 12. External Interrupt (IRQ)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

12.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

12.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .179

12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .179

Section 13. Keyboard Interrupt Module (KBI)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .186

13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

13.8.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .187

13.8.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .188

Section 14. Low-Voltage Inhibit (LVI)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

13

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

14.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .192

14.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .192

14.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

Section 15. Monitor ROM (MON)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

15.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .198

15.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

15.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Section 16. Input/Output (I/O) Ports

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

16.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

16.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .216

16.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . .218

16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

16.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

16.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .220

Technical Data

14

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

16.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

16.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .223

16.5.3 Port C Input Pullup Enable Register. . . . . . . . . . . . . . . . . .225

16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

16.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

16.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . .228

16.6.3 Port D Input Pullup Enable Register. . . . . . . . . . . . . . . . . .230

16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

16.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

16.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .232

Section 17. Random-Access Memory (RAM)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Section 18. Serial Communications

Interface Module (SCI)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18.5.2.1

18.5.2.2

18.5.2.3

18.5.2.4

18.5.2.5

18.5.2.6

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .245

Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .247

Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .247

18.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

15

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

18.5.3.1

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .252

Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

18.5.3.2

18.5.3.3

18.5.3.4

18.5.3.5

18.5.3.6

18.5.3.7

18.5.3.8

18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .258

18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

18.8.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .258

18.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .258

18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

18.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .259

18.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .262

18.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .265

18.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

18.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

18.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

18.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .274

Section 19. System Integration Module (SIM)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278

19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .281

19.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

19.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . .281

19.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .282

19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .282

19.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

19.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .284

Technical Data

16

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

19.4.2.1

19.4.2.2

19.4.2.3

19.4.2.4

19.4.2.5

19.4.2.6

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

Computer Operating Properly (COP) Reset. . . . . . . . . .286

Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .286

Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .286

Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .287

Monitor Mode Entry Module Reset (MODRST) . . . . . . .287

19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

19.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .287

19.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . .288

19.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .288

19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

19.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

19.6.1.1

19.6.1.2

19.6.1.3

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .292

19.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

19.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

19.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .295

19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

19.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .298

19.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .300

19.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .301

Section 20. Serial Peripheral Interface Module (SPI)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

20.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

17

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

20.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

20.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .309

20.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .310

20.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .312

20.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .313

20.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .315

20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

20.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

20.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .324

20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

20.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .325

20.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .325

20.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

20.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

20.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

20.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

20.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .330

20.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

Section 21. Timebase Module (TBM)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

Technical Data

18

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .337

21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338

21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

21.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

21.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

Section 22. Timer Interface Module (TIM)

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

22.5.3.1

22.5.3.2

Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .348

Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .349

22.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .349

22.5.4.1

22.5.4.2

22.5.4.3

Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .350

Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .351

PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

22.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

22.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .356

22.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

19

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

22.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .359

22.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .360

22.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .363

Section 23. Electrical Specifications

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .366

23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .367

23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .368

23.7 3.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .370

23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372

23.9 3.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

23.10 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .374

23.11 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . .377

23.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

23.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

23.14 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

23.15 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .384

23.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .387

23.17 Clock Generation Module Characteristics . . . . . . . . . . . . . . .387

23.17.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .387

23.17.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .388

23.18 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

Technical Data

20

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 24. Mechanical Specifications

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

24.3 40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .392

24.4 42-Pin Shrink Dual in-Line Package (SDIP) . . . . . . . . . . . . . .392

24.5 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .393

Section 25. Ordering Information

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

Appendix A. MC68HC08GP32

A.1

A.2

A.3

A.4

A.5

A.6

A.7

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400

Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

A.8

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .403

5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . .403

3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . .404

Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .405

A.8.1

A.8.2

A.8.3

A.8.4

A.9

ROM MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . .406

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

21

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Technical Data

22

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

List of Figures

Figure

Title

Page

1-1

1-2

1-3

1-4

1-5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .37

42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .38

44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2-1

2-2

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .47

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .74

Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .77

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .85

Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .85

Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .86

5-1

5-2

5-3

5-4

ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

ADC Status and Control Register (ADSCR). . . . . . . . . . . . . . .93

ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . .95

6-1

6-2

6-3

6-4

6-5

6-6

6-7

Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .99

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Break Status and Control Register (BRKSCR). . . . . . . . . . . .101

Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .102

Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .102

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .103

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .104

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

23

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

Figure

Title

Page

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . .119

CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .122

PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .123

PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .126

PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .127

PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .128

PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .129

PLL Reference Divider Select Register (PMDS) . . . . . . . . . .130

7-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

8-1

8-2

Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .138

Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .138

9-1

9-2

COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .145

10-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . .152

11-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . .166

11-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . .171

11-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . .172

11-4 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . .172

12-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .177

12-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .177

12-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .180

13-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .183

13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

13-3 Keyboard Status and Control Register (INTKBSCR) . . . . . . .187

13-4 Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . .188

14-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Technical Data

24

MC68HC908GP32•MC68HC08GP32 — Rev. 6

List of Figures

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

Figure

Title

Page

14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .191

14-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .193

15-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

15-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .201

15-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .208

15-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .209

16-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .212

16-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .215

16-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .216

16-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

16-5 Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . .218

16-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .219

16-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .220

16-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

16-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .222

16-10 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .223

16-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

16-12 Port C Input Pullup Enable Register (PTCPUE). . . . . . . . . . .225

16-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .226

16-14 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .228

16-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-16 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . . . .230

16-17 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .231

16-18 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .232

16-19 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

18-1 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .241

18-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .242

18-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

18-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .249

18-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

25

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

Figure

Title

Page

18-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

18-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

18-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .260

18-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .263

18-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .265

18-12 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .268

18-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

18-14 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .272

18-15 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .273

18-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .274

19-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

19-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .280

19-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

19-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

19-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .284

19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

19-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

19-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .291

19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .293

19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .293

19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .294

19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

19-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .296

19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .296

19-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .298

19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .298

19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .300

19-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .301

20-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .306

20-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .307

Technical Data

26

MC68HC908GP32•MC68HC08GP32 — Rev. 6

List of Figures

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

Figure

Title

Page

23-4 Typical High-Side Driver Characteristics –

Port PTC4–PTC0 (V_DD= 2.7 Vdc) . . . . . . . . . . . . . . . . . .375

23-5 Typical High-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (V_DD= 5.5 Vdc). . . . . . . .376

23-6 Typical High-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (V_DD= 2.7 Vdc). . . . . . . .376

23-7 Typical Low-Side Driver Characteristics –

Port PTA7–PTA0 (V_DD= 5.5 Vdc). . . . . . . . . . . . . . . . . . .377

23-8 Typical Low-Side Driver Characteristics –

Port PTA7–PTA0 (V_DD= 2.7 Vdc). . . . . . . . . . . . . . . . . . .377

23-9 Typical Low-Side Driver Characteristics –

Port PTC4–PTC0 (V_DD= 4.5 Vdc) . . . . . . . . . . . . . . . . . .378

23-10 Typical Low-Side Driver Characteristics –

Port PTC4–PTC0 (V_DD= 2.7 Vdc) . . . . . . . . . . . . . . . . . .378

23-11 Typical Low-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (V_DD= 5.5 Vdc). . . . . . . .379

23-12 Typical Low-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (V_DD= 2.7 Vdc). . . . . . . .379

23-13 Typical Operating IDD,

with All Modules Turned On (–40 °C to 85 °C) . . . . . . . . .380

23-14 Typical Wait Mode IDD,

with all Modules Disabled (–40 °C to 85 °C) . . . . . . . . . . .380

23-15 Typical Stop Mode IDD,

with all Modules Disabled (–40 °C to 85 °C) . . . . . . . . . . .381

23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

23-17 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386

A-1 MC68HC08GP32 Block Diagram . . . . . . . . . . . . . . . . . . . . . .399

A-2 MC68HC08GP32 Memory Map . . . . . . . . . . . . . . . . . . . . . . .400

A-3 Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . .402

A-4 Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . .402

A-5 Typical Operating I_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404

A-6 Typical Wait Mode I_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

A-7 Typical Stop Mode I_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

Technical Data

28

MC68HC908GP32•MC68HC08GP32 — Rev. 6

List of Figures

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32

List of Tables

Table

Title

Page

2-1

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4-1

4-2

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5-1

5-2

Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7-1

7-3

7-2

Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .125

PRE1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .125

10-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

14-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

15-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .199

15-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .203

15-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .205

15-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .205

15-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .206

15-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .206

15-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .207

15-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .207

16-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .214

16-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

16-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

29

List of Tables

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Tables

Table

Title

Page

16-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

16-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

18-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

18-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

18-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

18-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .262

18-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .274

18-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

18-8 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .276

19-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .279

19-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

19-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

19-4 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

20-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

20-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .333

21-1 Timebase Rate Selection for OSC1 = 32.768-kHz. . . . . . . . .337

22-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

22-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .362

25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

A-1 Summary of MC68HC08GP32 and MC68HC908GP32

differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

A-2 ROM MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . .406

Technical Data

30

MC68HC908GP32•MC68HC08GP32 — Rev. 6

List of Tables

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 1. General Description

1.1 Contents

1.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3

1.3.1

1.3.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Standard Features of the MC68HC908GP32. . . . . . . . . . . .32

Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.4

1.5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Pins (V_DDand V_SS). . . . . . . . . . . . . . . . . . . .39

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .40

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

CGM Power Supply Pins (V_DDAand V_SSA) . . . . . . . . . . . . .41

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .41

ADC Power Supply/Reference Pins

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

(V_DDAD/V_REFHand V_SSAD/V_REFL) . . . . . . . . . . . . . . . . . .41

Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) .41

Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .41

1.6.8

1.6.9

1.6.10 Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . .42

1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . .42

1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

31

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.2 Introduction

The MC68HC908GP32 is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the

family use the enhanced M68HC08 central processor unit (CPU08) and

are available with a variety of modules, memory sizes and types, and

package types.

1.3 Features

For convenience, features have been organized to reflect:

•

Standard features of the MC68HC908GP32

Features of the CPU08

1.3.1 Standard Features of the MC68HC908GP32

•

High-performance M68HC08 architecture optimized for

C-compilers

•

Fully upward-compatible object code with M6805, M146805, and

M68HC05 Families

•

8-MHz internal bus frequency

FLASH program memory security¹

On-chip programming firmware for use with host personal

computer which does not require high voltage for entry

•

In-system programming

System protection features:

– Optional computer operating properly (COP) reset

– Low-voltage detection with optional reset and selectable trip

points for 3.0-V and 5.0-V operation

– Illegal opcode detection with reset

– Illegal address detection with reset

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.

Technical Data

32

MC68HC908GP32•MC68HC08GP32 — Rev. 6

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Features

•

Low-power design; fully static with stop and wait modes

Standard low-power modes of operation:

– Wait mode

– Stop mode

•

Master reset pin and power-on reset (POR)

32 Kbytes of on-chip FLASH memory with in-circuit programming

capabilities of FLASH program memory

•

512 bytes of on-chip random-access memory (RAM)

Serial peripheral interface module (SPI)

Serial communications interface module (SCI)

Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)

with selectable input capture, output compare, and PWM

capability on each channel

•

8-channel, 8-bit successive approximation analog-to-digital

converter (ADC)

BREAK module (BRK) to allow single breakpoint setting during

in-circuit debugging

•

Internal pullups on IRQ and RST to reduce customer system cost

Clock generator module with on-chip 32-kHz crystal compatible

PLL (phase-lock loop)

•

Up to 33 general-purpose input/output (I/O) pins, including:

– 26 shared-function I/O pins

– Five or seven dedicated I/O pins, depending on package

choice

•

Selectable pullups on inputs only on ports A, C, and D. Selection

is on an individual port bit basis. During output mode, pullups are

disengaged.

•

High current 10-mA sink/10-mA source capability on all port pins

Higher current 15-mA sink/source capability on PTC0–PTC4

Timebase module with clock prescaler circuitry for eight user

selectable periodic real-time interrupts with optional active clock

source during stop mode for periodic wakeup from stop using an

external 32-kHz crystal

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

33

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

•

Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG

register to allow user selection of having the oscillator enabled or

disabled during stop mode

•

8-bit keyboard wakeup port

5-mA maximum current injection on all port pins to maintain input

protection

•

40-pin plastic dual-in-line package (PDIP), 42-pin shrink dual-in-

line package (SDIP), or 44-pin quad flat pack (QFP)

Specific features of the MC68HC908GP32 in 40-pin PDIP are:

– Port C is only 5 bits: PTC0–PTC4

– Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM

module

•

Specific features of the MC68HC908GP32 in 42-pin SDIP are:

– Port C is only 5 bits: PTC0–PTC4

– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules

Specific features of the MC68HC908GP32 in 44-pin QFP are:

– Port C is 7 bits: PTC0–PTC6

– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules

1.3.2 Features of the CPU08

Features of the CPU08 include:

•

Enhanced HC05 programming model

Extensive loop control functions

16 addressing modes (eight more than the HC05)

16-bit index register and stack pointer

Memory-to-memory data transfers

Fast 8 × 8 multiply instruction

Fast 16/8 divide instruction

Binary-coded decimal (BCD) instructions

Optimization for controller applications

Efficient C language support

Technical Data

34

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

MCU Block Diagram

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908GP32. Text in

parentheses within a module block indicates the module name. Text in

parentheses next to a signal indicates the module which uses the signal.

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

35

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Assignments

1.5 Pin Assignments

V

(PLL)

PTA7/KBD7

DDA

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PTA6/KBD6

PTA5/KBD5

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

SSA

2

CGMXFC (PLL)

OSC2

3

4

OSC1

RST

5

6

PTC0

7

PTC1

8

V

/V

(ADC)

PTC2

SSAD REFL

9

/V

PTC3

DDAD REFH

10

11

12

13

14

15

16

17

18

19

20

PTC4

PTB7/AD7

PTE0/TxD

PTE1/RxD

IRQ

PTB6/AD6

PTB5/AD5

PTB4/AD4

PTB3/AD3

PTB2/AD2

PTD0/SS

PTD1/MISO

PTD2/MOSI

PTD3/SPSCK

PTB1/AD1

PTB0/AD0

V

PTD5/T1CH1

PTD4/T1CH0

SS

V

DD

Pins not available on 40-pin package

Internal connection

Connected to ground

Unconnected

PTC5

PTC6

PTD6/T2CH0

PTD7/T2CH1

Unconnected

Figure 1-2. 40-Pin PDIP Pin Assignments

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

37

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

PTA7/KBD7

PTA6/KBD6

PTA5/KBD5

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

V

(PLL)

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

DDA

V

2

SSA

CGMXFC (PLL)

OSC2

3

4

OSC1

RST

5

6

PTC0

7

PTC1

8

V

/V

(ADC)

SSAD REFL

PTC2

9

/V

DDAD REFH

PTC3

10

11

12

13

14

15

16

17

18

19

20

21

PTB7/AD7

PTC4

PTB6/AD6

PTB5/AD5

PTB4/AD4

PTB3/AD3

PTB2/AD2

PTE0/TxD

PTE1/RxD

IRQ

PTD0/SS

PTD1/MISO

PTD2/MOSI

PTD3/SPSCK

PTB1/AD1

PTB0/AD0

PTD7/T2CH1

V

SS

PTD6/T2CH0

PTD5/T1CH1

V

DD

PTD4/T1CH0

Pins not available on 42-pin package

Internal connection

Connected to ground

PTC5

PTC6

Figure 1-3. 42-Pin SDIP Pin Assignments

Technical Data

38

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Functions

RST

PTC0

PTA1/KBD1

PTA0/KBD0

1

33

2

32

31

30

29

28

27

26

25

24

PTC1

V

/V

3

SSAD REFL

PTC2

/V

4

DDAD REFH

PTC3

PTB7/AD7

PTB6/AD6

PTB5/AD5

5

PTC4

6

PTC5

7

PTC6

PTB4/AD4

PTB3/AD3

PTB2/AD2

PTB1/AD1

8

PTE0/TxD

PTE1/RxD

IRQ

9

10

11

23

Figure 1-4. 44-Pin QFP Pin Assignments

1.6 Pin Functions

Descriptions of the pin functions are provided here.

1.6.1 Power Supply Pins (V and V )

DD

SS

V

_DDand V_SSare the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 1-5

shows. Place the C1 bypass capacitor as close to the MCU as possible.

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

39

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Use a high-frequency-response ceramic capacitor for C1. C2 is an

optional bulk current bypass capacitor for use in applications that require

the port pins to source high current levels.

MCU

V

SS

DD

C1

0.1 µF

+

C2

V

DD

NOTE: Component values shown

represent typical applications.

Figure 1-5. Power Supply Bypassing

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator

circuit. See Section 7. Clock Generator Module (CGMC).

1.6.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. This pin contains an internal pullup

resistor. See Section 19. System Integration Module (SIM).

1.6.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. This pin contains an

internal pullup resistor. See Section 12. External Interrupt (IRQ).

Technical Data

40

MC68HC908GP32•MC68HC08GP32 — Rev. 6

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Functions

1.6.5 CGM Power Supply Pins (V

and V

)

DDA

SSA

V_DDAand V_SSAare the power supply pins for the analog portion of the

clock generator module (CGM). Connect the V_DDApin to the same

voltage potential as V_DD, and the V_SSApin to the same voltage potential

as V_SS. Decoupling of these pins should be as per the digital supply. See

Section 7. Clock Generator Module (CGMC).

1.6.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Section 7. Clock Generator Module (CGMC).

1.6.7 ADC Power Supply/Reference Pins (V

/V

and V

/V

)

DDAD REFH

SSAD REFL

V_DDADand V_SSADare the power supply pins for the analog-to-digital

converter (ADC). Connect the V_DDADpin to the same voltage potential

as V_DD, and the V_SSADpin to the same voltage potential as V_SS.

Decoupling of these pins should be as per the digital supply. See

Section 5. Analog-to-Digital Converter (ADC).

V_REFHis the high reference supply for the ADC, and is internally

connected to V_DDAD

V_REFLis the low reference supply for the ADC, and is internally

connected to V_SSAD

.

1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7—PTA0/KBD0)

PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all

of the port A pins can be programmed to serve as keyboard interrupt

pins. See Section 16. Input/Output (I/O) Ports and Section 13.

Keyboard Interrupt Module (KBI).

These port pins also have selectable pullups when configured for input

mode. The pullups are disengaged when configured for output mode.

The pullups are selectable on an individual port bit basis.

1.6.9 Port B I/O Pins (PTB7/AD7—PTB0/AD0)

PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can

also be used for analog-to-digital converter (ADC) inputs. See Section

16. Input/Output (I/O) Ports and Section 5. Analog-to-Digital

Converter (ADC).

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

41

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.6.10 Port C I/O Pins (PTC6—PTC0)

PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See

Section 16. Input/Output (I/O) Ports. PTC5 and PTC6 are only

available on 44-pin QFP package.

These port pins also have selectable pullups when configured for input

mode. The pullups are disengaged when configured for output mode.

The pullups are selectable on an individual port bit basis.

1.6.11 Port D I/O Pins (PTD7/T2CH1—PTD0/SS)

PTD7–PTD0 are special-function, bidirectional I/O port pins.

PTD0–PTD3 can be programmed to be serial peripheral interface (SPI)

pins, while PTD4–PTD7 can be individually programmed to be timer

interface module (TIM1 and TIM2) pins. See Section 22. Timer

Interface Module (TIM), Section 20. Serial Peripheral Interface

Module (SPI), and Section 16. Input/Output (I/O) Ports. PTD6 and

PTD7 are only available on 42-SDIP and 44-pin QFP packages.

These port pins also have selectable pullups when configured for input

mode. The pullups are disengaged when configured for output mode.

The pullups are selectable on an individual port bit basis.

1.6.12 Port E I/O Pins (PTE1/RxD—PTE0/TxD)

PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins

can also be programmed to be serial communications interface (SCI)

pins. See Section 18. Serial Communications Interface Module (SCI)

and Section 16. Input/Output (I/O) Ports.

NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic

level (either V_DDor V_SS). Although the I/O ports of the

MC68HC908GP32 do not require termination, termination is

recommended to reduce the possibility of static damage.

Technical Data

42

MC68HC908GP32•MC68HC08GP32 — Rev. 6

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 2. Memory Map

2.1 Contents

2.2

2.3

2.4

2.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .43

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.2 Introduction

The CPU08 can address 64 Kbytes of memory space. The memory

map, shown in Figure 2-1, includes:

•

32,256 bytes of user FLASH memory

512 bytes of random-access memory (RAM)

36 bytes of user-defined vectors

307 bytes of monitor ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address

reset. In the memory map (Figure 2-1) and in register figures in this

document, unimplemented locations are shaded.

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

43

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU

operation. In the Figure 2-1 and in register figures in this document,

reserved locations are marked with the word Reserved or with the

letter R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area

of $0000–$003F. Additional I/O registers have these addresses:

•

$FE00; SIM break status register, SBSR

$FE01; SIM reset status register, SRSR

$FE02; reserved, SUBAR

$FE03; SIM break flag control register, SBFCR

$FE04; interrupt status register 1, INT1

$FE05; interrupt status register 2, INT2

$FE06; interrupt status register 3, INT3

$FE07; reserved

$FE08; FLASH control register, FLCR

$FE09; break address register high, BRKH

$FE0A; break address register low, BRKL

$FE0B; break status and control register, BRKSCR

$FE0C; LVI status register, LVISR

$FF7E; FLASH block protect register, FLBPR

$FFFF; COP control register, COPCTL

Data registers are shown in Figure 2-2. Table 2-1 is a list of vector

locations.

Technical Data

44

MC68HC908GP32•MC68HC08GP32 — Rev. 6

Memory Map

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

$0000

I/O Registers

64 Bytes

↓

$003F

$0040

↓

RAM

512 Bytes

$023F

$0240

↓

Unimplemented

32,192 Bytes

$7FFF

$8000

↓

FLASH Memory

32,256 Bytes

$FDFF

$FE00

$FE01

$FE02

$FE03

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

$FE0A

$FE0B

$FE0C

$FE0D

↓

SIM Break Status Register (SBSR)

SIM Reset Status Register (SRSR)

Reserved (SUBAR)

SIM Break Flag Control Register (SBFCR)

Interrupt Status Register 1 (INT1)

Interrupt Status Register 2 (INT2)

Interrupt Status Register 3 (INT3)

Reserved

FLASH Control Register (FLCR)

Break Address Register High (BRKH)

Break Address Register Low (BRKL)

Break Status and Control Register (BRKSCR)

LVI Status Register (LVISR)

Unimplemented

3 Bytes

$FE0F

Figure 2-1. Memory Map

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

45

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

$FE10

↓

Unimplemented

16 Bytes

Reserved for Compatibility with Monitor Code

for A-Family Parts

$FE1F

$FE20

↓

Monitor ROM

307 Bytes

$FF52

$FF53

↓

Unimplemented

43 Bytes

$FF7D

$FF7E

$FF7F

↓

FLASH Block Protect Register (FLBPR)

Unimplemented

93 Bytes

$FFDB

$FFDC

↓

Note: $FFF6–$FFFD

reserved for

8 security bytes

FLASH Vectors

36 Bytes

$FFFF

Figure 2-1. Memory Map (Continued)

Technical Data

46

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

PTA7

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

Port A Data Register

(PTA)

$0000

Unaffected by reset

PTB4 PTB3

Unaffected by reset

PTC4 PTC3

Unaffected by reset

PTD4 PTD3

Unaffected by reset

PTB7

0

PTB6

PTC6

PTD6

PTB5

PTC5

PTD5

PTB2

PTC2

PTD2

PTB1

PTC1

PTD1

PTB0

PTC0

PTD0

Port B Data Register

(PTB)

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

Port C Data Register

(PTC)

PTD7

Port D Data Register

(PTD)

DDRA7

0

DDRA6

0

DDRA5

0

DDRA4

0

DDRA3

DDRA2

DDRA1

DDRA0

Data Direction Register A

(DDRA)

0

DDRB3

0

DDRB2

0

DDRB1

0

DDRB0

0

DDRB7

DDRB6

0

DDRB5

0

DDRB4

0

Data Direction Register B

(DDRB)

0

DDRC6

0

DDRC5

0

DDRC4

0

DDRC3 DDRC2 DDRC1 DDRC0

Data Direction Register C

(DDRC)

0

DDRD7

DDRD6

DDRD5

DDRD4

DDRD3 DDRD2 DDRD1 DDRD0

Data Direction Register D

(DDRD)

0

PTE1

PTE0

Port E Data Register

(PTE)

Unaffected by reset

Unimplemented Write:

Reset:

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

47

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Unimplemented Write:

Reset:

$000A

0

Read:

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

Unimplemented Write:

Reset:

0

DDRE1

0

DDRE0

0

Read:

Data Direction Register E

(DDRE)

Write:

Reset:

Read:

0

Port A Input Pullup Enable

PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Register Write:

(PTAPUE)

Reset:

0

Read:

Port C Input Pullup Enable

PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0

Register Write:

(PTCPUE)

Reset:

0

Read:

Port D Input Pullup Enable

PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Register Write:

(PTDPUE)

Reset:

0

SPRIE

0

SPE

0

Read:

DMAS

SPMSTR

CPOL

CPHA

SPWOM

0

SPTIE

0

SPI Control Register

(SPCR)

Write:

Reset:

0

1

0

1

Read: SPRF

OVRF

MODF

SPTE

SPI Status and Control

ERRIE

MODFEN

SPR1

SPR0

Register Write:

(SPSCR)

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

0

1

0

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SPI Data Register

(SPDR)

Unaffected by reset

LOOPS

0

ENSCI

0

TXINV

0

M

WAKE

0

ILTY

0

PEN

0

PTY

0

SCI Control Register 1

(SCC1)

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)

Technical Data

48

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

TCIE

0

5

SCRIE

0

4

ILIE

0

3

TE

2

RE

0

1

RWU

0

Bit 0

SBK

0

Read:

Write:

Reset:

Read:

Write:

Reset:

SCTIE

SCI Control Register 2

(SCC2)

$0014

0

R8

T8

DMARE DMATE

ORIE

NEIE

FEIE

PEIE

SCI Control Register 3

(SCC3)

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

U

0

Read: SCTE

Write:

TC

SCRF

IDLE

OR

NF

FE

PE

SCI Status Register 1

(SCS1)

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

1

0

BKF

RPF

SCI Status Register 2

(SCS2)

0

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SCI Data Register

(SCDR)

Unaffected by reset

SCP1

SCP0

R

SCR2

SCR1

0

SCR0

0

SCI Baud Rate Register

(SCBR)

0

KEYF

0

ACKK

0

Keyboard Status

IMASKK MODEK

and Control Register Write:

(INTKBSCR)

Reset:

0

KBIE7

0

KBIE1

0

Read:

Keyboard Interrupt Enable

KBIE6

0

KBIE5

0

KBIE4

0

KBIE3

KBIE2

0

KBIE0

Register Write:

(INTKBIER)

Reset:

0

Read: TBIF

Time Base Module Control

Register Write:

TBR2

TBR1

TBR0

TBIE

TBON

0

R

TACK

0

(TBCR)

Reset:

Read:

0

MODE

0

IRQF

IRQ Status and Control

IMASK

Register Write:

(INTSCR)

Reset:

ACK

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

49

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Register Name

Configuration Register 2

Bit 7

6

5

4

3

2

1

Bit 0

Read:

0

OSC-

STOPENB

SCIBD-

SRC

$001E

(CONFIG2)† Write:

Reset:

0

STOP

0

COPD

0

Read:

COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3^†SSREC

Configuration Register 1

(CONFIG1)^†

$001F

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027

Write:

Reset:

Read:

0

TOF

0

Timer 1 Status and Control

TOIE

TSTOP

PS2

PS1

PS0

Register Write:

(T1SC)

Reset:

TRST

0

1

0

9

0

Read: Bit 15

14

13

12

11

10

Bit 8

Timer 1 Counter

Register High Write:

(T1CNTH)

Reset:

0

6

0

5

0

4

0

3

0

2

0

1

0

Read:

Bit 7

Bit 0

Timer 1 Counter

Register Low Write:

(T1CNTL)

Reset:

0

Bit 15

1

0

Read:

Timer 1 Counter Modulo

14

13

12

11

10

9

Bit 8

Register High Write:

(T1MODH)

Reset:

1

Bit 0

1

Read:

Timer 1 Counter Modulo

Bit 7

1

6

1

5

1

4

1

3

2

1

Register Low Write:

(T1MODL)

Reset:

1

ELS0B

0

1

ELS0A

0

1

TOV0

0

Read: CH0F

Timer 1 Channel 0 Status

and Control Register Write:

CH0IE

0

MS0B

0

MS0A

0

CH0MAX

0

(T1SC0)

Reset:

Read:

Timer 1 Channel 0

Bit 15

14

13

12

11

10

9

Bit 8

Register High Write:

(T1CH0H)

Reset:

Indeterminate after reset

Read:

Timer 1 Channel 0

Bit 7

6

5

4

3

2

1

Bit 0

Register Low Write:

(T1CH0L)

Reset:

Indeterminate after reset

† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)

Technical Data

50

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

CH1IE

0

5

4

MS1A

0

3

ELS1B

0

2

ELS1A

0

1

TOV1

0

Bit 0

CH1MAX

0

Read: CH1F

0

Timer 1 Channel 1 Status

and Control Register Write:

$0028

0

(T1SC1)

Reset:

0

Read:

Timer 1 Channel 1

Bit 15

14

13

12

11

10

9

Bit 8

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0031

Register High Write:

(T1CH1H)

Reset:

Indeterminate after reset

Read:

Timer 1 Channel 1

Bit 7

6

5

4

3

2

1

Bit 0

PS0

Register Low Write:

(T1CH1L)

Reset:

Indeterminate after reset

Read:

TOF

0

TRST

0

Timer 2 Status and Control

TOIE

TSTOP

PS2

PS1

Register Write:

(T2SC)

Reset:

0

1

0

9

0

Read: Bit 15

14

13

12

11

10

Bit 8

Timer 2 Counter

Register High Write:

(T2CNTH)

Reset:

0

6

0

5

0

4

0

3

0

2

0

1

0

Read:

Bit 7

Bit 0

Timer 2 Counter

Register Low Write:

(T2CNTL)

Reset:

0

Bit 15

1

0

Read:

Timer 2 Counter Modulo

14

13

12

11

10

9

Bit 8

Register High Write:

(T2MODH)

Reset:

1

Bit 0

1

Read:

Timer 2 Counter Modulo

Bit 7

6

1

5

1

4

1

3

2

1

Register Low Write:

(T2MODL)

Reset:

1

ELS0B

0

1

ELS0A

0

1

TOV0

0

Read: CH0F

Timer 2 Channel 0 Status

and Control Register Write:

CH0IE

0

MS0B

0

MS0A

0

CH0MAX

0

(T2SC0)

Reset:

Read:

Timer 2 Channel 0

Bit 15

14

13

12

11

10

9

Bit 8

Register High Write:

(T2CH0H)

Reset:

Indeterminate after reset

R = Reserved

= Unimplemented

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

51

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Register Name

Timer 2 Channel 0

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Bit 7

6

5

4

3

2

1

Bit 0

$0032

Register Low Write:

(T2CH0L)

Reset:

Indeterminate after reset

Read: CH1F

0

Timer 2 Channel 1 Status

and Control Register Write:

CH1IE

MS1A

0

ELS1B

ELS1A

TOV1

CH1MAX

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

0

(T2SC1)

Reset:

0

9

0

Read:

Timer 2 Channel 1

Bit 15

14

13

12

11

10

Bit 8

Register High Write:

(T2CH1H)

Reset:

Indeterminate after reset

Read:

Timer 2 Channel 1

Bit 7

6

5

4

3

2

1

Bit 0

Register Low Write:

(T2CH1L)

Reset:

Indeterminate after reset

Read:

PLL Control Register

Write:

PLLF

PLLIE

0

PLLON

1

BCS

PRE1

PRE0

VPR1

VPR0

(PCTL)

Reset:

0

Read:

LOCK

PLL Bandwidth Control

AUTO

ACQ

R

Register Write:

(PBWC)

Reset:

0

MUL11

0

MUL10

0

MUL9

0

MUL8

0

Read:

PLL Multiplier Select High

Register Write:

(PMSH)

Reset:

0

Read:

PLL Multiplier Select Low

MUL7

0

MUL6

1

MUL5

0

MUL4

0

MUL3

0

MUL2

0

MUL1

0

MUL0

0

Register Write:

(PMSL)

Reset:

Read:

PLL VCO Range Select

VRS7

VRS6

VRS5

VRS4

VRS3

0

VRS2

0

VRS1

0

VRS0

0

Register Write:

(PMRS)

Reset:

0

1

0

Read:

PLL Reference Divider

RDS3

0

RDS2

RDS1

RDS0

1

Select Register Write:

(PMDS)

Reset:

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)

Technical Data

52

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Analog-to-Digital Status

and Control Register Write:

COCO

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

$003C

(ADSCR)

Reset:

0

1

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Analog-to-Digital Data

$003D

$003E

$003F

$FE00

Register Write:

(ADR)

Reset:

0

ADIV2

0

ADIV1

0

ADIV0

0

ADICLK

0

Read:

Analog-to-Digital Clock

Register Write:

(ADCLK)

Reset:

0

Read:

Unimplemented Write:

Reset:

Read:

SBSW

Note

0

R

0

SIM Break Status Register

(SBSR)

Write:

Reset:

Note: Writing a logic 0 clears SBSW.

Read: POR

Write:

COP

ILOP

ILAD

MODRST

LVI

SIM Reset Status Register

(SRSR)

$FE01

POR:

Read:

1

0

SIM Upper Byte Address

R

$FE02

$FE03

$FE04

$FE05

Register Write:

(SUBAR)

Reset:

Read:

SIM Break Flag Control

BCFE

R

Register Write:

(SBFCR)

Reset:

0

IF6

R

Read:

IF5

R

IF4

R

IF3

R

IF2

R

IF1

R

0

R

0

R

Interrupt Status Register 1

(INT1)

Write:

Reset:

Read:

Write:

Reset:

0

IF14

R

IF13

R

IF12

R

IF11

R

IF10

R

IF9

R

IF8

R

IF7

R

Interrupt Status Register 2

(INT2)

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

53

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Register Name

Bit 7

6

0

5

0

4

0

3

0

2

0

1

IF16

R

Bit 0

IF15

R

Read:

Write:

Reset:

Read:

0

R

0

Interrupt Status Register 3

(INT3)

$FE06

R

0

R

0

R

0

R

0

R

0

R

0

$FE07

$FE08

$FE09

$FE0A

$FE0B

$FE0C

$FF7E

$FFFF

Reserved Write:

Reset:

0

Read:

HVEN

MASS

ERASE

PGM

0

FLASH Control Register

(FLCR)

Write:

Reset:

Read:

0

Bit 15

0

13

0

12

0

11

0

10

0

9

0

1

Break Address

14

Bit 8

0

Register High Write:

(BRKH)

Reset:

0

Read:

Break Address

Register Low Write:

Bit 7

0

6

0

5

4

3

2

Bit 0

(BRKL)

Reset:

0

Read:

Break Status and Control

BRKE

BRKA

Register Write:

(BRKSCR)

Reset:

0

Read: LVIOUT

Write:

LVI Status Register

(LVISR)

Reset:

Read:

0

BPR7

U

0

BPR6

U

0

BPR5

U

0

BPR4

U

0

BPR3

U

0

BPR2

U

0

BPR1

U

0

BPR0

U

FLASH Block Protect

Register Write:

†

(FLBPR)

Reset:

Read:

Low byte of reset vector

COP Control Register

(COPCTL)

Write:

Writing clears COP counter (any value)

Unaffected by reset

Reset:

† Non-volatile FLASH register

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)

Technical Data

54

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Input/Output (I/O) Section

.

Table 2-1. Vector Addresses

Vector Priority Vector Address

Lowest

Vector

Timebase Vector (High)

$FFDC

$FFDD

$FFDE

$FFDF

$FFE0

$FFE1

$FFE2

$FFE3

$FFE4

$FFE5

$FFE6

$FFE7

$FFE8

$FFE9

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

$FFFF

IF16

IF15

IF14

IF13

IF12

IF11

IF10

IF9

Timebase Vector (Low)

ADC Conversion Complete Vector (High)

ADC Conversion Complete Vector (Low)

Keyboard Vector (High)

Keyboard Vector (Low)

SCI Transmit Vector (High)

SCI Transmit Vector (Low)

SCI Receive Vector (High)

SCI Receive Vector (Low)

SCI Error Vector (High)

SCI Error Vector (Low)

SPI Transmit Vector (High)

SPI Transmit Vector (Low)

SPI Receive Vector (High)

SPI Receive Vector (Low)

TIM2 Overflow Vector (High)

TIM2 Overflow Vector (Low)

TIM2 Channel 1 Vector (High)

TIM2 Channel 1 Vector (Low)

TIM2 Channel 0 Vector (High)

TIM2 Channel 0 Vector (Low)

TIM1 Overflow Vector (High)

TIM1 Overflow Vector (Low)

TIM1 Channel 1 Vector (High)

TIM1 Channel 1 Vector (Low)

TIM1 Channel 0 Vector (High)

TIM1 Channel 0 Vector (Low)

PLL Vector (High)

IF8

IF7

IF6

IF5

IF4

IF3

IF2

PLL Vector (Low)

IRQ Vector (High)

IF1

IRQ Vector (Low)

SWI Vector (High)

—

SWI Vector (Low)

Reset Vector (High)

—

Highest

Reset Vector (Low)

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

55

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Technical Data

56

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 3. Low-Power Modes

3.1 Contents

3.2

3.2.1

3.2.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3

3.3.1

3.3.2

Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4

3.4.1

3.4.2

Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5

3.5.1

3.5.2

Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6

3.6.1

3.6.2

Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7

3.7.1

3.7.2

Computer Operating Properly Module (COP). . . . . . . . . . . . . .61

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.8

3.8.1

3.8.2

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9

3.9.1

3.9.2

Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63

3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

MC68HC908GP32•MC68HC08GP32 — Rev. 6

MOTOROLA

Technical Data

57

Low-Power Modes