MC68HC908GP32 [FREESCALE]
M68HC08 Microcontrollers; M68HC08微控制器
| 型号： | MC68HC908GP32 |
| 厂家： | 
Freescale |
| 描述： | M68HC08 Microcontrollers |
| 文件： | 总282页 (文件大小：1866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908GP32
MC68HC08GP32
Data Sheet
M68HC08
Microcontrollers
MC68HC908GP32
Rev. 7
03/2006
freescale.com
MC68HC908GP32
MC68HC08GP32
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2001, 2006. All rights reserved.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Revision
Level
Page
Number(s)
Date
Description
In Table 15-1, second cell in "Comment" column, corrected PTC to
PTC1.
199
337
387
397
341
In Figure 21-2, Timebase control register, bit 0 is a reserved bit.
July,
2001
5
Updated crystal oscillator component values in 23.17.1 CGM
Component Specifications.
Added appendix A: MC68HC08GP32 — ROM part.
Section 22. Timer Interface Module (TIM) — Timer discrepancies
corrected throughout this section.
August,
2002
6
6.1
7
Section 24. Mechanical Specifications — Replaced incorrect 44-pin QFP
drawing, case 824E to case 824A.
393
Throughout
38
August,
2005
Updated to meet Freescale identity guidelines.
3.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information.
March,
2006
23.16.1 CGM Component Specifications — Updated to reflect correct
values.
260
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List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 4 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Chapter 5 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Chapter 6 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Chapter 7 Clock Generator Module (CGMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 8 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Chapter 9 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Chapter 10 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Chapter 11 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Chapter 12 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Chapter 13 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Chapter 14 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Chapter 15 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Chapter 16 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Chapter 17 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Chapter 18 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .159
Chapter 19 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Chapter 20 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Chapter 21 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Chapter 22 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Chapter 23 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Chapter 24 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Chapter 25 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Appendix A MC68HC08GP32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
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List of Chapters
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Table of Contents
Chapter 1
General Description
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2
1.2.1
1.2.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standard Features of the MC68HC908GP32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL). . . . . . . . . . . . . . . . 25
Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port E I/O Pins (PTE1/RxD–PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
1.5.11
1.5.12
Chapter 2
Memory Map
2.1
2.2
2.3
2.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 3
Low-Power Modes
3.1
3.1.1
3.1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2
3.2.1
3.2.2
Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3
3.3.1
3.3.2
Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Table of Contents
3.4
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.1
3.4.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5
3.5.1
3.5.2
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6
3.6.1
3.6.2
Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7
3.7.1
3.7.2
External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8
3.8.1
3.8.2
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9
3.9.1
3.9.2
Low-Voltage Inhibit Module (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Serial Communications Interface Module (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10.1
3.10.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.1
3.11.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12.1
3.12.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.13.1
3.13.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.14 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 4
Resets and Interrupts
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.4
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-Voltage Inhibit Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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4.3
4.3.1
4.3.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TIM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
KBD0–KBD7 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.2.9
4.3.2.10
4.3.2.11
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
ADC (Analog-to-Digital Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 5
Analog-to-Digital Converter (ADC)
5.1
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.5
5.5.1
5.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.6
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) . . . . . . . . . . . 57
ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . 58
ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6.1
5.6.2
5.6.3
5.7
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.7.1
5.7.2
5.7.3
Chapter 6
Break Module (BRK)
6.1
6.2
6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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6.3.1
6.3.2
6.3.3
6.3.4
Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4
6.4.1
6.4.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.5
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5.1
6.5.2
6.5.3
6.5.4
Chapter 7
Clock Generator Module (CGMC)
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CGMC External Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CGMC Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CGMC CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.5
CGMC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.7.1
7.7.2
7.7.3
7.8
Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.8.1
7.8.2
7.8.3
Chapter 8
Configuration Register (CONFIG)
8.1
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 9
Computer Operating Properly (COP)
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.3
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.4
9.5
9.6
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.7
9.7.1
9.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.8
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 10
Central Processor Unit (CPU)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.1
10.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 11
FLASH Memory
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.4 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.6 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.7 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.7.1
FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Chapter 12
External Interrupt (IRQ)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.4 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 13
Keyboard Interrupt Module (KBI)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.5.1
13.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.1
13.7.2
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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Chapter 14
Low-Voltage Inhibit (LVI)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3.1
14.3.2
14.3.3
14.3.4
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.6.1
14.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Chapter 15
Monitor ROM (MON)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Chapter 16
Input/Output (I/O) Ports
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.2.1
16.2.2
16.2.3
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
16.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
16.3.1
16.3.2
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
16.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
16.4.1
16.4.2
16.4.3
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5.1
16.5.2
16.5.3
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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16.6 Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
16.6.1
16.6.2
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Chapter 17
Random-Access Memory (RAM)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
17.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 18
Serial Communications Interface Module (SCI)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
18.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
18.4.1
18.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
18.4.2.1
18.4.2.2
18.4.2.3
18.4.2.4
18.4.2.5
18.4.2.6
18.4.3
18.4.3.1
18.4.3.2
18.4.3.3
18.4.3.4
18.4.3.5
18.4.3.6
18.4.3.7
18.4.3.8
18.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.5.1
18.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.7.1
18.7.2
PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
18.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
18.8.1
18.8.2
18.8.3
18.8.4
18.8.5
18.8.6
18.8.7
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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Chapter 19
System Integration Module (SIM)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
19.2 SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
19.2.1
19.2.2
19.2.3
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
19.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
19.3.1
19.3.2
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Monitor Mode Entry Module Reset (MODRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.3.2.1
19.3.2.2
19.3.2.3
19.3.2.4
19.3.2.5
19.3.2.6
19.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.4.1
19.4.2
19.4.3
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
19.5.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
19.5.1.1
19.5.1.2
19.5.1.3
19.5.2
19.5.3
19.5.4
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
19.6.1
19.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
19.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.7.1
19.7.2
19.7.3
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Chapter 20
Serial Peripheral Interface Module (SPI)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
20.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
20.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
20.4.1
20.4.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
20.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
20.5.1
20.5.2
Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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20.5.3
20.5.4
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
20.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
20.7 Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
20.7.1
20.7.2
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
20.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
20.9 Resetting the SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
20.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
20.10.1
20.10.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
20.11 SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
20.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
20.12.1
20.12.2
20.12.3
20.12.4
20.12.5
MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
20.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
20.13.1
20.13.2
20.13.3
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 21
Timebase Module (TBM)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
21.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
21.4 Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
21.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
21.6.1
21.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Chapter 22
Timer Interface Module (TIM)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
22.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
22.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
22.4.1
22.4.2
22.4.3
22.4.3.1
22.4.3.2
TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
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22.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
22.4.4.1
22.4.4.2
22.4.4.3
22.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
22.6.1
22.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
22.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
22.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
22.9.1
22.9.2
22.9.3
22.9.4
22.9.5
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Chapter 23
Electrical Specifications
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
23.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
23.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
23.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
23.5 5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
23.6 3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
23.7 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
23.8 3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
23.9 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
23.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
23.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
23.13 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
23.14 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
23.16.1
23.16.2
CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Chapter 24
Mechanical Specifications
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
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Chapter 25
Ordering Information
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
25.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Appendix A
MC68HC08GP32
A.1
A.2
A.3
A.4
A.5
A.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Mask Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
A.7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
A.7.1
A.7.2
A.7.3
A.7.4
A.8
ROM MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
18
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC908GP32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
1.2 Features
For convenience, features have been organized to reflect:
•
•
Standard features of the MC68HC908GP32
Features of the CPU08
1.2.1 Standard Features of the MC68HC908GP32
•
•
•
•
•
High-performance M68HC08 architecture optimized for C-compilers
Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
8-MHz internal bus frequency
FLASH program memory security(1)
On-chip programming firmware for use with host personal computer which does not require high
voltage for entry
•
•
In-system programming
System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip points for 3.0-V and 5.0-V
operation
– Illegal opcode detection with reset
– Illegal address detection with reset
•
•
Low-power design; fully static with stop and wait modes
Standard low-power modes of operation:
– Wait mode
– Stop mode
•
•
Master reset pin and power-on reset (POR)
32 Kbytes of on-chip FLASH memory with in-circuit programming capabilities of FLASH program
memory
•
•
•
512 bytes of on-chip random-access memory (RAM)
Serial peripheral interface module (SPI)
Serial communications interface module (SCI)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
19
General Description
•
Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel
•
•
•
•
•
8-channel, 8-bit successive approximation analog-to-digital converter (ADC)
BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging
Internal pullups on IRQ and RST to reduce customer system cost
Clock generator module with on-chip 32-kHz crystal compatible PLL (phase-lock loop)
Up to 33 general-purpose input/output (I/O) pins, including:
– 26 shared-function I/O pins
– Five or seven dedicated I/O pins, depending on package choice
Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
•
•
•
•
High current 10-mA sink/10-mA source capability on all port pins
Higher current 15-mA sink/source capability on PTC0–PTC4
Timebase module with clock prescaler circuitry for eight user selectable periodic real-time
interrupts with optional active clock source during stop mode for periodic wakeup from stop using
an external 32-kHz crystal
•
Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG register to allow user selection of
having the oscillator enabled or disabled during stop mode
8-bit keyboard wakeup port
5-mA maximum current injection on all port pins to maintain input protection
40-pin plastic dual-in-line package (PDIP), 42-pin shrink dual-in-line package (SDIP), or 44-pin
quad flat pack (QFP)
•
•
•
•
•
•
Specific features of the MC68HC908GP32 in 40-pin PDIP are:
– Port C is only 5 bits: PTC0–PTC4
– Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM module
Specific features of the MC68HC908GP32 in 42-pin SDIP are:
– Port C is only 5 bits: PTC0–PTC4
– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules
Specific features of the MC68HC908GP32 in 44-pin QFP are:
– Port C is 7 bits: PTC0–PTC6
– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules
1.2.2 Features of the CPU08
Features of the CPU08 include:
•
•
•
•
•
•
•
•
•
•
Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
20
Freescale Semiconductor
MCU Block Diagram
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GP32. Text in parentheses within a module block
indicates the module name. Text in parentheses next to a signal indicates the module which uses the
signal.
INTERNAL BUS
M68HC08 CPU
PTA7/KBD7–
PTA0/KBD0 †
PROGRAMMABLE TIMEBASE
MODULE
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
SINGLE BREAKPOINT BREAK
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 32,256 BYTES
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
USER RAM — 512 BYTES
8-BIT KEYBOARD
INTERRUPT MODULE
MONITOR ROM — 307 BYTES
PTC6 †
PTC5 †
2-CHANNEL TIMER INTERFACE
MODULE 1
USER FLASH VECTOR SPACE — 36 BYTES
PTC4 † ‡
PTC3 † ‡
PTC2 † ‡
PTC1 † ‡
PTC0 † ‡
2-CHANNEL TIMER INTERFACE
MODULE 2
CLOCK GENERATOR MODULE
OSC1
32-kHz OSCILLATOR
OSC2
SERIAL COMMUNICATIONS
INTERFACE MODULE
PTD7/T2CH1 †
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTD3/SPSCK †
PTD2/MOSI †
PTD1/MISO †
PTD0/SS †
PHASE-LOCKED LOOP
CGMXFC
COMPUTER OPERATING
PROPERLY MODULE
24 INTR SYSTEM INTEGRATION
MODULE
* RST
* IRQ
SERIAL PERIPHERAL
INTERFACE MODULE
SINGLE EXTERNAL IRQ
MODULE
MONITOR MODULE
VDDAD/VREFH
VSSAD/VREFL
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTE1/RxD
PTE0/TxD
DATA BUS SWITCH
MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
VDD
SECURITY
MODULE
VSS
VDDA
POWER
CONFIGURATION REGISTER 1
MODULE
VSSA
MONITOR MODE ENTRY
MODULE
CONFIGURATION REGISTER 2
MODULE
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
21
General Description
1.4 Pin Assignments
VDDA (PLL)
PTA7/KBD7
PTA6/KBD6
PTA5/KBD5
PTA4/KBD4
PTA3/KBD3
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSSA (PLL)
2
CGMXFC (PLL)
OSC2
3
4
OSC1
RST
5
PTA2/KBD2
6
PTC0
PTA1/KBD1
7
PTC1
PTA0/KBD0
8
VSSAD/VREFL (ADC)
VDDAD/VREFH (ADC)
PTC2
9
PTC3
10
11
12
13
14
15
16
17
18
19
20
PTC4
PTB7/AD7
PTE0/TxD
PTE1/RxD
IRQ
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
VSS
PTB1/AD1
PTB0/AD0
PTD5/T1CH1
PTD4/T1CH0
VDD
Pins Not Available
on 40-Pin Package
Internal
Connection
Connected to ground
Connected to ground
Unconnected
PTC5
PTC6
PTD6/T2CH0
PTD7/T2CH1
Unconnected
Figure 1-2. 40-Pin PDIP Pin Assignments
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
22
Freescale Semiconductor
Pin Assignments
PTA7/KBD7
PTA6/KBD6
PTA5/KBD5
PTA4/KBD4
PTA3/KBD3
VDDA (PLL)
VSSA (PLL)
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2
CGMXFC (PLL)
OSC2
3
4
OSC1
RST
5
PTA2/KBD2
6
PTA1/KBD1
PTC0
7
PTA0/KBD0
PTC1
8
VSSAD/VREFL (ADC)
VDDAD/VREFH (ADC)
PTC2
9
PTC3
10
11
12
13
14
15
16
17
18
19
20
21
PTB7/AD7
PTC4
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTE0/TxD
PTE1/RxD
IRQ
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
VSS
PTB1/AD1
PTB0/AD0
PTD7/T2CH1
PTD6/T2CH0
PTD5/T1CH1
VDD
PTD4/T1CH0
Pins Not Available
on 42-Pin Package
Internal
Connection
PTC5
PTC6
Connected to ground
Connected to ground
Figure 1-3. 42-Pin SDIP Pin Assignments
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
23
General Description
RST
PTC0
PTA1/KBD1
PTA0/KBD0
1
33
2
32
31
30
29
28
27
26
25
24
PTC1
VSSAD/VREFL
VDDAD/VREFH
PTB7/AD7
3
PTC2
4
PTC3
5
PTC4
PTB6/AD6
6
PTB5/AD5
PTC5
7
PTC6
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
8
PTE0/TxD
PTE1/RxD
IRQ
9
10
11
23
Figure 1-4. 44-Pin QFP Pin Assignments
1.5 Pin Functions
Descriptions of the pin functions are provided here.
1.5.1 Power Supply Pins (V and V )
DD
SS
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response
ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that
require the port pins to source high current levels.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
24
Freescale Semiconductor
Pin Functions
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
NOTE: Component values shown
represent typical applications.
Figure 1-5. Power Supply Bypassing
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 7 Clock
Generator Module (CGMC).
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset
of the entire system. It is driven low when any internal reset source is asserted. This pin contains an
internal pullup resistor. See Chapter 19 System Integration Module (SIM).
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor.
See Chapter 12 External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (V
and V
)
DDA
SSA
VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM).
Connect the VDDA pin to the same voltage potential as VDD, and the VSSA pin to the same voltage
potential as VSS. Decoupling of these pins should be as per the digital supply. See Chapter 7 Clock
Generator Module (CGMC)
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 7 Clock Generator Module
(CGMC)
1.5.7 ADC Power Supply/Reference Pins (V
/V
and V
/V
)
DDAD REFH
SSAD REFL
VDDAD and VSSAD are the power supply pins for the analog-to-digital converter (ADC). Connect the VDDAD
pin to the same voltage potential as VDD, and the VSSAD pin to the same voltage potential as VSS.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
25
General Description
Decoupling of these pins should be as per the digital supply. See Chapter 5 Analog-to-Digital Converter
(ADC).
VREFH is the high reference supply for the ADC, and is internally connected to VDDAD. VREFL is the low
reference supply for the ADC, and is internally connected to VSSAD
.
1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0)
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be
programmed to serve as keyboard interrupt pins. See Chapter 16 Input/Output (I/O) Ports and Chapter
13 Keyboard Interrupt Module (KBI).
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital
converter (ADC) inputs. See Chapter 16 Input/Output (I/O) Ports and Chapter 5 Analog-to-Digital
Converter (ADC).
1.5.10 Port C I/O Pins (PTC6–PTC0)
PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See Chapter 16 Input/Output (I/O) Ports.
PTC5 and PTC6 are only available on 44-pin QFP package.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins. PTD0–PTD3 can be programmed to be
serial peripheral interface (SPI) pins, while PTD4–PTD7 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Chapter 22 Timer Interface Module (TIM), Chapter 20 Serial
Peripheral Interface Module (SPI), and Chapter 16 Input/Output (I/O) Ports. PTD6 and PTD7 are only
available on 42-SDIP and 44-pin QFP packages.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins can also be programmed to be
serial communications interface (SCI) pins. See Chapter 18 Serial Communications Interface Module
(SCI) and Chapter 16 Input/Output (I/O) Ports.
NOTE
Any unused inputs and I/O ports should be tied to an appropriate logic level
(either VDD or VSS). Although the I/O ports of the MC68HC908GP32 •
MC68HC08GP32 do not require termination, termination is recommended
to reduce the possibility of static damage.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
26
Freescale Semiconductor
Chapter 2
Memory Map
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
•
•
•
•
32,256 bytes of user FLASH memory
512 bytes of random-access memory (RAM)
36 bytes of user-defined vectors
307 bytes of monitor ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1)
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and
in register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$003F. Additional I/O
registers have these addresses:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
$FE00; SIM break status register, SBSR
$FE01; SIM reset status register, SRSR
$FE02; reserved, SUBAR
$FE03; SIM break flag control register, SBFCR
$FE04; interrupt status register 1, INT1
$FE05; interrupt status register 2, INT2
$FE06; interrupt status register 3, INT3
$FE07; reserved
$FE08; FLASH control register, FLCR
$FE09; break address register high, BRKH
$FE0A; break address register low, BRKL
$FE0B; break status and control register, BRKSCR
$FE0C; LVI status register, LVISR
$FF7E; FLASH block protect register, FLBPR
$FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
27
Memory Map
$0000
↓
I/O Registers
64 Bytes
$003F
$0040
↓
RAM
512 Bytes
$023F
$0240
↓
Unimplemented
32,192 Bytes
$7FFF
$8000
↓
FLASH Memory
32,256 Bytes
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
↓
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved (SUBAR)
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Interrupt Status Register 3 (INT3)
Reserved
FLASH Control Register (FLCR)
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
LVI Status Register (LVISR)
Unimplemented
3 Bytes
$FE0F
$FE10
↓
Unimplemented
16 Bytes
Reserved for Compatibility with Monitor Code
for A-Family Parts
$FE1F
$FE20
↓
Monitor ROM
307 Bytes
$FF52
$FF53
↓
Unimplemented
43 Bytes
$FF7D
$FF7E
$FF7F
↓
FLASH Block Protect Register (FLBPR)
Unimplemented
93 Bytes
$FFDB
$FFDC
↓
Note: $FFF6–$FFFD
reserved for
8 security bytes
FLASH Vectors
36 Bytes
$FFFF
Figure 2-1. Memory Map
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
28
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
0
PTB6
PTC6
PTD6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
Port C Data Register
(PTC)
PTD7
Port D Data Register
(PTD)
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
DDRB1
0
0
DDRB0
0
DDRB7
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
Data Direction Register B
(DDRB)
0
0
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Data Direction Register C
(DDRC)
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
Unimplemented Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRE1
0
0
DDRE0
0
Read:
Data Direction Register E
(DDRE)
Write:
Reset:
Read:
0
0
0
0
0
0
Port A Input Pullup Enable
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
29
Memory Map
Addr.
Register Name
Port C Input Pullup Enable
Register Write:
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
$000E
(PTCPUE)
Reset:
Read:
0
0
0
0
0
0
0
0
Port D Input Pullup Enable
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
Register Write:
(PTDPUE)
Reset:
Read:
Write:
Reset:
Read:
0
0
0
0
0
0
0
SPE
0
0
DMAS
SPRIE
SPMSTR
CPOL
CPHA
SPWOM
0
SPTIE
0
SPI Control Register
(SPCR)
0
0
1
0
1
SPRF
OVRF
MODF
SPTE
SPI Status and Control
ERRIE
MODFEN
SPR1
SPR0
Register Write:
(SPSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
0
0
0
1
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by reset
LOOPS
0
ENSCI
TXINV
0
M
0
WAKE
0
ILTY
0
PEN
0
PTY
0
SCI Control Register 1
(SCC1)
0
TCIE
0
SCTIE
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2
(SCC2)
0
0
R8
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
SCI Control Register 3
(SCC3)
U
U
0
0
0
0
0
0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
SCI Status Register 1
(SCS1)
1
1
0
0
0
0
0
0
BKF
RPF
SCI Status Register 2
(SCS2)
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register
(SCDR)
Unaffected by reset
SCP1
SCP0
R
SCR2
SCR1
SCR0
SCI Baud Rate Register
(SCBR)
0
0
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status
IMASKK
MODEK
and Control Register Write:
(INTKBSCR)
Reset:
Read:
0
0
KBIE6
0
0
KBIE5
0
0
0
0
KBIE1
0
0
Keyboard Interrupt Enable
KBIE7
KBIE4
0
KBIE3
KBIE2
KBIE0
Register Write:
(INTKBIER)
Reset:
Read:
0
0
0
0
TBIE
0
0
R
0
TBIF
Time Base Module Control
TBR2
0
TBR1
0
TBR0
TBON
0
Register Write:
(TBCR)
TACK
0
Reset:
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
30
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
IRQF
2
0
1
IMASK
0
Bit 0
Read:
IRQ Status and Control
MODE
$001D
Register Write:
(INTSCR)
ACK
0
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
OSC-
STOPENB
Configuration Register 2
SCIBDSRC
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
(CONFIG2)† Write:
Reset:
0
0
0
0
0
0
SSREC
0
0
STOP
0
0
COPD
0
Read:
COPRS
LVISTOP LVIRSTD LVIPWRD LVI5OR3†
Configuration Register 1
(CONFIG1)†
Write:
Reset:
Read:
0
TOF
0
0
0
0
0
0
0
Timer 1 Status and Control
TOIE
TSTOP
PS2
PS1
PS0
Register Write:
(T1SC)
TRST
0
Reset:
Read:
0
0
1
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
Timer 1 Counter
Register High Write:
(T1CNTH)
Reset:
Read:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 1 Counter
Register Low Write:
(T1CNTL)
Reset:
Read:
0
Bit 15
1
0
0
0
0
0
0
0
Bit 8
1
Timer 1 Counter Modulo
14
13
12
11
10
9
Register High Write:
(T1MODH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
1
1
1
1
1
1
Timer 1 Counter Modulo
Register Low
(T1MODL)
Bit 7
6
1
5
1
4
1
3
2
1
Bit 0
1
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Timer 1 Channel 0 Status and
Control Register (T1SC0)
0
Timer 1 Channel 0
Bit 15
14
13
12
11
10
9
Bit 8
Register High Write:
(T1CH0H)
Reset:
Read:
Indeterminate after reset
Timer 1 Channel 0
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T1CH0L)
Reset:
Indeterminate after reset
† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Read:
Write:
Reset:
Read:
CH1F
0
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
Timer 1 Channel 1 Status and
Control Register (T1SC1)
$0028
$0029
$002A
0
0
0
0
0
0
0
9
0
Timer 1 Channel 1
Bit 15
14
13
12
11
10
Bit 8
Register High Write:
(T1CH1H)
Reset:
Read:
Indeterminate after reset
Timer 1 Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T1CH1L)
Reset:
Indeterminate after reset
R = Reserved
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
31
Memory Map
Addr.
Register Name
Timer 2 Status and Control
Register Write:
Bit 7
TOF
0
6
5
4
0
3
0
2
1
Bit 0
Read:
TOIE
TSTOP
PS2
PS1
PS0
$002B
TRST
0
(T2SC)
Reset:
Read:
0
0
1
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
Timer 2 Counter
Register High Write:
(T2CNTH)
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
Reset:
Read:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
Timer 2 Counter
Register Low Write:
(T2CNTL)
Reset:
Read:
0
Bit 15
1
0
0
0
0
0
0
0
Bit 8
1
Timer 2 Counter Modulo
14
13
12
11
10
9
Register High Write:
(T2MODH)
Reset:
Read:
1
1
1
1
1
1
Timer 2 Counter Modulo
Bit 7
6
1
5
1
4
1
3
2
1
Bit 0
1
Register Low Write:
(T2MODL)
Reset:
Read:
Write:
Reset:
Read:
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Timer 2 Channel 0 Status and
Control Register (T2SC0)
0
Timer 2 Channel 0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Register High Write:
(T2CH0H)
Reset:
Read:
Indeterminate after reset
Timer 2 Channel 0
6
5
0
4
3
2
1
Bit 0
Register Low Write:
(T2CH0L)
Reset:
Read:
Write:
Reset:
Read:
Indeterminate after reset
CH1F
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
Timer 2 Channel 1 Status and
Control Register (T2SC1)
0
0
0
0
0
0
0
9
0
Timer 2 Channel 1
Bit 15
14
13
12
11
10
Bit 8
Register High Write:
(T2CH1H)
Reset:
Read:
Indeterminate after reset
Timer 2 Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T2CH1L)
Reset:
Read:
Write:
Reset:
Read:
Indeterminate after reset
PLLF
PLLIE
0
PLLON
1
BCS
PRE1
PRE0
VPR1
VPR0
PLL Control Register
(PCTL)
0
0
0
0
0
0
0
0
0
0
LOCK
PLL Bandwidth Control
AUTO
ACQ
R
Register Write:
(PBWC)
Reset:
Read:
0
0
0
0
0
0
0
0
0
MUL11
0
0
MUL10
0
0
MUL9
0
0
MUL8
0
PLL Multiplier Select High
Register Write:
(PMSH)
Reset:
Read:
0
MUL7
0
0
MUL6
1
0
MUL5
0
0
PLL Multiplier Select Low
MUL4
MUL3
0
MUL2
MUL1
MUL0
0
Register Write:
(PMSL)
Reset:
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
32
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
VRS3
0
2
VRS2
0
1
VRS1
0
Bit 0
VRS0
0
Read:
PLL VCO Range Select
VRS7
VRS6
VRS5
VRS4
$003A
Register Write:
(PMRS)
Reset:
Read:
0
0
1
0
0
0
0
0
PLL Reference Divider
RDS3
0
RDS2
0
RDS1
0
RDS0
1
$003B
$003C
$003D
$003E
$003F
$FE00
Select Register Write:
(PMDS)
Reset:
Read:
0
0
0
0
Analog-to-Digital Status and
COCO
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Control Register Write:
(ADSCR)
Reset:
Read:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Analog-to-Digital Data
Register Write:
(ADR)
Reset:
Read:
0
ADIV2
0
0
ADIV1
0
0
ADIV0
0
0
ADICLK
0
0
0
0
0
0
0
0
0
Analog-to-Digital Clock
Register Write:
(ADCLK)
Reset:
Read:
0
0
0
0
Unimplemented Write:
Reset:
Read:
SBSW
Note
0
R
R
R
R
R
R
R
0
SIM Break Status Register
(SBSR)
Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
SIM Reset Status Register
(SRSR)
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
Write:
POR:
1
0
0
0
0
0
0
0
Read:
SIM Upper Byte Address
Register Write:
(SUBAR)
R
R
R
R
R
R
R
R
Reset:
Read:
SIM Break Flag Control
BCFE
R
R
R
R
R
R
R
Register Write:
(SBFCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
IF6
R
IF5
R
IF4
R
IF3
R
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IF16
R
IF15
R
Interrupt Status Register 3
(INT3)
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
0
R
R
0
R
R
0
R
R
R
0
Reserved Write:
Reset:
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
33
Memory Map
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
PGM
0
Read:
Write:
Reset:
Read:
HVEN
MASS
ERASE
FLASH Control Register
(FLCR)
$FE08
0
Bit 15
0
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
1
Break Address
14
Bit 8
0
$FE09
$FE0A
$FE0B
Register High Write:
(BRKH)
Reset:
Read:
0
Break Address
Register Low Write:
(BRKL)
Bit 7
0
6
0
5
4
3
2
Bit 0
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
Break Status and Control
BRKE
0
BRKA
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: LVIOUT
$FE0C LVI Status Register (LVISR) Write:
Reset:
0
BPR7
U
0
BPR6
U
0
BPR5
U
0
BPR4
U
0
BPR3
U
0
BPR2
U
0
BPR1
U
0
BPR0
U
Read:
FLASH Block Protect
Register Write:
$FF7E
$FFFF
†
(FLBPR)
Reset:
Read:
Write:
Reset:
Low byte of reset vector
COP Control Register
(COPCTL)
Writing clears COP counter (any value)
Unaffected by reset
† Non-volatile FLASH register
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
34
Freescale Semiconductor
Input/Output (I/O) Section
.
Table 2-1. Vector Addresses
Vector Priority
Vector
Address
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
Timebase Vector (High)
Timebase Vector (Low)
Lowest
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIM2 Overflow Vector (High)
TIM2 Overflow Vector (Low)
TIM2 Channel 1 Vector (High)
TIM2 Channel 1 Vector (Low)
TIM2 Channel 0 Vector (High)
TIM2 Channel 0 Vector (Low)
TIM1 Overflow Vector (High)
TIM1 Overflow Vector (Low)
TIM1 Channel 1 Vector (High)
TIM1 Channel 1 Vector (Low)
TIM1 Channel 0 Vector (High)
TIM1 Channel 0 Vector (Low)
PLL Vector (High)
IF8
IF7
IF6
IF5
IF4
IF3
IF2
PLL Vector (Low)
IRQ Vector (High)
IF1
IRQ Vector (Low)
SWI Vector (High)
—
SWI Vector (Low)
Reset Vector (High)
—
Highest
Reset Vector (Low)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
35
Memory Map
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
36
Freescale Semiconductor
Chapter 3
Low-Power Modes
3.1 Introduction
The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08
MCUs and are entered through instruction execution. This section describes how each module acts in the
low-power modes.
3.1.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but
the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See Chapter 8 Configuration Register
(CONFIG).)
3.1.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock
is disabled if the OSCSTOPENB bit in the CONFIG register is at a logic 0. (See Chapter 8 Configuration
Register (CONFIG).)
3.2 Analog-to-Digital Converter (ADC)
3.2.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
3.2.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
3.3 Break Module (BRK)
3.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if the SBSW bit in the break status register is set.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
37
Low-Power Modes
3.3.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the
SBSW bit in the break status register. The STOP instruction does not affect break module register states.
3.4 Central Processor Unit (CPU)
3.4.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
•
3.4.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
3.5 Clock Generator Module (CGM)
3.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
3.5.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
3.6 Computer Operating Properly Module (COP)
3.6.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
38
Freescale Semiconductor
External Interrupt Module (IRQ)
3.6.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent
inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the
STOP bit.
3.7 External Interrupt Module (IRQ)
3.7.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of wait mode.
3.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
3.8 Keyboard Interrupt Module (KBI)
3.8.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
3.8.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
3.9 Low-Voltage Inhibit Module (LVI)
3.9.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
3.9.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
39
Low-Power Modes
3.10 Serial Communications Interface Module (SCI)
3.10.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
3.10.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
3.11 Serial Peripheral Interface Module (SPI)
3.11.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module
can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
3.11.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI
operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
3.12 Timer Interface Module (TIM1 and TIM2)
3.12.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU
out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
3.12.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the
TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
40
Freescale Semiconductor
Timebase Module (TBM)
3.13 Timebase Module (TBM)
3.13.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
3.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
3.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt
vector:
•
•
•
•
•
•
•
•
External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the
program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
Break interrupt — A break interrupt loads the program counter with the contents of $FFFC and
$FFFD.
Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU
and loads the program counter with the contents of $FFFE and $FFFF.
Low-voltage inhibit module (LVI) reset — A power supply voltage below the Vtripf voltage resets the
MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
Clock generator module (CGM) interrupt — A CPU interrupt request from the phase-locked loop
(PLL) loads the program counter with the contents of $FFF8 and $FFF9.
Keyboard module (KBI) interrupt — A CPU interrupt request from the KBI module loads the
program counter with the contents of $FFE0 and $FFE1.
Timer 1 interface module (TIM1) interrupt — A CPU interrupt request from the TIM1 loads the
program counter with the contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the
program counter with the contents of:
•
– $FFEC and $FFED; TIM2 overflow
– $FFEE and $FFEF; TIM2 channel 1
– $FFF0 and $FFF1; TIM2 channel 0
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
41
Low-Power Modes
•
Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads
the program counter with the contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI
loads the program counter with the contents of:
•
– $FFE2 and $FFE3; SCI transmitter
– $FFE4 and $FFE5; SCI receiver
– $FFE6 and $FFE7; SCI receiver error
•
•
Analog-to-digital converter module (ADC) interrupt — A CPU interrupt request from the ADC loads
the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete.
Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program
counter with the contents of: $FFDC and $FFDD; TBM interrupt.
3.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an
interrupt vector:
•
External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
•
External interrupt — A high-to-low transition on an external interrupt pin loads the program counter
with the contents of locations:
– $FFFA and $FFFB; IRQ pin
– $FFE0 and $FFE1; keyboard interrupt pins
•
•
•
Low-voltage inhibit (LVI) reset — A power supply voltage below the LVItripf voltage resets the MCU
and loads the program counter with the contents of locations $FFFE and $FFFF.
Break interrupt — A break interrupt loads the program counter with the contents of locations $FFFC
and $FFFD.
Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents
of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit
stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay
during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
42
Freescale Semiconductor
Chapter 4
Resets and Interrupts
4.1 Introduction
Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes
the MCU to its startup condition. An interrupt vectors the program counter to a service routine.
4.2 Resets
A reset immediately returns the MCU to a known startup condition and begins program execution from a
user-defined memory location.
4.2.1 Effects
A reset:
•
•
•
Immediately stops the operation of the instruction being executed
Initializes certain control and status bits
Loads the program counter with a user-defined reset vector address from locations $FFFE and
$FFFF
•
Selects CGMXCLK divided by four as the bus clock
4.2.2 External Reset
A logic 0 applied to the RST pin for a time, tIRL, generates an external reset. An external reset sets the
PIN bit in the SIM reset status register.
4.2.3 Internal Reset
Sources:
•
•
•
•
•
Power-on reset (POR)
Computer operating properly (COP)
Low-power reset circuits
Illegal opcode
Illegal address
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external
devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
43
Resets and Interrupts
PULLED LOW BY MCU
32 CYCLES
RST PIN
32 CYCLES
CGMXCLK
INTERNAL
RESET
Figure 4-1. Internal Reset Timing
4.2.3.1 Power-On Reset
A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the
POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The
POR is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
•
Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
•
•
•
Drives the RST pin low during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
•
Sets the POR and LP bits in the SIM reset status register and clears all other bits in the register
OSC1
PORRST(1)
4096
32
32
CYCLES CYCLES CYCLES
CGMXCLK
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
44
Freescale Semiconductor
Resets
4.2.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
4.2.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVItripf voltage.
An LVI reset:
•
Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles after the power supply voltage rises to the LVItripr voltage
•
Drives the RST pin low for as long as VDD is below the LVItripr voltage and during the oscillator
stabilization delay
•
•
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
•
Sets the LVI bit in the SIM reset status register
4.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal
opcode reset.
4.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
4.2.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared
following a read of the register. Reset service can read the SIM reset status register to clear the register
after power-on reset and to determine the source of any subsequent reset.
The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the SRSR may be set
in addition to whatever other bits are set.
NOTE
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
45
Resets and Interrupts
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 4-3. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ = VDD
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
46
Freescale Semiconductor
Interrupts
4.3.1 Effects
An interrupt:
•
•
•
Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
Loads the program counter with a user-defined vector address
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
5
4
3
2
1
1
2
3
4
5
INDEX REGISTER (LOW BYTE)*
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
UNSTACKING
ORDER
•
•
•
$00FF DEFAULT ADDRESS ON RESET
*High byte of index register is not stacked.
Figure 4-4. Interrupt Stacking Order
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
47
Resets and Interrupts
After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
example shown in Figure 4-5, if an interrupt is pending upon exit from the interrupt service routine, the
pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
LDA #$FF
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 4-5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
48
Freescale Semiconductor
Interrupts
FROM RESET
YES
BREAK
INTERRUPT
?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT
?
NO
CGM
INTERRUPT
?
NO
OTHER
INTERRUPTS
?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
YES
YES
NO
RTI
INSTRUCTION
?
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
NO
Figure 4-6. Interrupt Processing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
49
Resets and Interrupts
4.3.2 Sources
The sources in Table 4-1 can generate CPU interrupt requests.
Table 4-1. Interrupt Sources
INT
Register
Flag
Vector
Address
Mask(1)
Priority(2)
Source
Flag
Reset
None
None
IRQF
None
None
None
None
IF1
0
0
1
$FFFE–$FFFF
$FFFC–$FFFD
SWI instruction
IRQ pin
IMASK
$FFFA–$FFFB
$FFF8–$FFF9
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
$FFEC–$FFED
CGM (PLL)
PLLF
CH0F
CH1F
TOF
PLLIE
CH0IE
CH1IE
TOIE
IF2
IF3
IF4
IF5
IF6
IF7
IF8
2
3
4
5
6
7
8
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
CH0F
CH1F
TOF
CH0IE
CH1IE
TOIE
SPI receiver full
SPI overflow
SPRF
OVRF
MODF
SPTE
OR
SPRIE
ERRIE
ERRIE
SPTIE
ORIE
IF9
9
$FFEA–$FFEB
$FFE8–$FFE9
SPI mode fault
SPI transmitter empty
SCI receiver overrun
SCI noise fag
IF10
10
NF
NEIE
IF11
11
$FFE6–$FFE7
SCI framing error
SCI parity error
SCI receiver full
SCI input idle
FE
FEIE
PE
PEIE
SCRF
IDLE
SCTE
TC
SCRIE
ILIE
IF12
IF13
12
13
$FFE4–$FFE5
$FFE2–$FFE3
SCI transmitter empty
SCI transmission complete
Keyboard pin
SCTIE
TCIE
KEYF
COCO
TBIF
IMASKK
AIEN
IF14
IF15
IF16
14
15
16
$FFE0–$FFE1
$FFDE–$FFDF
$FFDC–$FFDD
ADC conversion complete
Timebase
TBIE
Note:
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
4.3.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
50
Freescale Semiconductor
Interrupts
4.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
4.3.2.3 IRQ Pin
A logic 0 on the IRQ pin latches an external interrupt request.
4.3.2.4 CGM
The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or
leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.
PLLF is in the PLL control register.
4.3.2.5 TIM1
TIM1 CPU interrupt sources:
•
TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter reaches the modulo value
programmed in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable bit, TOIE,
enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and control
register.
•
TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.
4.3.2.6 TIM2
TIM2 CPU interrupt sources:
•
TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter reaches the modulo value
programmed in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE,
enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control
register.
•
TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU
interrupt requests. CHxF and CHxIE are in the TIM2 channel x status and control register.
4.3.2.7 SPI
SPI CPU interrupt sources:
•
SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register
to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control
register.
•
SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit
data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control
register.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
51
Resets and Interrupts
•
Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin goes high during a
transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if
the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE,
enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
•
Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data
register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control
register.
4.3.2.8 SCI
SCI CPU interrupt sources:
•
SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register transfers a character
to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU
interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2.
•
Transmission complete bit (TC) — TC is set when the transmit shift register and the SCI data
register are empty and no break or idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status
register 1. TCIE is in SCI control register 2.
•
•
•
SCI receiver full bit (SCRF) — SCRF is set when the receive shift register transfers a character to
the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2.
Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic 1s shift in from the RxD pin.
The idle line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
Receiver overrun bit (OR) — OR is set when the receive shift register shifts in a new character
before the previous character was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1.
ORIE is in SCI control register 3.
•
Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters,
including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control
register 3.
•
•
Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver expects a stop bit. The
framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
Parity error bit (PE) — PE is set when the SCI detects a parity error in incoming data. The parity
error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
52
Freescale Semiconductor
Interrupts
4.3.2.9 KBD0–KBD7 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt request.
4.3.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
4.3.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
4.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 4-2. Interrupt Source Flags
Interrupt Status
Interrupt Source
Register Flag
Reset
—
—
SWI instruction
IRQ pin
IF1
CGM (PLL)
IF2
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receive
IF3
IF4
IF5
IF6
IF7
IF8
IF9
SPI transmit
SCI error
IF10
IF11
IF12
IF13
IF14
IF15
IF16
SCI receive
SCI transmit
Keyboard
ADC conversion complete
Timebase
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
53
Resets and Interrupts
4.3.3.1 Interrupt Status Register 1
Address:
$FE04
Bit 7
6
IF5
R
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF6
R
R
0
R
0
0
0
0
0
0
0
R = Reserved
Figure 4-7. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 and Bit 0 — Always read 0
4.3.3.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
6
IF13
R
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF14
R
0
0
0
0
0
0
0
0
R = Reserved
Figure 4-8. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
4.3.3.3 Interrupt Status Register 3
Address:
$FE06
Bit 7
6
0
5
0
4
0
3
0
2
0
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
0
R
0
R
0
R
0
R
0
0
0
0
R = Reserved
Figure 4-9. Interrupt Status Register 3 (INT3)
IF16–IF15 — Interrupt Flags 16–15
This flag indicates the presence of an interrupt request from the source shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bits 7–2 — Always read 0
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
54
Freescale Semiconductor
Chapter 5
Analog-to-Digital Converter (ADC)
5.1 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
5.2 Features
Features of the ADC module include:
•
•
•
•
•
•
Eight channels with multiplexed input
Linear successive approximation with monotonicity
8-bit resolution
Single or continuous conversion
Conversion complete flag or conversion complete interrupt
Selectable ADC clock
5.3 Functional Description
The ADC provides eight pins for sampling external sources at pins PTB7/AD7–PTB0/AD0. An analog
multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in
(VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC data register and sets a flag or
generates an interrupt. (See Figure 5-1.)
5.3.1 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The
channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides
the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR
will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC
will return a logic 0.
5.3.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the
input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a
straight-line linear conversion.
NOTE
Inside the ADC module, the reference voltages VREFH is connected to the
ADC analog power, VDDAD; and VREFL is connected to the ADC analog
ground, VSSAD. Therefore, the ADC input voltage should not exceed these
analog supply voltages.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
55
Analog-to-Digital Converter (ADC)
INTERNAL
DATA BUS
READ DDRBx
WRITE DDRBx
DISABLE
DDRBx
PTBx
RESET
WRITE PTBx
PTBx
ADC CHANNEL x
READ PTBx
DISABLE
ADC DATA REGISTER
ADC
VOLTAGE IN
CONVERSION
COMPLETE
ADCH4–ADCH0
(VADIN
)
CHANNEL
SELECT
INTERRUPT
LOGIC
ADC
ADC CLOCK
AIEN COCO
CGMXCLK
CLOCK
GENERATOR
BUS CLOCK
ADIV2–ADIV0 ADICLK
Figure 5-1. ADC Block Diagram
NOTE
Connect the VDDAD pin to the same voltage potential as the VDD pin, and
connect the VSSAD pin to the same voltage potential as the VSS pin.
The VDDAD pin should be routed carefully for maximum noise immunity.
5.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
16 to 17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time
× bus frequency
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
56
Freescale Semiconductor
Interrupts
5.3.4 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and
will stay set until the next write of the ADC status and control register or the next read of the ADC data
register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs
between writes to the ADSCR.
5.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
5.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
5.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption standby modes.
5.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
5.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
5.6 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7–PTB0/AD0.
5.6.1 ADC Analog Power Pin (V
)/ADC Voltage Reference High Pin (V
)
REFH
DDAD
The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage
potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results.
NOTE
For maximum noise immunity, route VDDAD carefully and place bypass
capacitors as close as possible to the package.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
57
Analog-to-Digital Converter (ADC)
5.6.2 ADC Analog Ground Pin (V
)/ADC Voltage Reference Low Pin (V
)
REFL
SSAD
The ADC analog portion uses VSSAD as its ground pin. Connect the VSSAD pin to the same voltage
potential as VSS.
NOTE
Route VSSAD cleanly to avoid any offset errors.
5.6.3 ADC Voltage In (V
)
ADIN
VADIN is the input voltage signal from one of the eight ADC channels to the ADC module.
5.7 I/O Registers
These I/O registers control and monitor ADC operation:
•
•
•
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADCLK)
5.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address:
$003C
Bit 7
6
AIEN
0
5
ADCO
0
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Read:
Write:
Reset:
COCO
0
Figure 5-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed except in the continuous conversion mode where it is set after the first conversion. This bit
is cleared whenever the ADSCR is written or whenever the ADR is read.
If the AIEN bit is a logic 1, the COCO becomes a read/write bit, which should be cleared to logic 0 for
CPU to service the ADC interrupt request. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
58
Freescale Semiconductor
I/O Registers
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight
channels, AD7–AD0, are available on this MCU. The channels are detailed in Table 5-1. Care should
be taken when using a port pin as both an analog and digital input simultaneously to prevent switching
noise from corrupting the analog signal. (See Table 5-1.)
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in Table 5-1, are used to verify the
operation of the ADC converter both in production test and for user applications.
Table 5-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
PTB0/AD0
PTB1/AD1
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
0
0
0
0
0
0
0
0
0
↓
1
1
0
0
0
0
0
0
0
0
1
↓
1
1
0
0
0
0
1
1
1
1
0
↓
1
1
0
0
1
1
0
0
1
1
0
↓
0
0
0
1
0
1
0
1
0
1
0
↓
0
1
Reserved
VREFH
VREFL
1
1
1
1
1
1
1
1
0
1
ADC power off
NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown
or reserved.
5.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Address:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
59
Analog-to-Digital Converter (ADC)
5.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address:
$003E
Bit 7
6
ADIV1
0
5
ADIV0
0
4
ADICLK
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
0
0
0
0
0
= Unimplemented
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 5-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal
ADC clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
----------------------------------------------------------------------- = 1 MHz
ADIV2–ADIV0
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
60
Freescale Semiconductor
Chapter 6
Break Module (BRK)
6.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
6.2 Features
Features of the break module include:
•
•
•
•
Accessible input/output (I/O) registers during the break interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
6.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 6-1 shows the
structure of the break module.
6.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
6.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
61
Break Module (BRK)
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 6-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
Read:
Write:
Reset:
Read:
R
R
R
R
R
R
R
SIM Break Status Register
(SBSR)
$FE00
SIM Break Flag Control Reg-
BCFE
0
R
R
R
R
R
R
R
$FE03
$FE09
$FE0A
$FE0B
ister Write:
(SBFCR)
Reset:
Read:
Break Address
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
Register High Write:
(BRKH)
Reset:
0
Read:
Break Address
Register Low Write:
Bit 7
0
6
0
5
4
3
2
Bit 0
(BRKL)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Figure 6-2. I/O Register Summary
6.3.3 TIM1 and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
6.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
62
Freescale Semiconductor
Low-Power Modes
6.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set. See Chapter 3 Low-Power Modes. Clear the SBSW bit by
writing logic 0 to it.
6.4.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
6.5 Break Module Registers
These registers control and monitor operation of the break module:
•
•
•
•
•
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
SIM break status register (SBSR)
SIM break flag control register (SBFCR)
6.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 6-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0
to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
63
Break Module (BRK)
6.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address:
$FE09
Bit 7
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Bit 15
0
Figure 6-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 6-5. Break Address Register Low (BRKL)
6.5.3 Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop or
wait mode. The flag is useful in applications requiring a return to stop or wait mode after exiting from a
break interrupt.
Address:
$FE00
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 6-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This read/write bit is set when a break interrupt causes an exit from stop or wait mode. Clear SBSW
by writing a logic 0 to it. Reset clears SBSW.
1 = Break interrupt during stop/wait mode
0 = No break interrupt during stop/wait mode
SBSW can be read within the break interrupt routine. The user can modify the return address on the stack
by subtracting 1 from it.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
64
Freescale Semiconductor
Break Module Registers
6.5.4 Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while
the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 6-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
65
Break Module (BRK)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
66
Freescale Semiconductor
Chapter 7
Clock Generator Module (CGMC)
7.1 Introduction
This section describes the clock generator module. The CGMC generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal.
7.2 Features
Features of the CGMC include:
•
Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
•
•
•
•
•
•
•
Low-frequency crystal operation with low-power operation and high-output frequency resolution
Programmable prescaler for power-of-two increases in frequency
Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
CPU interrupt on entry or exit from locked condition
Configuration register bit to allow oscillator operation during stop mode
7.3 Functional Description
The CGMC consists of three major submodules:
•
•
•
Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
Figure 7-1 shows the structure of the CGMC.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
67
Clock Generator Module (CGMC)
OSCILLATOR (OSC)
OSC2
CGMXCLK
(TO: SIM, TIMTB15A, ADC)
OSC1
SIMOSCEN (FROM SIM)
OSCSTOPENB
(FROM CONFIG)
PHASE-LOCKED LOOP (PLL)
CGMRDV
CGMRCLK
CGMXFC
REFERENCE
DIVIDER
A
B
CGMOUT
(TO SIM)
CLOCK
SELECT
CIRCUIT
÷
2
S*
BCS
R
RDS3–RDS0
SIMDIV2
*WHEN S = 1,
CGMOUT = B
VDDA
VSSA
(FROM SIM)
VPR1–VPR0
VRS7–VRS0
L
2E
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
CGMVCLK
PLL ANALOG
AUTOMATIC
MODE
CONTROL
PLLIREQ
(TO SIM)
LOCK
DETECTOR
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL11–MUL0
PRE1–PRE0
2P
N
CGMVDV
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER
Figure 7-1. CGMC Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
68
Freescale Semiconductor
Functional Description
7.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
7.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
7.3.3 PLL Circuits
The PLL consists of these circuits:
•
•
•
•
•
•
•
Voltage-controlled oscillator (VCO)
Reference divider
Frequency prescaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the
CGM/XFC pin changes the frequency within this range. By design, fVRS is equal to the nominal
center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
(L × 2E)fNOM
.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
RDV = fRCLK/R. With an external crystal
(30 kHz–100 kHz), always set R = 1 for specified performance. With an external high-frequency clock
source, use R to divide the external frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output
is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N × 2P). (See 7.3.6
Programming the PLL for more information.)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
69
Clock Generator Module (CGMC)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 7.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
7.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
•
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 7.5.2 PLL Bandwidth Control Register.)
•
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 7.3.8 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ bit is set.
7.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 7.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See 7.3.8 Base Clock Selector Circuit.) If
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See 7.6
Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
•
The ACQ bit (See 7.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of
the filter. (See 7.3.4 Acquisition and Tracking Modes.)
•
The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for
more information.)
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
70
Freescale Semiconductor
Functional Description
•
•
The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 7.5.1 PLL Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
fBUSMAX
.
The following conditions apply when in manual mode:
•
•
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 7.8
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
•
Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
•
•
The LOCK bit is disabled.
CPU interrupts from the CGMC are disabled.
7.3.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES
.
2. Calculate the desired VCO frequency (four times the desired bus frequency).
f
= 4 × f
VCLKDES
BUSDES
3. Choose a practical PLL (crystal) reference frequency, fRCLK, and the reference clock divider, R.
Typically, the reference crystal is 32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is
P
2 N
R
f
= ----------- (f
)
RCLK
VCLK
P, the power of two multiplier, and N, the range multiplier, are integers.
In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 23 Electrical
Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus
frequency can be determined using equation in 2 above.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
71
Clock Generator Module (CGMC)
When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES
and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with
practical choices of fRCLK, and choose the fRCLK that gives the lowest R.
,
f
f
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
⎧
⎨
⎩
⎫
⎬
⎭
VCLKDES
VCLKDES
-------------------------
-------------------------
R = round R
×
– integer
MAX
f
f
RCLK
RCLK
4. Select a VCO frequency multiplier, N.
R × f
⎛
⎜
⎝
⎞
⎟
⎠
VCLKDES
------------------------------------
N = round
f
RCLK
Reduce N/R to the lowest possible R.
5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table:
Current N Value
P
0 < N ≤ N
0
max
N
< N ≤ N
× 2
1
2
3
max
max
N
N
× 2 < N ≤ N
× 4
max
max
max
max
× 4 < N ≤ N
× 8
Then recalculate N:
R × f
⎛
⎜
⎝
⎞
⎟
⎠
VCLKDES
------------------------------------
P
N = round
f
× 2
RCLK
6. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS
.
P
f
= (2 × N ⁄ R) × f
VCLK
RCLK
f
= (f
) ⁄ 4
VCLK
BUS
7. Select the VCO’s power-of-two range multiplier E, according to this table:
Frequency Range
0 < fVCLK < 9,830,400
E
0
1
2
9,830,400 ≤ fVCLK < 19,660,800
19,660,800 ≤ fVCLK < 39,321,600
NOTE: Do not program E to a value of 3.
8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz
f
⎛
⎜
⎝
⎞
⎟
⎠
VCLK
--------------------------
L = round
E
2 × f
NOM
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
72
Freescale Semiconductor
Functional Description
9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
E
f
= (L × 2 )f
VRS
NOM
For proper operation,
E
f
× 2
NOM
--------------------------
f
– f
≤
VCLK
VRS
2
10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper
operation, fVCLK must be within the application’s tolerance of fVCLKDES, and fVRS must be as close
as possible to fVCLK
.
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of
R.
NOTE
The values for P, E, N, L, and R can only be programmed when the PLL is
off (PLLON = 0).
Table 7-1 provides numeric examples (numbers are in hexadecimal notation):
Table 7-1. Numeric Example
fBUS
fRCLK
R
1
1
1
1
1
1
1
1
N
P
0
0
0
0
0
0
0
0
E
0
1
1
1
2
2
2
2
L
2.0 MHz
2.4576 MHz
2.5 MHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
F5
D1
80
83
D1
80
82
C0
D0
12C
132
1E9
258
263
384
3D1
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
73
Clock Generator Module (CGMC)
7.3.7 Special Programming Exceptions
The programming method described in 7.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
•
•
A 0 value for R or N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 7.3.8 Base Clock Selector Circuit.)
7.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
7.3.9 CGMC External Connections
In its typical configuration, the CGMC requires up to nine external components. Five of these are for the
crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-2.
Figure 7-2 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 7-2 also shows the external components for the PLL:
•
•
Bypass capacitor, CBYP
Filter network
Routing should be done with great care to minimize signal cross talk and noise.
See 23.16.1 CGM Component Specifications for capacitor and resistor values.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
74
Freescale Semiconductor
I/O Signals
SIMOSCEN
OSCSTOPENB
(FROM CONFIG)
CGMXCLK
VSSA
VDDA
OSC1
OSC2
RS
CGMXFC
VDD
RB
10 kΩ
CBYP
0.1 µF
0.01 µF
0.033 µF
X1
C1
C2
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
Figure 7-2. CGMC External Connections
7.4 I/O Signals
The following paragraphs describe the CGMC I/O signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 7-2.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
75
Clock Generator Module (CGMC)
7.4.4 PLL Analog Power Pin (V
)
DDA
VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage
potential as the VDD pin.
NOTE
Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
7.4.5 PLL Analog Ground Pin (V
)
SSA
VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage
potential as the VSS pin.
NOTE
Route VSSA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
7.4.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and
PLL.
7.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)
OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during
stop mode. If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default),
the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.
7.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 7-2 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
7.4.9 CGMC Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGMC. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
7.4.10 CGMC CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
76
Freescale Semiconductor
CGMC Registers
7.5 CGMC Registers
These registers control and monitor operation of the CGMC:
•
•
•
•
•
•
PLL control register (PCTL)
(See 7.5.1 PLL Control Register.)
PLL bandwidth control register (PBWC)
(See 7.5.2 PLL Bandwidth Control Register.)
PLL multiplier select register high (PMSH)
(See 7.5.3 PLL Multiplier Select Register High.)
PLL multiplier select register low (PMSL)
(See 7.5.4 PLL Multiplier Select Register Low.)
PLL VCO range select register (PMRS)
(See 7.5.5 PLL VCO Range Select Register.)
PLL reference divider select register (PMDS)
(See 7.5.6 PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr.
Register Name
Bit 7
PLLIE
0
6
PLLF
5
PLLON
1
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
BCS
PRE1
PRE0
VPR1
VPR0
PLL Control Register
(PCTL)
$0036
0
0
0
0
0
0
0
0
0
0
LOCK
PLL Bandwidth Control
AUTO
ACQ
R
$0037
$0038
Register Write:
(PBWC)
Reset:
Read:
0
0
0
0
0
0
0
0
0
MUL11
0
0
MUL10
0
0
MUL9
0
0
MUL8
0
PLL Multiplier Select High
Register Write:
(PMSH)
Reset:
Read:
0
0
0
0
PLL Multiplier Select Low
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
MUL2
0
MUL1
0
MUL0
0
$0039
Register Write:
(PMSL)
Reset:
Read:
PLL VCO Range Select
VRS7
VRS6
VRS5
VRS4
VRS3
0
VRS2
0
VRS1
0
VRS0
0
$003A
$003B
NOTES:
Register Write:
(PMRS)
Reset:
Read:
0
0
1
0
0
0
0
0
PLL Reference Divider
RDS3
RDS2
0
RDS1
0
RDS0
1
Select Register Write:
(PMDS)
Reset:
0
0
0
0
0
= Unimplemented
R
= Reserved
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
77
Clock Generator Module (CGMC)
7.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address:
$0036
Bit 7
6
5
PLLON
1
4
BCS
0
3
PRE1
0
2
PRE0
0
1
VPR1
0
Bit 0
VPR0
0
Read:
Write:
Reset:
PLLF
PLLIE
0
0
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 7.3.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGMC output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 7.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
78
Freescale Semiconductor
CGMC Registers
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
7.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
Table 7-2. PRE1 and PRE0 Programming
PRE1 and PRE0
P
0
1
2
3
Prescaler Multiplier
00
01
10
11
1
2
4
8
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.5 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when
the PLLON bit is set. Reset clears these bits.
Table 7-3. VPR1 and VPR0 Programming
VCO Power-of-Two
Range Multiplier
VPR1 and VPR0
E
00
01
10
11
0
1
2
1
2
4
8
3(1)
1. Do not program E to a value of 3.
7.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
•
•
•
•
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
79
Clock Generator Module (CGMC)
Address:
$0037
Bit 7
6
5
ACQ
0
4
0
3
0
2
0
1
0
Bit 0
R
Read:
Write:
Reset:
LOCK
AUTO
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 7-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
7.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
Address:
$0038
Bit 7
0
6
0
5
4
0
3
MUL11
0
2
MUL10
0
1
MUL9
0
Bit 0
MUL8
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) A value of $0000 in
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
80
Freescale Semiconductor
CGMC Registers
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address:
$0038
Bit 7
6
MUL6
1
5
MUL5
0
4
MUL4
0
3
MUL3
0
2
MUL2
0
1
MUL1
0
Bit 0
MUL0
0
Read:
Write:
Reset:
MUL7
0
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
7.5.5 PLL VCO Range Select Register
NOTE
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address:
$003A
Bit 7
6
VRS6
1
5
VRS5
0
4
VRS4
0
3
VRS3
0
2
VRS2
0
1
VRS1
0
Bit 0
VRS0
0
Read:
Write:
Reset:
VRS7
0
Figure 7-8. PLL VCO Range Select Register (PMRS)
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.1 PLL Control Register.), controls the
hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
81
Clock Generator Module (CGMC)
PCTL is set. (See 7.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 7.3.8 Base
Clock Selector Circuit and 7.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
NOTE
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
7.5.6 PLL Reference Divider Select Register
NOTE
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
Address:
$003B
Bit 7
0
6
0
5
4
0
3
RDS3
0
2
RDS2
0
1
RDS1
0
Bit 0
RDS0
1
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 7-9. PLL Reference Divider Select Register (PMDS)
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See 7.3.7 Special Programming Exceptions.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE
The default divide value of 1 is recommended for all applications.
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Special Modes
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
7.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The WAIT instruction does not affect the CGMC. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
7.7.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the
PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the
crystal clock divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
7.7.3 CGMC During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 19.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
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Freescale Semiconductor
83
Clock Generator Module (CGMC)
7.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
7.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz.
Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5% of the
100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
7.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV
.
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency fXCLK and the
R value programmed in the reference divider. (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and
7.5.6 PLL Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See 7.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to VDDA. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
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Acquisition/Lock Time Specifications
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
7.8.3 Choosing a Filter
As described in 7.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the
stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage.
Either of the filter networks in Figure 7-10 is recommended when using a 32.768kHz reference crystal.
Figure 7-10 (a) is used for applications requiring better stability. Figure 7-10 (b) is used in low-cost
applications where stability is not critical.
CGMXFC
CGMXFC
10 kΩ
0.01 µF
0.47 µF
0.033 µF
VSSA
VSSA
(a)
(b)
Figure 7-10. PLL Filter
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Clock Generator Module (CGMC)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Chapter 8
Configuration Register (CONFIG)
8.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
enable or disable these options:
•
•
•
•
•
•
Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
COP timeout period (218 – 24 or 213 – 24 CGMXCLK cycles)
STOP instruction
Computer operating properly module (COP)
Low-voltage inhibit (LVI) module control and voltage trip point selection
Enable/disable the oscillator (OSC) during stop mode
8.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
register may be read at anytime.
NOTE
On a FLASH device, the options except LVI5OR3 are one-time writeable by
the user after each reset. The LVI5OR3 bit is one-time writeable by the user
only after each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writeable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in Figure 8-1 and Figure 8-2.
Address:
$001E
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
OSCSTOPENB SCIBDSRC
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-1. Configuration Register 2 (CONFIG2)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
87
Configuration Register (CONFIG)
Address:
$001F
Bit 7
6
5
4
3
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3
See Note
0
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 8-2. Configuration Register 1 (CONFIG1)
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See 3.5
Clock Generator Module (CGM) subsection 3.5.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See Chapter 9 Computer Operating
Properly (COP).)
1 = COP timeout period = 213 – 24 CGMXCLK cycles
0 = COP timeout period = 218 – 24 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP. (See
3.5.2 Stop Mode.)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Chapter 14 Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Chapter 14 Low-Voltage Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
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Freescale Semiconductor
Functional Description
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. (See Chapter 14 Low-Voltage Inhibit
(LVI).) The voltage mode selected for the LVI should match the operating VDD. See Chapter 23
Electrical Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE
When the LVISTOP is enabled, the system stabilization time for power on
reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the MCU
is not protected from a low power condition. However, when using the short
stop recovery configuration option, the 32-CGMXCLK delay is less than the
LVI’s turn-on time and there exists a period in startup where the LVI is not
protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 9 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Configuration Register (CONFIG)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Chapter 9
Computer Operating Properly (COP)
9.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG register.
9.2 Functional Description
Figure 9-1 shows the structure of the COP module.
RESET CIRCUIT
12-BIT COP PRESCALER
CGMXCLK
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SEL
(FROM CONFIG)
Figure 9-1. COP Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 218 – 24 or 213 – 24
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 213 – 24 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout
period of 250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset
by clearing the COP counter and stages 12 through 5 of the prescaler.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state,
VTST on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
9.3 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1.
9.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
9.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
9.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 9.4 COP Control Register) clears the COP
counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low
byte of the reset vector.
9.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
9.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
9.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
COP Control Register
9.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 8 Configuration Register (CONFIG).)
9.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. (See
Chapter 8 Configuration Register (CONFIG).)
9.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 9-2. COP Control Register (COPCTL)
9.5 Interrupts
The COP does not generate CPU interrupt requests.
9.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
9.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
9.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
93
Computer Operating Properly (COP)
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
9.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Chapter 10
Central Processor Unit (CPU)
10.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
10.2 Features
Features of the CPU include:
•
•
•
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
•
Low-power stop and wait modes
10.3 CPU Registers
Figure 10-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
95
Central Processor Unit (CPU)
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 10-1. CPU Registers
10.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 10-2. Accumulator (A)
10.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15 14 13 12 11 10
Bit
0
9
0
8
0
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 10-3. Index Register (H:X)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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CPU Registers
10.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 10-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
10.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 10-5. Program Counter (PC)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Central Processor Unit (CPU)
10.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
1
1
5
1
1
4
H
X
3
2
N
X
1
Z
X
Bit 0
Read:
Write:
Reset:
V
I
C
X
1
X
X = Indeterminate
Figure 10-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
98
Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
10.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
10.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
•
10.5.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
10.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
99
Central Processor Unit (CPU)
10.7 Instruction Set Summary
Table 10-1 provides a summary of the M68HC08 instruction set.
Table 10-1. Instruction Set Summary (Sheet 1 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
ꢀ
ꢀ
ꢀ
ꢀ
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
9EEB ff
9EDB ee ff
2
3
4
4
3
2
4
5
Add without Carry
A ← (A) + (M)
IX1
IX
SP1
SP2
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
AND #opr
AND opr
IMM
DIR
EXT
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IX2
Logical AND
A ← (A) & (M)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
DIR
INH
38 dd
48
4
1
1
4
3
5
ASLX
Arithmetic Shift Left
(Same as LSL)
INH
58
C
0
ꢀ
ꢀ
ASL opr,X
ASL ,X
IX1
68 ff
78
b7
b7
b0
b0
IX
ASL opr,SP
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
37 dd
47
4
1
1
4
3
5
INH
57
C
Arithmetic Shift Right
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
IX1
67 ff
77
IX
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
Branch if Greater Than (Signed
Operands)
3
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
100
Freescale Semiconductor
Instruction Set Summary
Table 10-1. Instruction Set Summary (Sheet 2 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
3
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IX2
Bit Test
(A) & (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
–
–
–
–
–
– REL
93 rr
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ꢀ
BRN rel
Branch Never
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
ꢀ
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
101
Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 3 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
5F
CLRH
Clear
0
–
–
–
–
0
1
– INH
IX1
8C
CLR opr,X
CLR ,X
6F ff
7F
IX
SP1
CLR opr,SP
9E6F ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
IX2
Compare A with M
(A) – (M)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
F1
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
33 dd
43
4
1
1
4
3
5
COMX
INH
53
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
1
COM opr,X
COM ,X
COM opr,SP
IX1
63 ff
73
9E63 ff
IX
SP1
CPHX #opr
CPHX opr
IMM
ꢀ
65 ii ii+1
75 dd
3
4
(H:X) – (M:M + 1)
ꢀ
DIR
CPX #opr
CPX opr
IMM
DIR
EXT
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
CPX opr
CPX ,X
IX2
Compare X with M
(X) – (M)
(A)10
ꢀ
–
–
ꢀ
ꢀ
ꢀ
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IX1
IX
F3
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
U –
–
–
ꢀ
ꢀ
ꢀ INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DIR
INH
3B dd rr
4B rr
DBNZX rel
Decrement and Branch if Not Zero
–
–
–
–
– INH
IX1
5B rr
DBNZ opr,X,rel
DBNZ X,rel
6B ff rr
7B rr
IX
SP1
DBNZ opr,SP,rel
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
3A dd
4A
4
1
1
4
3
5
DECX
INH
5A
Decrement
Divide
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
–
DEC opr,X
DEC ,X
DEC opr,SP
IX1
6A ff
7A
9E6A ff
IX
SP1
A ← (H:A)/(X)
DIV
–
–
ꢀ INH
52
7
H ← Remainder
EOR #opr
EOR opr
IMM
DIR
EXT
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IX2
Exclusive OR M with A
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
A ← (A ⊕ M)
IX1
IX
F8
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
3C dd
4C
4
1
1
4
3
5
INCX
INH
5C
Increment
ꢀ
–
INC opr,X
INC ,X
IX1
6C ff
7C
IX
INC opr,SP
SP1
9E6C ff
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
102
Freescale Semiconductor
Instruction Set Summary
Table 10-1. Instruction Set Summary (Sheet 4 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
JMP opr
DIR
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
EXT
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
– IX2
IX1
IX
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IX2
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
–
45 ii jj
55 dd
3
4
DIR
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
IX2
–
IX1
IX
SP1
SP2
LSL opr
LSLA
DIR
INH
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
INH
58
C
0
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
LSL opr,X
LSL ,X
LSL opr,SP
IX1
68 ff
78
9E68 ff
b7
b7
b0
b0
IX
SP1
LSR opr
LSRA
DIR
INH
34 dd
44
4
1
1
4
3
5
LSRX
INH
54
0
C
Logical Shift Right
0
ꢀ
LSR opr,X
LSR ,X
IX1
64 ff
74
IX
LSR opr,SP
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
Move
0
–
–
0
–
–
ꢀ
ꢀ
–
IMD
IX+D
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
DIR
INH
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
INH
50
Negate (Two’s Complement)
ꢀ
–
–
ꢀ
ꢀ
ꢀ
NEG opr,X
NEG ,X
NEG opr,SP
IX1
60 ff
70
9E60 ff
IX
SP1
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IX2
Inclusive OR A and M
A ← (A) | (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
87
8B
89
2
2
2
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
103
Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 5 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PULA
PULH
PULX
Pull A from Stack
Pull H from Stack
Pull X from Stack
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
86
8A
88
2
2
2
ROL opr
ROLA
DIR
INH
39 dd
49
4
1
1
4
3
5
ROLX
INH
59
C
Rotate Left through Carry
Rotate Right through Carry
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ROL opr,X
ROL ,X
ROL opr,SP
IX1
69 ff
79
9E69 ff
b7
b0
IX
SP1
ROR opr
RORA
DIR
INH
36 dd
46
4
1
1
4
3
5
RORX
INH
56
C
ꢀ
ROR opr,X
ROR ,X
IX1
66 ff
76
b7
b0
IX
ROR opr,SP
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
–
– INH
81
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
IX2
A ← (A) – (M) – (C)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
ꢀ
ꢀ
– IX1
IX
F7
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
ꢀ
ꢀ
– DIR
35 dd
4
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
STOP
I ← 0; Stop Processing
–
–
– INH
8E
1
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
– IX1
IX
FF
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
Subtract
A ← (A) – (M)
ꢀ
ꢀ
IX1
IX
F0
SP1
SP2
9EE0 ff
9ED0 ee ff
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
104
Freescale Semiconductor
Opcode Map
Table 10-1. Instruction Set Summary (Sheet 6 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
A ← (CCR)
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
TST opr
TSTA
DIR
INH
3D dd
4D
3
1
1
3
2
4
TSTX
INH
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
ꢀ
ꢀ
–
TST opr,X
TST ,X
TST opr,SP
IX1
6D ff
7D
9E6D ff
IX
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
(SP) ← (H:X) – 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
I bit ← 0; Inhibit CPU clocking
WAIT
Enable Interrupts; Wait for Interrupt
–
–
0
–
–
– INH
8F
1
until interrupted
A
Accumulator
n
Any bit
C
Carry/borrow bit
opr Operand (one or two bytes)
PC Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
Relative program counter offset byte
Relative program counter offset byte
H
H
Undefined
Overflow bit
Index register low byte
Zero bit
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
ii
Logical AND
Logical OR
IMD
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
⊕
Logical EXCLUSIVE OR
Contents of
( )
–( ) Negation (two’s complement)
#
IX+
Immediate value
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
:
ꢀ
—
N
Negative bit
10.8 Opcode Map
See Table 10-2.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
105
Table 10-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
RTI
INH
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
2
IX1 3 SP1 1 IX
5
1
1
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2 2 IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1 1 IX
3
BRN
REL 3 DIR
5
4
4
6
4
4
3
BLT
2
3
4
4
5
3
4
2
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
CBEQ
RTS
CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
IMM 3 IMM 3 IX1+
4
SP1 2 IX+
INH
REL 2 IMM 2 DIR
EXT 3 IX2
SP2 2 IX1
SP1 1 IX
3
5
7
3
2
DAA
3
BGT
2
SBC
3
SBC
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
SBC
5
SBC
SP2 2 IX1
5
CPX
SP2 2 IX1
5
AND
SP2 2 IX1
5
BIT
SP2 2 IX1
5
LDA
SP2 2 IX1
5
STA
SP2 2 IX1
5
EOR
SP2 2 IX1
5
ADC
SP2 2 IX1
3
SBC
4
SBC
SP1 1 IX
4
CPX
SP1 1 IX
4
AND
SP1 1 IX
4
BIT
SP1 1 IX
4
LDA
SP1 1 IX
4
STA
SP1 1 IX
4
EOR
SP1 1 IX
4
ADC
SP1 1 IX
2
SBC
BRSET1 BSET1
BHI
MUL
INH
DIV
INH
NSA
3
DIR
5
2
DIR
4
REL
1
1
1
2
2
3
2
2
2
2
2
INH
1
INH
3
REL 2 IMM 2 DIR
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
3
BLE
2
CPX
3
CPX
4
CPX
3
CPX
2
CPX
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
COM
SWI
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1 1 IX
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
4
LSR
1
LSRA
INH
1
LSRX
INH
5
LSR
SP1 1 IX
3
LSR
2
2
2
AND
IMM 2 DIR
3
AND
4
AND
3
AND
2
AND
4
BRSET2 BSET2
TAP
TXS
3
DIR
5
2
DIR
4
1
3
1
INH
INH
2
2
2
2
2
2
2
2
4
3
4
4
1
2
2
BIT
3
BIT
4
BIT
3
BIT
2
BIT
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
CPHX
TPA
TSX
3
DIR
5
2
DIR
4
IMM 2 DIR
2
DIR
3
INH
INH
IMM 2 DIR
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
LDA
4
LDA
3
LDA
2
LDA
6
BRSET3 BSET3
RORA
RORX
ROR
SP1 1 IX
5
ASR
SP1 1 IX
5
LSL
SP1 1 IX
5
ROL
SP1 1 IX
ROR
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
3
BEQ
REL 2 DIR
3
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
3
ASR
1
3
STA
4
STA
3
STA
2
STA
7
BRCLR3 BCLR3
TAX
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INH
4
LSL
3
LSL
1
3
EOR
4
EOR
3
EOR
2
EOR
8
BRSET4 BSET4 BHCC
CLC
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
INH
4
ROL
3
ROL
1
3
ADC
4
ADC
3
ADC
2
ADC
9
BRCLR4 BCLR4 BHCS
SEC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
INH
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
4
DEC
5
DEC
SP1 1 IX
3
DEC
2
3
ORA
4
ORA
5
ORA
SP2 2 IX1
5
ADD
SP2 2 IX1
3
ORA
4
ORA
SP1 1 IX
4
ADD
SP1 1 IX
2
ORA
A
B
C
D
E
F
BRSET5 BSET5
CLI
3
DIR
5
2
DIR
4
INH
5
3
3
5
6
4
2
3
ADD
4
ADD
3
ADD
2
ADD
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
DBNZ
SEI
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
SP1 2 IX
INH
3
4
INC
5
INC
SP1 1 IX
4
TST
SP1 1 IX
3
INC
1
2
JMP
4
JMP
3
JMP
2
BRSET6 BSET6
BMC
INCA
INCX
INC
RSP
JMP
3
DIR
5
2
DIR
4
REL 2 DIR
INH
1
INH
1
IX1
3
INH
2
DIR
4
2
2
IX1
5
1
1
IX
3
BMS
3
TST
2
TST
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
4
JSR
IX
2
LDX
BRCLR6 BCLR6
TSTA
TSTX
TST
NOP
JSR
JSR
3
DIR
5
2
DIR
4
REL 2 DIR
3
INH
5
INH
4
IX1
4
INH
2
2
2
IX1
3
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
LDX
SP2 2 IX1
5
STX
SP2 2 IX1
4
LDX
SP1 1 IX
4
STX
SP1 1 IX
BRSET7 BSET7
BIL
MOV
MOV
MOV
MOV
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
DD
DIX+
IMD
3
2
IX+D
1
1
4
4
3
3
3
CLR
1
CLRA
INH
1
CLRX
INH
4
CLR
SP1 1 IX
2
CLR
3
STX
4
STX
3
STX
2
STX
BRCLR7 BCLR7
BIH
CLR
IX1
3
DIR
2
DIR
REL 2 DIR
3
1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
Chapter 11
FLASH Memory
11.1 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program, erase, and read operations are
enabled through the use of an internal charge pump.
11.2 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional 36 bytes of user vectors and one byte
of block protection. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. Memory in
the FLASH array is organized into two rows per page basis. For the 32K word by 8-Bit Embedded FLASH
Memory, the page size is 128 bytes per page. Hence the minimum erase page size is 128 bytes. Program
and erase operation operations are facilitated through control bits in FLASH Control Register (FLCR).
Details for these operations appear later in this section. The address ranges for the user memory and
vectors are:
•
•
•
•
$8000–$FDFF; user memory.
$FF7E; FLASH block protect register.
$FE08; FLASH control register.
$FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors.
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
107
FLASH Memory
11.3 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address:
$FE08
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 11-1. FLASH Control Register (FLCR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 32Kbyte FLASH array for mass erase operation.
1 = MASS erase operation selected
0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
108
Freescale Semiconductor
FLASH Page Erase Operation
11.4 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH memory to read as logic 1:
1. Set the ERASE bit, and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address range desired.
4. Wait for a time, tnvs (min. 10µs)
5. Set the HVEN bit.
6. Wait for a time, tErase (min. 1ms)
7. Clear the ERASE bit.
8. Wait for a time, tnvh (min. 5µs)
9. Clear the HVEN bit.
10. After a time, trcv (typ. 1µs), the memory can be accessed again in read mode.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
11.5 FLASH Mass Erase Operation
Use this step-by-step procedure to erase entire FLASH memory to read as logic 1:
1. Set both the ERASE bit, and the MASS bit in the FLASH control register.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tnvs (min. 10µs)
5. Set the HVEN bit.
6. Wait for a time, tMErase (min. 4ms)
7. Clear the ERASE bit.
8. Wait for a time, tnvhl (min. 100µs)
9. Clear the HVEN bit.
10. After a time, trcv (min. 1µs), the memory can be accessed again in read mode.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
1. When in Monitor mode, with security sequence failed (see 15.4 Security), write to the FLASH block protect register instead of
any FLASH address.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
109
FLASH Memory
11.6 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $0080 and $XXC0. Use this step-by-step procedure to program
a row of FLASH memory (Figure 11-2 is a flowchart representation):
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address within the row address range desired.
4. Wait for a time, tnvs (min. 10µs).
5. Set the HVEN bit.
6. Wait for a time, tpgs (min. 5µs).
7. Write data to the FLASH address to be programmed. (See note.)
8. Wait for a time, tPROG (min. 30µs).
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit. (See note.)
11. Wait for a time, tnvh (min. 5µs).
12. Clear the HVEN bit.
13. After time, trcv (min. 1µs), the memory can be accessed in read mode again.
NOTE
The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH address programmed to clearing PGM bit
(step 7 to step 10), must not exceed the maximum programming time,
t
PROG max.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum. See 23.17
Memory Characteristics
11.7 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting a block of memory from unintentional erase or program
operations due to system malfunction. This protection is done by using of a FLASH Block Protect Register
(FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH
memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or
PROGRAM operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
110
Freescale Semiconductor
FLASH Block Protection
1
2
3
Set PGM bit
Algorithm for programming
a row (64 bytes) of FLASH memory
Read the FLASH block protect register
Write any data to any FLASH address
within the row address range desired
4
5
6
Wait for a time, tnvs
Set HVEN bit
Wait for a time, tpgs
7
8
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Completed
Y
programming
this row?
N
10
Clear PGM bit
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
11
12
13
Wait for a time, tnvh
Clear HVEN bit
must not exceed the maximum programming
time, tPROG max.
This row program algorithm assumes the row/s
to be programmed are initially erased.
Wait for a time, trcv
End of programming
Figure 11-2. FLASH Programming Flowchart
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
111
FLASH Memory
When the FLBPR is program with all 0’s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in
11.7.1 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any
erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The FLBPR itself
can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage
also allows entry from reset into the monitor mode.
11.7.1 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and
therefore can only be written during a programming sequence of the FLASH memory. The value in this
register determines the starting location of the protected range within the FLASH memory.
Address:
$FF7E
Bit 7
6
BPR6
U
5
BPR5
U
4
BPR4
U
3
BPR3
U
2
BPR2
U
1
BPR1
U
Bit 0
BPR0
U
Read:
Write:
Reset:
BPR7
U
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 11-3. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Bits
These eight bits represent bits [14:7] of a 16-bit memory address.
Bit-15 is logic 1 and bits [6:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries)
within the FLASH memory.
16-bit memory address
Start address of FLASH block protect
0
0
0
0
0
0
0
FLBPR value
1
Figure 11-4. FLASH Block Protect Start Address
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
The entire FLASH memory is protected.
$8080 (1000 0000 1000 0000)
$8100 (1000 0001 0000 0000)
and so on...
$00
$01 (0000 0001)
$02 (0000 0010)
$FE (1111 1110)
$FF00 (1111 1111 0000 0000)
$FF
The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
112
Freescale Semiconductor
Wait Mode
11.8 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the
FLASH, otherwise the operation will discontinue, and the FLASH will be on Standby Mode.
11.9 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the
FLASH, otherwise the operation will discontinue, and the FLASH will be on Standby Mode
NOTE
Standby Mode is the power saving mode of the FLASH module in which all
internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
113
FLASH Memory
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
114
Freescale Semiconductor
Chapter 12
External Interrupt (IRQ)
12.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
12.2 Features
Features of the IRQ module include:
•
•
•
•
•
•
A dedicated external interrupt pin (IRQ)
IRQ interrupt control bits
Hysteresis buffer
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Internal pullup resistor
12.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 12-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
•
Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the
IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of
the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear,
or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt remains set until both of
the following occur:
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
115
External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
RESET
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
CLR
D
Q
IRQ
INTERRUPT
REQUEST
SYNCHRONIZER
CK
IRQ
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
MODE
0
Read:
Write:
Reset:
0
0
0
0
IRQF
0
ACK
0
IMASK
0
IRQ Status and Control
Register (INTSCR)
$001D
0
0
0
0
0
= Unimplemented
Figure 12-2. IRQ I/O Register Summary
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
116
Freescale Semiconductor
IRQ Pin
12.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
•
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
12.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during
the break state. See Chapter 6 Break Module (BRK).
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic
0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has
no effect on the IRQ interrupt flags.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
117
External Interrupt (IRQ)
12.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
•
•
•
•
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address:
$001D
Bit 7
6
5
0
4
0
3
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
IRQF
ACK
0
0
0
0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears
ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
118
Freescale Semiconductor
Chapter 13
Keyboard Interrupt Module (KBI)
13.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are
accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup
device is also enabled on the pin.
13.2 Features
•
Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard
interrupt mask
•
•
•
•
Hysteresis buffers
Programmable edge-only or edge- and level- interrupt sensitivity
Exit from low-power modes
I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port
bit(s)
13.3 Functional Description
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its
internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt
request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
•
If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as
long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
119
INTERNAL BUS
VECTOR FETCH
DECODER
KBD0
ACKK
VDD
KEYF
RESET
CLR
.
.
.
TO PULLUP ENABLE
D
Q
SYNCHRONIZER
CK
KB0IE
KEYBOARD
INTERRUPT
REQUEST
IMASKK
KBD7
MODEK
TO PULLUP ENABLE
KB7IE
Figure 13-1. Keyboard Module Block Diagram
Addr.
Register Name
Keyboard Status
and Control Register Write:
Bit 7
6
5
4
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
0
0
0
0
KEYF
0
ACKK
0
$001A
(INTKBSCR)
Reset:
0
KBIE7
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
Read:
Keyboard Interrupt Enable
KBIE2
0
KBIE1
0
KBIE0
0
$001B
Register Write:
(INTKBIER)
Reset:
= Unimplemented
Figure 13-2. I/O Register Summary
Keyboard Initialization
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKK bit in the keyboard status and control register (INTKBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFE0 and $FFE1.
•
Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
13.4 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore,
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
121
Keyboard Interrupt Module (KBI)
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction
register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
13.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
13.5.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
13.5.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
13.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE
bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during
the break state has no effect. (See 13.7.1 Keyboard Status and Control Register.)
13.7 I/O Registers
These registers control and monitor operation of the keyboard module:
•
•
Keyboard status and control register (INTKBSCR)
Keyboard interrupt enable register (INTKBIER)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
122
Freescale Semiconductor
I/O Registers
13.7.1 Keyboard Status and Control Register
The keyboard status and control register:
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 13-3. Keyboard Status and Control Register (INTKBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic
0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from
generating interrupt requests. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears
MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
123
Keyboard Interrupt Module (KBI)
13.7.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard
interrupt pin.
Address: $001B
Bit 7
KBIE7
0
6
KBIE6
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt
requests. Reset clears the keyboard interrupt enable register.
1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
124
Freescale Semiconductor
Chapter 14
Low-Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin
and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF
.
14.2 Features
Features of the LVI module include:
•
•
•
Programmable LVI reset
Selectable LVI trip voltage
Programmable stop mode operation
14.3 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD,
enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI
module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode
bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3,
enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit
enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip points are shown
in Chapter 23 Electrical Specifications.
NOTE
After a power-on reset (POR) the LVI’s default mode of operation is 3 V. If
a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5-V operation. Note that this must be done after every power-on
reset since the default will revert back to 3-V mode after each power-on
reset. If the VDD supply is below the 5-V mode trip voltage but above the
3-V mode trip voltage when POR is released, the part will operate because
VTRIPF defaults to 3-V mode after a POR. So, in a 5-V system care must be
taken to ensure that VDD is above the 5-V mode trip voltage after POR is
released.
NOTE
If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the VDD supply is not above the VTRIPR for 5-V mode, the MCU
will immediately go into reset. The LVI in this case will hold the part in reset
until either VDD goes above the rising 5-V trip point, VTRIPR, which will
release reset or VDD decreases to approximately 0 V which will re-trigger
the power-on reset and reset the trip point to 3-V operation.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
125
Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See 8.2
Functional Description for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See
19.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The
output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG1
FROM CONFIG1
LVIRSTD
LVIPWRD
FROM CONFIG
VDD > LVITrip = 0
LVI RESET
LOW VDD
DETECTOR
VDD ≤ LVITrip = 1
LVIOUT
LVI5OR3
FROM CONFIG1
Figure 14-1. LVI Module Block Diagram
Addr.
Register Name
Bit 7
Read: LVIOUT
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
$FE0C LVI Status Register (LVISR) Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
14.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
14.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
126
Freescale Semiconductor
LVI Status Register
14.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until
VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than
VTRIPF by the hysteresis voltage, VHYS.
14.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See
Chapter 23 Electrical Specifications for the actual trip point voltages.)
14.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.
Address: $FE0C
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage.
(See Table 14-1.) Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
14.5 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
127
Low-Voltage Inhibit (LVI)
14.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
14.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
14.6.2 Stop Mode
If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
128
Freescale Semiconductor
Chapter 15
Monitor ROM (MON)
15.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM
allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode
entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE
and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
15.2 Features
Features of the monitor ROM include:
•
•
•
•
•
•
•
Normal user-mode pin functionality
One pin dedicated to serial communication between monitor ROM and host computer
Standard mark/space non-return-to-zero (NRZ) communication with host computer
Execution of code in RAM or FLASH
FLASH memory security feature(1)
FLASH memory programming interface
Enhanced PLL (phase-locked loop) option to allow use of external 32.768-kHz crystal to generate
internal frequency of 2.4576 MHz
•
•
307 bytes monitor ROM code size ($FE20 to $FF52)
Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
•
Standard monitor mode entry if high voltage, VTST, is applied to IRQ
15.3 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 15-1 shows an
example circuit used to enter monitor mode and communicate with a host computer via a standard
RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
129
Monitor ROM (MON)
68HC908GP32
RST
0.1 µF
V
TST
RESET VECTORS
$FFFE
(SEE NOTE 3)
10 kΩ
(SEE NOTES 2
AND 3)
$FFFF
C
D
SW2
IRQ
V
DD
V
DDA
CGMXFC
10 k
0.033 µF
SW3
C
C
OSC1
(SEE NOTE 2)
6–30 pF
1
20
MC145407
D
+
+
+
OSC2
PTA7
10
10
µ
F
F
10 µF
SW4
(SEE NOTE 2)
3
4
18
17
V
V
V
SS
32.768 kHz XTAL
SSAD
SSA
330 kΩ
D
V
6–30 pF
DD
10 µF
µ
+
2
19
DB-25
2
V
5
6
16
15
DD
V
3
7
DD
V
DDAD
0.1 µF
V
DD
V
DD
1
2
6
4
14
3
MC74HC125
10 k
Ω
PTA0
PTC3
5
V
DD
V
DD
7
A
PTC0
PTC1
SW1
(SEE NOTE 1)
B
Notes:
1. For monitor mode entry when IRQ = VTST
:
SW1: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
SW1: Position B — Bus clock = CGMXCLK ÷ 2
2. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator.
SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL.
3. See Table 15-1 for IRQ voltage level requirements.
Figure 15-1. Monitor Mode Circuit
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
130
Freescale Semiconductor
Functional Description
The monitor code has been updated from previous versions of the monitor code to allow enabling the PLL
to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a
low-frequency crystal. This addition, which is enabled when IRQ is held low out of reset, is intended to
support serial communication/ programming at 9600 baud in monitor mode by stepping up the external
frequency (assumed to be 32.768 kHz) by a fixed amount to generate the desired internal frequency
(2.4576 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when
the reset vector is not blank because entry into monitor mode in this case requires VTST on IRQ.
15.3.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
1. If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high
– IRQ = VTST (PLL off)
2. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ pullup; PLL off)
3. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 32.768 kHz (crystal)
– IRQ = VSS (this setting initiates the PLL to boost the external 32.768 kHz to an internal bus
frequency of 2.4576 MHz)
If VTST is applied to IRQ and PTC3 is low upon monitor mode entry (above condition set 1), the bus
frequency is a divide-by-two of the input clock. If PTC3 is high with VTST applied to IRQ upon monitor
mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when
entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied
to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage
is either VDD or VSS), then all port C pin requirements and conditions, including the PTC3 frequency
divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial POR reset. Once the part has been
programmed, the traditional method of applying a voltage, VTST, to IRQ
must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these conditions:
•
If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or
3), the COP is always disabled regardless of the state of IRQ or RST.
•
If monitor mode was entered with VTST on IRQ (condition set 1), then the COP is disabled as long
as VTST is applied to either IRQ or RST.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
131
Table 15-1. Monitor Mode Signal Requirements and Options
For Serial
Communication
External
Clock(1)
$FFFE/
$FFFF
Bus
Frequency
IRQ RESET
PLL PTC0 PTC1 PTC3
CGMOUT
COP
Comment
Baud
PTA0 PTA7
Rate(2) (3)
No operation until
reset goes high
X
GND
VDD
or
VTST
X
X
X
X
1
X
0
X
0
X
0
0
Disabled
Disabled
X
1
X
0
1
0
1
0
PTC0 and PTC1
voltages only
required if IRQ =
9600
DNA
9600
DNA
4.9152
MHz
4.9152
MHz
2.4576
MHz
VTST
OFF
VTST
;
X
1
PTC0 and PTC1
voltages only
required if IRQ =
VDD
or
VTST
9.8304
MHz
4.9152
MHz
2.4576
MHz
VTST
X
OFF
1
0
1
Disabled
VTST
;
X
1
X
1
0
1
0
9600
DNA
9600
$FF
(blank)
9.8304
MHz
4.9152
MHz
2.4576
MHz
External frequency
always divided by 4
VDD
VDD
OFF
ON
X
X
X
X
X
X
Disabled
Disabled
PLL enabled
(BCS set)
in monitor code
$FF
(blank)
32.768
kHz
4.9152
MHz
2.4576
MHz
VDD
GND
X
1
DNA
Enters user mode
— will encounter
an illegal address
reset
VDD
or
$FF
(blank)
VTST
OFF
OFF
X
X
X
X
X
X
X
X
—
—
—
—
Enabled
Enabled
X
X
—
GND
Not
$FF
(progra-
mmed)
VDD
or
VTST
VDD
or
GND
X
X
—
Enters user mode
Notes:
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA7 = 0 → serial, PTA7 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
Functional Description
The second condition states that as long as VTST is maintained on the IRQ pin after entering monitor
mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied
to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST
can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor
mode.
Figure 15-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just
1 x VDD voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate
of 9600, as the internal bus frequency is automatically set to the external frequency divided by four.
POR RESET
NO
NORMAL USER
MODE
IS VECTOR
BLANK?
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
NO
POR
TRIGGERED?
YES
Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with pin configuration shown in Figure 15-1 by pulling RST low and then high. The
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See 15.4 Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
NOTE
The PTA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST low will not exit
monitor mode in this situation.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
133
Monitor ROM (MON)
Table 15-2 summarizes the differences between user mode and monitor mode.
Table 15-2. Mode Differences
Functions
Modes
Reset
Reset
Break
Break
SWI
SWI
Vector High
Vector Low
Vector High
Vector Low
Vector High
Vector Low
User
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
Monitor
15.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
NEXT
START
BIT
START
BIT
BIT 6
STOP
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
BIT 7
Figure 15-3. Monitor Data Format
15.3.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-4. Break Transaction
15.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTC3 pin (when
IRQ is set to VTST) upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the
PTC3 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512.
If monitor mode was entered with VDD on IRQ, then the divide by ratio is set at 1024, regardless of PTC3.
If monitor mode was entered with VSS on IRQ, then the internal PLL steps up the external frequency,
presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require
that the reset vector is blank.
Table 15-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle. See 23.7 5.0-V Control Timing and 23.8 3.0-V Control Timing for this limit.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
134
Freescale Semiconductor
Functional Description
Table 15-3. Monitor Baud Rate Selection
External
Frequency
Internal
Baud Rate
IRQ
PTC3
Frequency
2.4576 MHz
2.4576 MHz
2.4576 MHz
2.4576 MHz
(BPS)
9600
9600
9600
9600
VTST
VTST
VDD
VSS
4.9152 MHz
9.8304 MHz
9.8304 MHz
32.768 kHz
0
1
X
X
15.3.5 Commands
The monitor ROM firmware uses these commands:
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
FROM HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
4
4
1
1
4
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-5. Read Transaction
FROM HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
1
WRITE
3
3
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-6. Write Transaction
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
135
Monitor ROM (MON)
A brief description of each monitor mode command is given in Table 15-4 through Table 15-9.
Table 15-4. READ (Read Memory) Command
Description
Operand
Read byte from memory
2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO
MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
Table 15-5. WRITE (Write Memory) Command
Description
Operand
Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by data byte
Data Returned None
Opcode
$49
Command Sequence
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
ECHO
WRITE
Table 15-6. IREAD (Indexed Read) Command
Description
Operand
Read next 2 bytes in memory from last address accessed
2-byte address in high byte:low byte order
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM
HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
136
Freescale Semiconductor
Functional Description
Table 15-7. IWRITE (Indexed Write) Command
Description
Operand
Write to last address accessed + 1
Single data byte
Data Returned None
Opcode $19
Command Sequence
FROM
HOST
DATA
DATA
IWRITE
IWRITE
ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
Table 15-8. READSP (Read Stack Pointer) Command
Description
Operand
Reads stack pointer
None
Returns incremented stack pointer value (SP + 1) in high-byte:low-byte
order
Data Returned
Opcode
$0C
Command Sequence
FROM
HOST
SP
HIGH
SP
LOW
READSP
READSP
ECHO
RETURN
Table 15-9. RUN (Run User Program) Command
Description
Operand
Executes PULH and RTI instructions
None
Data Returned None
Opcode $28
Command Sequence
FROM
HOST
RUN
RUN
ECHO
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
137
Monitor ROM (MON)
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
CONDITION CODE REGISTER
ACCUMULATOR
SP + 1
SP + 2
SP + 3
SP + 4
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER SP + 5
LOW BYTE OF PROGRAM COUNTER SP + 6
SP + 7
Figure 15-7. Stack Pointer at Monitor Mode Entry
15.4 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. (See Figure 15-8.)
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
138
Freescale Semiconductor
Security
VDD
RST
4096 + 32 CGMXCLK CYCLES
24 BUS CYCLES
PTA7
256 BUS CYCLES (MINIMUM)
FROM HOST
FROM MCU
PTA0
1
1
4
1
4
2
1
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-8. Monitor Mode Entry Timing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
139
Monitor ROM (MON)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
140
Freescale Semiconductor
Chapter 16
Input/Output (I/O) Ports
16.1 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable
as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with
pullup devices if configured as input port bits. The pullup devices are automatically and dynamically
disabled when a port bit is switched to output mode.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
0
PTB6
PTC6
PTD6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
Port C Data Register
(PTC)
PTD7
Port D Data Register
(PTD)
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
(DDRB)
= Unimplemented
Figure 16-1. I/O Port Register Summary
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
141
Input/Output (I/O) Ports
Addr.
Register Name
Bit 7
6
5
4
3
2
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
Data Direction Register C
(DDRC)
$0006
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
$0007
$0008
$000C
$000D
$000E
$000F
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
0
0
0
0
0
0
0
0
0
0
DDRE1
0
DDRE0
0
Data Direction Register E
(DDRE)
0
0
Port A Input Pullup Enable
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
0
Read:
Port C Input Pullup Enable
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Register Write:
(PTCPUE)
Reset:
0
0
0
0
0
0
0
0
Read:
Port D Input Pullup Enable
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Register Write:
(PTDPUE)
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-1. I/O Port Register Summary (Continued)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
142
Freescale Semiconductor
Introduction
Table 16-1. Port Control Register Bits Summary
Port
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
DDR
Module Control
KBIE0
Pin
DDRA0
DDRA1
DDRA2
DDRA3
DDRA4
DDRA5
DDRA6
DDRA7
DDRB0
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
DDRB6
DDRB7
DDRC0
DDRC1
DDRC2
DDRC3
DDRC4
DDRC5
DDRC6
DDRD0
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRD7
DDRE0
DDRE1
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTA5/KBD5
PTA6/KBD6
PTA7/KBD7
PTB0/AD0
PTB1/AD1
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
PTC0
KBIE1
KBIE2
KBIE3
KBIE4
KBIE5
KBIE6
KBIE7
A
KBD
B
ADC
ADCH4–ADCH0
PTC1
PTC2
C
PTC3
PTC4
PTC5
PTC6
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
PTD7/T2CH1
PTE0/TxD
PTE1/RxD
SPI
SPE
D
E
ELS0B:ELS0A
ELS1B:ELS1A
ELS0B:ELS0A
ELS1B:ELS1A
TIM1
TIM2
SCI
ENSCI
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
143
Input/Output (I/O) Ports
16.2 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI)
module. Port A also has software configurable pullup devices if configured as an input port.
16.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
KBD4 KBD3
Alternate Function:
KBD7
KBD6
KBD5
KBD2
KBD1
KBD0
Figure 16-2. Port A Data Register (PTA)
PTA7–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD7–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard interrupt control register (KBICR)
enable the port A pins as external interrupt pins. See Chapter 13 Keyboard Interrupt Module (KBI).
16.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the
output buffer.
Address:
$0004
Bit 7
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
DDRA7
0
Figure 16-3. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA7–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
144
Freescale Semiconductor
Port A
Figure 16-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
PTAx
RESET
WRITE PTA ($0000)
PTAx
VDD
PTAPUEx
INTERNAL
PULLUP
DEVICE
READ PTA ($0000)
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes the operation of the port A pins.
Table 16-2. Port A Pin Functions
Accesses to DDRA
Read/Write
Accesses to PTA
PTAPUE Bit
DDRA Bit
PTA Bit
I/O Pin Mode
Read
Write
(4)
X(1)
X
PTA7–PTA0(3)
1
0
DDRA7–DDRA0
Pin
Input, VDD
Input, Hi-Z(2)
Output
PTA7–PTA0(3)
PTA7–PTA0
0
X
0
1
DDRA7–DDRA0
DDRA7–DDRA0
Pin
X
PTA7–PTA0
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device
16.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
0
Figure 16-5. Port A Input Pullup Enable Register (PTAPUE)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
145
Input/Output (I/O) Ports
PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
16.3 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter
(ADC) module.
16.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Write:
Reset:
Unaffected by reset
AD4 AD3
Alternate Function:
AD7
AD6
AD5
AD2
AD1
AD0
Figure 16-6. Port B Data Register (PTB)
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
AD7–AD0 — Analog-to-Digital Input Bits
AD7–AD0 are pins used for the input channels to the analog-to-digital converter module. The channel
select bits in the ADC status and control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry.
NOTE
Care must be taken when reading port B while applying analog voltages to
AD7–AD0 pins. If the appropriate ADC channel is not enabled, excessive
current drain may occur if analog voltages are applied to the PTBx/ADx pin,
while PTB is read as a digital input. Those ports not selected as analog
input channels are considered digital I/O ports.
16.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the
output buffer.
Address:
$0005
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 16-7. Data Direction Register B (DDRB)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
146
Freescale Semiconductor
Port B
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB7–DDRB0], configuring all port
B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 16-8 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 16-8. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-3 summarizes the operation of the port B pins.
Table 16-3. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
Write
DDRB Bit
PTB Bit
I/O Pin Mode
Read
Pin
X(1)
X
Input, Hi-Z(2)
Output
PTB7–PTB0(3)
PTB7–PTB0
0
1
DDRB7–DDRB0
DDRB7–DDRB0
PTB7–PTB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
147
Input/Output (I/O) Ports
16.4 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup
devices if configured as an input port.
16.4.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the seven port C pins.
NOTE
Bit 6 and bit 5 of PTC are not available in a 40-pin dual in-line package and
42-pin shrink dual in-line package.
Address:
$0002
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Unaffected by reset
= Unimplemented
Figure 16-9. Port C Data Register (PTC)
PTC6–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
16.4.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the
output buffer.
Address:
$0006
Bit 7
0
6
DDRC6
0
5
DDRC5
0
4
DDRC4
0
3
DDRC3
0
2
DDRC2
0
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 16-10. Data Direction Register C (DDRC)
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port
C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
148
Freescale Semiconductor
Port C
Figure 16-11 shows the port C I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package and 42-pin
shrink dual in-line package, PTC5 and PTC6 are connected to ground
internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and
PTC6 as inputs.
READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
VDD
PTCPUEx
INTERNAL
PULLUP
DEVICE
READ PTC ($0002)
Figure 16-11. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-4 summarizes the operation of the port C pins.
Table 16-4. Port C Pin Functions
Accesses to DDRC
Read/Write
Accesses to PTC
PTCPUE Bit
DDRC Bit
PTC Bit
I/O Pin Mode
Read
Write
(4)
X(1)
X
PTC6–PTC0(3)
1
0
DDRC6–DDRC0
Pin
Input, VDD
Input, Hi-Z(2)
Output
PTC6–PTC0(3)
PTC6–PTC0
0
X
0
1
DDRC6–DDRC0
DDRC6–DDRC0
Pin
X
PTC6–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
149
Input/Output (I/O) Ports
16.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the seven port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
Address:
$000E
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
16.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
16.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
NOTE
Bit 7 and bit 6 of PTD are not available in a 40-pin dual in-line package.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Write:
Reset:
Unaffected by reset
T1CH0 SPSCK
Alternate Function: T2CH1
T2CH0
T1CH1
MOSI
MISO
SS
Figure 16-13. Port D Data Register (PTD)
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD7/T2CH1–PTD6/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 22 Timer Interface Module (TIM).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
150
Freescale Semiconductor
Port D
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See Chapter 22 Timer Interface Module (TIM).
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See Table 16-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.
16.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the
output buffer.
Address:
$0007
Bit 7
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Read:
Write:
Reset:
DDRD7
0
Figure 16-14. Data Direction Register D (DDRD)
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port
D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
151
Input/Output (I/O) Ports
Figure 16-15 shows the port D I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package, PTD6 and
PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to
configure PTD6 and PTD7 as outputs.
READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PTD ($0003)
PTDx
PTDx
VDD
PTDPUEx
INTERNAL
PULLUP
DEVICE
READ PTD ($0003)
Figure 16-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-5 summarizes the operation of the port D pins.
Table 16-5. Port D Pin Functions
Accesses to DDRD
Read/Write
Accesses to PTD
PTDPUE Bit
DDRD Bit
PTD Bit
I/O Pin Mode
Read
Write
(4)
X(1)
X
PTD7–PTD0(3)
1
0
DDRD7–DDRD0
Pin
Input, VDD
Input, Hi-Z(2)
Output
PTD7–PTD0(3)
PTD7–PTD0
0
X
0
1
DDRD7–DDRD0
DDRD7–DDRD0
Pin
X
PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Port E
16.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address:
$000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
0
0
0
0
0
0
0
0
Figure 16-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
16.6 Port E
Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface
(SCI) module.
16.6.1 Port E Data Register
The port E data register contains a data latch for each of the two port E pins.
Address:
$0008
Bit 7
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
0
PTE1
PTE0
Write:
Reset:
Unaffected by reset
Alternate Function:
RxD
TxD
= Unimplemented
Figure 16-17. Port E Data Register (PTE)
PTE1 and PTE0 — Port E Data Bits
PTE1 and PTE0 are read/write, software programmable bits. Data direction of each port E pin is under
the control of the corresponding bit in data direction register E.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 16-6.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
153
Input/Output (I/O) Ports
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 18 Serial Communications Interface Module (SCI).
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 18 Serial Communications Interface Module (SCI).
16.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the
output buffer.
Address:
$000C
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
DDRE1
0
Bit 0
DDRE0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-18. Data Direction Register E (DDRE)
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE1 and DDRE0, configuring all
port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16-19 shows the port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 16-19. Port E I/O Circuit
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
154
Freescale Semiconductor
Port E
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-6 summarizes the operation of the port E pins.
Table 16-6. Port E Pin Functions
Accesses to DDRE
Read/Write
Accesses to PTE
DDRE Bit
PTE Bit
I/O Pin Mode
Read
Write
X(1)
X
Input, Hi-Z(2)
Output
PTE1–PTE0(3)
PTE1–PTE0
0
1
DDRE1–DDRE0
DDRE1–DDRE0
Pin
PTE1–PTE0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
155
Input/Output (I/O) Ports
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
156
Freescale Semiconductor
Chapter 17
Random-Access Memory (RAM)
17.1 Introduction
This section describes the 512 bytes of RAM (random-access memory).
17.2 Functional Description
Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently
access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Random-Access Memory (RAM)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Chapter 18
Serial Communications Interface Module (SCI)
18.1 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed
asynchronous communications with peripheral devices and other MCUs.
NOTE
References to DMA (direct-memory access) and associated functions are
only valid if the MCU has a DMA module. This MCU does not have the DMA
function. Any DMA-related register bits should be left in their reset state for
normal MCU operation.
18.2 Features
Features of the SCI module include:
•
•
•
•
•
•
•
•
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
32 programmable baud rates
Programmable 8-bit or 9-bit character length
Separately enabled transmitter and receiver
Separate receiver and transmitter CPU interrupt requests
Programmable transmitter output polarity
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
•
•
•
•
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
159
Serial Communications Interface Module (SCI)
18.3 Pin Name Conventions
The generic names of the SCI I/O pins are:
•
•
RxD (receive data)
TxD (transmit data)
SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI
input or output reflects the name of the shared port pin. Table 18-1 shows the full names and the generic
names of the SCI I/O pins.
The generic pin names appear in the text of this section.
Table 18-1. Pin Name Conventions
Generic Pin Names:
Full Pin Names:
RxD
TxD
PTE1/RxD
PTE0/TxD
18.4 Functional Description
Figure 18-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial
communication among the MCU and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate generator. During normal
operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes
received data.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the
CONFIG2 register ($001E). Source selection values are shown in Figure 18-1.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
160
Freescale Semiconductor
Functional Description
INTERNAL BUS
SCI DATA
REGISTER
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
TRANSMIT
SHIFT REGISTER
PTE1/RxD
PTE0/TxD
TXINV
SCTIE
TCIE
SCRIE
ILIE
R8
T8
DMARE
DMATE
TE
SCTE
TC
RE
RWU
SBK
SCRF
IDLE
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
LOOPS
ENSCI
LOOPS
RECEIVE
CONTROL
FLAG
CONTROL
TRANSMIT
CONTROL
WAKEUP
CONTROL
SCIBDSRC
FROM
CONFIG2
M
BKF
RPF
ENSCI
WAKE
ILTY
PEN
PTY
SL
A
PRE-
SCALER
BAUD
DIVIDER
CGMXCLK
÷ 4
X
BUS CLOCK
B
SL = 0 => X = A
SL = 1 => X = B
DATA SELECTION
CONTROL
÷16
Figure 18-1. SCI Module Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
161
Serial Communications Interface Module (SCI)
Addr.
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
TXINV
0
4
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
M
0
SCI Control Register 1
(SCC1)
$0013
SCTIE
TCIE
0
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2
(SCC2)
$0014
$0015
$0016
$0017
$0018
$0019
0
0
R8
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
SCI Control Register 3
(SCC3)
U
U
0
0
0
0
0
0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
SCI Status Register 1
(SCS1)
1
1
0
0
0
0
0
0
BKF
RPF
SCI Status Register 2
(SCS2)
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register
(SCDR)
Unaffected by reset
SCP1
0
SCP0
R
0
SCR2
SCR1
0
SCR0
0
SCI Baud Rate Register
(SCBR)
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 18-2. SCI I/O Register Summary
18.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 18-3.
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
PARITY
BIT
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCC1 SET
PARITY
BIT
NEXT
START
BIT
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
STOP
BIT
Figure 18-3. SCI Data Formats
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
162
Freescale Semiconductor
Functional Description
18.4.2 Transmitter
Figure 18-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source
selection values are shown in Figure 18-4.
SCIBDSRC
FROM
CONFIG2
SL
X
CGMXCLK
BUS CLOCK
A
B
SL = 0 => X = A
SL = 1 => X = B
INTERNAL BUS
PRE- BAUD
SCALER DIVIDER
÷ 16
÷ 4
SCI DATA REGISTER
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
PTE0/TxD
TXINV
M
PEN
PTY
PARITY
GENERATION
T8
DMATE
TRANSMITTER
CONTROL LOGIC
DMATE
SCTIE
SCTE
SCTE
SBK
DMATE
SCTE
LOOPS
ENSCI
TE
SCTIE
SCTIE
TC
TC
TCIE
TCIE
Figure 18-4. SCI Transmitter
18.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)
is the ninth bit (bit 8).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
163
Serial Communications Interface Module (SCI)
18.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin. The SCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register
2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing
to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the PTE0/TxD pin goes to the idle
condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the
transmitter and receiver relinquish control of the port E pins.
18.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
•
•
•
•
•
•
Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
18.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
164
Freescale Semiconductor
Functional Description
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the SCDR.
18.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at
logic 1. (See 18.8.1 SCI Control Register 1.)
18.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
18.4.3 Receiver
Figure 18-5 shows the structure of the SCI receiver.
18.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
18.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the PTE1/RxD pin. The SCI
data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
165
Serial Communications Interface Module (SCI)
INTERNAL BUS
SCR1
SCR2
SCR0
SCIBDSRC
FROM
CONFIG2
SCP1
SCI DATA REGISTER
SCP0
SL
X
CGMXCLK
BUS CLOCK
PRE- BAUD
SCALER DIVIDER
A
B
÷ 16
÷ 4
11-BIT
RECEIVE SHIFT REGISTER
SL = 0 => X = A
SL = 1 => X = B
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
PTE1/RxD
ALL 0s
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
ILIE
DMARE
SCRF
SCRIE
DMARE
SCRIE
SCRF
SCRIE
DMARE
DMARE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 18-5. SCI Receiver Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
166
Freescale Semiconductor
Functional Description
18.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see Figure 18-6):
•
•
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
PTE1/RxD
SAMPLES
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 18-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 18-2 summarizes the results of the start bit verification samples.
Table 18-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
001
010
011
100
101
110
111
Yes
Yes
Yes
No
0
1
1
0
1
0
0
0
Yes
No
No
No
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
167
Serial Communications Interface Module (SCI)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 18-3 summarizes the results of the data bit samples.
Table 18-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-4
summarizes the results of the stop bit samples.
Table 18-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
001
010
011
100
101
110
111
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
18.4.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is set.
18.4.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
168
Freescale Semiconductor
Functional Description
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
Figure 18-7 shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 18-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-7, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
154 – 147
× 100 = 4.54%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 18-7, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
170 – 163
× 100 = 4.12%
-------------------------
170
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
169
Serial Communications Interface Module (SCI)
Fast Data Tolerance
Figure 18-8 shows how much a fast received character can be misaligned without causing a noise error
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 18-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
·
154 – 160
× 100 = 3.90%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
170 – 176
× 100 = 3.53%
-------------------------
170
18.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
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Functional Description
Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTE1/RxD pin can bring
the receiver out of the standby state:
•
Address mark — An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle character on the PTE1/RxD pin
wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes
the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line
type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after
the start bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
18.4.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the PTE1/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
18.4.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
•
•
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error
CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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171
Serial Communications Interface Module (SCI)
18.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
18.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to Chapter 3 Low-Power Modes for information on exiting wait mode.
18.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to Chapter 3 Low-Power Modes for information on exiting stop mode.
18.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
18.7 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
•
•
PTE0/TxD — Transmit data
PTE1/RxD — Receive data
18.7.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin
with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE2
bit in data direction register E (DDRE).
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I/O Registers
18.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with
port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit
in data direction register E (DDRE).
18.8 I/O Registers
These I/O registers control and monitor SCI operation:
•
•
•
•
•
•
•
SCI control register 1 (SCC1)
SCI control register 2 (SCC2)
SCI control register 3 (SCC3)
SCI status register 1 (SCS1)
SCI status register 2 (SCS2)
SCI data register (SCDR)
SCI baud rate register (SCBR)
18.8.1 SCI Control Register 1
SCI control register 1:
•
•
•
•
•
•
•
•
Enables loop mode operation
Enables the SCI
Controls output polarity
Controls character length
Controls SCI wakeup method
Controls idle character detection
Enables parity function
Controls parity type
Address:
$0013
Bit 7
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
Write:
Reset:
LOOPS
0
Figure 18-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from
the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
173
Serial Communications Interface Module (SCI)
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 18-5.)
The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the PTE1/RxD pin. Reset clears
the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count
after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 18-5.) When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Figure 18-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 18-5.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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I/O Registers
Table 18-5. Character Format Selection
Control Bits
Character Format
M
0
1
0
0
1
1
PEN and PTY
Start Bits
Data Bits
Parity
None
None
Even
Odd
Stop Bits
Character Length
0X
0X
10
11
10
11
1
1
1
1
1
1
8
9
7
7
8
8
1
1
1
1
1
1
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Even
Odd
18.8.2 SCI Control Register 2
SCI control register 2:
•
Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
•
•
•
•
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Address:
$0014
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
SCTIE
0
Figure 18-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Serial Communications Interface Module (SCI)
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the PTE0/TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the PTE0/TxD returns to the idle condition (logic 1). Clearing and then
setting TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic
1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s between them. Reset clears the
SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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I/O Registers
18.8.3 SCI Control Register 3
SCI control register 3:
•
•
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
•
Parity error interrupts
Address:
$0015
Bit 7
R8
6
T8
U
5
DMARE
0
4
DMATE
0
3
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
ORIE
U
0
= Unimplemented
U = Unaffected
Figure 18-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
DMATE — DMA Transfer Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Serial Communications Interface Module (SCI)
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE.
(See 18.8.4 SCI Status Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
18.8.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
•
•
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
PE
Read:
Write:
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
1
1
0
0
0
0
0
0
= Unimplemented
Figure 18-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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I/O Registers
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set.
TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may
be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is
set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 18-13 shows the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an
SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1
and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
179
Serial Communications Interface Module (SCI)
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 18-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
18.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
•
•
Break character detected
Incoming data
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
I/O Registers
Address:
$0017
Bit 7
6
5
0
4
0
3
0
2
0
1
Bit 0
RPF
Read:
Write:
Reset:
BKF
0
0
0
0
= Unimplemented
Figure 18-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In
SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
18.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
Address:
$0018
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by reset
Figure 18-15. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the
data to be transmitted, T7:T0. Reset has no effect on the SCDR.
NOTE
Do not use read/modify/write instructions on the SCI data register.
18.8.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
181
Serial Communications Interface Module (SCI)
Address:
$0019
Bit 7
6
5
SCP1
0
4
SCP0
0
3
2
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
R
SCR2
0
0
0
0
= Unimplemented
R
= Reserved
Figure 18-16. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 18-6. Reset clears SCP1
and SCP0.
Table 18-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in Table 18-7. Reset clears
SCR2–SCR0.
Table 18-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0
Baud Rate Divisor (BD)
000
001
010
011
100
101
110
111
1
2
4
8
16
32
64
128
Use this formula to calculate the SCI baud rate:
SCI clock source
baud rate = --------------------------------------------
64 × PD × BD
where:
SCI clock source = fBUS or CGMXCLK (selected by SCIBDSRC bit in CONFIG2 register)
PD = prescaler divisor
BD = baud rate divisor
Table 18-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when fBUS is
selected as SCI clock source.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
182
Freescale Semiconductor
I/O Registers
Table 18-8. SCI Baud Rate Selection Examples
Baud Rate
(fBUS = 4.9152 MHz)
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
SCP1 and SCP0
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
1
2
76,800
38,400
19,200
9600
4800
2400
1200
600
1
4
1
8
1
16
32
64
128
1
1
1
1
3
25,600
12,800
6400
3200
1600
800
3
2
3
4
3
8
3
16
32
64
128
1
3
3
400
3
200
4
19,200
9600
4800
2400
1200
600
4
2
4
4
4
8
4
16
32
64
128
1
4
4
300
4
150
13
13
13
13
13
13
13
13
5908
2954
1477
739
2
4
8
16
32
64
128
369
185
92
46
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
183
Serial Communications Interface Module (SCI)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
184
Freescale Semiconductor
Chapter 19
System Integration Module (SIM)
19.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 19-1. Table 19-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
•
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
•
•
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Table 19-1 shows the internal signal names used in this section.
Table 19-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
CGMOUT
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
185
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷ 2
CLOCK
CONTROL
VDD
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULLUP
DEVICE
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
MASTER
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
RESET PIN CONTROL
CONTROL
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 19-1. SIM Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
Read:
Write:
Reset:
R
R
R
R
R
R
R
SIM Break Status Register
(SBSR)
$FE00
Note: Writing a logic 0 clears SBSW.
Read:
SIM Reset Status Register
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
$FE01
$FE02
Write:
(SRSR)
POR:
1
0
0
0
0
0
0
0
Read:
SIM Upper Byte Address
Write:
R
R
R
R
R
R
R
R
Register (SUBAR)
Reset:
= Unimplemented
R
= Reserved
Figure 19-2. SIM I/O Register Summary
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
186
Freescale Semiconductor
SIM Bus Clock Control and Generation
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
0
IF6
R
IF5
R
IF4
R
IF3
R
IF2
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
$FE04
$FE05
$FE06
R
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IF16
R
IF15
R
Interrupt Status Register 3
(INT3)
R
R
R
R
R
0
R
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 19-2. SIM I/O Register Summary (Continued)
19.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 19-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 7 Clock Generator Module
(CGMC).)
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
TO TIMTB15A, ADC
SIM
SIMOSCEN
OSCSTOPENB
FROM
CONFIG
SIM COUNTER
IT12
TO REST
OF CHIP
CGMRCLK
CGMOUT
SIMDIV2
BUS CLOCK
GENERATORS
IT23
÷ 2
TO REST
OF CHIP
PHASE-LOCKED LOOP (PLL)
PTC3
MONITOR MODE
USER MODE
Figure 19-3. CGM Clock Signals
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
187
System Integration Module (SIM)
19.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
19.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
19.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 19.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
19.3 Reset and System Initialization
The MCU has these reset sources:
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 19.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 19.7 SIM Registers.)
19.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.
See Table 19-2 for details. Figure 19-4 shows the relative timing.
Table 19-2. PIN Bit Set Timing
Reset Type
POR/LVI
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
188
Freescale Semiconductor
Reset and System Initialization
CGMOUT
RST
VECT H VECT L
IAB
PC
Figure 19-4. External Reset Timing
19.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.
See Figure 19-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. (See Figure 19-6.)
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 19-5.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 19-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 19-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
19.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
189
System Integration Module (SIM)
At power-on, these events occur:
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
•
•
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IRST
IAB
$FFFE
$FFFF
Figure 19-7. POR Recovery
19.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least
every 213 – 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, VTST on the RST pin disables the COP module.
19.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
190
Freescale Semiconductor
SIM Counter
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
19.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
19.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the
LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
19.3.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is
entered in the condition where the reset vectors are blank ($FF). (See 15.3.1 Entering Monitor Mode.)
When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all
internal reset sources.
19.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of
CGMXCLK.
19.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
19.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of
4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
19.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 19.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 19.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
191
System Integration Module (SIM)
19.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
•
Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
•
•
Break interrupts
19.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 19-8 shows
interrupt entry timing. Figure 19-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). (See Figure 19-10.)
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
R/W
Figure 19-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
R/W
CCR
A
X
PC – 1 [15:8] PC – 1 [7:0] OPCODE OPERAND
Figure 19-9. Interrupt Recovery Timing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
192
Freescale Semiconductor
Exception Control
FROM RESET
YES
BREAK
INTERRUPT?
NO
YES
I BIT SET?
NO
YES
IRQ
INTERRUPT?
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 19-10. Interrupt Processing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
193
System Integration Module (SIM)
19.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 19-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
CLI
BACKGROUND
LDA #$FF
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 19-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
19.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
194
Freescale Semiconductor
Exception Control
19.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 19-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 19-3. Interrupt Sources
Interrupt Status
Register Flag
Priority
Highest
Interrupt Source
Reset
SWI instruction
IRQ pin
—
—
IF1
PLL
IF2
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receiver full
SPI transmitter empty
SCI receive error
SCI receive
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
IF12
IF13
IF14
IF15
IF16
SCI transmit
Keyboard
ADC conversion complete
Timebase module
Lowest
Interrupt Status Register 1
Address:
$FE04
Bit 7
IF6
R
6
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF5
R
R
0
R
0
0
0
0
0
0
0
R
= Reserved
Figure 19-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
195
System Integration Module (SIM)
Interrupt Status Register 2
Address:
$FE05
Bit 7
IF14
R
6
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF13
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-13. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address:
$FE06
Bit 7
0
6
5
0
4
0
3
0
2
0
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
R
0
R
0
R
0
R
0
0
0
0
0
R
= Reserved
Figure 19-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the source shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
19.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
19.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 22 Timer Interface Module (TIM).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module
to see how each module is affected by the break state.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
196
Freescale Semiconductor
Low-Power Modes
19.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
19.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
19.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 19-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module (COP) is enabled and remains
active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 19-15. Wait Mode Entry Timing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
197
System Integration Module (SIM)
Figure 19-16 and Figure 19-17 show the timing for WAIT recovery.
IAB
IDB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 19-16. Wait Recovery from Interrupt or Break
32
CYCLES
32
CYCLES
IAB
$6E0B
$A6
RST VCT H RST VCT L
IDB $A6
RST
$A6
CGMXCLK
Figure 19-17. Wait Recovery from Internal Reset
19.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status
register (SBSR).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
198
Freescale Semiconductor
SIM Registers
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 19-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
Figure 19-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 19-19. Stop Mode Recovery from Interrupt or Break
19.7 SIM Registers
The SIM has three memory-mapped registers. Table 19-4 shows the mapping of these registers.
Table 19-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
SBSR
Access Mode
User
SRSR
User
SBFCR
User
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
199
System Integration Module (SIM)
19.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop
mode or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
R
= Reserved
Note: Writing a logic 0 clears SBSW.
Figure 19-20. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. Writing 0 to the SBSW bit clears it.
19.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
0
Read:
Write:
Reset:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 19-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
200
Freescale Semiconductor
SIM Registers
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ = VDD
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
19.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is
in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 19-22. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
201
System Integration Module (SIM)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Chapter 20
Serial Peripheral Interface Module (SPI)
20.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous,
serial communications with peripheral devices.
20.2 Features
Features of the SPI module include:
•
•
•
•
•
•
•
Full-duplex operation
Master and slave modes
Double-buffered operation with separate transmit and receive registers
Four master mode frequencies (maximum = bus frequency ÷ 2)
Maximum slave mode frequency = bus frequency
Serial clock with programmable polarity and phase
Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
•
•
•
•
•
Mode fault error flag with CPU interrupt capability
Overflow error flag with CPU interrupt capability
Programmable wired-OR mode
I2C (inter-integrated circuit) compatibility
I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port
bit(s)
20.3 Pin Name Conventions
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial
clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI
shares four I/O pins with four parallel I/O ports.
The full names of the SPI I/O pins are shown in Table 20-1. The generic pin names appear in the text that
follows.
Table 20-1. Pin Name Conventions
SPI Generic
Pin Names:
MISO
MOSI
SS
SPSCK
CGND
Full SPI
Pin Names:
VSS
SPI PTD1/MISO
PTD2/MOSI
PTD0/SS
PTD3/SPSCK
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
203
Serial Peripheral Interface Module (SPI)
20.4 Functional Description
Figure 20-1 summarizes the SPI I/O registers and Figure 20-2 shows the structure of the SPI module.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
DMAS
SPRIE
SPMSTR
CPOL
CPHA
SPWOM
0
$0010 SPI Control Register (SPCR) Write:
Reset:
0
0
1
0
1
Read:
SPRF
OVRF
MODF
SPTE
ERRIE
MODFEN
SPR1
SPR0
SPI Status and Control
Register (SPSCR)
$0011
$0012
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
1
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by reset
= Unimplemented
Figure 20-1. SPI I/O Register Summary
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See
16.4.3 Port C Input Pullup Enable Register.)
The following paragraphs describe the operation of the SPI module.
20.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See 20.13.1 SPI Control Register.)
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See Figure 20-3.)
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 20.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
204
Freescale Semiconductor
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
CGMOUT ÷ 2
FROM SIM
MISO
7
6
5
4
3
2
1
0
÷ 2
MOSI
÷ 8
÷ 32
CLOCK
DIVIDER
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SPSCK
SS
SPMSTR SPE
SELECT
M
S
CLOCK
LOGIC
SPR1
SPR0
SPMSTR CPHA
CPOL
RESERVED
MODFEN
ERRIE
SPTIE
SPRIE
DMAS
SPE
SPWOM
TRANSMITTER CPU INTERRUPT REQUEST
RESERVED
SPI
CONTROL
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRF
SPTE
OVRF
MODF
Figure 20-2. SPI Module Block Diagram
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
VDD
Figure 20-3. Full-Duplex Master-Slave Connections
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
205
Serial Peripheral Interface Module (SPI)
20.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input
for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is complete. (See 20.7.2 Mode Fault Error.)
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is
twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only
controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its
transmit data register. The slave must write to its transmit data register at least one bus cycle before the
master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the
MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of
the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is
clear, the falling edge of SS starts a transmission. (See 20.5 Transmission Formats.)
NOTE
SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
20.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted
in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select
line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate
multiple-master bus contention.
20.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits
in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects
an active high or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The
clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master
device to communicate with peripheral slaves having different requirements.
NOTE
Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing
the SPI enable bit (SPE).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
206
Freescale Semiconductor
Transmission Formats
20.5.2 Transmission Format When CPHA = 0
Figure 20-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a
replacement for data sheet parametric information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured
as general-purpose I/O not affecting the SPI. (See 20.7.2 Mode Fault Error.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure 20-5.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
LSB
FROM MASTER
MISO
FROM SLAVE
MSB
SS; TO SLAVE
CAPTURE STROBE
Figure 20-4. Transmission Format (CPHA = 0)
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
207
Serial Peripheral Interface Module (SPI)
20.5.3 Transmission Format When CPHA = 1
Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
20.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
MSB
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
FROM MASTER
MISO
LSB
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
Figure 20-6. Transmission Format (CPHA = 1)
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
20.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See Figure 20-7.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since
the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
208
Freescale Semiconductor
Queuing Transmission Data
SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 20-7. This delay is
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 8;
LATEST
LATEST
LATEST
8 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 20-7. Transmission Start Delay (Master)
20.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
209
Serial Peripheral Interface Module (SPI)
to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 20-8 shows
the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL =
1:0).
1
3
8
WRITE TO SPDR
SPTE
5
10
2
SPSCK
CPHA:CPOL = 1:0
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
3
6
BYTE 1
5
4
3
2
1
6
BYTE 2
5
4
2
1
6
BYTE 3
5
4
4
9
SPRF
READ SPSCR
READ SPDR
6
11
7
12
1
2
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
7
8
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
3
4
10
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11
12
CPU READS SPSCR WITH SPRF BIT SET.
CPU READS SPDR, CLEARING SPRF BIT.
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
Figure 20-8. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes
between transmissions as in a system with a single data buffer. Also, if no new data is written to the data
buffer, the last value contained in the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. The SPTE indicates when the next write can occur.
20.7 Error Conditions
The following flags signal SPI error conditions:
•
Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift
register sets the OVRF bit. The new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control register.
•
Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS)
is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
210
Freescale Semiconductor
Error Conditions
20.7.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous
transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe
occurs in the middle of SPSCK cycle 7. (See Figure 20-4 and Figure 20-6.) If an overflow occurs, all data
received after the overflow and before the OVRF bit is cleared does not transfer to the receive data
register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive
data register before the overflow occurred can still be read. Therefore, an overflow error always indicates
the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading
the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 20-11.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 20-9 shows how it is possible to miss an overflow. The first part of Figure 20-9 shows how it is
possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by
the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR
are read.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ
SPSCR
2
5
5
READ
SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 2 SETS SPRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 20-9. Missed Read of Overflow Condition
In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 20-10 illustrates this process. Generally, to avoid this second
SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Serial Peripheral Interface Module (SPI)
BYTE 1
BYTE 2
5
BYTE 3
7
BYTE 4
11
SPI RECEIVE
COMPLETE
1
SPRF
OVRF
READ
SPSCR
2
4
6
9
12
14
READ
SPDR
3
8
10
13
1
2
8
9
BYTE 1 SETS SPRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11
12
13
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
5
6
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
20.7.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and
the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI
pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state
of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
•
•
The SS pin of a slave SPI goes high during a transmission
The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 20-11.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS
goes to logic 0. A mode fault in a master SPI causes the following events to occur:
•
•
•
•
•
If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
The SPE bit is cleared.
The SPTE bit is set.
The SPI state counter is cleared.
The data direction register of the shared I/O port regains control of port drivers.
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Interrupts
NOTE
To prevent bus contention with another master SPI after a mode fault error,
clear all SPI bits of the data direction register of the shared I/O port before
enabling the SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.
When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins
when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK
returns to its idle level following the shift of the last data bit. (See 20.5 Transmission Formats.)
NOTE
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows
the difference between a MODF occurring when the SPI is a master and
when it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and
later unselected (SS is at logic 1) even if no SPSCK is sent to that slave.
This happens because SS at logic 0 indicates the start of the transmission
(MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a
slave can be selected and then later unselected with no transmission
occurring. Therefore, MODF does not occur since a transmission was
never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the
ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort
the SPI transmission by clearing the SPE bit of the slave.
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This
entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
20.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests.
Table 20-2. SPI Interrupts
Flag
Request
SPTE
Transmitter empty
SPI transmitter CPU interrupt request
(DMAS = 0, SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver CPU interrupt request
(DMAS = 0, SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
MODF
Mode fault
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Serial Peripheral Interface Module (SPI)
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt
requests, regardless of the state of the SPE bit. (See Figure 20-11.)
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
NOT AVAILABLE
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
DMAS
NOT AVAILABLE
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 20-11. SPI Interrupt Request Generation
The following sources in the SPI status and control register can generate CPU interrupt requests:
•
SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.
•
SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.
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Freescale Semiconductor
Resetting the SPI
20.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is
low. Whenever SPE is low, the following occurs:
•
•
•
•
•
The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new complete transmission.
All the SPI port logic is defaulted back to being general-purpose I/O.
These items are reset only by a system reset:
•
•
•
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
20.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
20.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). (See 20.8 Interrupts.)
20.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
20.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See Chapter 19 System Integration Module (SIM).)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Serial Peripheral Interface Module (SPI)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
20.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are:
•
•
•
•
•
MISO — Data received
MOSI — Data transmitted
SPSCK — Serial clock
SS — Slave select
CGND — Clock ground (internally connected to VSS)
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a
single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins
are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD
.
20.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
20.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
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Freescale Semiconductor
I/O Signals
20.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
20.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See 20.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 20-12.
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-12. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See 20.13.2 SPI Status and Control
Register.)
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 20.7.2 Mode Fault Error.) For the state of
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. (See Table 20-3.)
Table 20-3. SPI Configuration
SPE
SPMSTR
MODFEN
SPI Configuration
Not enabled
State of SS Logic
General-purpose I/O; SS ignored by SPI
Input-only to SPI
X(1)
0
1
1
1
X
X
0
0
Slave
1
Master without MODF
Master with MODF
General-purpose I/O; SS ignored by SPI
Input-only to SPI
1
1
Note 1. X = Don’t care
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
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Serial Peripheral Interface Module (SPI)
20.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to VSS as shown in Table 20-1.
20.13 I/O Registers
Three registers control and monitor SPI operation:
•
•
•
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
20.13.1 SPI Control Register
The SPI control register:
•
•
•
•
•
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address: $0010
Bit 7
SPRIE
0
6
5
SPMSTR
1
4
CPOL
0
3
CPHA
1
2
SPWOM
0
1
SPE
0
Bit 0
SPTIE
0
Read:
Write:
Reset:
DMAS
0
= Unimplemented
Figure 20-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
DMAS — DMA Select Bit
This read only bit has no effect on this version of the SPI. This bit always reads as a 0.
0 = SPRF DMA and SPTE DMA service requests disabled (SPRF CPU and SPTE CPU interrupt
requests enabled)
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
20-4 and Figure 20-6.) To transmit data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
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I/O Registers
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure
20-4 and Figure 20-6.) To transmit data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between
bytes. (See Figure 20-12.) Reset sets the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 20.9
Resetting the SPI.) Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
20.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
•
•
•
•
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
•
•
•
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address: $0011
Bit 7
6
ERRIE
0
5
4
3
2
MODFEN
0
1
SPR1
0
Bit 0
SPR0
0
Read:
Write:
Reset:
SPRF
OVRF
MODF
SPTE
0
0
0
1
= Unimplemented
Figure 20-14. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Serial Peripheral Interface Module (SPI)
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears
the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with
MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
NOTE
Do not write to the SPI data register unless the SPTE bit is high.
During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is
enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of
MODFEN. (See 20.12.4 SS (Slave Select).)
If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. (See 20.7.2 Mode
Fault Error.)
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I/O Registers
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 20-4. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Table 20-4. SPI Master Baud Rate Selection
SPR1 and SPR0
Baud Rate Divisor (BD)
00
01
10
11
2
8
32
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Baud rate = --------------------------
2 × BD
where:
CGMOUT = base clock output of the clock generator module (CGM)
BD = baud rate divisor
20.13.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. (See Figure 20-2.)
Address: $0012
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by reset
Figure 20-15. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
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Serial Peripheral Interface Module (SPI)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Chapter 21
Timebase Module (TBM)
21.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by the external crystal clock. This TBM version uses 15 divider
stages, eight of which are user selectable.
21.2 Features
Features of the TBM module include:
•
Software programmable 1-Hz, 4-Hz, 16-Hz, 256-Hz, 512-Hz, 1024-Hz, 2048-Hz, and 4096-Hz
periodic interrupt using external 32.768-kHz crystal
•
User selectable oscillator clock source enable during stop mode to allow periodic wakeup from stop
21.3 Functional Description
NOTE
This module is designed for a 32.768-kHz oscillator.
This module can generate a periodic interrupt by dividing the crystal frequency, CGMXCLK. The counter
is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 21-1, starts counting when
the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set.
If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the
TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated
at approximately half of the overflow period. Subsequent events occur at the exact period.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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223
Timebase Module (TBM)
TBON
÷ 2 ÷ 2 ÷ 2
÷ 2
÷ 2
÷ 16
÷ 2
÷ 32
÷ 2
÷ 64
CGMXCLK
÷ 8
÷ 128
TBMINT
÷ 2 ÷ 2 ÷ 2 ÷ 2
÷ 2 ÷ 2
÷ 2048
÷ 2 ÷ 2
÷ 8192
÷ 32768
TBIF
TBIE
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
SEL
Figure 21-1. Timebase Block Diagram
21.4 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the
rate.
Address:
$001C
Bit 7
6
TBR2
0
5
TBR1
0
4
TBR0
0
3
2
1
TBON
0
Bit 0
R
Read:
Write:
Reset:
TBIF
0
TACK
0
TBIE
0
0
0
= Unimplemented
R
= Reserved
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
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Interrupts
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768-kHz
Timebase Interrupt Rate
TBR2
TBR1
TBR0
Divider
Hz
1
ms
1000
250
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32768
8192
2048
128
64
4
16
62.5
~ 3.9
~2
256
512
1024
2048
4096
32
~1
16
~0.5
~0.24
8
NOTE
Do not change TBR2:TBR0 bits while the timebase is enabled
(TBON = 1).
TACK — Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
21.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
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Timebase Module (TBM)
21.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
21.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
21.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during STOP mode. In stop mode the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
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Chapter 22
Timer Interface Module (TIM)
22.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 22-1
is a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
22.2 Features
Features of the TIM include:
•
Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
•
•
•
•
•
Buffered and unbuffered pulse-width-modulation (PWM) signal generation
Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
22.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. The full names
of the TIM I/O pins are listed in Table 22-1. The generic pin names appear in the text that follows.
Table 22-1. Pin Name Conventions
TIM Generic Pin Names:
T[1,2]CH0
PTD4/T1CH0
PTD6/T2CH0
T[1,2]CH1
PTD5/T1CH1
PTD7/T2CH1
TIM1
TIM2
Full TIM
Pin Names:
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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227
Timer Interface Module (TIM)
22.4 Functional Description
Figure 22-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels. If a channel is configured as input capture, then an internal pullup device may be enabled for
that channel. (See 16.5.3 Port D Input Pullup Enable Register.)
PRESCALER SELECT
INTERNAL
PRESCALER
BUS CLOCK
TSTOP
PS2
PS1
PS0
TRST
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CH0MAX
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
T[1,2]CH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
T[1,2]CH1
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
CH1IE
Figure 22-1. TIM Block Diagram
Figure 22-2 summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Freescale Semiconductor
Functional Description
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
0
Timer 1 Status and Control
TOIE
TSTOP
PS2
PS1
PS0
$0020
Register Write:
(T1SC)
Reset:
TRST
0
0
0
1
0
0
0
9
0
Read:
Bit 15
14
13
12
11
10
Bit 8
Timer 1 Counter
Register High Write:
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
(T1CNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Read:
Bit 7
Bit 0
Timer 1 Counter
Register Low Write:
(T1CNTL)
Reset:
0
Bit 15
1
0
0
0
0
0
0
0
Bit 8
1
Read:
Timer 1 Counter Modulo
14
13
12
11
10
9
Register High Write:
(T1MODH)
Reset:
1
1
1
1
1
1
Read:
Timer 1 Counter Modulo
Bit 7
6
1
5
1
4
1
3
2
1
Bit 0
1
Register Low Write:
(T1MODL)
Reset:
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read:
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Timer 1 Channel 0 Status and
Control Register (T1SC0)
Write:
Reset:
Read:
0
Timer 1 Channel 0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Register High Write:
(T1CH0H)
Reset:
Indeterminate after reset
Read:
Timer 1 Channel 0
6
5
0
4
3
2
1
Bit 0
Register Low Write:
(T1CH0L)
Reset:
Indeterminate after reset
Read:
CH1F
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
Timer 1 Channel 1 Status and
Control Register (T1SC1)
Write:
Reset:
Read:
0
0
0
0
0
0
0
9
0
Timer 1 Channel 1
Bit 15
14
13
12
11
10
Bit 8
Register High Write:
(T1CH1H)
Reset:
Indeterminate after reset
Read:
Timer 1 Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T1CH1L)
Reset:
Indeterminate after reset
Read:
TOF
0
TRST
0
0
Timer 2 Status and Control
TOIE
0
TSTOP
1
PS2
0
PS1
0
PS0
0
Register Write:
(T2SC)
Reset:
0
0
0
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 1 of 2)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
229
Timer Interface Module (TIM)
Addr.
Register Name
Timer 2 Counter
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
$002C
Register High Write:
(T2CNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Read:
Bit 7
Bit 0
Timer 2 Counter
Register Low Write:
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
(T2CNTL)
Reset:
0
Bit 15
1
0
0
0
0
0
0
0
Bit 8
1
Read:
Timer 2 Counter Modulo
14
13
12
11
10
9
Register High Write:
(T2MODH)
Reset:
1
1
1
1
1
1
Read:
Timer 2 Counter Modulo
Bit 7
6
1
5
1
4
1
3
2
1
Bit 0
1
Register Low Write:
(T2MODL)
Reset:
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read:
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Timer 2 Channel 0 Status and
Control Register (T2SC0)
Write:
Reset:
Read:
0
Timer 2 Channel 0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Register High Write:
(T2CH0H)
Reset:
Indeterminate after reset
Read:
Timer 2 Channel 0
6
5
0
4
3
2
1
Bit 0
Register Low Write:
(T2CH0L)
Reset:
Indeterminate after reset
Read:
CH1F
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
Timer 2 Channel 1 Status and
Control Register (T2SC1)
Write:
Reset:
Read:
0
0
0
0
0
0
0
9
0
Timer 2 Channel 1
Bit 15
14
13
12
11
10
Bit 8
Register High Write:
(T2CH1H)
Reset:
Indeterminate after reset
Read:
Timer 2 Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T2CH1L)
Reset:
Indeterminate after reset
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 2 of 2)
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Functional Description
22.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
22.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
22.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
22.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 22.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
•
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
•
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
22.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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231
Timer Interface Module (TIM)
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
22.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 22-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to
set the pin if the state of the PWM pulse is logic 0.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000. See 22.9.1 TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
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Functional Description
22.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 22.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
•
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
22.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Timer Interface Module (TIM)
22.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 22-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB:ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 22-3.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM channel 0 status and
control register (TSC0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 22.9.4 TIM Channel Status and Control Registers.)
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Interrupts
22.5 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
22.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
22.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
22.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
22.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 19.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
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Timer Interface Module (TIM)
22.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0,
and T2CH1 as described in 22.3 Pin Name Conventions.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
22.9 I/O Registers
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0, TSC1)
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
22.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
•
•
•
•
•
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 22-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
236
Freescale Semiconductor
I/O Registers
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 22-2 shows. Reset clears the PS[2:0] bits.
Table 22-2. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
22.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
237
Timer Interface Module (TIM)
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-6. TIM Counter Registers Low (TCNTL)
22.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $002E
Bit 7
Bit 15
1
6
14
1
5
13
1
4
12
1
3
11
1
2
10
1
1
9
1
Bit 0
Bit 8
1
Read:
Write:
Reset:
Figure 22-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7
Bit 7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
Bit 0
Bit 0
1
Read:
Write:
Reset:
Figure 22-8. TIM Counter Modulo Register Low (TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
238
Freescale Semiconductor
I/O Registers
22.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
•
•
•
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
CH0F
0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
0
Figure 22-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
CH1F
0
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1IE
0
0
0
= Unimplemented
Figure 22-10. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
239
Timer Interface Module (TIM)
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 22-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table
22-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is
available as a general-purpose I/O pin. Table 22-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 22-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Toggle output on compare
X0
X1
00
00
00
01
01
01
1X
1X
1X
00
00
01
10
11
01
10
11
01
10
11
Output preset
Input capture
Output compare or PWM
Clear output on compare
Set output on compare
Toggle output on compare
Buffered output
compare or
buffered PWM
Clear output on compare
Set output on compare
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
240
Freescale Semiconductor
I/O Registers
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 22-11 shows, the CHxMAX bit takes effect in the cycle
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
COMPARE
CHxMAX
Figure 22-11. CHxMAX Latency
22.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
241
Timer Interface Module (TIM)
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
Indeterminate after reset
Figure 22-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
Indeterminate after reset
Figure 22-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
Indeterminate after reset
Figure 22-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035
Bit 7
6
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
Indeterminate after reset
Figure 22-15. TIM Channel 1 Register Low (TCH1L)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
242
Freescale Semiconductor
Chapter 23
Electrical Specifications
23.1 Introduction
This section contains electrical and timing specifications.
23.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 23.5 5.0-V DC Electrical Characteristics for guaranteed operating
conditions.
Characteristic(1)
Symbol
Value
Unit
V
V
Supply voltage
Input voltage
–0.3 to + 6.0
DD
V
V
– 0.3 to V + 0.3
DD
V
In
SS
Maximum current per pin excluding V , V , and PTC0–PTC4
DD SS
I
15
25
mA
mA
mA
mA
°C
IPTC0–PTC4
Maximum current for pins PTC0–PTC4
I
Maximum current into V
DD
150
mvdd
I
Maximum current out of V
SS
150
mvss
T
Storage temperature
Note:
–55 to +150
stg
1. Voltages referenced to VSS
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the range
VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused
inputs are connected to an appropriate logic voltage level (for example,
either VSS or VDD).
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
243
Electrical Specifications
23.3 Functional Operating Range
Characteristic
Symbol
Value
Unit
TA
Operating temperature range
–40 to +85
°C
3.0 10%
5.0 10%
VDD
Operating voltage range
V
23.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
40-pin PDIP
42-pin SDIP
60
60
95
θJA
°C/W
44-pin QFP
PI/O
PD
I/O pin power dissipation
Power dissipation(1)
User determined
W
W
PD = (IDD × VDD) + PI/O
K/(TJ + 273 °C)
=
PD × (TA + 273 °C)
+ PD2 × θJA
Constant(2)
K
W/°C
°C
TJ
TA + (PD × θJA)
Average junction temperature
Notes:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and
TJ can be determined for any value of TA.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
244
Freescale Semiconductor
5.0-V DC Electrical Characteristics
23.5 5.0-V DC Electrical Characteristics
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
Output high voltage
(I
(I
(I
= –2.0 mA) all I/O pins
V
Load
Load
Load
OH
VDD – 0.8
VDD – 1.5
VDD – 0.8
—
—
—
—
—
—
—
—
50
V
V
V
= –10.0 mA) all I/O pins
= –10.0 mA) pins PTC0–PTC4 only
V
OH
V
OH
I
I
I
mA
Maximum combined I
for port C, port E,
OH1
OH
port PTD0–PTD3
—
—
50
mA
mA
—
—
Maximum combined I
for port PTD4–PTD7,
OH2
OH
port A, port B
100
Maximum total I for all port pins
OHT
OH
Output low voltage
(I
(I
(I
= 1.6 mA) all I/O pins
V
Load
Load
Load
OL
—
—
—
—
—
—
—
—
0.4
1.5
1.0
50
V
V
V
= 10 mA) all I/O pins
V
OL
V
= 15 mA) pins PTC0–PTC4 only
OL
I
mA
Maximum combined I for port C, port E,
OL1
OL
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
—
—
—
—
50
mA
mA
I
OL2
OL
port A, port B
100
I
Maximum total I for all port pins
OLT
OL
Input high voltage
All ports, IRQ, RST, OSC1
V
0.7 × VDD
VDD
—
—
V
V
IH
Input low voltage
All ports, IRQ, RST, OSC1
V
V
0.2 × VDD
IL
SS
VDD supply current
Run(3)
Wait(4)
—
—
15
4
20
8
mA
mA
Stop(5)
25 °C
25 °C with TBM enabled(6)
IDD
—
—
—
—
—
3
20
300
50
500
—
—
—
—
—
µA
µA
µA
µA
µA
25 °C with LVI and TBM enabled(6)
–40 °C to 85 °C with TBM enabled(6)
–40 °C to 85 °C with LVI and TBM enabled(6)
I/O ports Hi-Z leakage current(7)
I
—
—
—
—
10
1
µA
µA
IL
I
Input current
In
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU
20
45
65
kΩ
C
Out
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
C
In
VTST
VDD + 2.5
3.90
Monitor mode entry voltage
—
9
V
V
VTRIPF
Low-voltage inhibit, trip falling voltage
4.25
4.50
Contined on next page
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
245
Electrical Specifications
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
VTRIPR
Low-voltage inhibit, trip rising voltage
4.20
4.35
4.60
V
Low-voltage inhibit reset/recover hysteresis
VHYS
—
100
—
mV
(V
+ V
= V
)
TRIPF
HYS
TRIPR
POR rearm voltage(8)
POR reset voltage(9)
VPOR
VPORRST
RPOR
0
0
—
700
—
100
800
—
mV
mV
POR rise time ramp rate(10)
Notes:
0.035
V/ms
1. VDD = 5.0 Vdc 10%, V = 0 Vdc, T = T to T , unless otherwise noted
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = V
.
SS
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 23.12 ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
23.6 3.0-V DC Electrical Characteristics
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
Output high voltage
(I
(I
(I
= –0.6 mA) all I/O pins
V
Load
Load
Load
OH
VDD – 0.3
VDD – 1.0
VDD – 0.5
—
—
—
—
—
—
—
—
30
V
V
V
= –4.0 mA) all I/O pins
= –4.0 mA) pins PTC0–PTC4 only
V
OH
V
OH
I
I
I
mA
Maximum combined I
for port C, port E,
OH1
OH
port PTD0–PTD3
—
—
30
60
mA
mA
—
—
Maximum combined I
for port PTD4–PTD7,
OH2
OH
port A, port B
Maximum total I for all port pins
OHT
OH
Output low voltage
(I
(I
(I
= 0.5 mA) all I/O pins
V
Load
Load
Load
OL
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
V
V
V
= 6.0 mA) all I/O pins
V
OL
V
= 10.0 mA) pins PTC0–PTC4 only
OL
I
mA
Maximum combined I for port C, port E,
OL1
OL
port PTD0–PTD3
Maximum combined I for port PTD4–PTD7,
—
—
—
—
30
60
mA
mA
I
OL2
OL
port A, port B
I
Maximum total I for all port pins
OLT
OL
Contined on next page
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
246
Freescale Semiconductor
3.0-V DC Electrical Characteristics
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
Input high voltage
All ports, IRQ, RST, OSC1
V
0.7 × VDD
VDD
—
V
IH
Input low voltage
All ports, IRQ, RST, OSC1
V
V
0.3 × VDD
—
V
IL
SS
VDD supply current
Run(3)
Wait(4)
—
—
4.5
1.65
8
4
mA
mA
Stop(5)
25 °C
25 °C with TBM enabled(6)
IDD
—
—
—
—
—
2
12
200
30
300
—
—
—
—
—
µA
µA
µA
µA
µA
25 °C with LVI and TBM enabled(6)
–40 °C to 85 °C with TBM enabled(6)
–40 °C to 85 °C with LVI and TBM enabled(6)
I/O ports Hi-Z leakage current(7)
I
—
—
—
—
10
1
µA
µA
IL
I
Input current
In
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU
20
45
65
kΩ
C
Out
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
C
In
VTST
VDD + 2.5
2.45
Monitor mode entry voltage
—
9
V
V
V
VTRIPF
VTRIPR
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
2.60
2.66
2.70
2.80
2.55
VHYS
—
60
—
mV
(V
+ V
= V
)
TRIPF
HYS
TRIPR
POR rearm voltage(8)
POR reset voltage(9)
VPOR
VPORRST
RPOR
0
0
—
700
—
100
800
—
mV
mV
POR rise time ramp rate(10)
Notes:
0.02
V/ms
1. VDD = 3.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = V
.
SS
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
247
Electrical Specifications
23.7 5.0-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation(2)
Crystal option
External clock option(3)
32
dc(4)
fOSC
100
32.8
kHz
MHz
fOP (fBUS
)
Internal operating frequency
—
122
50
8.2
—
MHz
ns
Internal clock period (1/fOP
)
tCYC
RST input pulse width low(5)
t
—
ns
IRL
IRQ interrupt pulse width low(6)
(edge-triggered)
t
50
—
—
ns
ILIH
tILIL
tCYC
IRQ interrupt pulse period
Note 8
16-bit timer(7)
Input capture pulse width
Input capture period
tTH, TL
tTLTL
t
ns
tCYC
—
—
Note 8
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. See 23.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus tCYC
.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
248
Freescale Semiconductor
3.0-V Control Timing
23.8 3.0-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation(2)
Crystal option
External clock option(3)
32
dc(4)
fOSC
100
16.4
kHz
MHz
fOP (fBUS
)
Internal operating frequency
—
4.1
—
MHz
ns
Internal clock period (1/fOP
)
tCYC
244
125
RST input pulse width low(5)
t
—
ns
IRL
IRQ interrupt pulse width low(6)
(edge-triggered)
t
125
—
—
ns
ILIH
tILIL
tCYC
IRQ interrupt pulse period
Note 8
16-bit timer(7)
Input capture pulse width
Input capture period
tTH, TL
tTLTL
t
ns
tCYC
—
—
Note 8
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. See 23.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus tCYC
.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
249
Electrical Specifications
23.9 Output High-Voltage Characteristics
0
–5
–10
–15
–20
–25
–30
–35
–40
–40
0
25
85
3
3.2
3.4
3.6
3.8
4.0
4.2
V
OH (V)
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 23-1. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 4.5 Vdc)
0
–5
–40
0
–10
25
85
–15
–20
–25
1.3
1.5
1.7
1.9
2.1
2.3
2.5
V
OH (V)
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 23-2. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 2.7 Vdc)
0
–5
–10
–40
0
25
85
–15
–20
–25
–30
–35
–40
3
3.2
3.4
3.6
3.8
4.0
4.2
VOH (V)
V
OH > VDD –0.8 V @ IOH = –10.0 mA
Figure 23-3. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 4.5 Vdc)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
250
Freescale Semiconductor
Output High-Voltage Characteristics
0
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
2.1
2.3
2.5
VOH (V)
VOH > VDD –0.5 V @ IOH = –4.0 mA
Figure 23-4. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc)
0
–10
–20
–40
0
25
85
–30
–40
–50
–60
–70
–80
–90
3
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
V
OH (V)
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 23-5. Typical High-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
0
–5
–40
0
–10
25
85
–15
–20
–25
1.3
1.5
1.7
1.9
2.1
2.3
2.5
VOH (V)
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 23-6. Typical High-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
251
Electrical Specifications
23.10 Output Low-Voltage Characteristics
35
30
25
20
15
10
5
–40
0
25
85
0
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL (V)
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 23-7. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 5.5 Vdc)
14
12
–40
0
25
10
8
85
6
4
2
0
1.6
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL (V)
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 23-8. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 2.7 Vdc)
60
50
40
30
20
10
0
–40
0
25
85
1.6
0.4
0.6
0.8
1.0
OL (V)
1.2
1.4
V
VOL < 1.0 V @ IOL = 15 mA
Figure 23-9. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 4.5 Vdc)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
252
Freescale Semiconductor
Output Low-Voltage Characteristics
30
25
20
15
10
5
–40
0
25
85
0
1.6
0.2
0.4
0.6
0.8
1.0
OL (V)
1.2
1.4
V
VOL < 0.8 V @ IOL = 10 mA
Figure 23-10. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc)
35
30
–40
0
25
85
25
20
15
10
5
0
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
OL (V)
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 23-11. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
14
12
–40
0
25
10
8
85
6
4
2
0
1.4
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
V
OL (V)
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 23-12. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
253
Electrical Specifications
23.11 Typical Supply Currents
16
14
12
10
8
6
4
5.5 V
3.6 V
2
0
0
1
2
3
4 5
fBUS (MHz)
6
7
8
9
Figure 23-13. Typical Operating IDD, with All Modules Turned On (–40 °C to 85 °C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5 V
3.6 V
0
1
2
3
4
fBUS (MHz)
5
6
7
8
Figure 23-14. Typical Wait Mode IDD, with all Modules Disabled (–40 °C to 85 °C)
1.35
1.30
1.25
1.20
1.15
1.10
5.5 V
3.6 V
1.05
1
0
1
2
3
4 5
fBUS (MHz)
6
7
8
9
Figure 23-15. Typical Stop Mode IDD, with all Modules Disabled (–40 °C to 85 °C)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
254
Freescale Semiconductor
ADC Characteristics
23.12 ADC Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
Comments
V
DDAD should be tied to
2.7
(VDD min)
5.5
(VDD max)
VDDAD
Supply voltage
V
the same potential as VDD
via separate traces.
VADIN
BAD
VDDAD
8
VADIN ≤ VREFH
Input voltages
Resolution
0
8
V
Bits
Absolute accuracy
(VREFL = 0 V,
VREFH = VDDAD = 5 V 10%)
AAD
—
1
LSB
MHz
Includes quantization
tAIC = 1/fADIC, tested only
at 1 MHz
fADIC
RAD
ADC internal clock
0.5
1.048
VREFH = VDDAD
VREFL = VSSAD
VREFL
VREFH
Conversion range
V
tADPU
tADC
tADS
ZADI
FADI
CADI
tAIC cycles
Power-up time
16
16
5
t
AIC cycles
Conversion time
17
—
Sample time(2)
tAIC cycles
Hex
Zero input reading(3)
VIN = VREFL
VIN = VREFH
Not tested
00
FE
—
01
Full-scale reading(3)
Input capacitance
FF
Hex
(20) 8
pF
Input leakage(4)
Port B
—
—
1
µA
Notes:
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc 10%, VREFL = 0
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
255
Electrical Specifications
23.13 5.0-V SPI Characteristics
Diagram
Characteristic(2)
Number(1)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/2
fOP
fOP/128
dc
MHz
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
tLead(S)
tLag(S)
tCYC
tCYC
tCYC
tCYC
1
2
1
128
—
2
3
Enable lead time
Enable lag time
1
1
—
—
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
4
5
6
7
ns
ns
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
30
30
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
30
30
—
—
ns
ns
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
8
9
0
0
40
40
ns
ns
Disable time, slave(4)
tDIS(S)
—
40
ns
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
10
—
—
50
50
ns
ns
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
11
0
0
—
—
ns
ns
Notes:
1. Numbers refer to dimensions in Figure 23-16 and Figure 23-17.
2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins.
DD
DD
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
256
Freescale Semiconductor
3.0-V SPI Characteristics
23.14 3.0-V SPI Characteristics
Diagram
Characteristic(2)
Number(1)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
f
/2
f
f
f
/128
OP
f
MHz
MHz
OP(M)
OP
dc
OP
OP(S)
Cycle time
Master
Slave
tCYC
tCYC
tCYC(M)
tCYC(S)
1
2
1
128
—
t
tCYC
tCYC
2
3
Enable lead time
Enable lag time
1
1
—
—
ead(s)
L
t
ag(s)
L
Clock (SPSCK) high time
Master
Slave
t
t
tCYC –35
1/2 tCYC –35
64 tCYC
—
4
5
6
7
ns
ns
SCKH(M)
SCKH(S)
Clock (SPSCK) low time
Master
Slave
t
t
tCYC –35
1/2 tCYC –35
64 tCYC
—
ns
ns
SCKL(M)
SCKL(S)
Data setup time (inputs)
Master
Slave
t
40
40
—
—
ns
ns
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
40
40
—
—
ns
ns
H(M)
t
H(S)
Access time, slave(3)
CPHA = 0
CPHA = 1
t
ns
ns
0
0
8
9
50
50
A(CP0)
t
A(CP1)
Disable time, slave(4)
t
—
50
ns
DIS(S)
Data valid time, after enable edge
Master
Slave(5)
t
t
60
60
10
—
—
ns
ns
V(M)
V(S)
Data hold time, outputs, after enable edge
Master
Slave
t
t
11
0
0
—
—
ns
ns
HO(M)
HO(S)
Notes:
1. Numbers refer to dimensions in Figure 23-16 and Figure 23-17.
2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins.
DD
DD
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
257
Electrical Specifications
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
5
4
SPSCK OUTPUT
CPOL = 0
NOTE
4
5
SPSCK OUTPUT
CPOL = 1
NOTE
6
7
MISO
INPUT
MSB IN
BITS 6–1
BITS 6–1
LSB IN
11
MASTER MSB OUT
10
11
MOSI
OUTPUT
MASTER LSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SPSCK OUTPUT
CPOL = 0
5
NOTE
NOTE
4
SPSCK OUTPUT
CPOL = 1
5
4
6
7
MISO
INPUT
MSB IN
BITS 6–1
BITS 6–1
LSB IN
11
10
10
MOSI
OUTPUT
MASTER MSB OUT
MASTER LSB OUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 23-16. SPI Master Timing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
258
Freescale Semiconductor
3.0-V SPI Characteristics
SS
INPUT
3
1
SPSCK INPUT
CPOL = 0
5
4
4
5
2
SPSCK INPUT
CPOL = 1
9
8
MISO
INPUT
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
11
6
7
10
MOSI
OUTPUT
MSB IN
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SPSCK INPUT
CPOL = 0
5
4
5
2
3
SPSCK INPUT
CPOL = 1
4
10
9
8
MISO
OUTPUT
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
6
7
10
MOSI
INPUT
MSB IN
LSB IN
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 23-17. SPI Slave Timing
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
259
Electrical Specifications
23.15 Timer Interface Module Characteristics
Characteristic
Symbol
Min
Max
Unit
t
, t
tCYC
Input capture pulse width
1
—
TIH TIL
23.16 Clock Generation Module Characteristics
23.16.1 CGM Component Specifications
Characteristic
Crystal reference frequency
Symbol
Min
30
—
Typ
Max
Unit
f
32.768
100
—
kHz
pF
XCLK
Crystal load capacitance(1)
Crystal fixed capacitance(2)
Crystal tuning capacitance(2)
Feedback bias resistor
C
L
12.5
15
C
1
—
—
pF
C
2
15
—
—
pF
R
B
1
10
22
MΩ
kΩ
Series resistor(3)
Notes:
R
S
100
330
470
1. Crystal manufacturer value.
2. Capacitor on OSC1 pin. Does not include parasitic capacitance due to package, pin, and board.
3. Capacitor on OSC2 pin. Does not include parasitic capacitance due to package, pin, and board.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
260
Freescale Semiconductor
Clock Generation Module Characteristics
23.16.2 CGM Electrical Specifications
Description
Operating voltage
Symbol
Min
2.7
Typ
—
Max
5.5
Unit
V
VDD
Operating temperature
Reference frequency
T
–40
30
25
85
°C
fRDV
32.768
38.4
—
100
—
kHz
kHz
Hz
fNOM
fVRS
Range nominal multiplier
—
VCO center-of-range frequency(1)
38.4 k
40.0 M
Medium-voltage VCO center-of-range frequency(2)
VCO range linear range multiplier
VCO power-of-two range multiplier
VCO multiply factor
f
38.4 k
—
—
—
—
1
40.0 M
255
4
Hz
VRS
L
1
2E
N
1
1
1
4095
8
2P
R
VCO prescale multiplier
Reference divider factor
1
1
15
fVCLK
VCO operating frequency
38.4 k
—
—
—
40.0 M
8.2
Hz
MHz
MHz
ms
Bus operating frequency(1)
fBUS
fBUS
tLock
tLock
Bus frequency @ medium voltage(2)
Manual acquisition time
—
—
—
—
—
—
4.1
50
50
Automatic lock time
ms
fRCLK
×
PLL jitter(3)
fJ
0.025%
× 2P N/4
0
—
Hz
External clock input frequency
PLL disabled
fOSC
fOSC
dc
—
—
32.8 M
1.5 M
Hz
Hz
External clock input frequency
PLL enabled
30 k
Notes:
1. 5.0 V 10% VDD
2. 3.0 V 10% VDD
3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
261
Electrical Specifications
23.17 Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
1.3
1
Max
—
Unit
V
V
RDR
FLASH program bus clock frequency
—
—
MHz
(1)
FLASH read bus clock frequency
FLASH page erase time
8k
1
8.4M
—
Hz
ms
f
ead
R
(2)
t
rase
E
(3)
rase
FLASH mass erase time
t
4
10
5
—
—
—
—
—
40
—
ms
µs
µs
µs
µs
µs
µs
ME
t
FLASH PGM/ERASE to HVEN set up time
FLASH high-voltage hold time
FLASH high-voltage hold time (mass erase)
FLASH program hold time
nvs
nvh
t
t
100
5
nvhl
t
pgs
t
FLASH program time
30
1
PROG
(4)
FLASH return to read time
t
rcv
(5)
FLASH cumulative program HV period
t
—
10k
10k
10
4
ms
HV
FLASH row erase endurance(6)
FLASH row program endurance(7)
—
—
—
—
—
—
Cycles
Cycles
Years
FLASH data retention time(8)
Notes:
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
t
HV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 64) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time speci-
fied.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
262
Freescale Semiconductor
Chapter 24
Mechanical Specifications
24.1 Introduction
This section gives the dimensions for:
•
•
•
40-pin plastic dual in-line package (case 711-03)
42-pin shrink dual in-line package (case 858-01)
44-pin plastic quad flat pack (case 824A-01)
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
263
Chapter 25
Ordering Information
25.1 Introduction
This section contains ordering numbers for the MC68HC908GP32.
25.2 MC Order Numbers
Table 25-1. MC Order Numbers
Operating
MC order number
Package
temperature range
MC68HC908GP32CP
MC68HC908GP32CB
MC68HC908GP32CFB
40-pin PDIP
42-pin SDIP
44-pin QFP
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
271
Ordering Information
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
272
Freescale Semiconductor
Appendix A
MC68HC08GP32
A.1 Introduction
This section introduces the MC68HC08GP32, the ROM part equivalent to the MC68HC908GP32. The
entire data book apply to this ROM device, with exceptions outlined in this appendix.
Table A-1. Summary of MC68HC08GP32 and MC68HC908GP32 Differences
MC68HC08GP32
32,256 bytes ROM
36 bytes ROM
MC68HC908GP32
32,256 bytes FLASH
36 bytes FLASH
Memory ($8000–$FDFF)
User vectors ($FFDC–$FFFF)
Mask option registers; defined by
mask; read only.
Configuration registers; write
once after reset.
Registers at $001E and $001F
Registers at $FE08 and $FF7E
$001E — MOR2
$001F — MOR1
$001E — CONFIG2
$001F — CONFIG1
FLASH related registers.
$FE08 — FLCR
Not used;
locations are reserved
$FF7E — FLBPR
Not used;
bit is reserved
MODRST: monitor mode entry
by blank reset vector bit.
Bit 2 at $FE01
Used for testing and FLASH
programming/erasing.
Monitor ROM ($FE20–$FF52)
Used for testing purposes only.
40-pin PDIP
42-pin SDIP
44-pin QFP
Available Packages
42-pin SDIP
44-pin QFP
A.2 MCU Block Diagram
Figure A-1 shows the block diagram of the MC68HC08GP32.
A.3 Memory Map
The MC68HC08GP32 has 32,256 bytes of user ROM from $8000 to $FDFF, and 36 bytes of user ROM
vectors from $FFDC to $FFFF. On the MC68HC908GP32, these memory locations are FLASH memory.
Figure A-2 shows the memory map of the MC68HC08GP32.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
273
MC68HC08GP32
INTERNAL BUS
M68HC08 CPU
PTA7/KBD7–
PTA0/KBD0 †
PROGRAMMABLE TIMEBASE
MODULE
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
SINGLE BREAKPOINT BREAK
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
USER ROM — 32,256 BYTES
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
USER RAM — 512 BYTES
8-BIT KEYBOARD
INTERRUPT MODULE
MONITOR ROM — 307 BYTES
PTC6 †
PTC5 †
2-CHANNEL TIMER INTERFACE
MODULE 1
USER ROM VECTOR SPACE — 36 BYTES
PTC4 † ‡
PTC3 † ‡
PTC2 † ‡
PTC1 † ‡
PTC0 † ‡
2-CHANNEL TIMER INTERFACE
MODULE 2
CLOCK GENERATOR MODULE
OSC1
32-kHz OSCILLATOR
OSC2
SERIAL COMMUNICATIONS
INTERFACE MODULE
PTD7/T2CH1 †
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTD3/SPSCK †
PTD2/MOSI †
PTD1/MISO †
PTD0/SS †
PHASE-LOCKED LOOP
CGMXFC
COMPUTER OPERATING
PROPERLY MODULE
24 INTR SYSTEM INTEGRATION
MODULE
* RST
* IRQ
SERIAL PERIPHERAL
INTERFACE MODULE
SINGLE EXTERNAL IRQ
MODULE
MONITOR MODULE
VDDAD/VREFH
VSSAD/VREFL
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTE1/RxD
PTE0/TxD
DATA BUS SWITCH
MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
VDD
SECURITY
MODULE
VSS
VDDA
POWER
MASK OPTION REGISTER 1
MODULE
VSSA
MONITOR MODE ENTRY
MODULE
MASK OPTION REGISTER 2
MODULE
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Shaded blocks indicate differences to MC68HC908GP32
Figure A-1. MC68HC08GP32 Block Diagram
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
274
Freescale Semiconductor
Memory Map
$0000
↓
I/O Registers
64 Bytes
$003F
$0040
↓
RAM
512 Bytes
$023F
$0240
↓
Unimplemented
32,192 Bytes
$7FFF
$8000
↓
ROM
32,256 Bytes
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE09
$FE0A
$FE0B
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
↓
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved (SUBAR)
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Interrupt Status Register 3 (INT3)
Reserved
Reserved
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
LVI Status Register (LVISR)
Unimplemented
3 Bytes
$FE0F
$FE10
↓
Unimplemented
16 Bytes
Reserved for Compatibility with Monitor Code
for A-Family Parts
$FE1F
$FE20
↓
Monitor ROM
307 Bytes
$FF52
$FF53
↓
Unimplemented
43 Bytes
$FF7D
$FF7E
$FF7F
↓
Reserved
Unimplemented
93 Bytes
$FFDB
$FFDC
↓
Note: $FFF6–$FFFD
reserved for
8 security bytes
ROM Vectors
36 Bytes
$FFFF
Figure A-2. MC68HC08GP32 Memory Map
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
275
MC68HC08GP32
A.4 Mask Option Registers
The two mask option registers at $001E and $001F (see Figure A-3 and Figure A-4) are read-only
registers. They are defined by mask options (hard-wired connections) specified at the same time as the
ROM code submission.
On the MC68HC908GP32, these two registers are called configuration registers (CONFIG2 and
CONFIG1).
Address: $001E
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
OSC-
STOPENB
Read:
SCIBDSRC
Write:
Reset:
Mask defined
= Unimplemented
Figure A-3. Mask Option Register 2 (MOR2)
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read: COPRS
Write:
LVISTOP LVIRSTD LVIPWRD LVI5OR3
SSREC
STOP
COPD
Reset:
Mask defined
= Unimplemented
Figure A-4. Mask Option Register 1 (MOR1)
The bit functions for these two registers are the same as the configuration registers in MC68HC908GP32
(see Chapter 8 Configuration Register (CONFIG)).
A.5 Reserved Registers
The two registers at $FE08 and $FF7E are reserved locations on the MC68HC08GP32.
On the MC68HC908GP32, these two locations are the FLASH control register and the FLASH block
protect register respectively.
A.6 Monitor ROM
The monitor program (monitor ROM, $FE20–$FF52) on the MC68HC08GP32 is for device testing only.
The monitor mode entry by blank reset vector bit, MODRST bit (bit 2 at $FE01), is not used in the ROM
device — the reset vector will always contain data in the MC68HC08GP32.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
276
Freescale Semiconductor
Electrical Specifications
A.7 Electrical Specifications
Electrical specifications for the MC68HC908GP32 apply to the MC68HC08GP32, except for the
parameters indicated below.
A.7.1 Functional Operating Range
Characteristic
Symbol
Value
V
Unit
C
M
TA
Operating temperature range
°C
–40 to +85
–40 to +105
–40 to +125
3V 10%
5V 10%
3V 10%
5V 10%
—
VDD
Operating voltage range
V
5V 10%
A.7.2 5.0-V DC Electrical Characteristics
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
VDD supply current
Run(3)
Wait(4)
Stop(5)
—
—
15
4
20
8
mA
mA
25 °C
—
—
—
—
—
—
2
20
300
—
50
—
—
—
35
—
—
µA
µA
µA
µA
µA
µA
IDD
25 °C with TBM enabled(6)
25 °C with LVI and TBM enabled(6)
–40 °C to 125 °C
–40 °C to 85 °C with TBM enabled(6)
500
–40 °C to 85 °C with LVI and TBM enabled(6)
V
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
3.90
4.00
4.25
4.35
4.50
4.60
V
V
TRIPF
V
TRIPR
V
—
100
—
mV
HYS
(VTRIPF + VHYS = VTRIPR
)
Notes:
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, T = T to T , unless otherwise noted
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V from rail. No
DD
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run I . Measured with all modules enabled.
DD
4. Wait I
measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
DD
Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
wait I . Measured with PLL and LVI enabled.
DD
DD
5. Stop I
is measured with OSC1 = V
.
SS
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
277
MC68HC08GP32
A.7.3 3.0-V DC Electrical Characteristics
Typ(2)
Characteristic(1)
Symbol
Min
Max
Unit
VDD supply current
Run(3)
Wait(4)
Stop(5)
—
—
5.2
1.65
8
4
mA
mA
25 °C
—
—
—
—
—
—
—
1
12
25
200
—
—
—
—
—
5
µA
µA
µA
µA
µA
µA
µA
25 °C with TBM enabled(6)
25 °C with TBM enabled(7)
IDD
25 °C with LVI and TBM enabled(6)
–40 °C to 85 °C
—
300
50
—
–40 °C to 85 °C with TBM enabled(7)
–40 °C to 85 °C with LVI and TBM enabled(6)
V
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
2.45
2.50
2.60
2.66
2.70
2.80
V
V
TRIPF
V
TRIPR
V
—
60
—
mV
HYS
(VTRIPF + VHYS = VTRIPR
)
Notes:
1. V
= 3.0 Vdc 10%, V = 0 Vdc, T = T to T , unless otherwise noted
SS A L H
DD
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V from rail. No
DD
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
affects run I . Measured with all modules enabled.
DD
4. Wait I
measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2 V from rail. No dc loads.
DD
Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
wait I . Measured with PLL and LVI enabled.
5. Stop I
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Measured with TBM enabled using 32kHz crystal.
DD
DD
is measured with OSC1 = VSS.
16
14
12
10
8
6
4
5.5 V
3.3 V
2
0
1
2
3
4
5
6
7
8
9
fBUS (MHz)
Figure A-5. Typical Operating IDD
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
278
Freescale Semiconductor
Electrical Specifications
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5 V
3.3 V
1
2
3
4
5
6
7
8
9
fBUS (MHz)
Figure A-6. Typical Wait Mode IDD
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5.5 V
3.3 V
1
2
3
4
5
6
7
8
9
fBUS (MHz)
Figure A-7. Typical Stop Mode IDD
A.7.4 Memory Characteristics
Characteristic
RAM data retention voltage
Notes:
Symbol
Min
1.3
Max
Unit
V
—
V
RDR
Since MC68HC08GP32 is a ROM device, FLASH memory electrical characteristics do not apply.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
279
MC68HC08GP32
A.8 ROM MC Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the
ROM Processing Center (RPC).
Table A-2. ROM MC Order Numbers
Operating
MC order number
Package
temperature range
–40 °C to +85 °C
–40 °C to +105 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +105 °C
–40 °C to +125 °C
MC68HC08GP32CB
MC68HC08GP32VB
MC68HC08GP32MB(1)
MC68HC08GP32CFB
MC68HC08GP32VFB
MC68HC08GP32MFB(1)
Notes:
42-pin SDIP
44-pin QFP
1. Temperature grade "M" is available for 5V operating voltage only.
MC68HC908GP32 • MC68HC08GP32 Data Sheet, Rev. 7
280
Freescale Semiconductor
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