MC44818D [MOTOROLA]
TV AND VCR PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND I2C BUS; 电视机，录像机PLL调谐电路1.3 GHz的预分频器和I2C总线
| 型号： | MC44818D |
| 厂家： | 
MOTOROLA |
| 描述： | TV AND VCR PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND I2C BUS |
| 文件： | 总8页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44818/D
TV AND VCR
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
The MC44818 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO.
This integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The MC44818 is a pin compatible drop in
replacement for the MC44817, where the only difference is the MC44818
has a fixed divide–by–8 prescaler (cannot be bypassed) and the MC44817
uses the three wire bus.
The MC44818 has a programmable 512/1024 reference divider and is
manufactured on a single silicon chip using Motorola’s high density bipolar
process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits).
2
AND I C BUS
SEMICONDUCTOR
TECHNICAL DATA
2
• Complete Single Chip System for MPU Control (I C Bus). Data and
Clock Inputs are 3–Wire Bus Compatible
• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512 and 1024.
• 3–State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
16
• Four Integrated PNP Band Buffers for 40 mA (V
to 14.4 V)
CC1
1
• Output Options for the Reference Frequency and the
Programmable Divider
D SUFFIX
PLASTIC PACKAGE
CASE 751B
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected
(SO–16)
MOSAIC is a trademark of Motorola, Inc.
PIN CONNECTIONS
1
2
3
4
5
6
7
8
16
SDA
SCL
AS
15
14
13
12
11
10
9
Lock
XTAL
Amp In
V
B
B
12 V
CC3
3
2
V
TUN
ORDERING INFORMATION
Operating
V
33 V
B
B
CC2
1
Temperature Range
Device
MC44818D
Package
SO–16
V
5.0 V
HF In
CC1
0
T
A
= –20° to +80°C
Gnd
(Top View)
Motorola, Inc. 1996
Rev 2
MC44818
Representative Block Diagram
Bands Out 30 mA
(40 mA at 0° to 80°C)
V
TUN
V
V
V
CC2
CC1
CC3
5.0 V
7
13 12 11 10
14
12 V
5
6
20 k
4
F
9
out
B
B
B
B
0
Amp In
3
2
1
Test
Logic
2.7 V
Buffers
F
ref
Operational
Amplifier
Latches
DTB1
T
13
Gnd
T , T , T
12 14
9
Phase
Comp
15
Lock
T
, T
10 11
DTB2
POR
P–On
Reset
Latches
6
F
out
F
ref
512/1024
16
4
AS
Data
Clock
CL
1
2
2
Shift Register
15 Bit
I C Bus
Receiver
Data
RL
Ref
15
Divider
DTF
Latches A
3
Osc
XTAL
Latches B
TDI
÷
8
8
Program Divider
15 Bit
HF Input
Latch Control
DTS, EN
Prescaler
F
out
This device contains 3,204 active transistors.
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Rating
Pin
Value
6.0
Unit
V
Power Supply Voltage (V
Band Buffer “Off” Voltage
Band Buffer “On” Current
)
7
10–13
CC1
14.4
V
10–13
50
mA
–
Band Buffer – Short Circuit Duration (0 to V
) (Note 2) 10–13
Continuous
40
CC3
Operational Amplifier Power Supply Voltage (V
)
6
V
CC2
Operational Amplifier Short Circuit Duration (0 to V
)
5
14
Continuous
14.4
–
CC2
Power Supply Voltage (V
Storage Temperature
)
V
CC3
–
–65 to +150
–20 to +80
10
°C
°C
sec
Operating Temperature Range
–
Band Buffer Operation (Note 1) at 50 mA each Buffer All
Buffers “On” Simultaneously
10–13
Operational Amplifier Output Voltage
RF Input Level (10 MHz to 1.3 GHz)
5
–
V
CC2
1.5
V
Vrms
NOTES: 1. At V
= V
= V
to 14.4 V and T = –20° to +80°C.
A
to 14.4 V and T = –20° to +80°C one buffer “On” only.
A
CC3
CC3
CC1
CC1
2. At V
2
MOTOROLA ANALOG IC DEVICE DATA
MC44818
ELECTRICAL CHARACTERISTICS (V
= 5.0 V, V
= 33 V, V
= 12 V, T = 25°C, unless otherwise noted.)
CC3 A
CC1
CC2
Characteristic
Pin
Min
4.5
–
Typ
5.0
37
Max
5.5
50
Unit
V
V
V
V
V
Supply Voltage Range
7
CC1
CC1
CC2
CC2
Supply Current (V
= 5.0 V)
7
mA
V
CC1
Supply Voltage Range
Supply Current (Output Open)
6
25
–
–
37
6
1.5
0.01
0.15
0.2
2.3
1.0
0.3
0.5
mA
µA
V
Band Buffer Leakage Current when “Off” at 12 V
10–13
10–13
10–13
–
Band Buffer Saturation Voltage when “On” at 30 mA
–
Band Buffer Saturation Voltage when “On” at 40 mA
–
V
only for 0° to 80°C
Data/Clock Current at 0 V
1, 2
2
–10
0
–
–
0
µA
µA
µA
V
Clock Current at 5.0 V
1.0
1.0
1.0
1.5
–
Data Current at 5.0 V Acknowledge “Off”
Data Saturation Voltage at 15 mA Acknowledge “On”
Data/Clock Input Voltage Low
Data/Clock Input Voltage High
Clock Frequency Range
1
0
–
1
–
–
1, 2
1, 2
2
–
–
V
3.0
–
–
V
–
100
4.05
kHz
MHz
Oscillator Frequency Range
3
3.15
3.2
Operational Amplifier Internal Reference Voltage
Operational Amplifier Input Current
DC Open Loop Voltage Gain
–
4
2.0
–15
100
0.3
–
2.75
0
3.2
15
–
V
nA
V/V
MHz
V
–
250
–
Gain Bandwidth Product (C = 1.0 nF)
–
–
L
V
out
Low, Sinking 50 µA
5
0.2
0.2
0
0.4
0.5
15
85
30
14.4
V
out
High, Sourcing 10 µA, V
– V
CC2 out
5
–
V
Phase Detector Current in the High Impedance State
Charge Pump High Current of Phase Comparator
Charge Pump Low Current of Phase Comparator
4
–15
30
nA
µA
µA
V
4
50
15
–
4
10
V
V
Supply Voltage Range
Supply Current
14
14
V
CC1
CC3
mA
CC3
All Buffers “Off”
One Buffer “On” when Open
One Buffer “On” at 40 mA
–
–
–
0.2
8.0
48
0.5
13
53
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the I C bus. The incoming information, consisting of a
4_STA CA FM FL CO BA STO
STA = Start Condition
2
chip address byte followed by two or four data bytes, is
treated in the I C bus receiver. The definition of the
STO = Stop Condition
CA = Chip Address Byte
2
permissible bus protocol is shown below:
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information
FL = Data Byte for Frequency Information
1_STA CA CO BA STO
2_STA CA FM FL STO
3_STA CA CO BA FM FL STO
Figure 1. Complete Data Transfer Process
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
P
STA
ADDRESS
CA
R/W
ACK
DATA
ACK
DATA
ACK
STO
3
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Figure 2 shows the five bytes of information that are
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceeded by a Logic “0”. If the
function bit is Logic “1” the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The two permissible bus protocols with five bytes are
shown in Figure 2.
Figure 2. Definition of Bytes
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
CO_Information
T
T
T
T
T
T
9
T
8
ACK
ACK
1
14
13
12
11
10
BA_Band Information
X
X
X
X
B
B
B
1
B
0
3
2
FM_Frequency Information
FL_Frequency Information
N
N
N
N
N
N
N
N
N
ACK
ACK
0
14
13
12
11
10
9
1
8
0
N
N
N
N
N
N
2
7
6
5
4
3
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
FM_Frequency Information
FL_Frequency Information
N
T
N
N
T
N
N
N
9
N
N
ACK
ACK
0
14
13
12
11
10
8
0
N
N
N
N
N
N
N
7
6
5
4
3
2
1
CO_Information
T
T
11
T
10
T
9
T
8
ACK
ACK
1
14
X
13
X
12
X
BA_Band Information
X
B
B
B
1
B
0
3
2
Chip Address
Bit T : Controls the Output of the Operational Amplifier
8
The chip address is programmable by Pin 16 (AS –
Address Select).
T
8
= 0
Normal Operation
Operational Amplifier Active
T
= 1
Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through 20 k Internal Pull–Up
Resistor
8
AS – Pin 16
Gnd to 0.1 V
Address (HEX.)
C0
C2
C4
C6
CC1
to 0.3 V
Open or 0.2 V
Bits T , T : Control the Phase Comparator
12
CC1
CC1
9
0.4 V
CC1
to 0.7 V
T
T
12
Function
CC1
CC1
9
0.8 V
CC1
to 1.1 V
1
0
1
0
1
Normal Operation
High Impedance
Upper Source “On” Only
Lower Source “On” Only
1
0
0
Bits B , B , B , B : Control the Band Buffers
0
1
2
3
Bits T , T : Control the Reference Ratio
10 11
B , B , B , B = 0
Buffer “Off”
Buffer “On”
0
1
2
3
B , B , B , B = 1
0
1
2
3
T
10
T
11
Division Ratio
Figure 3. Equivalent Circuit of the Integrated
Band Buffers
0
0
1
1
0
1
0
1
512
1024
1024
512
V
12 V
CC3
25 V
Protection
Bit T : Switches the Internal Signals F
13 ref
and F
to
BY2
Bit T : the Band Buffer Outputs (Test)
13
I
B
I
SUB
Gnd
T
13
T
13
= 0
= 1
Normal Operation
Test Mode
“On”/“Off”
30 mA (40 mA
at 0 to 80°C)
F
F
Output at B (Pin 12)
2
ref
Out
Output at B (Pin 13)
BY2
3
B
…B
0
3
Bits B and B have to be “On”, B = B = 1 in the test mode.
NOTE:
I
I
I
+ I
= 8.0 mA Typical, 13 mA Max
= Base Current
= Substrate Current of PNP
2
3
2
3
B
B
SUB
SUB
F
F
is the reference frequency.
ref
is the output frequency of the programmable divider, divided by two.
BY2
4
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Bit T : Controls the Charge Pump Current of the
14
Lock Detector
Bit T : Phase Comparator
The lock detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
14
T
14
T
13
= 0
= 1
Pump Current 15 µA Typical
Pump Current 50 µA Typical
The Programmable Divider
Figure 4. Equivalent Circuit of the Lock Output
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
V
5.0 V
CC1
200
µ
A Typical
2.0 k
Lock
100 k
25 V Protection
The division ratio definition is given by:
N = 16384 x N + 8192 x N + … + 4 x N + 2 x N + N
Maximum Ratio 32767
14
13
2
1
0
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
Minimum Ratio 17
N
… N are the different bits for frequency information.
0
14
At power “on” the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
needs 28.5 V supply (V
guaranteed maximum tuning voltage of 28 V.
as minimum voltage for a
CC2)
Figure NO TAG shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Oscillator
The Phase Comparator
The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
Figure 5. Typical Tuner Application
IF
External Switching
UHF
VHF
B III
13
12
11
10
14 12 V
5.0 V
V
B
B
B
B
0
CC3
7
8
3
2
1
Antenna
Filter
Mixer
2
1
16
SCL
SDA
AS
Bus
Rec
B. P. Filter
MC44818
1.0 nF
3
Osc &
Ref Div
÷8
Program
Divider
Pres
12 pF
F
osc
3.2/4.0 MHz
Phase
Comp
Gnd
9
2.7 V
4
Oscillator
6
5
15
Lock
(Note 1)
47 nF
V
TUN
47 k
AGC
330 p
(Note 2)
NOTES: 1. On some layouts the 100 Ω resistor will not be required.
2. C = 330 pF minimum is required for stability.
2
33 V
22 nF
5
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Figure 6. HF Sensitivity Test Circuit
Bus
Bus Controller
V
CC3
1
2
14
MC44818
V
7
CC1
HF
8
Gnd
9
B
10
B
11
B
12
B
3
0
1
2
13
HF Generator
HF Out Gnd
1.0 nF
Frequency
Counter
50
Ω Cable
4.7 k
4.7 k
390 Ω
In
390
Ω
50
Ω
Device is in test mode. B , B are “On” and B , B are “Off”.
2
3
0
1
Sensitivity is level of HF generator on 50 Ω load (without Pin 8 loading).
HF CHARACTERISTICS (See Figure NO TAG)
Characteristic
Pin
Min
Typ
Max
Unit
V
DC Bias
8
–
1.6
–
Input Voltage Range
80–150 MHz
150–600 MHz
600–950 MHz
950–1300 MHz
mVrms
8
8
8
8
10
5.0
10
50
–
–
–
–
315
315
315
315
Figure 7. Typical HF Input Impedance
–j
+j
0
0.5
0.5
0.5
Z
= 50 Ω
O
1.3 GHz
1
2
1
1
1.0 GHz
2
2
500 MHz
50 MHz
6
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Figure 8. Pin Circuit Schematic
V
V
CC1
CC1
132 k
96 k
150 k
50 k
500
50
1/2 V
SDA 1
16 AS
CC1
Data input
(I C bus)
Address Select
(I C bus)
2
2
20 V
20 V
96 k
ACK
V
V
CC1
CC1
132 k
96 k
2.0 k
20 V
500
1/2 V
SCL 2
Clock input (supplied
by a microprocessor
15 LOCK
Lock detector output
CC1
20 V
96 k
2
100 k
via I C bus)
14 V
CC3
Positive supply for integrated
band buffers (12 V)
20 V
100
XTAL 3
Crystal oscillator
(3.2 MHz or 4.0 MHz)
5.0 V
20 V
13 B
3
“On”/“Off”
“On”/“Off”
“On”/“Off”
“On”/“Off”
10 k
2.0 k
20 V
AMP IN 4
Negative input of
operation amplifier and
charge pump output
20 V
20 V
20 V
12 B
2
20 k
Band buffer outputs
can drive up to 30 mA
(40 mA at 0° to 80°C)
100
V
5
TUN
Operational amplifier
output which provides
the tuning voltage
20 V
20 V
11 B
1
V
6
CC2
20 V
20 V
Operational amplifier
positive supply (33 V)
V
7
CC1
Positive supply of
the circuit (5.0 V)
5.0 V
5.0 V
10 B
0
18 k
2.0 k
1.2
…
1.8 V
HF IN 8
HF input from
local oscillator
2.0 k
9 GND
Circuit Ground
7
MOTOROLA ANALOG IC DEVICE DATA
MC44818
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SO–16)
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T–
0.19
0.10
0.25
0.25
0.009
0.009
J
SEATING
PLANE
M
K
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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MC44818/D
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