MC44827 [MOTOROLA]
LOW-POWER PLL TUNING CIRCUIT; 低功耗的PLL调谐电路
| 型号： | MC44827 |
| 厂家： | 
MOTOROLA |
| 描述： | LOW-POWER PLL TUNING CIRCUIT |
| 文件： | 总8页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44827/D
The MC44827/27B are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
The MC44827 has programmable 512/1024 reference divider while the
MC44827B has a fixed reference divider of 1024.
LOW–POWER
PLL TUNING CIRCUIT
The MC44827/27B offer the same features as MC44817/17B but has
improved sensitivity performance and reduced power dissipation. The low
frequency preamplifier has been removed and the operational amplifier
pull–up resistor has been increased to 60 kΩ.
FOR 3–WIRE BUS WITH
1.3 GHz PRESCALER
SEMICONDUCTOR
TECHNICAL DATA
The MC44827/27B are controlled via a 3–wire bus. The MC44827/27B
2
have the same functions as the MC44828 which is I C bus controlled. The
MC44827/27B and the MC44828 can be exchanged to allow conversion
2
between 3–wire bus and I C bus control.
The MC44827/27B are manufactured on a single silicon chip using
Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self
Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (3–Wire Bus). Data and
16
2
Clock Inputs are I C Bus Compatible
• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• 3–State Phase/Frequency Comparator
1
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
• Four Integrated PNP Band Buffers can drive up to 40 mA
(TSSOP–16)
(V
to 14.4 V)
CC1
• Output Options for the Reference Frequency and the
Programmable Divider
• Bus Protocol for 18 or 19 Bit Transmission
• Extra 34–Bit Protocol for Test and Further Features
• High Sensitivity Preamplifier
PIN CONNECTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
• Lower Power Consumption, 200 mW Typical
DA
CL
EN
Lock
V
• Improved Prescaler with Higher Margins for Sensitivity and
Temperature Range
• Lock Detector with Push–Pull Output
• Space–Saving TSSOP Package
• ESD Protected to MIL–STD–883C, Method 3015.7 (1.5 kΩ,100 pF)
XTAL
Amp In
12 V
CC3
B3
B2
MOSAIC is a trademark of Motorola, Inc.
V
TUN
V
33 V
B1
B0
CC2
V
5.0 V
CC1
ORDERING INFORMATION
Operating
HF In
Gnd
Device
MC44827DTB
MC44827BDTB
Package
Temperature Range
(Top View)
T
= –20° to +80°C
TSSOP–16
A
Motorola, Inc. 1998
Rev 1
MC44827/27B
Figure 1. Representative Block Diagram
V
TUN
V
5.0 V
V
12 V
14
V
CC1
7
CC3
CC2 33 V
6
13 12 11 10
5
12 V
60 k (1)
4
F
out
B3 B2 B1 B0
Buffers
Amp In
Test
Logic
V
ref
F
ref
Operational
Amplifier
Latches
DTB1
9
T4
T0
… T2
Phase
Comp
Gnd
15
T5
Lock
P–On
Reset
DTB2
POR
Latches
6
F
out
F
ref
16
512/1024
B = 1024 Only
4
CL
EN
1
Shift Register
15 Bit
3–Wire Bus
Receiver
Data
DA
2
Ref
Divider
15
RL
CL
DTF
Latches A
3
Osc
XTAL
Latches B
TDI
Preamp 1
8
÷
8
Program Divider
15 Bit
Latch Control
DTS, EN
Prescaler
F
HF In
out
This device contains 3,204 active transistors.
NOTE: 1. This part may be used with an external pull–up resistor of 20 kΩ to remain compatible with MC44817/17B
designed tuners. Pin 6 is left open. The internal pull–up can also be used with an external resistor in parallel.
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Rating
Pin
Value
6.0
Unit
V
Power Supply Voltage (V
Band Buffer “Off” Voltage
Band Buffer “On” Current
)
7
CC1
10–13
14.4
50
V
10–13
mA
–
Band Buffer Pin Shorted to Ground or V
CC3
(Short Circuit Duration) (Note 1)
10–13
Continuous
40
Operational Amplifier Power Supply Voltage (V
)
6
V
CC2
Operational Amplifier Pin Shorted to Ground or V
(Short Circuit Duration)
5
Continuous
14.4
–
CC2
Power Supply Voltage (V
Storage Temperature
)
14
V
CC3
–
–65 to +150
–20 to +80
10
°C
°C
s
Operating Temperature Range
–
Band Buffer Operation (Note 2) at 50 mA each Buffer All Buffers “On” Simultaneously
Operational Amplifier Output Voltage
10–13
5
8
V
CC2
1.5
V
RF Input Level (80 MHz to 1.3 GHz)
Vrms
NOTES: 1. At V
= V
= V
to 14.4 V and T = –20° to +80°C one buffer “On” only.
CC3
CC3
CC1
CC1
A
2. At V
to 14.4 V and T = –20° to +80°C.
A
3. ESD data available upon request.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
ELECTRICAL CHARACTERISTICS (Parameter Type: A–100% Tested, B–100% Correlation Tested, C–Characterized on Samples,
D–Design Parameter. V
= 5.0 V; V
= 33 V; V
= 12 V; T = 25°C, unless otherwise noted.)
CC1
CC2
Characteristic
CC3 A
Pin
7
Min
4.5
25
Typ
5.0
32
Max
5.5
37
Unit
V
Type
A
V
CC1
V
CC2
V
CC3
V
CC1
V
CC2
V
CC3
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
6
V
A
14
7
V
CC1
–
12
14.4
30
V
A
Supply Current (V
= 5.0 V; V
= 12 V) One Buffer “On”
= 15 V
23
mA
mA
mA
A
CC1
CC3
Supply Current (Output Open) V
6
–
0.3
1.0
A
TUN
Supply Current
14
A
All Buffers “Off”
One Buffer “On” when Open
One Buffer “On” at 40 mA
–
–
–
0.15
6.5
46.5
0.3
8.0
50
Band Buffer Leakage Current when “Off” at 12 V
Band Buffer Saturation Voltage when “On” at 30 mA
Band Buffer Saturation Voltage when “On” at 40 mA
Data/Clock/Enable Current at 0 V
10–13
–
–
0.01
0.15
0.2
–
1.0
0.3
0.5
0
µA
V
A
B
A
A
A
A
A
D
D
A
A
B
C
A
B
A
A
A
10–13
10–13
–
V
1, 2, 16
–10
0
µA
µA
V
Data/Clock/Enable Current at 5.0 V
Data/Clock/Enable Input Voltage Low
Data/Clock/Enable Input Voltage High
Clock Frequency Range
1, 2, 16
–
1.0
1.5
–
1, 2, 16
–
–
1, 2, 16
3.0
–
–
V
2
3
–
4
–
–
5
5
4
4
4
–
100
4.05
3.5
15
–
kHz
MHz
V
Oscillator Frequency Range
3.15
1.8
–15
100
0.3
–
3.2
2.75
0
Operational Amplifier Internal Reference Voltage
Operational Amplifier Input Current
DC Open Loop Gain
nA
–
250
–
Gain Bandwidth Product (CL = 1.0 nF)
–
MHz
mV
V
V
out
Low, Sinking 50 µA (Note 1)
80
0.2
0
200
0.5
15
85
30
V
High, Sourcing 3.0 µA, V
– V
CC2 out
–
out
Phase Comparator 3–State Current
–15
30
10
nA
µA
µA
Charge Pump High Current of Phase Comparator
Charge Pump Low Current of Phase Comparator
NOTE: 1. Using the internal 60 kΩ pull–up resistor only.
50
15
Figure 3. Typical Prescaler Input Sensitivity
Figure 2. HF (Prescaler Input) Sensitivity Test Circuit
40
20
0
Bus
V
CC3
Bus Controller
16
1
2
14
Guaranteed Operating Area
MC44827/27B
V
7
CC1
HF
8
Gnd
9
B0
10
B1
11
B2
12
B3
13
–20
–40
HF Generator
HF Out Gnd
1.0 nF
3.9 k
3.9 k 3.9 k
Counter
In
–60
0
50
Ω
Cable
50
Ω
3.9 k
600
RF In (MHz)
200
400
800
1000
1200
1400
NOTES: 1. Device is in test mode. B2, B3 are “On” and B0, B1 are “Off”.
2. Sensitivity is level of HF generator on 50 Ω load.
3
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (V
CC1
= 5.0 V, T = 25°C.) (See Figure 2.)
A
Frequency Range
Pin
Min
Typ
1.6
–
Max
Unit
V
Type
A
DC Bias
80–150 MHz
8
–
–
8
10
5.0
10
50
315
315
315
315
mVrms
mVrms
mVrms
mVrms
C
150–600 MHz
600–950 MHz
950–1300 MHz
8
–
C
8
–
C
8
–
C
Figure 4. Pin Circuit Schematic
V
V
CC1
CC1
132 k
96 k
96 k
132 k
500
500
1/2 V
1/2 V
DA 1
Data input
16 EN
Enable input
CC1
CC1
(3–wire bus)
(3–wire bus)
20 V
20 V
96 k
96 k
V
V
CC1
CC1
132 k
96 k
500
2.0 k
1/2 V
96 k
CL 2
15 Lock
Lock detector output
CC1
Clock input (supplied
by a microprocessor
via 3–wire bus)
20 V
20 V
100 k
5.0 k
14 V
CC3
Positive supply for integrated
band buffers (12 V)
20 V
100
XTAL 3
Crystal oscillator
(3.2 MHz or 4.0 MHz)
5.0 V
20 V
13 B3
“On”/“Off”
2.0 k
20 V
10 k
20 V
AMP In 4
Negative input of
operation amplifier and
phase comparator output
20 V
20 V
20 V
12 B2
“On”/“Off”
“On”/“Off”
“On”/“Off”
60 k
Band buffer outputs
can drive up to 30 mA
(40 mA at 0° to 80°C)
100
V
5
TUN
Operational amplifier
output which provides
the tuning voltage
20 V
20 V
11 B1
V
6
CC2
20 V
20 V
Operational amplifier
positive supply (33 V)
V
7
CC1
Positive supply of
5.0 V
5.0 V
10 B0
9 Gnd
the circuit (5.0 V)
18 k
2.0 k
1.2
… 1.8 V
HF In 8
Input to
prescaler
2.0 k
Circuit Ground
4
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
PIN FUNCTION DESCRIPTION
Pin
Symbol
DA
Description
1
3–wire bus data input
2
CL
3–wire bus clock input
3
XTAL
Amp In
Crystal oscillator (3.2 MHz or 4 MHz)
4
Negative operational amplifier input and phase comparator output
Operational amplifier output which provides the tuning voltage
Operational amplifier positive supply (33 V)
Positive supply of the circuit (5 V)
Asymmetrical HF input
5
V
TUN
V
CC2
V
CC1
6
7
8
HF In
Gnd
9
Ground
10,11,12,13
B
0
to B
PNP Band buffer outputs
3
14
15
16
V
Positive supply for integrated band buffers (12 V)
Lock detector output
CC3
Lock
EN
3–wire bus enable input
Data Format and Bus Receiver
reset. The reset pulse is generated only if EN goes negative
after the 18th clock pulse (signal RL).
The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the I C–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
34 Bit Data Transmission
(For Test and Additional Features)
2
In the test mode, the programmable divider receives a 15
bit byte and the data is transferred to latches A on the
negative edge of clock pulse 19 (signal DTF). The
information for test is received on clock pulses 20 to 26 and
transmitted to the latches on the negative edge of pulse 34
(signal DTB2). These latches have a power–on reset. The
power–on reset sets the programmable divider to a counting
ratio of 256 or higher and resets the corresponding latches to
the test bits T0 to T6 (signal POR). The bus receiver is not
disturbed if the data format is wrong. Unused bits are
ignored. If for example the Enable signal goes low after clock
pulse 9, bits one to four are accepted as valid buffer
information and the other bits are ignored. If more than 34
bits are received, bit 35 and the following are ignored.
18 and 19 Bit Data Transmission
The programmable divider may receive a division ratio
coded by a 14 bit (18 bit transmission) or 15 bit (19 bit
transmission). The data is transmitted to the programmable
divider (latches A) on the negative going edge of clock pulse
19 or on the negative edge of the EN–signal if EN goes down
after the 18th clock pulse (signal DTF). If the programmable
divider receives a 14 bit byte, its MSB (bit N14) is internally
Figure 5. Bus Timing Diagram
Standard Bus Protocol 18 or 19 Bit
Data
1
4
5
18 19
Clock
Buffers
Counting Ratio
Enable
Bus Protocol for Test and Features
19 20
1
4
5
26 27
33 34
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 T6 T5 T4 T3 T2 T1 T0 X7 X6 X5 X4 X3 X2 X1 X0
Buffers
Counting Ratio
Test & Features
Not Used
5
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
Definition of Permissible Bus Protocols
Figure 6. Equivalent Circuit of the Integrated
Band Buffers
1. Bus Protocol for 18 Bit
V
12 V
CC3
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3
N2 N1 N0
Max Counting Ratio 16363
N14 is Reset Internally
20
…25 V
Protection
Saturation Voltage
0.15 V Typical
0.3 V Max
I
B
Gnd
I
SUB
2. Bus Protocol for 19 Bit
“On”/“Off”
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4
N3 N2 N1 N0
Max Counting Ratio 32767
30 mA (40 mA
at 0 to 80 C)
°
Out
B0 B3
…
NOTES:
I
I
I
+ I
= 5.5 mA Typical
= Base Current
= Substrate Current of PNP
B
B
SUB
B0 to B3: Control of Band Buffers
N0 to N14: Programmable Divider Counting Ratio
SUB
N14 = MSB; N = LSB
0
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
Bit T5: Defines the Division Ratio of the Reference
Bit T : Divider
5
N0 = Last Shifted Bit
T5 = 0
= 1
Division Ratio 512
Division Ratio 1024
T
5
3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 B0 N14…N0 Y6 T5 T4 Y3 T2 T1 T0 X7
X6…X1 X0
NOTE: The division ratio of the reference divider can only be
programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 is fixed.
T0 to T2: Control the Phase Comparator (Note 1)
T4: Switches Test Signals to the Buffer Outputs
T5: Division Ratio of the Reference Divider
B Version T5 = “X”
– X0 to X7: Are Random
OPERATING DESCRIPTION
Introduction
A representative block diagram and typical system
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
– Y3 and Y6: Are Not Used
B3 = First Shifted Bit
X0 = Last Shifted Bit
The Programmable Divider
Definition of the Bits for Test and Features
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
Bit T0: Defines the Charge Pump Current of the
Bit T : Phase Comparator
0
T0 = 0
= 1
Pump Current 50 µA Typical
Pump Current 15 µA Typical
T
0
Bits T1 and T2: Define the Digital Function of the Phase
Bits T and T : Comparator
1
2
N = 16384 x N14 + 8132 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
T2 T1 State
Output Function of Phase Comparator
Normal Operation
0
0
1
1
0
1
0
1
1
2
3
4
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
N0 … N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
High Impedance (3–State)
Upper Source “On”, Lower Source “Off”
Lower Source “On”, Upper Source “Off”
NOTE: 1. The phase comparator pulls high if the input frequency is too
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse. This guarantees operation in the linear region.
The Prescaler
The divide by 8 prescaler has a preamplifier which
guarantees high input sensitivity.
The offset pulse is a positive current pulse (upper source).
The Phase Comparator
Bit T4: Switches the Internal Frequencies F
and
ref
The phase comparator is both phase and frequency
sensitive and has very low output leakage current in the high
impedance state.
Bit T : FBY2 to the Buffer Outputs (B2, B3)
4
T4 = 0
= 1
Normal Operation
F Switched to Buffer Output B2
T
4
ref
FBY2 Switched to Buffer Output B3
Lock Detector
The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
NOTE: Bits B2 and B3 have to be one in this case.
is the reference frequency.
F
ref
FBY2 is the output frequency of the programmable divider,
divided by two.
6
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
Figure 7. Equivalent Circuit of the Lock Output
The Oscillator
The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground
in series with a capacitor. The crystal operates in the series
resonance mode.
V
5.0 V
CC1
200
µA Typical
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
2.0 k
Lock
Power Dissipation
100 k
“On”/“Off”
25 V Protection
The typical power dissipation of the circuit is about
5.0 k
200 mW (V
= 15 V with internal pull–up of 60 kΩ, one
TUN
buffer “On” at 30 mA). It is calculated with the following
formula:
“Off”/“On”
V
– V
CC2
60 kΩ
TUN
PD
V
x I
x V
CC1
x I
CC1
CC2
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
V
V
x I
CC3
CC3
sat(buffer)
out(buffer)
needs 28.5 V supply (V
guaranteed maximum tuning voltage of 28 V.
Figure 8 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
as minimum voltage for a
32 – 15
60
CC2)
(
)
(
)
12 x 6.5
Example: 5 x 23
x 32
206.5
(
)
0.15 x 30
Figure 8. Typical Tuner Application
IF
External Switching
14 12 V
UHF
VHF
B III
13
B3
12
B2
11
10
5.0 V
V
B1 B0
CC3
7
8
Antenna
Filter
Mixer
2
1
16
CL
DA
EN
Bus
Rec
B. P. Filter
MC44827/27B
1.0 nF
÷
Pres
8
3
Program
Divider
Osc &
Ref Div
12 pF
F
osc
3.2/4.0 MHz
Phase
Comp
Gnd
9
V
ref
Oscillator
6
5
4
15
Lock
V
TUN
120 k
AGC
18 nF
330 p
(Note 1)
33 V
8.2 nF
NOTE: 1. 330 pF minimum is required for stability.
7
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
OUTLINE DIMENSIONS
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F–01
(TSSOP–16)
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
S
0.15 (0.006) T
U
K
K1
NOTES:
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2
3
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
–U–
SECTION N–N
L
J
4
5
PIN 1
IDENT.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
6
7
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
–V–
N
F
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
0.193
0.169
–––
0.002
0.020
DETAIL E
–W–
C
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
–T–
D
G
K1
L
6.40 BSC
0.252 BSC
M
0
8
0
8
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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