MC44824D [MOTOROLA]
TV AND VCR PLL TUNING CIRCUITS WITH 1.3 GHz PRESCALER AND I2C BUS; 1.3 GHz的预分频器和I2C总线的电视机和VCR PLL调谐电路
| 型号： | MC44824D |
| 厂家： | 
MOTOROLA |
| 描述： | TV AND VCR PLL TUNING CIRCUITS WITH 1.3 GHz PRESCALER AND I2C BUS |
| 文件： | 总8页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44824/D
TV AND VCR
PLL TUNING CIRCUITS
WITH 1.3 GHz PRESCALER
The MC44824/25 are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
2
AND I C BUS
The MC44824/25 are manufactured on a single silicon chip using
Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self
Aligned Implanted Circuits).
14
1
2
• Complete Single Chip System for MPU Control (I C Bus). Data and
D SUFFIX
PLASTIC PACKAGE
CASE 751A
Clock Inputs are 3–Wire Bus Compatible
• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider
(SO–14)
• Reference Divider: Programmable for Division Ratios 512 and 1024
• 3–State Phase/Frequency Comparator
• 4 Programmable Chip Addresses
16
• 3 Output Buffers (MC44824) respectively 5 Output Buffers (MC44825)
1
for 10 mA/15 V
D SUFFIX
PLASTIC PACKAGE
CASE 751B
• Operational Amplifier for use with External NPN Transistor
• SO–14 Package for MC44824 and SO–16 for MC44825
• High Sensitivity Preamplifier
(SO–16)
• Fully ESD Protected
PIN CONNECTIONS
MC44824
MOSAIC is a trademark of Motorola, Inc.
1
2
3
4
5
6
7
14
13
12
11
10
9
PD
XTAL1
XTAL2
SDA
UD
GND
HF2
HF1
SCL
V
B
CC
1
B
7
8
CA
B
2
(Top View)
MC44825
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PD
XTAL1
XTAL2
SDA
UD
GND
HF2
HF1
ORDERING INFORMATION
Operating
Device
MC44824D
MC44825D
Package
SO–14
SCL
V
Temperature Range
CC
B
7
B
0
T
A
= –20° to +80°C
B
B
4
1
2
SO–16
CA
B
(Top View)
Motorola, Inc. 1996
Rev 1
MC44824/25
Representative Block Diagram
V
UD
14
CC
5.0 V 10
(12)
6
(6)
8
(9)
9
(10)
(7)
(11)
(16)
1 (1)
F
out
B
B
B
B
B
0
PD
7
4
2
1
Test
Logic
2.7 V
Operational
Amplifier
Buffers
F
ref
Latches
DTB1
13 (15)
T
8
Gnd
Phase
Comp
T , T , T
12 14
9
T
13
T
, T
10 11
DTB2
P–On
Reset
Latches
7
F
F
ref
out
POR
CL
512/1024
7 (8)
4
CA
SDA
SCL
4 (4)
5 (5)
2
Shift Register
15 Bit
I C Bus
Receiver
Data
RL
Ref
Divider
DTF
Latches A
Latches B
2 (2)
3 (3)
XTAL1
XTAL2
3.2 or 4.0
MHz Osc
Gnd
TDI
Preamp
11 (13)
12 (14)
÷
8
HF Input1
HF Input2
Program Divider
15 Bit
Latch Control
DTS, EN
Prescaler
F
out
MC44825 Pin Numbers ( )
This device contains 3,204 active transistors.
PIN FUNCTION DESCRIPTION
Pin
MC44824
MC44825
Symbol
Description
1
1
PD
XTAL1
Input of tuning voltage amplifier
2
2
First crystal input is the active pin at the oscillators
Second crystal input is the internal ground
Data input
3
4
3
XTAL2
SDA
4
2
5
5
SCL
Clock input of the I C bus
6, 8, 9
–
–
B , B , B
1
Band buffer (open collector) outputs for up to 10 mA
Band buffer (open collector) outputs for up to 10 mA
Chip address selection pin
7
2
6, 7, 9, 10, 11
B , B , B , B , B
7
4
2
1
0
7
8
12
CA
10
V
CC
Supply voltage, typical 5.0 V
11, 12
13
13, 14
15
HF1/HF2
GND
Symmetric HF inputs from local oscillator
Ground
14
16
UD
Output of the tuning voltage amplifier. Needs an external NPN with pull–up
resistor to drive the varicaps
2
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Pin
Rating
MC44824
MC44825
Value
Unit
Power Supply Voltage
10
12
6.0
V
(V
CC
)
Band Buffer “Off” Voltage
Band Buffer “On” Current
Storage Temperature
6, 8, 9
6, 7, 9, 10, 11
15
V
6, 8, 9
6, 7, 9, 10, 11
15
mA
°C
°C
–
–
–
–
–65 to +150
–20 to +80
Operating Temperature
Range
RF Input Level (10 MHz
to 1.3 GHz)
11, 12
13, 14
1.5
Vrms
ELECTRICAL CHARACTERISTICS (V
= 5.0 V, T = 25°C, unless otherwise noted.)
CC
A
Pin
MC44824
MC44825
Characteristic
Min
4.5
–
Typ
5.0
40
0.01
1.6
–
Max
5.5
55
Unit
V
V
V
Supply Voltage Range
10
10
12
CC
Supply Current (V
= 5.0 V)
12
mA
µA
V
CC
CC
Band Buffer Leakage Current when “Off” at 12 V
Band Buffer Saturation Voltage when “On” at 10 mA
Data Saturation Voltage at 15 mA Acknowledge “On”
Data/Clock/Enable Current at 0 V
6, 8, 9
6, 8, 9
4
6, 7, 9, 10, 11
–
1.0
1.8
1.0
0
6, 7, 9, 10, 11
–
4
4, 5
4, 5
4, 5
4, 5
5
–
V
4, 5
4, 5
4, 5
4, 5
5
–10
0
–
µA
µA
V
Data/Clock/Enable Current at 5.0 V
–
1.0
1.5
–
Data/Clock/Enable Input Voltage Low
Data/Clock/Enable Input Voltage High
Clock Frequency Range
–
–
3.0
–
–
V
–
100
4.05
15
kHz
MHz
nA
nA
µA
µA
Oscillator Frequency Range
2, 3
1
2, 3
1
3.15
–15
–15
30
100
3.2
0
Operational Amplifier Input Current
Phase Detector Current in High Impedance State
1
1
0
15
Charge Pump Current of Phase Comparator, T = 0
14
1
1
40
125
60
Charge Pump Current of Phase Comparator, T = 1
14
1
1
200
HF CHARACTERISTICS (See Figure NO TAG)
Pin
MC44824
MC44825
Characteristic
Min
Typ
Max
Unit
V
DC Bias
11, 12
13, 14
–
1.6
–
Input Voltage Range
80–150 MHz
150–600 MHz
600–950 MHz
950–1300 MHz
mVrms
11, 12
11, 12
11, 12
11, 12
13, 14
13, 14
13, 14
13, 14
10
5.0
10
50
–
–
–
–
315
315
315
315
3
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 1. HF Sensitivity Test Circuit
2
I C Bus
Bus Controller
V
CC
SDA, SCL
5.0 V
V
CC
MC44824/25
HF
1.0 nF
HF
Gnd
B
B
2
7
HF Generator
HF Out Gnd
Frequency
Counter
In
1.0 nF
50
Ω Cable
470
470
V
CC
50
Ω
Device is in test mode. B and B are “On”.
2
7
Sensitivity is level of HF generator on 50 Ω load.
Figure 2. Typical HF Input Impedance
–j
+j
0
0.5
0.5
0.5
Z
= 50 Ω
O
1.3 GHz
1
2
1
1
1.0 GHz
2
2
500 MHz
50 MHz
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the I C bus. The incoming information, consisting of a
4_STA CA FM FL CO BA STO
STA = Start Condition
2
chip address byte followed by two or four data bytes, is
treated in the I C bus receiver. The definition of the
STO = Stop Condition
CA = Chip Address Byte
2
permissible bus protocol is shown below:
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information (MSB’s)
FL = Data Byte for Frequency Information (LSB’s)
1_STA CA CO BA STO
2_STA CA FM FL STO
3_STA CA CO BA FM FL STO
4
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 3. Complete Data Transfer Process
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
P
STA
ADDRESS
CA
R/W
ACK
DATA
ACK
DATA
ACK
STO
Figure 4 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third data byte
is ignored.
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceded by a Logic “0”. If the
function bit is Logic “1” the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
If five or more data bytes are received, the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The two permissible bus protocols with five bytes are
shown in Figure 4.
Figure 4. Definition of Bytes
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
CO_Information
T
T
T
T
T
T
9
T
8
ACK
ACK
1
14
13
12
11
10
BA_Band Information
B
7
X
X
B *
4
X
B
B
1
B *
0
2
FM_Frequency Information
FL_Frequency Information
N
N
N
N
N
N
N
N
8
ACK
ACK
0
14
13
12
11
10
9
1
N
N
N
N
N
N
N
7
6
5
4
3
2
0
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
FM_Frequency Information
FL_Frequency Information
N
N
N
N
N
N
9
N
N
ACK
ACK
0
14
13
12
11
10
8
0
N
N
N
N
N
N
N
7
6
5
4
3
2
1
CO_Information
T
T
T
T
T
T
T
ACK
ACK
1
14
X
13
X
12
11
X
10
9
8
BA_Band Information
B
7
B *
B
B
B *
0
4
2
1
* B and B are only available on MC44825. On MC44824 this data is random.
0
4
Chip Address
Bit T : Controls the Output of the Operational Amplifier
8
The chip address is programmable by Pin 7 (8), CA.
T
= 0
Normal Operation
Operational Amplifier Active
8
CA – Pin 7 (8)
Gnd to 0.1 V
Address (HEX.)
T
8
= 1
Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through an External Pull–Up
Resistor
C0
C2
C4
C6
CC1
to 0.3 V
Open or 0.2 V
CC1
CC1
Bits T , T : Control the Phase Comparator
12
9
0.4 V
0.8 V
to 0.7 V
CC1
CC1
CC1
CC1
T
T
12
Function
9
to 1.1 V
1
0
1
0
1
Normal Operation
High Impedance
Upper Source “On” Only
Lower Source “On” Only
Bits B , B , B , B , B : Control the Band Buffers
0
1
2
4
7
1
0
0
B , B , B , B , B = 0
Buffer “Off”
Buffer “On”
0
0
1
1
2
2
4
4
7
7
B , B , B , B , B = 1
5
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Bits T , T : Control the Reference Ratio
10 11
The division ratio definition is given by:
N = 16384 x N + 8192 x N + … + 4 x N + 2 x N + N
14
13
2
1
0
T
10
T
11
Division Ratio
Maximum Ratio 32767
0
0
1
1
0
1
0
1
512
Minimum Ratio 17
1024
1024
512
Where N … N
information.
are the different bits for frequency
0
14
The counter may be used for any ratio between 17 and
32767 and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the I C bus.
Bit T : Switches the Internal Signals F
13 ref
and F
to
BY2
Bit T : the Band Buffer Outputs (Test)
13
T
13
T
13
= 0
= 1
Normal Operation
Test Mode
2
At power–on, the whole bus receiver is reset and the
programmable divider is set to a counting ration of N = 256 or
higher.
F
F
Output at B
7
BY2
ref
Output at B
2
2
The first I C message must be sent only when the
Bits B and B have to be “Off”, B = B = 0 in the test mode.
2
7
2
7
F
F
is the reference frequency.
POWER ON RESET is completed.
ref
is the output frequency of the programmable divider, divided by two.
BY2
The Prescaler
Bit T : Controls the Charge Pump Current of the
14
The prescaler has a preamplifier which guarantees high
input sensitivity.
Bit T : Phase Comparator
14
The Phase Comparator
T
T
= 0
= 1
Pump Current 40 µA Typical
Pump Current 125 µA Typical
14
13
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Band Buffers
The Tuning Voltage Amplifier
BA_Band Information
MC44824 14 Pin version
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external NPN with a pull–up resistor to generate the tuning
voltage.
The amplifier can be switched “Off” through bit T . When
bit T is “One”, the amplifier is “Off”. The tuning voltage is
8
B
X
X
X
X
X
B
B
B
B
X
B
ACK
ACK
7
2
1
MC44825 16 Pin version
8
B
X
X
B
4
7
2
1
0
The band buffers are open collector buffers and are active
“low” at Bn = 1. They are designed for 10 mA with a typical
“On” resistance of 160 Ω. These buffers are designed to
withstand relative high output voltage in the “Off” state.
B and B buffers may also be used to output internal IC
then pulled high by the external pull–up resistor.
Figure 5 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 5 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
2
7
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit B and/or B have to be zero if the buffers are used
for these additional functions.
2
7
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground “or
between Pins 2 and 3” through a series capacitor. The crystal
oscillates in its series resonance mode.
The voltage at Pin 13 XTAL1, has low amplitude and low
harmonic distortion.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division
ratio out of the latches B. Latches B are loaded from latches
A by means of signal TDI which is synchronous to the
programmable divider output signal.
Pin XTAL2 is the internal ground of the oscillator; it is
connected internally to ground Pin 13 (15).
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
6
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 5. Typical Tuner Applications
UHF
VHF
B III
6
8
9
IF
5.0 V
10
B
B
B
1
7
2
Antenna
Filter
Mixer
5
4
7
SCL
SDA
CA
Bus
Rec
B. P. Filter
MC44824
1.0 nF
12
2
Osc &
Ref Div
÷
Pres
8
Program
Divider
11
12 pF
F
osc
3.2/4.0 MHz
1.0 nF
Phase
Comp
3
Gnd
13
2.7 V
1
Oscillator
16
33 V
22 k
AGC
V
TUN
47 k
47 nF
330 p
(See Note)
22 nF
External Switching
6
UHF
VHF
B III
7
9
10
11
IF
5.0 V
B
4
B
B
1
B
B
7
12
2
0
Antenna
Filter
Mixer
5
4
8
SCL
SDA
CA
Bus
Rec
B. P. Filter
MC44825
1.0 nF
14
13
2
3
Osc &
Ref Div
÷8
Program
Divider
Pres
12 pF
F
osc
3.2/4.0 MHz
1.0 nF
Phase
Comp
Gnd
15
2.7 V
1
Oscillator
16
33 V
22 k
AGC
V
TUN
47 k
47 nF
330 p
(See Note)
22 nF
NOTE:
C = 330 pF minimum is required for stability.
2
7
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE F
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SO–16)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
ISSUE J
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
16
9
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–B–
P 8 PL
M
S
0.25 (0.010)
B
1
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
G
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MC44824/D
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