MC44826D [MOTOROLA]
TV AND VCR I2C PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND MIX/OSC DECODER; 电视机，录像机I2C PLL调谐1.3 GHz的预分频器电路，混合/ OSC解码器
| 型号： | MC44826D |
| 厂家： | 
MOTOROLA |
| 描述： | TV AND VCR I2C PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND MIX/OSC DECODER |
| 文件： | 总8页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44826/D
The MC44826 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO. This
integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The circuit has a band decoder that
provides the band switching signal for the mixer/oscillator circuit. The decoder
TV AND VCR
2
I C PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND MIX/OSC DECODER
is controlled by the buffer bits or independently by extra bits T and T .
6
7
The MC44826 has a programmable 512/1024 reference divider and is
manufactured on a single silicon chip using Motorola’s high density bipolar
process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits).
SEMICONDUCTOR
TECHNICAL DATA
2
• Complete Single Chip System for MPU Control (I C Bus)
• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512 and 1024
• 3–State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
• Four Programmable Chip Addresses
• Integrated Band Decoder for the Mixer/Oscillator Circuit
• Band Buffers with Low “On” Voltage (0.4 V Maximum at 15 mA)
14
1
• Fully ESD Protected to MIL–STD–883C, Method 3015.7
(2000 V, 1.5 kΩ, 150 pF)
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
MOSAIC is a trademark of Motorola, Inc.
PIN CONNECTIONS
V
PHO
Xtal
1
2
3
4
5
6
7
14
13
12
11
10
9
TUN
Gnd
HF
1
DEC
SDA
HF
2
ORDERING INFORMATION
Operating
V
SCL
CA
CC1
Temperature Range
Device
Package
B
1
MC44826D
T
A
= –20° to +80°C
SO–14
B
8
B
5
3
(Top View)
Motorola, Inc. 1996
Rev 1
MC44826
Representative Block Diagram
V
V
CC2
TUN
RL
CL
Bands Out
V
CC1
DEC
5.0 V
5
12
8
7
6
1
Mixer/Oscillator
Band Decoder
14
B
B
B
1
F
2
5
3
out
PHO
2.7 V
Test
Logic
Buffers
F
ref
Operational
Amplifier
T
6
7
Latches
T
T
8
DTB1
Gnd
T
13
Phase
Comp
T , T , T
12 14
9
T
, T
10 11
DTB2
POR
P–On
Reset
Latches
7
F
F
out
ref
512/1024
9
3
CA
SDA
SCL
CL
2
Shift Register
15 Bit
11
10
I C Bus
Receiver
Data
RL
Ref
Divider
DTF
Latches A
Latches B
13 Xtal
Osc
12 pF
TDI
3.2/4.0
MHz
Preamp
3
4
÷
8
HF
HF
1
2
Program Divider
15 Bit
Latch Control
DTS, EN
Prescaler
F
out
This device contains 3,204 active transistors.
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Rating
Power Supply Voltage (V
Pin
5
Value
Unit
V
)
6.0
CC1
Band Buffer “Off” Voltage
Band Buffer “On” Current
6, 7, 8
6, 7, 8
1
15
V
20
mA
V
Operational Amplifier Power Supply (V
RF Input Level 10 MHz to 1.3 GHz
Storage Temperature
)
40
1.5
CC2
3, 4
–
Vrms
°C
°C
V
–65 to +150
–20 to +80
7
Operating Temperature Range
Bus Input Voltage (Positive)
Bus Input Voltage (Negative)
–
10, 11
10, 11
–0.5
V
2
MOTOROLA ANALOG IC DEVICE DATA
MC44826
ELECTRICAL CHARACTERISTICS (V
= 5.0 V, V
= 33 V, T = 25°C, unless otherwise noted.)
CC2 A
CC1
Characteristic
Pin
Min
4.5
25
–
Typ
5.0
35
0.01
0.2
–
Max
5.5
50
Unit
V
V
V
Supply Voltage Range
5
CC1
Supply Current (V
= 5.0 V)
5
mA
µA
V
CC1
CC1
Band Buffer Leakage Current when “Off” at 12 V
6, 7, 8
6, 7, 8
10, 11
10, 11
10, 11
10, 11
11
1.0
0.4
0
Band Buffer Saturation Voltage when “On” at 15 mA
Data/Clock Current at 0 V (Acknowledge “Off”)
Data/Clock Current at 5.0 V (Acknowledge “Off”)
Data/Clock Input Voltage Low
–
–10
0
µA
µA
V
–
1.0
1.5
–
–
–
Data/Clock Input Voltage High
3.0
–
–
V
Data Saturation Voltage at 3.0 mA (Acknowledge “On”)
Decoder “High” Level Sourcing 100 µA
Decoder “Medium” Level Sourcing 15 µA
Decoder “Low” Level Sinking 20 µA
Clock Frequency Range
0.25
–
0.4
V
12
3.4
1.7
0
V
CC1
2.3
V
12
–
V
12
–
0.8
100
4.05
V
10
–
–
kHz
MHz
Oscillator Frequency Range
13
3.15
3.2
Operational Amplifier Internal Reference Voltage
Operational Amplifier Input Current
–
14
2.0
–15
100
0.3
–
2.75
0
3.2
15
V
nA
V/V
MHz
V
DC Open Loop Gain (R = 22 kΩ)
14, 1
14, 1
1
250
–
1000
–
L
Gain Bandwidth Product (C = 0.5 nF)
L
V
Low (R = 22 kΩ)
0.25
0
0.4
15
out
Phase Detector Current in High Impedance State
Charge Pump Current of Phase Comparator (T = 0)
L
14
–15
30
nA
µA
µA
V
14
40
50
14
Charge Pump Current of Phase Comparator (T = 1)
14
90
125
33
150
36
14
V
CC2
Supply Voltage Range
1
25
PIN FUNCTION DESCRIPTION
Pin
1
Function
Description
V
/V
Output of the tuning voltage amplifier. Needs an external pull–up resistor to drive the varicaps
TUN CC2
2
Gnd
Ground
3, 4
5
HF / HF
Symmetric HF inputs from local oscillator
Supply voltage. Typical 5.0 V
Band buffer outputs
1
2
V
CC1
6, 7, 8
9
B , B , B
1
3
5
CA
Chip address selection pin
2
10
SCL
SDA
DEC
Xtal
Clock input of the I C bus
11
Data input
12
Band decoder output for the mixer/oscillator circuit
Crystal input
13
14
PHO
Input of tuning voltage amplifier
3
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Figure 1. Typical Prescaler Input Sensitivity
5.0
–5.0
–15
Guaranteed Operating Area
–25
–35
–45
600
RF In (MHz)
0
200
400
800
1000
1200
1400
NOTE:
V
= 4.5 to 5.5 V, T = – 20° to +80°C
CC A
HF CHARACTERISTICS (See Figure 1)
Characteristic
Pin
Min
Typ
Max
Unit
V
DC Bias
3, 4
–
1.6
–
Input Voltage Range
50–950 MHz
950–1300 MHz
mVrms
3, 4
3, 4
10
50
–
–
315
315
Figure 2. RF Sensitivity Test Circuit
2
I C Bus Controller
10, 11
2
7
+5.0 V
5
MC44826
V
CC1
3
4
8
B
3
4.0 k
B
HF In
5
1.0 nF
1.0 nF
+12 V
RF Generator
4.0 kΩ
(50
Ω)
50
Ω
Frequency Counter
Device is in test mode, B and B are “On”, B is “Off”.
5
3
1
Sensitivity is the level of the HF generator on 50 Ω load.
4
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Figure 3. Typical HF Input Impedance
–j
+j
0
0.5
0.5
0.5
Z
= 50 Ω
O
1.3 GHz
1
2
1
1
1.0 GHz
2
2
500 MHz
50 MHz
Figure 4. Complete Data Transfer Process
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
P
STA
ADDRESS
CA
R/W
ACK
DATA
ACK
DATA
ACK
STO
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the I C bus. The incoming information, consisting of a
bytes of control and band information and two bytes of
frequency information.
2
chip address byte followed by two or four data bytes, is
treated in the I C bus receiver. The definition of the
permissible bus protocol is shown below:
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
2
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceded by a Logic “0”. If the
function bit is Logic “1” the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
1_STA CA CO BA STO
2_STA CA FM FL STO
3_STA CA CO BA FM FL STO
4_STA CA FM FL CO BA STO
STA = Start Condition
STO = Stop Condition
CA = Chip Address Byte
CO = Data Byte for Control Information
BA = Band Information
The two permissible bus protocols with five bytes are
shown in Figure 5.
FM = Data Byte for Frequency Information (MSB’s)
FL = Data Byte for Frequency Information (LSB’s)
The Data and Clock inputs (Pins 10 and 11) are high
impedance when the supply voltage V
5.5 V.
is between 0 and
CC1
Figure 5 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
5
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Chip Address
The chip address is programmable by Pin 9 (CA – Address
Select).
CA – Pin 9
–0.04 V to 0.1 V
Address (HEX.)
C6
C4
C2
C0
CC1
Open or 0.2 V
CC1
to 0.3 V
CC1
CC1
CC1
0.42 V
0.9 V
to 0.75 V
CC1
to 1.2 V
CC1
CC1
Figure 5. Definition of Bytes
CA_Chip Address
CO_Information
1
1
0
0
0
0/1
0/1
0
ACK
T
14
T
13
T
12
T
11
T
10
T
9
T
8
ACK
ACK
1
BA_Band Information
T
7
T
6
B
5
X
B
3
X
B
1
X
FM_Frequency Information
FL_Frequency Information
N
N
N
N
N
N
N
N
ACK
ACK
0
14
13
12
11
10
9
1
8
0
N
N
N
N
N
N
N
7
6
5
4
3
2
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
FM_Frequency Information
FL_Frequency Information
N
N
N
T
N
N
N
9
N
N
ACK
ACK
0
14
13
12
11
10
8
0
N
N
N
N
N
N
N
7
6
5
4
3
2
1
CO_Information
T
14
T
13
T
11
T
10
T
9
T
8
ACK
ACK
1
12
X
BA_Band Information
T
7
T
B
B
X
B
1
X
6
5
3
Figure 6. Typical Tuner Application
IF
UHF
VHF
B III
M/O
12
8
7
6
5.0 V
5
Band Decoder
B
B
B
1
5
3
Antenna
Filter
Mixer
11
10
9
SDA
SCL
CA
Bus
Rec
B. P. Filter
1.0 nF
3
4
13
Osc &
Ref Div
÷
Pres
8
Program
Divider
12 pF
F
osc
3.2/4.0 MHz
1.0 nF
Phase
Comp
MC44826
Gnd
2
2.7 V
14
Oscillator
1
R
L
(Note 1)
47 nF
V
TUN
33 V
47 k
AGC
330 p
(Note 2)
NOTES: 1. On some layouts the 100 Ω resistor will not be required.
2. C = 330 pF minimum is required for stability.
2
22 nF
6
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Bits B , B , B : Control the Band Buffers
The band buffers are open collector buffers and are active
1
3
5
“low” at Bn = 1. They are designed for 15 mA with a typical
“On” voltage of 200 mV. These buffers are designed to
withstand relative high output voltage in the “Off” state.
B and B buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
B , B , B = 0
Buffer “Off”
Buffer “On”
1
3
5
B , B , B = 1
0
1
3
Bit T : Controls the Output of the Operational Amplifier
3
5
8
T
= 0
Normal Operation
Operational Amplifier Active
8
8
The bit B and/or B have to be one if the buffers are used
3
5
T
= 1
Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through the External Pull–Up
for these additional functions.
Resistor R
The Programmable Divider
L
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
Bits T , T : Control the Phase Comparator
12
9
T
9
T
12
Function
1
0
1
0
1
Normal Operation
High Impedance
Upper Source “On” Only
Lower Source “On” Only
1
0
0
Bits T , T : Control the Reference Divider
10 11
The division ratio definition is given by:
N = 16384 x N + 8192 x N + … + 4 x N + 2 x N + N
Maximum Ratio 32767
Minimum Ratio 256
T
T
Division Ratio
14
13
2
1
0
10
11
0
0
1
1
0
1
0
1
512
1024
1024
512
Where N … N
information.
are the different bits for frequency
0
14
The counter may be used for any ratio between 256 and
32767, and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
Bit T : Switches the Internal Signals F
13 ref
and F
to
BY2
Bit T : the Band Buffer Outputs (Test)
13
The data transfer between latches A and B (signal TDI) is
T
13
T
13
= 0
= 1
Normal Operation
Test Mode
2
also initiated by any start condition on the I C bus.
At power–on the whole bus receiver is reset and the bit N
8
F
F
Output at B (Pin 7)
3
ref
of the programmable divider is set to N = 1. Thus the
8
Output at B (Pin 8)
BY2
5
programmable divider starts with a division ratio of 256 or
higher.
Bits B and B have to be “On”, B = B = 1 in the test mode.
3
5
3
5
F
F
is the reference frequency.
2
ref
The first I C message must be sent only when the
is the output frequency of the programmable divider, divided by two.
BY2
POWER ON RESET is completed. Division ratios of N < 256
are not allowed.
Bit T : Controls the Charge Pump Current of the
14
Bit T : Phase Comparator
The Prescaler
14
The prescaler has a preamplifier which guarantees high
input sensitivity.
T
14
T
13
= 0
= 1
Pump Current 40 µA Typical
Normal Operation. Pump Current 125 µA Typical
The Phase Comparator
Bits T , T : Mixer/Oscillator Band Decoder
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
6
7
The band decoder provides the band switching signal for
the mixer/oscillator circuit. The buffer bits control the decoder
output. The decoder can be controlled by the buffer bits or
The Tuning Voltage Amplifier
independently by the control bits T and T as per the tables
6
7
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external pull–up resistor to generate the tuning voltage.
below.
T
7
T
6
Decoder Output DEC
0
0
Decoder Output Controlled by Buffer Bits
The amplifier can be switched “Off” through bit T . When
8
B , B , B
0 to 0.8 V
1
3
5
bit T is “One”, the amplifier is “Off”. The tuning voltage is
0
1
1
1
0
1
8
then pulled high by the external pull–up resistor.
1.8 to 2.1 V
3.4 V to V
(V
= 4.5 to 5.5 V)
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
CC1 CC1
B
5
B
B
1
Decoder Output DEC
1.8 to 2.1 V
3
The Oscillator
0
0
1
X
X
X
0
1
0
0 to 0.8 V
3.4 V to V
(V
The oscillator uses a 3.2 or 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in its series
resonance mode.
The voltage at Pin 13, has low amplitude and low
harmonic distortion.
CC1
= 4.5 to 5.5 V)
Undefined
CC1
1
X
1
BA_Band Information
The negative impedance of the crystal input (Pin 13) is
about 3.0 kΩ.
T
7
T
6
B
5
X
B
3
X
B
1
X
ACK
7
MOTOROLA ANALOG IC DEVICE DATA
MC44826
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
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MC44826/D
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