MT8812AE1 [MICROSEMI]
Cross Point Switch, 1 Func, 12 Channel, CMOS, PDIP40, LEAD FREE, PLASTIC, MS-011AC, DIP-40;
| 型号： | MT8812AE1 |
| 厂家： | 
Microsemi |
| 描述： | Cross Point Switch, 1 Func, 12 Channel, CMOS, PDIP40, LEAD FREE, PLASTIC, MS-011AC, DIP-40 光电二极管 输出元件 |
| 文件： | 总10页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO-CMOS
MT8812
8 x 12 Analog Switch Array
Data Sheet
September 2011
Features
•
•
•
•
•
•
•
•
•
Internal control latches and address decoder
Ordering Information
Short set-up and hold times
MT8812AP1
44 Pin PLCC*
MT8812APR1 44 Pin PLCC*
Tubes
Tape & Reel
Tubes
Wide operating voltage: 4.5 V to 14.5 V
14Vpp analog signal capability
MT8812AE1
40 Pin PDIP*
*Pb Free Matte Tin
R
ON 65 max. @ VDD=14V, 25C
-0C to +70C
RON 10 @ VDD=14V, 25C
Full CMOS switch for low distortion
Minimum feedthrough and crosstalk
Low power consumption ISO-CMOS technology
Description
The Zarlink MT8812 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation and
high reliability. The device contains a 8 x12 array of
crosspoint switches along with a 7 to 96 line decoder
and latch circuits. Any one of the 96 switches can be
addressed by selecting the appropriate seven input
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input.
Applications
•
•
•
•
•
PBX systems
Mobile radio
Test equipment /instrumentation
Analog/digital multiplexers
Audio/Video switching
STROBE
DATA RESET
VDD
VSS
1
1
AX0
AX1
AX2
AX3
AY0
AY1
AY2
8 x 12
Switch
Array
7 to 96
Decoder
Xi I/O
(i=0-11)
Latches
96
96
• • • • • • • • • • • • • • • • • • •
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT8812
Data Sheet
Change Summary
Changes from the August 2005 issue to the September 2011 issue.
Page
Item
Change
1
Ordering Information
Removed leaded packages as per PCN notice.
1
2
3
4
5
40
39
Y3
AY2
RESET
AX3
AX0
NC
VDD
Y2
DATA
Y1
NC
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
44 43 42 41
6 5 4 3 2
1
7
NC
NC
X6
39
NC
8
6
38
37
36
35
34
33
32
31
30
29
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC
9
7
NC
X6
X7
X8
X9
X10
X11
NC
10
11
12
13
14
15
16
8
X7
9
X8
10
11
12
13
14
15
16
17
18
19
20
X9
X10
X11
NC
NC
NC
17
Y7
NC
Y6
1819 20 2122 2324 25 2627 28
STROBE
Y5
VSS
40 PIN PLASTIC DIP
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
2
1
2
3
Y3
AY2
Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
Y2 Address Line (Input).
3
RESET Master RESET (Input): this is used to turn off all switches. Active High.
4,5
6,7
8-13
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs).
6-8
NC
No Connection.
9-14
X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the
switch array.
14
15
16
17
18
15-17
18
NC
Y7
NC
Y6
No Connection.
Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
No Connection.
-
19
Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
20
STROBE STROBE (Input): enables function selected by address and data. Address must be
stable before STROBE goes high and DATA must be stable on the falling edge of the
STROBE. Active High.
19
21
Y5
Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
2
Zarlink Semiconductor Inc.
MT8812
Data Sheet
Pin Description
Pin #
Name
Description
20
21
22
23
VSS
Y4
Ground Reference.
Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27 28-31
NC
No Connection.
28 - 33 32-37 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the
switch array.
34
35
36
37
38
38,39
40
NC
Y0
NC
Y1
No Connection.
Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
No Connection.
-
41
Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
42
DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High.
39
40
43
44
Y2
Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
VDD
Positive Power Supply.
Functional Description
The MT8812 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there
are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X
input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on
and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in
which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the
DATA input line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on
the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on
and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory
location are altered when data is written into memory. The remaining switches retain their previous states. Any
combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A
logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all
crosspoint switches.
Address Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a
location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data can be changed while STROBE is high, however, the
corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of
STROBE in order for correct data to be written to the latch.
3
Zarlink Semiconductor Inc.
MT8812
Data Sheet
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
Supply Voltage
VDD
VSS
-0.3
-0.3
16.0
V
V
VDD+0.3
VDD+0.3
VDD+0.3
15
2
3
4
5
6
Analog Input Voltage
Digital Input Voltage
VINA
VIN
I
-0.3
V
VSS-0.3
V
Current on any I/O Pin
Storage Temperature
mA
C
W
TS
PD
-65
+150
Package Power Dissipation
PLASTIC DIP
0.6
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics
Sym. Min.
Typ.
Max.
Units
Test Conditions
1
2
3
Operating Temperature
Supply Voltage
TO
0
25
70
C
V
VDD
VINA
4.5
VSS
14.5
VDD
Analog Input Voltage
V
4
Digital Input Voltage
VIN
VSS
VDD
V
DC Electrical Characteristics†- Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
Quiescent Supply Current
IDD
1
100
A
All digital inputs at VIN=VSS or
VDD
7
15
mA
nA
All digital inputs at VIN=2.4V
Off-state Leakage Current
(See G.9 in Appendix)
IOFF
1
500
IVXi - VYjI = VDD - VSS
See Appendix, Fig. A.1
3
4
5
Input Logic “0” level
VIL
VIH
0.8
10
V
V
Input Logic “1” level
2.4
Input Leakage (digital pins)
ILEAK
0.1
A
All digital inputs at VIN = VSS
or VDD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
4
Zarlink Semiconductor Inc.
MT8812
Data Sheet
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym.
25C
60C
70C
Units
Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state
VDD=14V
Resistance VDD=12V
VDD=10V
RON
45
60
65
65
85
95
75
95
110
260
V
SS=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
V
DD= 5V
145 220
(See G.1, G.2, G.3 in
Appendix)
2 Difference in on-state
resistance between two
switches
RON
5
10
10
10
VDD=14V, VSS=0,
V
DC=VDD/2,
IVXi-VYjI = 0.4V
(See G.4 in Appendix)
See Appendix, Fig. A.2
AC Electrical Characteristics† - Crosspoint Performance-VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics
Sym. Min. Typ.‡ Max. Units
Test Conditions
f=1 MHz
f=1 MHz
1
2
3
Switch I/O Capacitance
CS
CF
20
0.2
45
pF
pF
Feedthrough Capacitance
Frequency Response
Channel “ON”
F3dB
MHz Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1k
20LOG(VOUT/VXi)=-3dB
See Appendix, Fig. A.3
4
5
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
FDT
0.01
-95
%
Switch is “ON”; VINA = 2Vpp
sinewave f= 1kHz; RL=1k
Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
dB
All Switches “OFF”; VINA
2Vpp sinewave f= 1kHz;
RL= 1k.
=
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk
-45
-90
-85
-80
dB
dB
dB
dB
VINA=2Vpp sinewave
f= 10MHz; RL = 75
V
INA=2Vpp sinewave
f= 10kHz; RL = 600
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
V
INA=2Vpp sinewave
f= 10kHz; RL = 1k
V
INA=2Vpp sinewave
f= 1kHz; RL = 10k
Refer to Appendix, Fig. A.5
for test circuit.
7
Propagation delay through
switch
tPS
30
ns
RL=1k; CL=50pF
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better.
5
Zarlink Semiconductor Inc.
MT8812
Data Sheet
AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics
Sym. Min. Typ.‡ Max.
Units
Test Conditions
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CXtalk
30
mVpp VIN=3V+VDC squarewave;
RIN=1k, RL=10k.
See Appendix, Fig. A.6
2
3
4
5
6
7
8
9
Digital Input Capacitance
Switching Frequency
CDI
FO
10
pF
MHz
ns
f=1MHz
20
Setup Time DATA to STROBE
Hold Time DATA to STROBE
Setup Time Address to STROBE
Hold Time Address to STROBE
STROBE Pulse Width
tDS
tDH
tAS
tAH
tSPW
tRPW
tS
10
10
10
10
20
40
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
RL= 1k, CL=50pF
ns
ns
ns
ns
RESET Pulse Width
ns
10 STROBE to Switch Status Delay
11 DATA to Switch Status Delay
12 RESET to Switch Status Delay
40
50
35
100
100
100
ns
tD
ns
tR
ns
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Refer to Appendix, Fig. A.7 for test circuit.
tRPW
50%
50%
RESET
tSPW
STROBE
50%
50%
50%
tAS
ADDRESS
50%
50%
tAH
DATA
50%
tDS
50%
tDH
ON
SWITCH*
OFF
tR
tR
tS
tD
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
6
Zarlink Semiconductor Inc.
MT8812
Data Sheet
AX0
AX1
AX2
AX3
AY0
AY1
AY2
Connection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
No Connection
No Connection
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
No Connection
No Connection
0
1
0
0
0
1
0
1
1
1
0
0
0
0
X0-Y1
X11-Y1
X0-Y2
X11-Y2
X0-Y3
X11-Y3
X0-Y4
X11-Y4
X0-Y5
X11-Y5
X0-Y6
0
1
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
1
1
1
1
X11-Y6
X0-Y7
0
1
0
0
0
1
0
1
1
1
1
1
1
1
X11-Y7
Table 1 - Address Decode Truth Table
This address has no effect on device status.
7
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
MT8812AP1
Cross Point Switch, 1 Func, 12 Channel, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
ZARLINK
MT8812AP1
Cross Point Switch, 1 Func, 12 Channel, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MICROSEMI
MT8812APR1
Cross Point Switch, 1 Func, 12 Channel, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
ZARLINK
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