MT8814AE [MITEL]
ISO-CMOS 8 x 12 Analog Switch Array; ISO- CMOS 8 ×12模拟开关阵列
| 型号： | MT8814AE |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | ISO-CMOS 8 x 12 Analog Switch Array |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO-CMOS
8 x 12 Analog Switch Array
MT8814
ISSUE 2
November 1988
Features
•
•
•
•
•
•
•
•
•
•
Internal control latches and address decoder
Ordering Information
Short set-up and hold times
MT8814AC
MT8814AE
MT8814AP
40 Pin Ceramic DIP
40 Pin Plastic DIP
44 Pin PLCC
Wide operating voltage: 4.5V to 13.2V
12Vpp analog signal capability
-40° to 85°C
R
65Ω max. @ V =12V, 25°C
DD
ON
∆R
≤ 10Ω @ V =12V, 25°C
DD
ON
Full CMOS switch for low distortion
Description
Minimum feedthrough and crosstalk
Separate analog and digital reference supplies
Low power consumption ISO-CMOS technology
The Mitel MT8814 is fabricated in MITEL’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 12
array of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
Applications
•
•
•
•
•
•
Key systems
PBX systems
zero to the DATA input. V is the ground reference
SS
Mobile radio
of the digital inputs. The range of the analog signal
Test equipment /instrumentation
Analog/digital multiplexers
Audio/Video switching
is from V
to V
.
Chip Select (CS) allows the
DD
EE
crosspoint array to be cascaded for matrix
expansion.
CS STROBE
DATA RESET
VDD
VEE
VSS
1
1
AX0
AX1
AX2
8 x 12
Switch
Array
7 to 96
Decoder
AX3
Xi I/O
(i=0-11)
Latches
AY0
AY1
96
96
AY2
• • • • • • • • • • • • • • • • • • •
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
3-33
MT8814 ISO-CMOS
1
2
3
4
5
40
39
Y3
AY2
RESET
AX3
AX0
NC
VDD
Y2
DATA
Y1
CS
Y0
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
44 43 42 41
6 5 4 3 2
1
7
AX0
NC
X6
39
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC
6
8
38
37
36
35
34
33
32
31
30
29
7
9
NC
NC
X0
8
10
11
12
13
14
15
16
X6
X7
9
X7
X1
X8
10
11
12
13
14
15
16
17
18
19
20
X9
X8
X2
X10
X9
X3
X10
X11
NC
X4
X11
NC
X5
Y7
NC
NC
AY1
AY0
AX2
AX1
Y4
VSS
Y7
VSS
Y6
17
18 19 20 21 22 23 24 25 26 27 28
STROBE
Y5
VSS
40 PIN CERDIP/PLASTIC DIP
44 PIN PLCC
Figure 2 - Pin Connections
Description
Pin Description
Pin #*
Name
1
2
3
Y3
Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
Y2 Address Line (Input).
AY2
RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of
CS. Active High.
4,5
6,7
AX3,AX0 X3 and X0 Address Lines (Inputs).
NC
No Connection.
8-13
X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch
array.
14
15
16
17
18
NC
Y7
No Connection
Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
Digital Ground Reference .
V
SS
Y6
Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.
Active High.
19
20
Y5
Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
Negative Power Supply.
V
EE
21
Y4
Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23
24, 25
26, 27
28 - 33
AX1,AX2 X1 and X2 Address Lines (Inputs).
AY0,AY1 Y0 and Y1 Address Lines (Inputs).
NC
No Connection.
X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch
array.
34
35
36
37
38
NC
Y0
CS
Y1
No Connection.
Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
Chip Select (Input): this is used to select the device. Active High.
Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
39
40
Y2
Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
Positive Power Supply.
V
DD
* Plastic DIP and CERDIP only
3-34
ISO-CMOS MT8814
Functional Description
Address Decode
The MT8814 is an analog switch matrix with an array
size of 8 x 12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 96
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX3). Data is
presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both
the CS (Chip Select) and STROBE inputs are high
and are latched on the falling edge of STROBE. A
logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0”
turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous states. Any
combination of X and Y inputs/outputs can be
interconnected by establishing appropriate patterns
in the control memory. A logical “1” on the RESET
input will asynchronously return all memory locations
to logical “0” turning off all crosspoint switches
regardless of whether CS is high or low. Two voltage
The seven address inputs along with the STROBE
and CS (Chip Select) are logically ANDed to form an
enable signal for the resettable transparent latches.
The DATA input is buffered and is used as the input
to all latches. To write to a location, RESET must be
low and CS must go high while the address and data
are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data
can be changed while STROBE is high, however, the
corresponding switch will turn on and off in
accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for
correct data to be written to the latch.
reference pins (V
and V ) are provided for the
SS
EE
MT8814 to enable switching of negative analog
signals. The range for digital signals is from V
to
to
DD
DD
V
V
while the range for analog signals is from V
SS
EE
.
V
and V
pins can be tied together if a
SS
EE
single voltage reference is needed.
3-35
MT8814 ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply Voltage
V
V
-0.3
-0.3
16.0
V
V
DD
SS
V
V
V
+0.3
DD
DD
DD
2
3
4
5
6
Analog Input Voltage
Digital Input Voltage
V
-0.3
+0.3
+0.3
V
V
INA
V
V
-0.3
SS
IN
Current on any I/O Pin
Storage Temperature
I
±15
mA
°C
T
-65
+150
S
Package Power Dissipation
PLASTIC DIP
CERDIP
P
P
0.6
1.0
W
W
D
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Operating Temperature
Supply Voltage
T
-40
4.5
25
85
°C
O
V
V
13.2
V
V
DD
SS
V
V
-4.5
EE
DD
3
4
Analog Input Voltage
Digital Input Voltage
V
V
V
V
V
V
INA
EE
DD
DD
V
V
IN
SS
DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Quiescent Supply Current
I
1
100
µA
All digital inputs at V =V or
DD
IN
SS
V
DD
0.4
1.5
mA
All digital inputs at V =2.4V +
IN
V
; V =7.0V
SS
SS
5
15
mA
nA
All digital inputs at V =3.4V
IN
2
Off-state Leakage Current
(See G.9 in Appendix)
I
±1
±500
IV - V I = V - V
Xi Yj DD EE
OFF
See Appendix, Fig. A.1
0.8+VSS
3
4
5
6
Input Logic “0” level
Input Logic “1” level
Input Logic “1” level
Input Leakage (digital pins)
V
V
V
V
V
=7.5V; V =0V
EE
IL
IH
IH
SS
SS
2.0+VSS
V
V
=6.5V; V =0V
EE
3.3
V
I
0.1
10
µA
All digital inputs at V = V
IN SS
LEAK
or V
DD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym
25°C
70°C
85°C
Units
Test Conditions
Typ Max Typ Max Typ Max
1 On-state
V
=12V
R
45
55
65
75
75
85
215
80
90
225
Ω
Ω
Ω
V
=V =0V,V =V /2,
SS EE DC DD
DD
DD
ON
Resistance V =10V
IV -V I = 0.4V
See Appendix, Fig. A.2
Xi Yj
V
= 5V
120 185
DD
(See G.1, G.2, G.3 in
Appendix)
2 Difference in on-state
resistance between two
switches
∆R
5
10
10
10
Ω
V
V
=12V, V =V =0,
SS EE
ON
DD
DC
=V /2,
DD
IV -V I = 0.4V
Xi Yj
(See G.4 in Appendix)
See Appendix, Fig. A.2
3-36
ISO-CMOS MT8814
AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
f=1 MHz
f=1 MHz
1
2
3
Switch I/O Capacitance
Feedthrough Capacitance
C
C
20
0.2
45
pF
pF
S
F
Frequency Response
Channel “ON”
F
MHz Switch is “ON”; V
= 2Vpp
INA
3dB
sinewave; R = 1kΩ
L
20LOG(V
/V )=-3dB
See Appendix, Fig. A.3
OUT Xi
4
5
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
FDT
0.01
-95
%
Switch is “ON”; V = 2Vpp
INA
sinewave f= 1kHz; R =1kΩ
L
Feedthrough
dB
All Switches “OFF”; V
=
INA
Channel “OFF”
2Vpp sinewave f= 1kHz;
Feed.=20LOG (V
/V )
R = 1kΩ.
OUT Xi
L
(See G.8 in Appendix)
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
X
-45
-90
-85
-80
dB
dB
dB
dB
V
=2Vpp sinewave
INA
talk
f= 10MHz; R = 75Ω.
L
V
=2Vpp sinewave
INA
f= 10kHz; R = 600Ω.
L
Xtalk=20LOG (V /V ).
Yj Xi
V
=2Vpp sinewave
INA
f= 10kHz; R = 1kΩ.
L
(See G.7 in Appendix).
V
=2Vpp sinewave
INA
f= 1kHz; R = 10kΩ.
L
Refer to Appendix, Fig. A.5
for test circuit.
7
Propagation delay through
switch
t
30
ns
R =1kΩ; C =50pF
L L
PS
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
‡
Characteristics
Control Input crosstalk to switch
Sym
Min
Typ
Max
Units
Test Conditions
1
CX
30
mVpp V =3V square wave;
talk
IN
(for CS, DATA, STROBE,
Address)
R =1kΩ, R =10kΩ.
See Appendix, Fig. A.6
f=1MHz
IN L
2
3
4
5
6
7
8
9
Digital Input Capacitance
C
F
10
pF
MHz
ns
DI
Switching Frequency
20
O
➀
Setup Time DATA to STROBE
Hold Time DATA to STROBE
Setup Time Address to STROBE
Hold Time Address to STROBE
Setup Time CS to STROBE
Hold Time CS to STROBE
t
10
10
10
10
10
10
20
40
R = 1kΩ, C =50pF
L L
DS
➀
➀
➀
t
ns
R = 1kΩ, C =50pF
L L
DH
t
ns
R = 1kΩ, C =50pF
L L
AS
AH
t
ns
R = 1kΩ, C =50pF
L L
➀
t
ns
R = 1kΩ, C =50pF
L L
CSS
CSH
➀
➀
➀
➀
➀
➀
t
ns
R = 1kΩ, C =50pF
L L
10 STROBE Pulse Width
t
ns
R = 1kΩ, C =50pF
L L
SPW
RPW
11 RESET Pulse Width
t
ns
R = 1kΩ, C =50pF
L L
12 STROBE to Switch Status Delay
13 DATA to Switch Status Delay
14 RESET to Switch Status Delay
t
40
50
35
100
100
100
ns
R = 1kΩ, C =50pF
L L
S
t
ns
R = 1kΩ, C =50pF
L L
D
t
ns
R = 1kΩ, C =50pF
L L
R
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
➀ Refer to Appendix, Fig. A.7 for test circuit.
3-37
MT8814 ISO-CMOS
tCSS
tCSH
50%
50%
tRPW
CS
50%
50%
RESET
tSPW
STROBE
50%
50%
50%
tAS
ADDRESS
50%
50%
tAH
DATA
50%
tDS
50%
tDH
ON
SWITCH*
OFF
tR
tR
tS
tD
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AX0
AX1
AX2
AX3
AY0
AY1
AY2
Connection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
No Connection 1
No Connection 1
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
➀
➀
No Connection
No Connection
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
0
↓
X0-Y1
↓ ↓
1
0
1
1
1
0
0
X11-Y1
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
X0-Y2
↓ ↓
1
0
1
1
0
1
0
X11-Y2
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
0
↓
X0-Y3
↓ ↓
1
0
1
1
1
1
0
X11-Y3
0
↓
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
X0-Y4
↓ ↓
1
0
1
1
0
0
1
X11-Y4
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
1
↓
X0-Y5
↓ ↓
1
0
1
1
1
0
1
X11-Y5
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
X0-Y6
↓ ↓
1
0
1
1
0
1
1
X11-Y6
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
1
↓
X0-Y7
↓ ↓
1
0
1
1
1
1
1
X11-Y7
Table 1. Address Decode Truth Table
This address has no effect on device status.
➀
3-38
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