MT28F800B5_技术文档

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

MT28F008B5

MT28F800B5

FLASH MEMORY

5V Only, Dual Supply (Smart 5)

0.18µm Process Technology

FEATURES

•

Eleven erase blocks:

16KB/8K-word boot block (protected)

Two 8KB/4K-word parameter blocks

Eight main memory blocks

40-Pin TSOP Type I

48-Pin TSOP Type I

•

Smart 5 technology (B5):

5V 10% VCC

5V 10% VPP application/

production programming¹

•

Advanced 0.18µm CMOS floating-gate process

Compatible with 0.3µm Smart 5 device

Address access time: 80ns

100,000 ERASE cycles

Industry-standard pinouts

Automated write and erase algorithm

Two-cycle WRITE/ERASE sequence

TSOP and SOP packaging options

Byte- or word-wide READ and WRITE

(MT28F800B5, 1 Meg x 8/512K x 16)

44-Pin SOP²

GENERAL DESCRIPTION

The MT28F008B5 (x8) and MT28F800B5 (x16/x8)

are nonvolatile, electrically block-erasable (Flash),

programmable read-only memories containing

8,388,608 bits organized as 524,288 words (16 bits) or

1,048,576 bytes (8 bits). Writing or erasing the device is

done with a 5V VPP voltage, while all operations are

performed with a 5V VCC. Due to process technology

advances, 5V VPP is optimal for application and pro-

duction programming. These devices are fabricated

with Micron’s advanced 0.18µm CMOS floating-gate

process.

OPTIONS

•

MARKING

Timing

80ns

-8

•

Configurations

1 Meg x 8

MT28F008B5

MT28F800B5

512K x 16/1 Meg x 8

Boot Block Starting Word Address

Top

•

T

B

Bottom

Operating Temperature Range

Commercial (0ºC to +70ºC)

Extended (-40ºC to +85ºC)

Packages

None

ET

The MT28F008B5 and MT28F800B5 are organized

into eleven separately erasable blocks. To ensure that

critical firmware is protected from accidental erasure

or overwrite, the devices feature a hardware-protected

boot block. This block may be used to store code

implemented in low-level system recovery. The

remaining blocks vary in density and are written and

erased with no additional security measures.

MT28F008B5

Plastic 40-pin TSOP Type I

(10mm x 29mm)

MT28F800B5

VG

Plastic 48-pin TSOP Type I

(12mm x 20mm)

Plastic 44-pin SOP (600 mil)

WG

SG²

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

Notes:

1. This generation of devices does not support 12V VPP

compatibility production programming; however, 5V

VPP application production programming can be used

with no loss of performance.

2. Contact factory for availability.

Part Number Example:

MT28F800B5WG-8 BET

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

Pin Assignment (Top View)

48-Pin TSOP Type I

44-PIN SOP¹

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RP#

VPP

WP#

NC

A18

A17

A7

A6

A5

A4

A3

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

VSS

VPP

A18

A17

A7

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RP#

2

WE#

A8

3

DQ15/(A - 1)

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

4

A9

A6

5

A10

A5

6

A11

A4

7

A12

9

A3

8

A13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A2

9

A14

A1

10

11

12

13

14

15

16

17

18

19

20

21

22

A15

A0

A16

CE#

VSS

BYTE#

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

DQ15/(A - 1)

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

VSS

CE#

A0

A2

A1

Order Number and Part Marking

MT28F800B5WG-8 B

MT28F800B5WG-8 T

MT28F800B5WG-8 BET

MT28F800B5WG-8 TET

Order Number and Part Marking

MT28F800B5SG-8 B

MT28F800B5SG-8 T

MT28F800B5SG-8 BET

MT28F800B5SG-8 TET

40-Pin TSOP Type I

A16

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17

VSS

NC

A19

A10

DQ7

DQ6

DQ5

DQ4

VCC

A15

A14

A13

A12

A11

A9

A8

WE#

RP#

VPP

WP#

A18

A7

A6

A5

A4

A3

9

10

11

12

13

14

15

16

17

18

19

20

VCC

NC

DQ3

DQ2

DQ1

DQ0

OE#

VSS

A2

A1

CE#

A0

Order Number and Part Marking

MT28F008B5VG-8 B

MT28F008B5VG-8 T

MT28F008B5VG-8 BET

MT28F008B5VG-8 TET

Notes: 1. Contact factory for availability.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

2

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

MUX

X - Decoder/Block Erase Control

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS

40-PIN

48-PIN

TSOP

44-PINSOP

TSOP

NUMBERS NUMBERS NUMBERS SYMBOL

TYPE

DESCRIPTION

43

9

11

14

26

12

WE#

WP#

CE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle.

If WE# is LOW, the cycle is either a WRITE to the command

execution logic (CEL) or to the memory array.

–

12

22

10

Input Write Protect: Unlocks the boot block when HIGH if VPP =

VPPH (5V) and RP# = VIH during a WRITE or ERASE. Does

not affect WRITE or ERASE operation on other blocks.

12

44

Input

Chip Enable: Activates the device when LOW. When CE# is

HIGH, the device is disabled and goes into standby power

mode.

RP#

Input

Reset/Power-Down: When LOW, RP# clears the status

register, sets the internal state machine (ISM) to the array

read mode and places the device in deep power-down

mode. All inputs, including CE#, are “Don’t Care,” and all

outputs are High-Z. RP# unlocks the boot block and

overrides the condition of WP# when at VHH; RP# must be

held at VIH during all other modes of operation.

14

33

24

–

28

47

OE#

Input

Output Enable: Enables data output buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

BYTE#

Byte Enable: If BYTE# = HIGH, the upper byte is active

through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-

Z, and all data is accessed through DQ0–DQ7. DQ15/(A - 1)

becomes the least significant address input.

11, 10, 9, 8, 21, 20, 19,

7, 6, 5, 4, 18, 17, 16,

42, 41, 40, 15, 14, 8, 7, 20, 19, 18,

25, 24,

23,22, 21,

A0–A18/

(A19)

Input

Address Inputs: Select a unique 16-bit word or 8-bit byte.

The DQ15/(A - 1) input becomes the lowest order address

when BYTE# = LOW (MT28F800B5) to allow for a selection

of an 8-bit byte from the 1,048,576 available.

39, 38, 37,

36, 35, 34,

3, 2

36, 6, 5, 4, 8, 7, 6, 5, 4,

3, 2, 1, 40,

13, 37

3, 2, 1, 48,

17, 16

31

–

45

DQ15/

(A-1)

Input/ Data I/O: MSB of data when BYTE# = HIGH.

Output

Address Input: LSB of address input when BYTE# = LOW

during READ or WRITE operation.

15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7 Input/

Data I/Os: Data output pins during any READ operation or

21, 24, 26,

28, 30

35, 38, 40,

42, 44

Output data input pins during a WRITE. These pins are used to

input commands to the CEL.

16, 18, 20,

22, 25, 27,

29

–

30, 32, 34,

36, 39, 41,

43

DQ8–

DQ14

Input/

Output

Data I/Os: Data output pins during any READ operation or

data input pins during a WRITE when BYTE# = HIGH. These

pins are High-Z when BYTE# is LOW.

1

11

13

VPP

Supply Write/Erase Supply Voltage: From a WRITE or ERASE

CONFIRM until completion of the WRITE or ERASE, VPP

must be at 5V. VPP = “Don’t Care” during all other

operations.

23

13, 32

–

30, 31

23, 39

29, 38

37

VCC

VSS

NC

Supply Power Supply: +5V 10%.

Supply Ground.

27, 46

9, 10, 15

–

No Connect: These pins may be driven or left unconnected.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

4

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F800B5)¹

DQ0–

DQ7

DQ8–

DQ14

DQ15/

A-1

FUNCTION

RP# CE# OE# WE# WP# BYTE# A0

A9

VPP

H

L

H

X

High-Z

Standby

RESET

READ

H

L

H

X

H

L

X

Data-Out Data-Out Data-Out

READ (word mode)

READ (byte mode)

Output Disable

Data-Out

High-Z

A-1

H

X

High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)²

ERASE SETUP

H

L

H

L

X

H

L

X

VPPH

X

20h

D0h

X

ERASE CONFIRM³

X

WRITE SETUP

10h/40h

Data-In

FFh

X

WRITE (word mode)⁴

WRITE (byte mode)⁴

READ ARRAY⁵

VPPH

X

Data-In

A-1

X

WRITE/ERASE (BOOT BLOCK)²

H

VHH

H

L

H

L

X

H

X

H

X

H

X

H

L

X

20h

D0h

X

ERASE SETUP

ERASE CONFIRM³

ERASE CONFIRM^{3, 6}

WRITE SETUP

VPPH

X

D0h

X

H

10h/40h

Data-In

FFh

X

WRITE (word mode)⁴

WRITE (word mode)^{4, 6}

WRITE (byte mode)⁴

WRITE (byte mode)^{4, 6}

READ ARRAY⁵

VHH

H

VPPH

X

Data-In

A-1

X

Data-In

VHH

H

X

L

H

X

DEVICE IDENTIFICATION ⁷

H

L

H

X

H

L

VID

X

89h

00h

–

Manufacturer

Compatibility (word

mode)⁸

High-Z

X

Manufacturer

Compatibility (byte

mode)

Device (word mode, top

boot)⁸

H

L

H

X

H

L

H

VID

X

9Ch

9Dh

88h

High-Z

88h

–

X

–

Device (byte mode, top

boot)

H

L

Device (word mode,

bottom boot)⁸

Device (byte mode,

bottom boot)

High-Z

X

Notes: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. A1–A8, A10–A17 = VIL.

8. Value reflects DQ8–DQ15.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

5

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F008B5)¹

FUNCTION

RP#

CE#

OE#

WE#

WP#

A0

A9

VPP

DQ0–DQ7

H

L

H

X

High-Z

Standby

RESET

READ

H

L

H

X

Data-Out

High-Z

READ

H

Output Disable

WRITE/ERASE (EXCEPT BOOT BLOCK)²

H

L

H

L

X

20h

D0h

ERASE SETUP

ERASE CONFIRM³

WRITE SETUP

WRITE⁴

VPPH

H

L

H

L

X

VPPH

X

10h/40h

Data-In

FFh

READ ARRAY⁵

WRITE/ERASE (BOOT BLOCK)²

H

VHH

L

H

L

X

20h

D0h

ERASE SETUP

ERASE CONFIRM³

VPPH

ERASE CONFIRM^{3, 6}

WRITE SETUP

WRITE⁴

H

L

H

L

H

X

VPPH

D0h

H

VHH

L

H

L

X

10h/40h

Data-In

VPPH

WRITE^{4, 6}

READ ARRAY⁵

H

L

H

L

H

X

VPPH

X

Data-In

FFh

DEVICE IDENTIFICATION⁷

Manufacturer Compatibility

Device (top boot)

H

L

H

X

L

VID

X

89h

98h

99h

H

Device (bottom boot)

Notes: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. A1–A8, A10–A19 = VIL.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

6

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

FUNCTIONAL DESCRIPTION

The MT28F800B5 and MT28F008B5 Flash memo-

ries incorporate a number of features ideally suited for

system firmware. The memory array is segmented into

individual erase blocks. Each block may be erased

without affecting data stored in other blocks. These

memory blocks are read, written and erased with com-

mands to the command execution logic (CEL). The

CEL controls the operation of the internal state

machine (ISM), which completely controls all WRITE,

BLOCK ERASE, and VERIFY operations. The ISM pro-

tects each memory location from over-erasure and

optimizes each memory location for maximum data

retention. In addition, the ISM greatly simplifies the

control necessary for writing the device in-system or in

an external programmer.

formed on the boot block. The remaining blocks

require that only the VPP voltage be present on the VPP

pin before writing or erasing.

Hardware-Protected Boot Block

This block of the memory array can be erased or

written only when the RP# pin is taken to VHH or when

the WP# pin is brought HIGH. (The WP# pin does not

apply to the SOP package.) This provides additional

security for the core firmware during in-system firm-

ware updates should an unintentional power fluctua-

tion or system reset occur. The MT28F800B5 and

MT28F008B5 are available with the boot block starting

at the bottom of the address space (“B” suffix) or the

top of the address space (“T” suffix).

The Functional Description provides detailed infor-

mation on the operation of the MT28F800B5 and

MT28F008B5 and is organized into these sections:

Selectable Bus Size (MT28F800B5)

The MT28F800B5 allows selection of an 8-bit (1 Meg

x 8) or 16-bit (512K x 16) data bus for reading and writ-

ing the memory. The BYTE# pin is used to select the

bus width. In the x16 configuration, control data is

read or written only on the lower 8 bits (DQ0–DQ7).

Data written to the memory array utilizes all active

data pins for the selected configuration. When the x8

configuration is selected, data is written in byte form;

when the x16 configuration is selected, data is written

in word form.

•

Overview

Memory Architecture

Output (READ) Operations

Input Operations

Command Set

ISM Status Register

Command Execution

Error Handling

WRITE/ERASE Cycle Endurance

Power Usage

Power-Up

Internal State Machine (ISM)

BLOCK ERASE and BYTE/WORD WRITE timing are

simplified with an ISM that controls all erase and write

algorithms in the memory array. The ISM ensures pro-

tection against over-erasure and optimizes write mar-

gin to each cell.

During WRITE operations, the ISM automatically

increments and monitors WRITE attempts, verifies

write margin on each memory cell and updates the

ISM status register. When BLOCK ERASE is performed,

the ISM automatically overwrites the entire addressed

block (eliminates over-erasure), increments and moni-

tors ERASE attempts, and sets bits in the ISM status

register.

OVERVIEW

Smart 5 Technology (B5)

Smart 5 operation allows maximum flexibility for in-

system READ, WRITE and ERASE operations. WRITE

and ERASE operations may be executed with a VPP

voltage of 3.3V or 5V. Due to process technology

advances, 5V VPP is optimal for application and pro-

duction programming. For any operation, VCC is at 5V.

Eleven Independently Eraseable

Memory Blocks

The MT28F800B5 and MT28F008B5 are organized

into eleven independently erasable memory blocks

that allow portions of the memory to be erased with-

out affecting the rest of the memory data. A special

boot block is hardware-protected against inadvertent

erasure or writing by requiring either a super-voltage

on the RP# pin or driving the WP# pin HIGH. (The WP#

pin does not apply to the SOP package.) One of these

two conditions must exist, along with the VPP voltage

(5V) on the VPP pin, before a WRITE or ERASE is per-

ISM Status Register

The ISM status register enables an external proces-

sor to monitor the status of the ISM during WRITE and

ERASE operations. Two bits of the 8-bit status register

are set and cleared entirely by the ISM. These bits indi-

cate whether the ISM is busy with an ERASE or WRITE

task and when an erase has been suspended. Addi-

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

7

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

tional error information is set in three other bits: VPP

status, write status, and erase status.

ERASE function is block-oriented. All READ and

WRITE operations are done on a random-access basis.

The boot block is protected from unintentional

ERASE or WRITE with a hardware protection circuit

which requires that a super-voltage be applied to RP#

or that the WP# pin be driven HIGH before erasure is

commenced. The boot block is intended for the core

firmware required for basic system functionality. The

remaining ten blocks do not require that either of

these two conditions be met before WRITE or ERASE

operations.

Command Execution Cell (CEL)

The CEL receives and interprets commands to the

device. These commands control the operation of the

ISM and the read path (i.e., memory array, ID register

or status register). Commands may be issued to the

CEL while the ISM is active. However, there are restric-

tions on what commands are allowed in this condition.

See the Command Execution section for more detail.

Boot Block

Deep Power-Down Mode

The hardware-protected boot block provides extra

security for the most sensitive portions of the firm-

ware. This 16KB block may only be erased or written

when the RP# pin is at the specified boot block unlock

voltage (VHH) or when the WP# pin is HIGH. During a

WRITE or ERASE of the boot block, the RP# pin must

be held at VHH or the WP# pin held HIGH until the

WRITE or ERASE is completed. (The WP# pin does not

apply to the SOP package.) The VPP pin must be at

VPPH (5V) when the boot block is written to or erased.

The MT28F800B5 and MT28F008B5 are available in

two configurations and top or bottom boot block. The

top boot block version supports processors of the x86

variety. The bottom boot block version is intended for

680X0 and RISC applications. Figure 1 illustrates the

memory address maps associated with these two ver-

sions.

To allow for maximum power conservation, the

MT28F800B5 and MT28F008B5 feature a very low cur-

rent, deep power-down mode. To enter this mode, the

RP# pin is taken to VSS 0.2V. In this mode, the current

draw is a maximum of 20µA. Entering deep power-

down also clears the status register and sets the ISM to

the read array mode.

MEMORY ARCHITECTURE

The MT28F800B5 and MT28F008B5 memory array

architecture is designed to allow sections to be erased

without disturbing the rest of the array. The array is

divided into eleven addressable blocks that vary in size

and are independently erasable. When blocks rather

than the entire array are erased, total device endur-

ance is enhanced, as is system flexibility. Only the

Figure 1: Memory Address Maps

Bottom Boot

MT28F800B5/008B5xx-xxB

Top Boot

MT28F800B5/008B5xx-xxT

WORD ADDRESS

BYTE ADDRESS

WORD ADDRESS

BYTE ADDRESS

7FFFFh

FFFFFh

7FFFFh

FFFFFh

128KB Main Block

96KB Main Block

16KB Boot Block

70000h

6FFFFh

E0000h

DFFFFh

7E000h

7DFFFh

7D000h

7CFFFh

7C000h

7BFFFh

FC000h

FBFFFh

FA000h

F9FFFh

F8000h

F7FFFh

8KB Parameter Block

60000h

5FFFFh

C0000h

BFFFFh

96KB Main Block

128KB Main Block

50000h

4FFFFh

A0000h

9FFFFh

70000h

6FFFFh

E0000h

DFFFFh

40000h

3FFFFh

80000h

7FFFFh

60000h

5FFFFh

C0000h

BFFFFh

30000h

2FFFFh

60000h

5FFFFh

50000h

4FFFFh

A0000h

9FFFFh

20000h

1FFFFh

40000h

3FFFFh

40000h

3FFFFh

80000h

7FFFFh

30000h

2FFFFh

60000h

5FFFFh

10000h

0FFFFh

20000h

1FFFFh

20000h

1FFFFh

40000h

3FFFFh

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

8KB Parameter Block

10000h

0FFFFh

20000h

1FFFFh

16KB Boot Block

00000h

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

8

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

Parameter Blocks

Status Register

The two 8KB parameter blocks store less sensitive

and more frequently changing system parameters and

also may store configuration or diagnostic coding.

These blocks are enabled for erasure when the VPP pin

is at VPPH. No super-voltage unlock or WP# control is

required.

Performing a READ of the status register requires

the same input sequencing as a READ of the array

except that the address inputs are “Don’t Care.” The

status register contents are always output on DQ0–

DQ7, regardless of the condition of BYTE# on the

MT28F800B5. DQ8–DQ15 are LOW when BYTE# is

HIGH, and DQ8–DQ14 are High-Z when BYTE# is

LOW. Data from the status register is latched on the

falling edge of OE# or CE#, whichever occurs last. If the

contents of the status register change during a read of

the status register, either OE# or CE# may be toggled

while the other is held LOW to update the output.

Following a WRITE or ERASE, the device automati-

cally enters the status register read mode. In addition,

a READ during a WRITE or ERASE produces the status

register contents on DQ0–DQ7. When the device is in

the erase suspend mode, a READ operation produces

the status register contents until another command is

issued. In certain other modes, READ STATUS REGIS-

TER may be given to return to the status register read

mode. All commands and their operations are

described in the Command Set and Command Execu-

tion sections.

Main Memory Blocks

The eight remaining blocks are general-purpose

memory blocks and do not require a super-voltage on

RP# or WP# control to be erased or written. These

blocks are intended for code storage, ROM-resident

applications or operating systems that require in-sys-

tem update capability.

OUTPUT (READ) OPERATIONS

The MT28F800B5 and MT28F008B5 feature three

different types of READs. Depending on the current

mode of the device, a READ operation produces data

from the memory array, status register or device iden-

tification register. In each of these three cases, the

WE#, CE# and OE# inputs are controlled in a similar

manner. Moving between modes to perform a specific

READ is described in the Command Execution section.

Identification Register

A READ of the two 8-bit device identification regis-

ters requires the same input sequencing as a READ of

the array. WE# must be HIGH, and OE# and CE# must

be LOW. However, ID register data is output only on

DQ0–DQ7, regardless of the condition of BYTE# on the

MT28F800B5. A0 is used to decode between the two

bytes of the device ID register; all other address inputs

are “Don’t Care.” When A0 is LOW, the manufacturer

compatibility ID is output, and when A0 is HIGH, the

device ID is output. DQ8–DQ15 are High-Z when

BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are

00h when the manufacturer compatibility ID is read

and 88h when the device ID is read.

To get to the identification register read mode,

READ IDENTIFICATION may be issued while the

device is in certain other modes. In addition, the iden-

tification register read mode can be reached by apply-

ing a super-voltage (VID) to the A9 pin. Using this

method, the ID register can be read while the device is

in any mode. When A9 is returned to VIL or VIH, the

device will return to the previous mode.

Memory Array

To read the memory array, WE# must be HIGH, and

OE# and CE# must be LOW. Valid data is output on the

DQ pins when these conditions are met, and a valid

address is given. Valid data remains on the DQ pins

until the address changes, or OE# or CE# goes HIGH,

whichever occurs first. The DQ pins continue to out-

put new data after each address transition as long as

OE# and CE# remain LOW.

The MT28F800B5 features selectable bus widths.

When the memory array is accessed as a 512K x 16,

BYTE# is HIGH, and data is output on DQ0–DQ15. To

access the memory array as a 1 Meg x 8, BYTE# must

be LOW, DQ8–DQ14 are High-Z, and all data is output

on DQ0–DQ7. The DQ15/(A-1) pin becomes the lowest

order address input so that 1,048,576 locations can be

read.

After power-up or RESET, the device is automati-

cally in the array read mode. All commands and their

operations are described in the Command Set and

Command Execution sections.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

9

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

INPUT OPERATIONS

The DQ pins are used either to input data to the

array or to input a command to the CEL. A command

input issues an 8-bit command to the CEL to control

the mode of operation of the device. A WRITE is used

to input data to the memory array. The following sec-

tion describes both types of inputs. More information

describing how to use the two types of inputs to write

or erase the device is provided in the Command Execu-

tion section.

Memory Array

A WRITE to the memory array sets the desired bits

to logic 0s but cannot change a given bit to a logic 1

from a logic 0. Setting any bits to a logic 1 requires that

the entire block be erased. To perform a WRITE, OE#

must be HIGH, CE# and WE# must be LOW, and VPP

must be set to VPPH. Writing to the boot block also

requires that the RP# pin be at VHH or WP# be HIGH.

A0–A18 (A19) provide the address to be written, while

the data to be written to the array is input on the DQ

pins. The data and addresses are latched on the rising

edge of CE# (CE#-controlled) or WE# (WE#-con-

trolled), whichever occurs first. A WRITE must be pre-

ceded by a WRITE SETUP command. Details on how to

input data to the array are described in the Write

Sequence section.

Commands

To perform a command input, OE# must be HIGH,

and CE# and WE# must be LOW. Addresses are “Don’t

Care” but must be held stable, except during an ERASE

CONFIRM (described in a later section). The 8-bit

command is input on DQ0–DQ7, while DQ8–DQ15 are

“Don’t Care” on the MT28F800B5. The command is

latched on the rising edge of CE# (CE#-controlled) or

WE# (WE#-controlled), whichever occurs first. The

condition of BYTE# has no effect on a command input.

Selectable bus sizing applies to WRITEs as it does to

READs on the MT28F800B5. When BYTE# is LOW (byte

mode), data is input on DQ0–DQ7, DQ8–DQ14 are

High-Z, and DQ15 becomes the lowest order address

input. When BYTE# is HIGH (word mode), data is

input on DQ0–DQ15.

Table 1:

Command Set

COMMAND

HEX CODE

DESCRIPTION

00h

RESERVED

This command and all unlisted commands are invalid and should not be

called. These commands are reserved to allow for future feature

enhancements.

FFh

90h

READ ARRAY

Must be issued after any other command cycle before the array can be read.

It is not necessary to issue this command after power-up or RESET.

IDENTIFY DEVICE

Allows the device and manufacturer compatibility ID to be read. A0 is used

to decode between the manufacturer compatibility ID (A0 = LOW) and

device ID (A0 = HIGH).

70h

READ STATUS REGISTER

Allows the status register to be read. Please refer to Table 2 for more

information on the status register bits.

50h

20h

CLEAR STATUS REGISTER

ERASE SETUP

Clears status register bits 3-5, which cannot be cleared by the ISM.

The first command given in the two-cycle ERASE sequence. The ERASE is not

completed unless followed by ERASE CONFIRM.

ERASE CONFIRM/RESUME

D0h

The second command given in the two-cycle ERASE sequence. Must follow

an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND

to resume the ERASE.

40h or 10h

B0h

WRITE SETUP

The first command given in the two-cycle WRITE sequence. The write data

and address are given in the following cycle to complete the WRITE.

ERASE SUSPEND

Requests a halt of the ERASE and puts the device into the erase suspend

mode. When the device is in this mode, only READ STATUS REGISTER, READ

ARRAY and ERASE RESUME commands may be executed.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

10Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

COMMAND SET

To simplify writing of the memory blocks, the

MT28F800B5 and MT28F008B5 incorporate an ISM

that controls all internal algorithms for writing and

erasing the floating gate memory cells. An 8-bit com-

mand set is used to control the device. Details on how

to sequence commands are provided in the Command

Execution section. Table 1 lists the valid commands.

in the write, erase, erase suspend or status register read

mode, READ STATUS REGISTER (70h) can be issued to

view the status register contents.

All of the defined bits are set by the ISM, but only

the ISM and erase suspend status bits are reset by the

ISM. The erase, write and VPP status bits must be

cleared using CLEAR STATUS REGISTER. If the VPP sta-

tus bit (SR3) is set, the CEL does not allow further write

or erase operations until the status register is cleared.

This enables the user to choose when to poll and clear

the status register. For example, the host system may

perform multiple BYTE WRITE operations before

checking the status register instead of checking after

each individual WRITE. Asserting the RP# signal or

powering down the device also clears the status regis-

ter.

ISM STATUS REGISTER

The 8-bit ISM status register (see Table 2) is polled

to check for WRITE or ERASE completion or any

related errors. During or following a WRITE, ERASE or

ERASE SUSPEND, a READ operation outputs the status

register contents on DQ0–DQ7 without prior com-

mand. While the status register contents are read, the

outputs are not updated if there is a change in the ISM

status unless OE# or CE# is toggled. If the device is not

Table 2:

Status Register

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

SR6

SR5

SR4

SR3

ISM STATUS

1 = Ready

0 = Busy

The ISMS bit displays the active status of the state machine during

WRITE or BLOCK ERASE operations. The controlling logic polls this bit

to determine when the erase and write status bits are valid.

ERASE SUSPEND STATUS

1 = ERASE suspended

0 = ERASE in progress/completed

Issuing an ERASE SUSPEND places the ISM in the suspend mode and

sets this and the ISMS bit to “1.” The ESS bit remains “1” until an

ERASE RESUME is issued.

ERASE STATUS

1 = BLOCK ERASE error

0 = Successful BLOCK ERASE

ES is set to “1” after the maximum number of ERASE cycles is executed

by the ISM without a successful verify. ES is only cleared by a CLEAR

STATUS REGISTER command or after a RESET.

WRITE STATUS

1 = WORD/BYTE WRITE error

0 = Successful WORD/BYTE WRITE

WS is set to “1” after the maximum number of WRITE cycles is

executed by the ISM without a successful verify. WS is only cleared by a

CLEAR STATUS REGISTER command or after a RESET.

VPP STATUS

1 = No VPP voltage detected

0 = VPP present

VPPS detects the presence of a VPP voltage. It does not monitor VPP

continuously, nor does it indicate a valid VPP voltage. The VPP pin is

sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be

cleared by CLEAR STATUS REGISTER or by a RESET.

SR0-2

RESERVED

Reserved for future use.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

11Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

COMMAND EXECUTION

Commands are issued to bring the device into dif-

ferent operational modes. Each mode allows specific

operations to be performed. Several modes require a

sequence of commands to be written before they are

reached. The following section describes the proper-

ties of each mode, and Table 3 lists all command

sequences required to perform the desired operation.

first cycle. The next cycle is the WRITE, during which

the write address and data are issued and VPP is

brought to VPPH. Writing to the boot block also

requires that the RP# pin be brought to VHH or the WP#

pin be brought HIGH at the same time VPP is brought

to VPPH. The ISM now begins to write the word or byte.

VPP must be held at VPPH until the write is completed

(SR7 = 1).

While the ISM executes the WRITE, the ISM status

bit (SR7) is at “0,” and the device does not respond to

any commands. Any READ operation produces the

status register contents on DQ0–DQ7. When the ISM

status bit (SR7) is set to a logic 1, the WRITE has been

completed, and the device enters status register read

mode until another command is given.

Read Array

The array read mode is the initial state of the device

upon power-up and after a RESET. If the device is in

any other mode, READ ARRAY (FFh) must be given to

return to the array read mode. Unlike the WRITE

SETUP command (40h), READ ARRAY does not need

to be given before each individual read access.

After the ISM has initiated the WRITE, it cannot be

aborted except by a RESET or by powering down the

part. Doing either during a WRITE corrupts the data

being written. If only the WRITE SETUP command has

been given, the WRITE may be nullified by performing

a null WRITE. To execute a null WRITE, FFh must be

written when BYTE# is LOW, or FFFFh must be written

when BYTE# is HIGH. When the ISM status bit (SR7)

has been set, the device is in the status register read

mode until another command is issued.

IDENTIFY DEVICE

IDENTIFY DEVICE (90h) may be written to the CEL

to enter the identify device mode. While the device is

in this mode, any READ produces the device ID when

A0 is HIGH and the manufacturer compatibility ID

when A0 is LOW. The device remains in this mode until

another command is given.

Write Sequence

Two consecutive cycles are needed to input data to

the array. WRITE SETUP (40h or 10h) is given in the

Table 3:

Command Sequences

BUS

FIRST CYCLE

SECOND CYCLE

CYCLES

COMMANDS

REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA NOTES

1

3

2

1

2

WRITE

X

FFh

90h

70h

50h

20h

B0h

40h

10h

1

2, 3

4

READ ARRAY

READ

IA

X

ID

IDENTIFY DEVICE

SRD

READ STATUS REGISTER

CLEAR STATUS REGISTER

ERASE SETUP/CONFIRM

ERASE SUSPEND/RESUME

WRITE SETUP/WRITE

WRITE

BA

X

D0h

WD

5, 6

WA

6, 7

ALTERNATE WORD/BYTE

WRITE

Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.

2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.

3. ID = Identify Data.

4. SRD = Status Register Data.

5. BA = Block Address (A12–A19).

6. Addresses are “Don’t Care” in first cycle but must be held stable.

7. WA = Address to be written; WD = Data to be written to WA.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

12Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

ERASE Sequence

ERASE Suspension

Executing an ERASE sequence sets all bits within a

block to logic 1. The command sequence necessary to

execute an ERASE is similar to that of a WRITE. To pro-

vide added security against accidental block erasure,

two consecutive command cycles are required to ini-

tiate an erase of a block. In the first cycle, addresses are

“Don’t Care,” and ERASE SETUP (20h) is given. In the

second cycle, VPP must be brought to VPPH, an address

within the block to be erased must be issued, and

ERASE CONFIRM (D0h) must be given. If a command

other than ERASE CONFIRM is given, the write and

erase status bits (SR4 and SR5) are set, and the device

is in the status register read mode.

The only command that may be issued while an

ERASE is in progress is ERASE SUSPEND. This com-

mand allows other commands to be executed while

pausing the ERASE in progress. When the device has

reached the erase suspend mode, the erase suspend

status bit (SR6) and ISM status bit (SR7) is set. The

device may now be given a READ ARRAY, ERASE

RESUME or READ STATUS REGISTER command. After

READ ARRAY has been issued, any location not within

the block being erased may be read. If ERASE RESUME

is issued before SR6 has been set, the device immedi-

ately proceeds with the ERASE in progress.

After the ERASE CONFIRM (D0h) is issued, the ISM

starts the ERASE of the addressed block. Any READ

operation outputs the status register contents on

DQ0–DQ7. VPP must be held at VPPH until the ERASE is

completed (SR7 = 1). When the ERASE is completed,

the device is in the status register read mode until

another command is issued. Erasing the boot block

also requires that either the RP# pin be set to VHH or

the WP# pin be held HIGH at the same time VPP is set

to VPPH.

ERROR HANDLING

After the ISM status bit (SR7) has been set, the VPP

(SR3), write (SR4) and erase (SR5) status bits may be

checked. If one or a combination of these three bits

has been set, an error has occurred. The ISM cannot

reset these three bits. To clear these bits, CLEAR STA-

TUS REGISTER (50h) must be given. If the VPP status

bit (SR3) is set, further write or erase operations can-

not resume until the status register is cleared. Table 4

lists the combination of errors.

Table 4:

Status Register Error Decode¹

STATUS BITS

SR5

SR4

SR3

ERROR DESCRIPTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No errors

VPP voltage error

WRITE error

WRITE error, VPP voltage not valid at time of WRITE

ERASE error

ERASE error, VPP voltage not valid at time of ERASE CONFIRM

Command sequencing error or WRITE/ERASE error

Command sequencing error, VPP voltage error, with WRITE and ERASE errors

Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

13Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE ENDURANCE

POWER-UP

The MT28F800B5 and MT28F008B5 are designed

and fabricated to meet advanced firmware storage

requirements. To ensure this level of reliability, VPP

must be at 5V 10% during WRITE or ERASE cycles.

Due to process technology advances, 5V VPP is optimal

for application and production programming.

The likelihood of unwanted WRITE or ERASE, oper-

ations is minimized because two consecutive cycles

are required to execute either operation. However, to

reset the ISM and to provide additional protection

while VCC is ramping, one of the following conditions

must be met:

•

RP# must be held LOW until VCC is at valid func-

tional level; or

POWER USAGE

•

CE# or WE# may be held HIGH and RP# must be

toggled from VCC-GND-VCC.

The MT28F800B5 and MT28F008B5 offer several

power-saving features that may be utilized in the array

read mode to conserve power. Deep power-down

mode is enabled by bringing RP# LOW. Current draw

(ICC) in this mode is a maximum of 20µA. When CE# is

HIGH, the device enters standby mode. In this mode,

maximum ICC current is 130µA. If CE# is brought HIGH

during a WRITE or ERASE, the ISM continues to oper-

ate, and the device consumes the respective active

power until the write or erase is completed.

After a power-up or RESET, the status register is

reset, and the device enters the array read mode.

Figure 2:

Power-Up/Reset Timing Diagram

RP#

Note 1

VCC

(5V)

t

AA

Address

VALID

Data

t

RWH

UNDEFINED

NOTE: 1. VCC must be within the valid operating range before RP#

goes HIGH.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

14Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

SELF-TIMED WRITE SEQUENCE

(WORD OR BYTE WRITE)¹

COMPLETE WRITE

STATUS-CHECK SEQUENCE

Start (WRITE completed)

Start

NO

4, 5

SR3 = 0?

YES

V^PPError

WRITE 40h or 10h

5

SR4 = 0?

YES

BYTE/WORD WRITE Error

V

PP = 5V

WRITE Word or Byte

Address/Data

WRITE Successful

STATUS REGISTER

READ

NO

SR7 = 1?

YES

2

Complete Status

Check (optional)

3

WRITE Complete

Notes: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.

2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register

is cleared.

3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.

4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further

WRITE or ERASE operations are allowed by the CEL.

5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

15Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

SELF-TIMED BLOCK ERASE SEQUENCE¹

COMPLETE BLOCK ERASE

STATUS-CHECK SEQUENCE

Start

Start (ERASE completed)

WRITE 20h

NO

YES

NO

5, 6

SR3 = 0?

YES

VPP Error

VPP = 5V

6

SR4, 5 = 1?

NO

Command Sequence Error

WRITE D0h,

Block Address

6

SR5 = 0?

BLOCK ERASE Error

STATUS REGISTER

READ

YES

ERASE Successful

NO

SR7 = 1?

YES

Suspend ERASE?

YES

4

2

Suspend

Sequence

Complete Status

Check (optional)

ERASE Resumed

3

ERASE Complete

Notes: 1. Sequence may be repeated to erase additional blocks.

2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register

is cleared.

3. To return to the array read mode, the FFh command must be issued.

4. Refer to the ERASE SUSPEND flowchart for more information.

5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further

WRITE or ERASE operations are allowed by the CEL.

6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

16Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

ERASE SUSPEND/RESUME SEQUENCE

Start (ERASE in progress)

WRITE B0h

(ERASE SUSPEND)

VPP = 5V

STATUS REGISTER

READ

NO

SR7 = 1?

YES

SR6 = 1?

YES

ERASE Completed

WRITE FFh

(READ ARRAY)

Done

NO

Reading?

YES

WRITE D0h

(ERASE RESUME)

Resume ERASE

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

17Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

*Stresses greater than those listed under “Absolute

ABSOLUTE MAXIMUM RATINGS*

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other condi-

tions above those indicated in the operational sections

of this specification is not implied. Exposure to abso-

lute maximum rating conditions for extended periods

may affect reliability.

Voltage on VCC Supply Relative to VSS .... -0.5V TO +6V**

Input Voltage Relative to VSS ................... -0.5V TO +6V**

VPP Voltage Relative TO VSS .....................-0.5V TO +5.5V^†

RP# or A9 Pin Voltage Relative to Vss... -0.5V to +12.6V^†

Temperature Under Bias..........................-40ºC to +85ºC

Storage Temperature (plastic) ...............-55ºC to +125ºC

Power Dissipation .......................................................1W

**VCC, input and I/O pins may transition to -2V for

<20ns and VCC + 2V for <20ns.

^†Voltage may pulse to -2V for <20ns and 14V for <20ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING

CONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

VCC

VIH

VIL

4.5

2

5.5

VCC + 0.5

0.8

V

1

Supply Voltage

Input High (Logic 1) Voltage, all inputs

Input Low (Logic 0) Voltage, all inputs

Device Identification Voltage, A9

-0.5

10

VID

12.6

DC OPERATING CHARACTERISTICS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

OUTPUT VOLTAGE LEVELS (TTL)

Output High Voltage (IOH = -2.5mA)

Output Low Voltage (IOL = 5.8mA)

VOH1

VOL

2.4

–

V

1

0.50

VOH2

IL

VCC - 0.4

–

V

1

OUTPUT VOLTAGE LEVELS (CMOS)

Output High Voltage (IOH = -100µA)

INPUT LEAKAGE CURRENT

Any input (0V ≤ VIN ≤ VCC); All other pins not under test = 0V

-1

–

1

µA

IID

500

10

INPUT LEAKAGE CURRENT: VHH INPUT

(10V ≤ VHH ≤ 12.6V = VID)

IHH

IOZ

–

INPUT LEAKAGE CURRENT: RP# INPUT

(10V ≤ RP# ≤ 12.6V = VHH)

OUTPUT LEAKAGE CURRENT

-10

(DOUT is disabled; 0V ≤ VOUT ≤ VCC)

Notes: 1. All voltages referenced to VSS.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

18Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

CAPACITANCE

(T_A= +25ºC; f = 1 MHz)

PARAMETER/CONDITION

SYMBOL

MAX

UNITS

Input Capacitance

CI

9

pF

Output Capacitance

CO

12

READ AND STANDBY CURRENT DRAIN¹

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

MAX

UNITS

NOTES

ICC1

55

mA

2, 3

READ CURRENT: WORD-WIDE, TTL INPUT LEVELS

(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)

READ CURRENT: WORD-WIDE, CMOS INPUT LEVELS

(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC

- 0.2V; RP# ≥ VCC - 0.2V)

ICC2

50

mA

2, 3

ICC3

ICC4

55

50

mA

2, 3

READ CURRENT: BYTE-WIDE, TTL INPUT LEVELS

(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)

READ CURRENT: BYTE-WIDE, CMOS INPUT LEVELS

CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC -

0.2V; RP# = VCC - 0.2V)

ICC5

2

mA

STANDBY CURRENT: TTL INPUT LEVELS

VCC power supply standby current (CE# = RP# = VIH;

Other inputs = VIL or VIH)

ICC6

ICC8

IPP1

IPP2

130

20

15

5

µA

STANDBY CURRENT: CMOS INPUT LEVELS

VCC power supply standby current (CE# = RP# = VCC - 0.2V)

DEEP POWER-DOWN CURRENT: VCC SUPPLY

(RP# = VSS 0.2V)

STANDBY OR READ CURRENT:

VPP SUPPLY (VPP ≤ 5.5V)

DEEP POWER-DOWN CURRENT: VPP SUPPLY

(RP# = VSS 0.2V)

Notes: 1. Vcc = MAX VCC during Icc tests.

2. Icc is dependent on cycle rates.

3. Icc is dependent on output loading. Specified values are obtained with the outputs open.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

19Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

READ TIMING PARAMETERS

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +5V 10%

AC CHARACTERISTICS

PARAMETER

-8/-8 ET

SYMBOL

MIN

MAX

UNITS

NOTES

^tRC

^tACE

^tAOE

^tAA

^tRWH

^tOD

80

ns

Read cycle time

80

40

1

Access time from CE#

Access time from OE#

80

Access time from address

1,000

20

RP# HIGH to output valid delay

OE# or CE# HIGH to output in High-Z

Output hold time from OE#, CE# or address change

RP# LOW pulse width

^tOH

^tRP

0

60

Notes: 1. OE# may be delayed by ^tACE - ^tAOE after CE# falls before ^tACE is affected.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

20Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

AC TEST CONDITIONS

Input pulse levels ......................................0.4V to 2.4V

Input rise and fall times.......................................<10ns

Input timing reference level .................... 0.8V and 2V

Output timing reference level ................. 0.8V and 2V

Output load........................1 TTL gate and CL = 100pF

WORD-WIDE READ CYCLE¹

V_IH

V_IL

A0–A18/(A19)

VALID ADDRESS

t

RC

t

AA

V_IH

V_IL

CE#

t

ACE

V_IH

V_IL

OE#

V_IH

V_IL

WE#

t

OD

t

AOE

OH

V_IH

V_IL

VALID DATA

DQ0–DQ15

t

RWH

V_IH

VIL

RP#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T ≤ +70ºC)

A

Extended Temperature (-40ºC ≤ T ≤ +85ºC)

A

-8/-8 ET

SYMBOL

MIN

MAX

UNITS

SYMBOL

MIN

MAX

UNITS

t

RC

80

ns

RWH

1,000

20

ns

t

80

40

80

ACE

OD

t

0

AOE

OH

t

AA

Notes: 1. BYTE# = HIGH (MT28F800B5 only).

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

21Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

BYTE-WIDE READ CYCLE¹

V_IH

V_IL

A0–A18/(A19)

VALID ADDRESS

t

RC

t

AA

V_IH

V_IL

CE#

t

ACE

V_IH

V_IL

OE#

V_IH

V_IL

WE#

t

OD

t

AOE

OH

V_IH

V_IL

VALID DATA

DQ0–DQ7

V_IH

V_IL

HIGH-Z

DQ8–DQ14

t

RWH

V_IH

V_IL

RP#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-8/-8 ET

SYMBOL

MIN

MAX

UNITS

SYMBOL

MIN

MAX

UNITS

t

80

ns

1,000

20

ns

RC

RWH

t

ACE

80

40

80

OD

t

0

AOE

OH

t

AA

Notes: 1. BYTE# = LOW (MT28F800B5 only).

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

22Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

RECOMMENDED DC WRITE/ERASE CONDITIONS¹

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +5V 10%

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

VPP WRITE/ERASE lockout voltage

VPP voltage during WRITE/ERASE operation

Boot block unlock voltage

VPPLK

VPPH

VHH

–

4.5

10

2

1.5

5.5

12.6

–

V

2

3

VCC WRITE/ERASE lockout voltage

VLKO

WRITE/ERASE CURRENT DRAIN

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +5V 10%

PARAMETER/CONDITION

SYMBOL

MAX

UNITS

NOTES

WORD WRITE CURRENT: VCC SUPPLY

WORD WRITE CURRENT: VPP SUPPLY

BYTE WRITE CURRENT: VCC SUPPLY

BYTE WRITE CURRENT: VPP SUPPLY

ERASE CURRENT: VCC SUPPLY

ICC9

IPP3

25

20

25

20

30

40

10

mA

4

5

ICC10

IPP4

ICC11

IPP5

ERASE CURRENT: VPP SUPPLY

ERASE SUSPEND CURRENT: VCC SUPPLY

(ERASE suspended)

ICC12

6

IPP6

200

µA

ERASE SUSPEND CURRENT: VPP SUPPLY

(ERASE suspended)

Notes: 1. WRITE operations are tested at VPP voltages equal to or less than the previous erase.

2. Absolute WRITE/ERASE protection when VPP ≤ VPPLK.

3. When 5V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE

operations.

4. Applies to MT28F800B5 only.

5. Applies to MT28F008B5 and MT28F800B5 with BYTE# = LOW.

6. Parameter is specified when device is not accessed. Actual current draw will be Icc12 plus read current if a READ

is executed while the device is in erase suspend mode.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

23Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS: WE#- (CE#-)CONTROLLED WRITES

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +5V 10%

AC CHARACTERISTICS

-8/-8 ET

PARAMETER

SYMBOL

MIN

MAX

UNITS

ns

NOTES

^tWC

^tWPH (^tCPH)

^tWP (^tCP)

^tAS

80

30

WRITE cycle time

ns

WE# (CE#) HIGH pulse width

WE# (CE#) pulse width

50

ns

50

ns

Address setup time to WE# (CE#) HIGH

Address hold time from WE# (CE#) HIGH

Data setup time to WE# (CE#) HIGH

Data hold time from WE# (CE#) HIGH

CE# (WE#) setup time to WE# (CE#) LOW

CE# (WE#) hold time from WE# (CE#) HIGH

VPP setup time to WE# (CE#) HIGH

RP# HIGH to WE# (CE#) LOW delay

RP# at VHH or WP# HIGH setup time to WE# (CE#) HIGH

WRITE duration (WORD or BYTE WRITE)

Boot BLOCK ERASE duration

^tAH

^tDS

^tDH

0

ns

50

ns

0

ns

^tCS (^tWS)

^tCH (^tWH)

^tVPS1

^tRS

0

ns

0

ns

200

1,000

100

4.5

100

500

200

0

ns

1

ns

^tRHS

ns

2

4

3

4

2

5

^tWED1

^tWED2

^tWED3

^tWED4

^tWB

^tVPH

^tRHH

^tREL

µs

ms

ns

Parameter BLOCK ERASE duration

Main BLOCK ERASE duration

WE# (CE#) HIGH to busy status (SR7 = 0)

VPP hold time from status data valid

RP# at VHH or WP# HIGH hold time from status data valid

Boot block relock delay time

ns

0

ns

100

ns

WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS

PARAMETER

TYP

MAX

UNITS

NOTES

0.5

1.5

1

7

14

–

s

6

Boot/parameter BLOCK ERASE time

Main BLOCK ERASE time

6

6, 7, 8

Main BLOCK WRITE time (byte mode)

Main BLOCK WRITE time (word mode)

1

–

Notes: 1. Measured with VPP = VPPH = 5V.

2. RP# should be held at VHH OR WP# held HIGH until boot block WRITE or ERASE is complete.

3. Polling status register before ^tWB is met may falsely indicate WRITE or ERASE completion.

4. WRITE/ERASE times are measured to valid status register data (SR7 = 1).

5. ^tREL is required to relock boot block after WRITE or ERASE to boot block.

6. Typical values measured at T_A= +25ºC.

7. Assumes no system overhead.

8. Typical WRITE times use checkerboard data pattern.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

24Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

WE#-CONTROLLED WRITE/ERASE

V_IH

V_IL

A0–A18/(A19)

Note 1

AIN

t

AH

t

AH

AS

V_IH

V_IL

CE#

OE#

t

CH

CS

V_IH

V_IL

t

WC

t

WP

t

WED1/2/3/4

WPH

V_IH

V_IL

t

WB

WE#

t

DH

t

DS

V_IH

V_IL

DQ0–DQ7/

Status

(SR7=0)

CMD

in

CMD/

Data-in

Status

(SR7=1)

CMD

in

DQ0–DQ15 ²

t

RS

RHS

RHH

V_HH

[Unlock boot block]

[5V VPP]

V_IH

RP# ³

V_IL

V_IH

WP# ³

V_IL

t

VPH

VPS1

V_PPH1

V_IL

VPP

WRITE or ERASE (block)

address asserted, and

WRITE data or ERASE

CONFIRM issued

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

WRITE SETUP or

ERASE SETUP input

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-8/-8 ET

MAX

SYMBOL

MIN

MAX

UNITS

SYMBOL

MIN

UNITS

t

80

30

50

0

ns

1,000

100

4.5

100

500

200

0

ns

µs

WC

RS

t

WPH

RHS

t

WP

WED1

WED2

WED3

WED4

WB

t

ms

ns

AS

t

AH

t

50

0

DS

t

DH

t

0

ns

CS

VPH

t

0

ns

CH

RHH

t

200

VPS1

Notes: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

25Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

CE#-CONTROLLED WRITE/ERASE

V_IH

V_IL

A0–A18/(A19)

Note 1

AIN

t

AH

t

AH

AS

V_IH

V_IL

WE#

OE#

t

WH

WS

V_IH

V_IL

t

WC

t

CP

t

WED1/2/3/4

CPH

V_IH

V_IL

CE#

t

WB

t

DH

t

DH

t

DS

V_IH

V_IL

Status

(SR7=0)

CMD

in

CMD/

Data-in

Status

(SR7=1)

CMD

in

DQ0–DQ7/

DQ0–DQ15 ²

t

RS

RHS

RHH

V_HH

[Unlock boot block]

V_IH

RP# ³

V_IL

[Unlock boot block]

[5V VPP]

V_IH

WP# ³

V_IL

t

VPH

VPS1

V_PPH1

V_IL

VPP

WRITE or ERASE (block)

address asserted, and

WRITE data or ERASE

CONFIRM issued

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

WRITE SETUP or

ERASE SETUP input

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-8/-8 ET

MAX

SYMBOL

MIN

MAX

UNITS

SYMBOL

MIN

UNITS

t

80

ns

1,000

100

4.5

100

500

200

0

ns

WC

RS

t

30

50

0

ns

µs

WPH

RHS

t

4

CP

WED1

WED2

WED3

WED4

WB

ms

ns

AS

AH

DS

50

0

DH

WS

WH

VPS1

0

ns

VPH

0

ns

RHH

200

Notes: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

26Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

40-PIN PLASTIC TSOP I

(10mm x 20mm)

.795 (20.20)

.780 (19.80)

.727 (18.47)

.721 (18.31)

.0197 (0.50)

TYP

.010 (0.25)

1

40

PIN #1 INDEX

.397 (10.08)

.391 (9.93)

.010 (0.25)

.006 (0.15)

20

21

.010 (0.25)

.004 (0.10)

.007 (0.18)

.005 (0.13)

GAGE

PLANE

.047 (1.20)

MAX

SEE DETAIL A

.008 (0.20)

.002 (0.05)

.024 (0.60)

.016 (0.40)

.0315 (0.80)

DETAIL A

Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

27Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

48-PIN PLASTIC TSOP I

(10mm x 20mm)

.795 (20.20)

.780 (19.80)

.727 (18.47)

.721 (18.31)

.0197 (0.50)

TYP

.010 (0.25)

1

48

PIN #1 INDEX

.475 (12.07)

.469 (11.91)

.010 (0.25)

.006 (0.15)

24

25

.010 (0.25)

.004 (0.10)

.007 (0.18)

.005 (0.12)

SEE DETAIL A

GAGE

PLANE

.047 (1.20) MAX

.008 (0.20)

.002 (0.05)

.024 (0.60)

.016 (0.40)

.0315 (0.80)

DETAIL A

Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

28Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

44-PIN PLASTIC SOP

(600 Mil)

1.113 (28.27)

1.107 (28.12)

.007 (0.18)

.020 (0.50)

.015 (0.38)

.005 (0.13)

.050 (1.27)

TYP

.643 (16.34)

.620 (15.74)

.499 (12.68)

.493 (12.52)

PIN #1 INDEX

.030 (0.76)

SEE DETAIL A

.004 (0.10)

.016 (0.40)

.010 (0.25)

.106 (2.70) MAX

GAGE PLANE

.010 (0.25)

.0315 (0.80)

DETAIL A

(ROTATED 90 CW)

.066 (1.72)

Notes: 1. Contact factory for availability

2. All dimensions in millimeters MAX/MIN or typical where noted.

3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

DATA SHEET DESIGNATION

No Marking This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are

subject to change, as further product development and data characterization sometimes occur.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

29Micron Technology, Inc. Reserves the right to change products or specifications without notice.

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

REVISION HISTORY

Rev. 3, ...............................................................................................................................................................................8/02

•

Removed PRELIMINARY designation

Changed ^tRS from 600ns (MIN) to 1,000ns (MIN)

Changed VOL from 0.45V (MAX) to 0.50V (MAX)

Rev. 2, PRELIMINARY....................................................................................................................................................12/01

•

Updated input capacitance specification

Updated ^tRWH specification

Original document, PRELIMINARY, Rev. 1....................................................................................................................7/01

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the Micron and M logos are trademarks and/or service marks of Micron Technology, Inc.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

Micron Technology, Inc. Reserves the right to change products or specifications without notice.

30


型号：	MT28F800B5
厂家：	MICRON TECHNOLOGY
描述：	FLASH MEMORY FL灰内存
文件：	总30页 (文件大小：1180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT28F800B5 [MICRON]

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