MT28S2M32B1LC [MICRON]
SYNCFLASH MEMORY; SyncFlash内存型号: | MT28S2M32B1LC |
厂家: | MICRON TECHNOLOGY |
描述: | SYNCFLASH MEMORY |
文件: | 总60页 (文件大小:1464K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
‡
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
SYNCFLASH®
MEMORY
MT28S4M16B1LC – 1 Meg x 16 x 4 banks
MT28S2M32B1LC – 512K x 32 x 4 banks
FEATURES
• PC133 SDRAM-compatible read timing
• Fully synchronous; all signals registered on
positive edge of system clock
PINASSIGNMENT(TopView)
86-PinTSOP
x32
x16
x16
x32
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths:
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
1
2
3
4
5
6
7
8
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
V
SS
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
NC
1, 2 , 4, 8, or full page (read)
1, 2, 4, or 8 (write)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
• LVTTL-compatible inputs and outputs
• Single 3.0V–3.6V power supply
Additional VHH hardware protect mode (RP#)
• Supports CAS latency of 1, 2, and 3
• Four-bank architecture supports true concurrent
operation with zero latency
Read any bank while programming or erasing
any other bank
• Deep power-down mode: 50µA (MAX)
• Cross-compatible Flash memory command set
VCCQ
DQ8
NC
VCC
VCC
VSS
VSS
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
DQM0
WE#
CAS#
RAS#
CS#
DQM1 DQM1
DNU
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
A9
NC
CLK
CKE
A11
A8
A7
A6
A5
A4
A3
NC
BA0
BA1
A10
A0
A1
A2
MCL
VCC
A2
DQM2
VCC
DQM3 MCL
VSS
VSS
RP#
RP#
VCCP
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
DQ24
VSS
VCCP
DNU
VCCQ
DNU
DNU
VSSQ
DNU
DNU
VCCQ
DNU
DNU
VSSQ
DNU
VSS
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
DNU
VSSQ
DNU
DNU
VCCQ
DNU
DNU
VSSQ
DNU
DNU
VCCQ
DNU
VCC
OPTIONS
• Configuration
MARKING
4 Meg x 16 (1 Meg x 16 x 4 banks)
2 Meg x 32 (512K x 32 x 4 banks)
4M16
2M32
• Read Timing (Cycle Time)
5.4ns @ CL3 (143 MHz)
5.4ns @ CL3 (133 MHz)
-7E
-75
NOTE: 1. The # symbol indicates signal is active LOW.
• Packages
2. FBGA ball assignment is on the next page.
86-pin OCPL2 TSOP (400 mil)
90-ball FBGA
TG
FG
KEYTIMINGPARAMETERS
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
None
ET1
ACCESS
SPEED
CLOCK
TIME
SETUP HOLD
TIME
GRADE FREQUENCY CL = 2* CL = 3* TIME
NOTE: 1. Contact factory for availability.
-7E
-7E
-75
-75
143 MHz
133 MHz
133 MHz
100 MHz
5.4ns 1.5ns 0.8ns
1.5ns 0.8ns
2. Off-center parting line.
5.4ns
6ns
Part Number Example:
5.4ns 1.5ns 0.8ns
1.5ns 0.8ns
MT28S4M16B1LCTG-7E
* CL = CAS (READ) Latency
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
©2002,MicronTechnology,Inc.
1
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRONWITHOUTNOTICE.PRODUCTSAREONLYWARRANTEDBYMICRONTOMEETMICRON’SPRODUCTIONDATASHEETSPECIFICATIONS.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
FBGABALLASSIGNMENT(TopView)
90-Ball FBGA – 2 Meg x 32
90-Ball FBGA – 4 Meg x 16
1
2
3
7
8
9
1
2
3
7
8
9
DNU
DNU
VSS
Vcc
DNU
DNU
A
B
C
D
E
DQ26
DQ24
VSS
Vcc
DQ23
DQ21
A
B
C
D
E
DNU
VSSQ
VSSQ
VccQ
VSS
VccQ
DNU
DNU
DNU
MCL
A5
VSSQ
DNU
DNU
NC
VccQ
DNU
DNU
NC
VSSQ
DNU
DNU
DNU
MCL
A0
DNU
VccQ
VccQ
VssQ
Vcc
DQ28
VSSQ
VSSQ
VccQ
VSS
VccQ
DQ27
DQ29
DQ31
DQM3
A5
VSSQ
DQ25
DQ30
NC
VccQ
DQ22
DQ17
NC
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ19
VccQ
VccQ
VssQ
Vcc
A3
A2
F
A3
A2
F
A4
A6
A10
NC
A1
G
H
J
A4
A6
A10
NC
A1
G
H
J
A7
A8
VccP
A11
A9
BA1
CS#
NC
A7
A8
VccP
A9
BA1
NC
CLK
CKE
BA0
CAS#
Vcc
RAS#
DQM0
VSSQ
VccQ
VccQ
DQ4
DQ2
CLK
CKE
BA0
CAS#
Vcc
CS#
RAS#
DQM0
VSSQ
VccQ
VccQ
DQ4
DQ2
DQM1
VccQ
VSSQ
VSSQ
DQ11
DQ13
RP#
WE#
DQ7
DQ5
DQ3
VSSQ
DQ0
K
L
DQM1
VccQ
VSSQ
VSSQ
DQ11
DQ13
RP#
DNU
Vss
WE#
DQ7
DQ5
DQ3
VSSQ
DQ0
K
L
DQ8
DQ10
DQ12
VccQ
DQ15
Vss
DQ8
DQ9
DQ14
VSSQ
Vss
DQ6
DQ1
VccQ
Vcc
M
N
P
DQ10
DQ12
VccQ
DQ15
DQ9
DQ14
VSSQ
Vss
DQ6
DQ1
VccQ
Vcc
M
N
P
R
R
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
2
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
GENERALDESCRIPTION
This 64Mb SyncFlash® data sheet is divided into
two major sections. The SDRAM Interface Functional
Description details compatibility with the SDRAM
memory, and the Flash Memory Functional Descrip-
tion specifies the symmetrical-sectored Flash architec-
ture and functional commands.
to be accessed. The address bits registered coincident
with the READ command are used to select the starting
column location for the burst access.
The 64Mb devices provide for programmable read
burst lengths of 1, 2, 4, or 8 locations, or the full page,
with a burst terminate option. The x16 device features
an 8-word internal write buffer and the x32 features an
8-Dword internal write buffer that support mode regis-
ter programmed burst write compatibility of 1, 2, 4, or 8
locations.
SyncFlash memory uses an internal pipelined archi-
tecture to achieve high-speed operation.
The 64Mb devices are designed to operate in 3.3V,
low-power memory systems. A deep power-down mode is
provided, along with a power-saving standby mode. All
inputs and outputs are LVTTL-compatible.
Micron’s 64Mb SyncFlash devices are nonvolatile,
electrically sector-erasable (Flash), programmable
read-only memory containing 67,108,864 bits. Each of
the x16’s 16,777,216-bit banks is organized as 4,096
rows by 256 columns by 16 bits. Each of the x32’s
16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32 bits.
The 64Mb devices are organized into 16 indepen-
dently erasable blocks. To ensure that critical firmware
is protected from accidental erasure or overwrite, the
devices feature sixteen (x32: 128K-Dword; x16: 256K-
word) hardware and software-lockable blocks.
A four-bank architecture supports true concurrent
operations. A read access to any bank can occur simul-
taneously with a background PROGRAM or ERASE op-
eration to any other bank.
SyncFlash memory offers substantial advances in
Flash operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation and the capability
to randomly change column addresses on each clock
cycle during a burst access.
All Flash operations are performed using either a
hardware command sequence (HCS) or a software com-
mand sequence (SCS). HCS operations are used by
memory controllers with native SyncFlash support.
Standard SDRAM controllers can use SCS to perform
Flash operations.
SyncFlash memory has a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CLK). Read accesses to the memory are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, followed by a READ com-
mand. The address bits registered coincident with the
ACTIVE command are used to select the bank and row
Please refer to Micron’s Web site (www.micron.com/
flash) for the latest data sheet.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
3
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TABLEOFCONTENTS
Functional Block Diagram – 4 Meg x 16 ...............
– 2 Meg x 32 ...............
5
6
7
Command Execution Logic (CEL)............... 31
Internal State Machine (ISM) ...................... 31
ISM Status Register ...................................... 31
Output (READ) Operations .............................. 32
Memory Array ............................................. 33
Status Register .............................................. 33
Device Configuration Register ..................... 33
Input Operations .............................................. 33
Memory Array ............................................. 33
Command Execution........................................ 33
Status Register .............................................. 33
Device Configuration .................................. 34
Program Sequence ....................................... 34
Erase Sequence ............................................. 34
Program and Erase NVMode Register ......... 34
Block Protect/Unprotect Sequence.............. 35
Device Protect Sequence .............................. 35
Chip Initialize Sequence .............................. 35
Disable LCR Sequence .................................. 36
Reset/Deep Power-Down Mode ....................... 36
Error Handling .................................................. 36
Program/Erase Cycle Endurance ....................... 36
Absolute Maximum Ratings ............................. 45
DC Electrical Characteristics
Pin and Ball Descriptions .......................................
SDRAM Interface Functional Description ....... 10
Initialization...................................................... 10
Register Definition............................................. 10
Mode Register .............................................. 10
Burst Length............................................ 10
Burst Type ............................................... 12
CAS Latency............................................ 12
Operating Mode ..................................... 12
Write Burst Mode ................................... 12
Commands........................................................ 13
Truth Table 1 (Commands and DQM Operation) ........ 13
Truth Table 2a (Harware Command
Sequences[HCS]) ................................................. 14
Truth Table 2b (Software Command
Sequences[SCS]) .................................................. 15
Command Inhibit........................................ 18
No Operation (NOP) ................................... 18
Load Mode Register ..................................... 18
Active............................................................ 18
Read ............................................................. 18
Write ............................................................ 18
Active Terminate .......................................... 18
Burst Terminate............................................ 18
Load Command Register ............................. 18
Operation .......................................................... 19
Bank/Row Activation .................................. 19
Reads ............................................................ 20
Write Bursts .................................................. 25
Active Terminate .......................................... 25
Power-Down ................................................ 25
Clock Suspend ............................................. 25
Burst Read/Single Write ............................... 26
Truth Table 3 (CKE) .................................................. 27
Truth Table 4 (Current State, Same Bank) .................. 28
Truth Table 5 (Current State, Different Bank) ............. 29
and Operating Conditions .......................... 45
ICC Specifications and Conditions .................... 46
Capacitance....................................................... 46
Electrical Characteristics and Recommended
AC Operating Conditions (Timing Table) .. 47
AC Functional Characteristics .......................... 48
Timing Waveforms
Initialize and Load Mode Register
RP# .............................................................. 49
FCS .............................................................. 50
Clock Suspend Mode........................................ 51
Reads
Read ............................................................. 52
Alternating Bank Read Accesses .................. 53
Full-Page Burst ............................................. 54
DQM Operation .......................................... 55
Program/Erase
Flash Memory Functional Description............ 30
Flash Command Sequences .............................. 30
Hardware Command Sequence (HCS) ....... 30
Software Command Sequence (SCS).......... 30
Memory Architecture ........................................ 31
Protected Blocks ........................................... 31
Bank a followed by READ to bank a .......... 56
Bank a followed by READ to bank b .......... 57
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
4
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
D E C O D E
C O M M
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
5
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
D E C O D E
C O M M A
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
6
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
PINANDBALLDESCRIPTIONS
TSOP PIN FBGA BALL
NUMBERS NUMBERS SYMBOL
TYPE
DESCRIPTION
68
J1
CLK
Input Clock: CLK is driven by the system clock. All SyncFlash memory
input signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the output
registers.
67
J2
CKE
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides STANDBY opera-
tion or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down
modes, where CKE becomes asynchronous until after exiting
the same mode. The input buffers, including CLK, are disabled
during power-down modes, providing low standby power.
CKE may be tied HIGH in systems where power-down modes
(other than RP# deep power-down) are not required.
20
J8
CS#
Input Chip Select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
19, 18, 17
16, 71
J9, K7, K8
K9, K1
RAS#,
CAS#, WE#
Input Command Inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
x16: DQM0, Input Input/Output Mask: DQM is an input mask signal for write
DQM1
accesses and an output enable signal for read accesses. Input
data is masked when DQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (after a
two-clock latency) when DQM is sampled HIGH during a READ
cycle. For x16, DQM0 corresponds to DQ0–DQ7, DQM1
corresponds to DQ8–DQ15. For x32, DQM0 corresponds to
DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corre-
sponds to DQ16–DQ23, DQM3 corresonds to DQ24–DQ31.
DQM0–DQM3 are in the same state when referenced as DQM.
16, 71, 28, K9, K1, F8, x32: DQM0
59
F2
–DQM3
A0–A11
25–27,
60–66, 24, F3, G1, G2,
G8, G9, F7,
Input Address Inputs: A0–A11 are sampled during the ACTIVE
command (row address A0–A11 [x16]; A0–A10 [x32]) and
READ/WRITE command (column-address A0–A7) to select one
location in the respective bank. The address inputs provide the
op-code during a LOAD MODE REGISTER command and the
com-code during an LCR command. For x16: A11 is pin 66 (J3),
and A9 is pin 70 (K3).
70
G3, H1, H2,
J3, K3, G7
22, 23
J7, H8
BA0, BA1
Input Bank Address Input(s): BA0, BA1 define to which bank the
ACTIVE, READ, or WRITE command is being applied.
(continued on next page)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
7
©2002,MicronTechnology,Inc.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
PIN AND BALL DESCRIPTIONS (continued)
TSOP PIN FBGA BALL
NUMBERS NUMBERS SYMBOL
TYPE
DESCRIPTION
30 K2 RP#
Input Initialize/Power-Down: Upon initial device power-up, a 100µs
delay after RP# has transitioned from LOW to HIGH is required
for internal device initialization, prior to issuing an executable
command. RP# clears the status register, sets the internal state
machine (ISM) to the array read mode, and places the device in
the deep power-down mode when LOW. All inputs, including
CS#, are “Don’t Care” and all outputs are High-Z. When RP# =
VHH, all protection modes are ignored during PROGRAM and
ERASE. This input also allows the device protect bit to be set to
“1” (protected) and allows the block protect bits at locations 0
and 15 to be set to “0” (unprotected). RP# must be held HIGH
during all other modes of operation.
2, 4, 5, 7, R8, N7, R9, DQ0–DQ15 x16: I/O Data I/O: Data bus.
8, 10, 11, N8, P9, M8,
13, 74, 76, M7, L8, L2,
77, 79, 80, M3, M2, P1,
82, 83, 85, N2, R1, N3,
R2
2, 4, 5, 7, R8, N7, R9, DQ0–DQ31 x32: I/O Data I/O: Data bus.
8, 10, 11, N8, P9, M8,
13, 74, 76, M7, L8, L2,
77, 79, 80, M3, M2, P1,
82, 83, 85, N2, R1, N3,
31, 33, 34, R2, E8, D7,
36, 37, 39, D8, B9, C8,
40, 42, 45, A9, C7, A8,
47, 48, 50, A2, C3, A1,
51, 53, 54, C2, B1, D2,
56
D3, E2
3, 9, 35,
41, 49,
55, 75, 81 M9, P2, P7,
N9
B2, B7, C9,
D9, E1, L1,
VCCQ
VSSQ
Supply DQ Power: Provide isolated power to DQs for improved noise
immunity.
6, 12, 32, B3, B8, C1,
38, 46, 52, D1, E9, L9,
Supply DQ Ground: Provide isolated ground to DQs for improved
noise immunity.
78, 84
M1, N1, P3,
P8
1, 15, 29, A7, F9, L7,
43 R7
44, 58, 72, A3, F1, L3,
VCC
VSS
Supply Power Supply: 3.0V–3.6V.
Supply Ground.
86
R3
(continued on next page)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
8
©2002,MicronTechnology,Inc.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
PIN AND BALL DESCRIPTIONS (continued)
TSOP PIN FBGA BALL
NUMBERS NUMBERS SYMBOL
TYPE
DESCRIPTION
57
H3
VCCP
Supply Program/Erase Supply Voltage: VCCP must be tied externally to
VCC. The VCCP pin sources current during device initialization,
PROGRAM, and ERASE operations.
14, 21, 69, E3, E7, H7,
73 H9
NC
–
No Connect: These pins may be driven or left unconnected.
31, 33, 34, E8, D7, D8, x16: DNU
36, 37, 39, B9, C8, A9,
–
Do Not Use.
40, 42, 45, C7, A8, A2,
47, 48, 50, C3, A1, C2,
51, 53, 54, B1, D2, D3,
56
E2
70
K3
x32: DNU
x16: MCL
28, 59
F8, F2
–
Must connect to Vss.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
9
©2002,MicronTechnology,Inc.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
SDRAMINTERFACE
FUNCTIONALDESCRIPTION
In general, the 64Mb SyncFlash memory devices
(1 Meg x 16 x 4 banks, 512K x 32 x 4 banks) are config-
ured as a quad-bank, nonvolatile SDRAM that operate
at 3.0V–3.6V and include a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 16,777,216-bit banks is
organized as 4,096 rows by 256 columns by 16 bits.
Each of the x32’s 16,777,216-bit banks is organized as
2,048 rows by 256 columns by 32 bits.
mode and ready for mode register programming or an
executable command. After initial programming of the
nvmode register, the contents are automatically loaded
into the mode register during initialization and the
device will power-up in the programmed state.
Note that when VCC is greater than 2.7V, either of the
initialization procedures can be issued.
RegisterDefinition
MODE REGISTER
Read accesses to the SyncFlash memory are identi-
cal to SDR SDRAM operation. Burst accesses start at a
selected location and continue for a programmed num-
ber of locations in a programmed sequence. Accesses
begin with the registration of an ACTIVE command,
followed by a READ command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank; x32: A0–A10, x16: A0–A11 select the
row). The address bits (A0–A7) registered coincident
with the READ command are used to select the starting
column location for the burst access.
All non-READ operations are controlled with either
an HCS or an SCS. Both the HCS and an SCS interface
can be used to initiate any of the internal program,
erase, initialization, or status operations. The term Flash
command sequence (FCS) refers to either HCS or SCS
operation.
The mode register is used to define the specific mode
of operation of the SyncFlash memory. This definition
includes the selection of a burst length, a burst type, a
CAS latency, and an operating mode, as shown in Fig-
ure 1. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is reprogrammed. The nvmode reg-
ister settings are transferred into the mode register
during initialization. The contents of the mode register
may be copied into the nvmode register with a PRO-
GRAM NVMODE REGISTER command. Details on erase
nvmode register and program nvmode register
command sequences are found in the Command Ex-
ecution section of the Flash Memory Functional
Description.
Mode register bits M0–M2 specify the burst length,
M3 specifies the burst type (sequential or interleaved),
M4–M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the WRITE burst mode,
and M10 and M11 are reserved for future use.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Prior to normal operation, the SyncFlash memory
must be initialized. The following sections provide
detailed information covering device initialization, reg-
ister definition, command descriptions, and device op-
eration.
Initialization
The device power-up procedure can be defined two
ways. The first is a hardware initiated power-up, where
power is applied to VCC, VCCQ, and VCCP (simulta-
neously). Then, with the clock stable, RP# must be
brought from LOW to HIGH. After RP# transitions HIGH,
the power-up initialization process will complete within
100µs. The second procedure is defined as a software
initiated power-up. In this case the initialization is
performed using the INITIALIZE DEVICE FCS opera-
tion. When the INITIALIZE DEVICE command is used,
the RP# pin does not require the LOW-to-HIGH transi-
tion typically required for initialization. After the INI-
TIALIZE DEVICE command has been issued, the
power-up initialization process will complete within
100µs.
BURST LENGTH
Read and write accesses to the SyncFlash memory
are burst oriented, with the burst length being pro-
grammable, as shown in Figure 1. The burst length
determines the maximum number of column locations
that can be accessed for a given READ or WRITE com-
mand. Burst lengths of 1, 2, 4, or 8 locations are avail-
able for both the sequential and the interleaved burst
types (read or write), and a full-page burst is available
for the sequential type (read only). The full-page burst
can be used in conjunction with the BURST TERMI-
NATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Early completion of either initialization procedure
can be detected by polling SR7 in the status register.
After initialization, the SyncFlash device is in standby
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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10
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1–A7 when the burst length is set to two, by
A2–A7 when the burst length is set to four, and by A3–
A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) are used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.
Table 1
Burst Definition
Burst
Length
StartingColumn
Address
OrderofAccessesWithinaBurst
Type=Sequential
Type=Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Figure 1
Mode Register Definition
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn,Cn+1,Cn+2
Cn+3,Cn+4...
…Cn-1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
A1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A0
Address Bus
8
1
11 10
9
8
6
5
4
1
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
*Program M11,
M10 = “0, 0” to
ensure compatibility
with future devices.
Burst Length
Full
Page
256
n = A0–A7
M2 M1 M0
M3 = 0
M3 = 1
Notsupported
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
(location0-255)
Cn...
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
NOTE: 1. For a burst length of two, A1–A7 select the block-
of-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A7 select the block-
of-four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A7 select the
block-of-eight burst; A0–A2 select the starting
column within the block.
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0–A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4,
or 8 words) is supported (not full page).
8. The contents of the mode register can be read
usingtheREADDEVICECONFIGURATIONcommand
(004h).
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
BURST TYPE
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 indicates the operating fre-
quencies at which each CAS latency setting can be used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type, and the
starting column address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to one, two, or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
OPERATING MODE
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to READ and
WRITE bursts (full-page burst WRITE not supported).
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via
M0–M2 applies to both read and write bursts; however,
if full-page burst length is selected in conjunction with
M9 = 0, the burst write length is 8 words for the x16 and
8-Dwords for the x32 (not full page). When M9 = 1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
Figure 2
CAS Latency
T0
T1
T2
CLK
COMMAND
READ
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
Table 2
CAS Latency
CAS Latency = 1
ALLOWABLE OPERATING
FREQUENCY (MHz)
T0
T1
T2
T3
CLK
CAS
CAS
CAS
COMMAND
READ
NOP
t
NOP
t
SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3
LZ
OH
DOUT
-7E
-75
£
£
50
50
£
£
133
100
£
£
143
133
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
12
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
COMMANDS
Truth Table 1 provides a quick reference of avail-
able commands for SDRAM-compatible operation. This
is followed by a written description of each command.
Additional truth tables appear later.
TRUTH TABLE 1
SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM ADDR
DQs NOTES
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
H
L
L
L
L
L
L
L
L
–
–
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
ACTIVE (Select bank and activate row)
READ (Select bank, column and start READ burst)
WRITE (Select bank, column and start WRITE)
BURST TERMINATE
Bank/Row
Bank/Col
X
X
2
3
H
H
H
L
L
Bank/Col Valid
3, 4
H
H
L
L
X
Active
X
ACTIVE TERMINATE
L
X
5
6, 7
8
LOAD COMMAND REGISTER
LOAD MODE REGISTER
L
H
L
Com-Code
X
L
L
Op-Code
X
Write Enable/Output Enable
Write Inhibit/Output High-Z
–
–
–
–
–
Active
High-Z
9
–
–
–
H
9
NOTE: 1. CKE is HIGH for all commands shown.
2. x32: A0–A10, x16: A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.
3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.
4. A PROGRAM SETUP command sequence (see Truth Table 2a) must be completed prior to executing a WRITE.
5. ACTIVETERMINATEisfunctionallyequivalenttotheSDRAMPRECHARGEcommand;however, PRECHARGE(deactivaterow
in bank or banks) is not required for SyncFlash memory.
A10 LOW: BA0 and BA1 determine the bank to be active terminated.
A10 HIGH: All banks are active terminated and BA0 and BA1 are “Don’t Care.”
6. A0–A7 define the com-code, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2a.
7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM auto refresh or self refresh mode, which is not required for
SyncFlash memory. LCR is the first cycle for Flash memory hardware command sequences (HCS). See Truth Table 2a.
After the hardware LCR function is disabled, SyncFlash will treat SDRAM REFRESH or AUTO REFRESH commands as NOPs.
A software command sequence (SCS) is available to perform all operations described in Truth Table 2b.
8. A0–A10 define the op-code written to the mode register. The mode register can be dynamically loaded each cycle,
t
provided MRD is satisfied. The default mode register value is stored in the nvmode register. The contents of the
nvmode register are automatically loaded into the mode register during device initialization.
9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
13
COMMANDS
The following Truth Tables provide a quick reference of available
commands for Flash memory interface operation. A written descrip-
tion of each command is found in the Flash Memory Functional
Description section.
TRUTH TABLE 2a – HARDWARE COMMAND SEQUENCES (HCS)
(Notes: 1–5; see notes on page 17)
FIRST CYCLE
BANK
CMD ADDR ADDR DQ RP# CMD
SECOND CYCLE
THIRD CYCLE
BANK
BANK
6
7
8
9
OPERATION
ADDR ADDR DQ RP#
CMD ADDR ADDR DQ
RP#
H
NOTES
READ DEVICE CONFIGURATION
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
PROGRAM SETUP/CONFIRM
LCR
LCR
LCR
LCR
LCR
90h
70h
50h
20h
40h
Bank
X
X
X
X
X
X
H
H
H
H
H
ACTIVE CAROW Bank
X
X
H
H
READ CACOL Bank
X
X
11, 12
ACTIVE
X
X
READ
X
X
H
X
Bank
Bank
ACTIVE Row
ACTIVE Row
Bank
Bank
X
X
H
H
WRITE
WRITE
X
Bank
Bank
D0h H/VHH 12, 13, 14
Col
D
IN
H/VHH
12, 13,
14, 15
10
PROTECT BLOCK/CONFIRM
LCR
60h
Bank
X
H
ACTIVE Row
Bank
X
H
WRITE
X
Bank LBDa(IN) H/VHH
12, 13,
15, 16
PROTECT DEVICE/CONFIRM
LCR
LCR
60h
60h
Bank
Bank
X
X
H
H
ACTIVE
ACTIVE
X
X
Bank
Bank
X
X
H
H
WRITE
WRITE
X
X
Bank LBDa(IN
)
V
HH
12, 13, 16
UNPROTECT BLOCKS/CONFIRM
Bank LBDb(IN) H/VHH
12, 13,
14, 15, 16
UNPROTECT DEVICE/CONFIRM
ERASE NVMODE REGISTER
LCR
LCR
LCR
60h
30h
A0h
Bank
Bank
X
X
X
H
H
H
ACTIVE
ACTIVE
ACTIVE
X
X
X
Bank
Bank
X
X
X
H
H
H
WRITE
WRITE
WRITE
X
X
X
Bank LBDb(IN
)
V
HH
12, 13, 16
12, 13
Bank
C0h
X
H
PROGRAM NVMODE REGISTER
Bank L
Bank L
Bank L
H
H
H
12, 13,
17, 18
DISABLE HARDWARE LCR
CHIP INITIALIZE
LCR
LCR
A0h
68h
Bank U
Bank
X
X
H
H
ACTIVE
ACTIVE
X
X
Bank U
Bank
X
X
H
H
WRITE
WRITE
X
X
Bank U
Bank
X
12, 13,
17, 18, 19
C0h
12, 13
SDRAM
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS)
(Notes: 1, 2, 4, 5; see notes on page 17)
OPERATION
FIRST
CYCLE
10
SECOND
CYCLE
THIRD
CYCLE
FOURTH
CYCLE
FIFTH
CYCLE
SIXTH
CYCLE
SEVENTH
CYCLE
EIGHTH
CYCLE
READ DEVICE CONFIGURATION
Command
ADDR
Bank Address
DQ
Active
88h
X
Write
90h
X
X
H
Active
Read
=
=
=
=
CAROW
CACOL
12
12
Bank
Bank
X
H
X
H
X
H
RP#
READ STATUS REGISTER
Command
Active
Write
Active
Read
ADDR =
Bank Address =
DQ =
88h
X
X
70h
X
X
X
X
X
H
X
X
X
H
RP# =
H
H
CLEAR STATUS REGISTER
Command
Active
Write
ADDR =
Bank Address =
DQ =
88h
X
X
50h
X
X
RP# =
H
H
ERASESETUP/CONFIRM
Command
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
20h
Active
Row
Write
X
ADDR=
BankAddress=
DQ =
X
X
X
H
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
X
H
X
H
55h
H
X
H
A0h
H
X
H
D0h
RP#=
H/VHH
PROGRAM SETUP/CONFIRM
Command
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
40h
Active
Row
Write
Col
ADDR =
Bank Address =
DQ =
X
X
X
H
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
X
H
X
H
55h
H
X
H
A0h
H
X
H
DIN
9
15
RP# =
H/VHH
PROTECT BLOCK/CONFIRM
Command
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
60h
Active
Write
X
11
ADDR =
Bank Address =
DQ =
X
X
X
H
Row
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
16
X
H
X
H
55
H
X
H
A0h
H
X
H
LBDa(IN)
9
15
RP# =
H/VHH
PROTECTDEVICE/CONFIRM
Command
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
60h
Active
X
Write
X
ADDR=
BankAddress=
DQ=
X
X
X
H
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
LBDa(IN)
VHH
16
X
H
X
H
55h
H
X
H
A0h
H
X
H
9
RP# =
(continued on next page)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
15
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS) (continued)
(Notes: 1, 2, 4, 5; see notes on page 17)
OPERATION
FIRST
CYCLE
10,16
SECOND
CYCLE
THIRD
CYCLE
FOURTH
CYCLE
FIFTH
CYCLE
SIXTH
CYCLE
SEVENTH
CYCLE
EIGHTH
CYCLE
UNPROTECTBLOCKS/CONFIRM
Command
ADDR=
Bank Address =
DQ =
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
60h
Active
X
Write
X
X
X
X
H
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
16
X
H
X
H
55h
H
X
H
A0h
H
X
H
LBDb(IN)
5
RP# =
VHH
UNPROTECTDEVICE/CONFIRM
Command
ADDR=
Bank Address =
DQ =
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
60h
Active
X
Write
X
X
X
X
H
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
16
X
H
X
H
55h
H
X
H
A0h
H
X
H
LBDb(IN)
H/VHH
5
RP# =
ERASENVMODEREGISTER
Command
ADDR=
Bank Address =
DQ =
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
30h
Active
X
Write
X
X
X
X
12
12
12
12
12
12
12
Bank
Bank
Bank
Bank
Bank
Bank
Bank
X
H
X
H
55h
H
X
H
A0h
H
X
H
C0h
H
RP# =
H
18
PROGRAMNVMODEREGISTER
Command
ADDR=
Bank Address =
DQ =
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
A0h
Active
X
Write
X
X
X
X
H
12
12
12
12
12
12
12
Bank L
Bank L
Bank L
Bank L
Bank L
A0h
H
Bank L
Bank L
X
H
X
H
55h
H
X
H
X
H
X
H
RP# =
19
DISABLEHARDWARELCR
Command
ADDR=
Active
Write
55
Active
55h
Write
2Ah
Active
80h
Write
A0h
Active
X
Write
X
X
X
X
H
12
12
12
12
12,18
12,18
12,18
Bank Address =
DQ =
RP# =
Bank U
Bank U
Bank U
Bank U
Bank U
A0h
H
Bank U
Bank U
X
H
X
H
55h
H
X
H
X
H
X
H
CHIPINITIALIZE
Command
ADDR=
Active
Write
55h
Active
55h
Write
2Ah
Active
80h
Write
68h
Active
X
Write
X
X
X
H
X
Bank
12
12
12
12
12
12
12
Bank Address =
DQ =
RP# =
Bank
Bank
Bank
Bank
Bank
Bank
X
H
X
H
55h
H
X
H
A0h
H
X
H
C0h
H
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
16
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
NOTE: 1. CMD=Command:decodedfromCS#, RAS#, CAS#, andWE#inputs.
2. NOP/COMMANDINHIBIT/BURSTTERMINATE/ACTIVETERMINATEcommands canbeissuedthroughouttheHCSorSCS.
Additionally,LOADCOMMANDREGISTERmaybeissuedthroughouttheSCS.
3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any
location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence
(see Note 14).
t
4. Tomeetthe RCDspecification, theappropriatenumberofNOP/COMMANDINHIBITcommandsmustbeissuedbetween
ACTIVEandREAD/WRITEcommands.
5. The ERASE, PROGRAM, PROTECT, and UNPROTECT operations are self-timed. The status register may be polled to monitor
theseoperations.
6. x32: A8–A10, x16: A8–A11 are “Don’t Care.”
7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.
8. x32 Data Inputs, DQ8–DQ31 are “Don’t Care” except for DIN, where all DQ31–DQ0 are driven.
x16 Data Inputs, DQ8–DQ15 are "Don’t Care" except for DIN, where all DQ15–DQ0 are driven.
Data Outputs: All unused bits are driven LOW.
9. VHH = 7.0V–8.5V
10. Address must be any row address in the block desired to be protected
11. CAROW, CACOL = Configurationaddress
Thisvaluechangesdependingonthebitlocationbeingaccessed
CAROW = X02h for block protect bit, which corresponds to the block row address: x32: X = 0, 2, 4, or 6h
x16: X = 0, 4, 8, or Ch
For all other bits CAROW = XXXh (“Don’t Care”)
CACOL= Valuesshownbelow
00h = Manufacturer compatibility ID = 2Ch
01h = DeviceIDMT28S4M16B1=D5h
DeviceIDMT28S2M32B1=D4h
02h = Block protect bit (BPB)
03h = Device protect bit (DPB)
04h = Moderegister
05h = Hardware load command register (LCR) bit
06h/07h = Reserved for future use
12. BA = Bank address must match for all the cycles, except for manufacturer ID/device ID/device protect where it is xxh.
13. Thepropercommandsequence(LCR/active/write)isneededtoinitiateanERASE, PROGRAM, PROTECT, orUNPROTECT
operation.
14. If the device protect bit is not set, RP# = VIH unprotects all sixteen ( x32: 128K-Dword, x16: 256K-word ) erasable blocks,
except for blocks 0 and 15. When RP# = VHH, all sixteen ( x32: 128K-Dword, x16: 256K-word) erasable blocks (including
blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# =
VIH, the block protect bits cannot be modified.
15. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, or UNPROTECT operation can still be initiated by
bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.
16. LBDa = Lock bit data
01h = Set block protect bit
F1h = Set device protect bit
If the DPB is not set, RP# = VIH; all blocks can be set
If the DPB is set, RP# = VIH; BPBs cannot be modified
RP# = VHH; all BPBs can be modified
To set DPB, RP# = VHH is a must
RP# = VHH; all blocks including 0 and 15 are unprotected (reset); DPB does not matter
LBDb = Lock bit data
D0h = Clear block and device protect bits
If the DPB is not set, RP# = VIH; all blocks except 0 and 15 are unprotected (reset)
If the DPB is set, RP# = VIH; block protect bits cannot be modified
RP# = VHH; all blocks including 0, 15, and DPB are unprotected (reset)
17. Bank L: [BA1,BA0] = [0,0] or [0,1]
Bank U: [BA1 BA0] = [1,0] or [1,1]
18. If [BA1, BA0] = [0,0] or [0,1], then WRITE NVMODE REGISTER operation is performed. If [BA1, BA0] = [1,0] or [1,1], then
DISABLEHARDWARELCRoperationisperformed.
19. Hardware LCR is preset to “1.” Hardware LCR bit is a one time programmable bit and cannot be reset to “1” after
programmedto“0.”
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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©2002,MicronTechnology,Inc.
17
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64Mb: x16, x32
SYNCFLASH MEMORY
COMMAND INHIBIT
WRITE
The COMMAND INHIBIT function prevents new
commands from being executed by the SyncFlash
memory, regardless of whether the CLK signal is en-
abled. The SyncFlash memory is effectively deselected.
Operations already in progress are not affected.
The WRITE command is used to initiate a burst write
access. A WRITE command must be preceded by LCR/
ACTIVE. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0–A7 se-
lects the column location.
Input data appearing on the DQs is written to the
memory array, subject to the DQM input logic level
appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will
be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that word/column
location. A WRITE command with DQM HIGH is con-
sidered a NOP.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to a SyncFlash memory that is selected
(CS# is LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A10. See
the mode register heading in the Register Definition
section. The LOAD MODE REGISTER command can
only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until
tMRD is met. The data in the nvmode register is auto-
matically loaded into the mode register upon power-
up initialization and is the default mode setting unless
dynamically changed with the LOAD MODE REGIS-
TER command.
ACTIVE TERMINATE
ACTIVE TERMINATE, which replaces the SDRAM
PRECHARGE command, is not required for SyncFlash
memory, but is functionally equivalent to the SDRAM
PRECHARGE command. ACTIVE TERMINATE can be
issued to terminate a BURST READ in progress and
may or may not be bank specific.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated as
shown in the Operation section of this data sheet.
BURST TERMINATE is not bank specific.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs (x32: A0–A10, x16: A0–A11)
selects the row. This row remains active for accesses
until the next ACTIVE command, power-down or reset.
LOAD COMMAND REGISTER (HCS ONLY)
The LOAD COMMAND REGISTER command in the
HCS is used to initiate Flash memory control commands
to the command execution logic (CEL). The CEL re-
ceives and interprets commands to the device. These
commands control the operation of the internal state
machine and the read path (i.e., memory array, ID reg-
ister or status register). However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section of Flash Memory Func-
tional Description for more details.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0–A7 selects the starting column location. Read
data appears on the DQs subject to the logic level on
the DQM input two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was regis-
tered LOW, the DQs will provide valid data.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 3
Activating a Specific Row in a
Specific Bank
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SyncFlash memory, a row in
that bank must be “opened.” (Note: A row will not be
activated for LCR/active/read or LCR/active/write com-
mand sequences. See Flash Memory Architecture sec-
tion for additional information). This is accomplished
via the ACTIVE command, which selects both the bank
and the row to be activated.
CLK
CKE
CS#
HIGH
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
RAS#
t
t
subject to the RCD specification. RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks rounded to 3. This is reflected in Figure 4,
CAS#
WE#
t
which covers any case where 2 < RCD (MIN)/tCK £ 3.
x32:
x16:
A0–A10
A0–A11
ROW
ADDRESS
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can be issued without having t o close
a previous active row, provided the minimum time in-
terval between successive ACTIVE commands to the
BANK
ADDRESS
BA0,BA1
t
same bank is defined by RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
Figure 4
t
t
t
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK £ 3
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or WRITE
t
RCD
DON’T CARE
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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64Mb: x16, x32
SYNCFLASH MEMORY
The new READ command should be issued x cycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of one,
two and three; data element n + 3 is either the last of a
burst of four, or the last desired of a longer burst. The
SyncFlash memory uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initi-
ated on any clock cycle following a previous READ com-
mand. Full-speed, random read accesses within a page
can be performed as shown in Figure 8, or each subse-
quent READ may be performed to a different bank.
READs
Read bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command.
During read bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each sub-
sequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
one, two and three CAS latency settings.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any read burst may be truncated with a
subsequent READ command, and data from a fixed-
length read burst may be immediately followed by data
from a subsequent READ command. In either case, a
continuous flow of data can be maintained. The first
data element from the new burst follows either the last
element of a completed burst, or the last desired data
element of a longer burst that is being truncated.
Figure 6
CAS Latency
T0
T1
T2
CLK
COMMAND
READ
NOP
t
t
LZ
OH
D
OUT
DQ
t
AC
Figure 5
READ Command
CAS Latency = 1
T0
T1
T2
T3
CLK
CLK
CKE
CS#
HIGH
COMMAND
READ
NOP
t
NOP
t
LZ
OH
D
OUT
DQ
t
AC
CAS Latency = 2
RAS#
T0
T1
T2
T3
T4
CAS#
WE#
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
D
OUT
DQ
t
AC
COLUMN
ADDRESS
A0–A7
CAS Latency = 3
DON’T CARE
UNDEFINED
BANK
ADDRESS
BA0, BA1
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 7
Consecutive Read Bursts
T0
T1
T2
T3
T4
T5
CLK
READ
NOP
NOP
NOP
READ
NOP
COMMAND
X = 0 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
n
D
n + 1
OUT
D
n + 2
OUT
DOUT
D
OUT
b
n + 3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
n
D
n + 1
OUT
DOUT
D
n + 3
OUT
D
OUT
b
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
n
DOUT
D
n + 2
OUT
D
n + 3
OUT
DOUT
b
n + 1
CAS Latency = 3
DON’T CARE
NOTE: Each READ command may be to either bank. DQM is LOW.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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©2002,MicronTechnology,Inc.
21
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 8
Random Read Accesses Within a Page
T0
T1
T2
T3
T4
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
D
OUT
D
OUT
x
D
OUT
m
n
a
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
DOUT
D
OUT
x
D
OUT
m
n
a
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
a
D
OUT
x
D
OUT
m
n
CAS Latency = 3
DON’T CARE
NOTE: Each READ command may be to either bank. DQM is LOW.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Data from any read burst may be truncated with a
subsequent WRITE command and data from a fixed-
length read burst may be immediately followed by data
from a subsequent WRITE command (subject to bus
turnaround limitations). The WRITE may be initiated
on the clock edge immediately following the last (or last
desired) data element from the read burst, provided
that I/O contention can be avoided. In a given system
design, there may be the possibility that the device
driving the input data would go Low-Z before the
SyncFlash memory DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read
data and the WRITE command.
The DQM input is used to avoid I/O contention as
shown in Figure 9. The DQM signal must be asserted
(HIGH) at least two clocks prior to the WRITE command
(DQM latency is two clocks for output buffers) to sup-
press data-out from the READ. Once the WRITE com-
mand is registered, the DQs will go High-Z (or remain
High-Z) regardless of the state of the DQM signal. The
DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buff-
ers) to ensure that the written data is not masked. Fig-
ure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle.
A fixed-length or full-page read burst can be trun-
cated with ACTIVE TERMINATE (which may or may
not be bank specific) or BURST TERMINATE (which is
not bank specific). The ACTIVE TERMINATE or BURST
TERMINATE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is the last desired data
element of a burst of four or the last desired of a longer
burst.
Figure 9
HCS READ to WRITE
Figure 10
HCS READ to WRITE with Extra Clock
Cycle
T0
T1
T2
T3
T4
CLK
T0
T1
T2
T3
T4
T5
CLK
DQM, H
DQM
READ
LCR
ACTIVE
NOP
WRITE
COMMAND
ADDRESS
READ
LCR
ACTIVE
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL b
BANK
ROW
40h
BANK,
ROW
BANK,
COL n
BANK,
COL b
40H
t
CK
t
HZ
t
HZ
D
OUT
n
DIN b
DQ
DOUT
n
DIN b
t
DQ
DS
t
DS
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
NOTE:
A CAS latency of three is used for illustration. The
READ command may be to any bank, and the WRITE
DON’T CARE
command may be to any bank. If a CAS latency of one is
used, then DQM is not required.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 11
Terminating a Read Burst
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 0 cycles
BANK,
COL n
DOUT
D
n + 1
OUT
D
n + 2
OUT
D
OUT
n
n + 3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COL n
D
OUT
n
D
n + 1
OUT
D
OUT
D
OUT
n + 2
n + 3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COL n
D
OUT
n
D
OUT
D
n + 2
OUT
D
n + 3
OUT
n + 1
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
WRITE BURSTS
terminate operation. ACTIVE TERMINATE is consid-
ered a NOP for banks not addresssed by A10, BA0, BA1
(see Figure 15).
Write bursts are initiated with a WRITE command as
shown in Figure 12. WRITE commands are preceded by
an FCS program command. The 2 Meg x 32 features a
32-byte internal buffer, while the 4 Meg x 16 features a
16-byte internal write buffer which supports mode reg-
ister programmed burst writes of 1, 2, 4, or 8 locations.
The starting column and bank addresses are provided
with the WRITE command. Once a WRITE command is
registered, a READ command can be executed as de-
fined by Truth Tables 4 and 5. An example is shown in
Figure 14.
POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. Entering power-down deacti-
vates the input and output buffers (excluding CKE)
after internal state machine operations (including
WRITE operations) are completed for power savings
while in standby (see Figure 16).
During write bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any
additional input data will be ignored (see Figure 13).
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting CKS).
See the Reset/Deep Power-Down description in the
Flash Memory Functional Description for maximum
power savings mode.
t
CLOCK SUSPEND
ACTIVE TERMINATE
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored, any data present on the DQ pins remains
driven, and burst counters are not incremented, as
long as the clock is suspended (see examples in Figures
17 and 18).
The ACTIVE TERMINATE command is functionally
equivalent to the SDRAM PRECHARGE command. Un-
like SDRAM, SyncFlash memory does not require a
PRECHARGE command to deactivate the open row in a
particular bank or the open rows in all banks. Asserting
input A10 HIGH during an ACTIVE TERMINATE com-
mand will terminate a BURST READ in any bank. When
A10 is low during an ACTIVE TERMINATE command,
BA0 and BA1 will determine which bank will undergo a
Figure 12
WRITE Command
Figure 13
Write Burst
CLK
T0
T1
T2
T3
CKE
CS#
HIGH
CK
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
RAS#
BANK,
COL n
CAS#
WE#
DIN
n
DIN
n + 1
NOTE: Burst length = 2. DQM is LOW.
COLUMN
ADDRESS
A0–A7
BA0, BA1
DON’T CARE
BANK
ADDRESS
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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©2002,MicronTechnology,Inc.
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ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
Figure 16
Power-Down
Coming out of a power-down sequence (active),
t
CKS (CKE setup time) must be greater than or equal to 3ns.
BURST READ/SINGLE WRITE
( (
) )
( (
) )
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. All WRITE commands result in the
access of a single column location (burst of one). READ
commands access columns according to the pro-
grammed burst length and sequence.
CLK
t
t
CKS
CKS
CKE
( (
) )
( (
) )
( (
) )
COMMAND
NOP
NOP
ACTIVE
t
All banks idle
RCD
Input buffers gated off
t
RAS
t
RC
Enter power-down mode.
Exit power-down mode.
Figure 14
HCS WRITE to READ
Figure 17
Clock Suspend During Write Burst
T0
T1
T2
T3
CLK
T0
T1
T2
T3
T4
T5
CK
WRITE
READ
NOP
NOP
COMMAND
ADDRESS
CKE
BANK,
COL n
BANK,
COL b
INTERNAL
CLOCK
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
D
n
IN
DbOUT
DQ
BANK,
COL n
NOTE:
A CAS latency of two is used for illustration.
The WRITE command may be to any bank and
the READ command may be to any bank. DQM is
LOW. For more details, refer to Truth Tables 4
and 5.
D
n
IN
D
n + 1
IN
DIN
n + 2
DQ
NOTE:
For this example, burst length = 4 or greater, and DQM is LOW.
Figure 18
Clock Suspend During Read Burst
Figure 15
Terminating a Write Burst
T0
T1
T2
T3
T4
T5
T6
T0
T1
T2
CLK
CKE
CK
COMMAND
ADDRESS
BURST
TERMINATE
NEXT
COMMAND
WRITE
INTERNAL
CLOCK
BANK,
COL n
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
(ADDRESS)
BANK,
COL n
DIN
n
(DATA)
DQ
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
NOTE:
DQMs are LOW, and burst
length >1. BURST TERMINATE
command causes data on DQ to
become invalid.
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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SYNCFLASH MEMORY
TRUTH TABLE 3 – CKE
(Notes: 1–4)
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
L
H
L
Clock Standby
Clock Suspend
Clock Standby
Clock Suspend
No Burst in Progress
Reading
X
Maintain Clock Standby
Maintain Clock Suspend
Exit Clock Standby
Exit Clock Suspend
Clock Standby
X
COMMAND INHIBIT or NOP
X
L
5
6
H
H
COMMAND INHIBIT or NOP
VALID
Clock Suspend
H
See Truth Table 4
NOTE: 1. “CKE ” is the logic state of CKE at clock edge n; “CKE ” was the state of CKE at the previous clock edge.
n
n-1
2. “CURRENT STATE” is the state of the SyncFlash memory immediately prior to clock edge n.
3. “COMMAND ” is the command registered at clock edge n and “ACTION ” is a result of COMMAND .
n
n
n
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that CKS
t
is met).
6. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
64Mb: x16, x32 SyncFlash
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SYNCFLASH MEMORY
TRUTH TABLE 4 – CURRENT STATE BANK n; COMMAND TO BANK n
(Notes: 1–6)
CURRENT
STATE
CS# RAS#CAS# WE# COMMAND/ACTION
NOTES
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
LOAD COMMAND REGISTER
Idle
L
L
L
LOAD MODE REGISTER
7
8
L
H
L
L
ACTIVE TERMINATE
H
H
L
H
L
READ (Select column and start Read burst)
WRITE (Select column and start WRITE)
ACTIVE TERMINATE
Row Active
L
H
L
L
8
L
H
H
L
LOAD COMMAND REGISTER
H
L
L
READ (Select column and start new Read burst)
ACTIVE TERMINATE
Read
Write
H
H
L
8
9
H
L
L
BURST TERMINATE
H
H
H
LOAD COMMAND REGISTER
H
L
L
READ (Select column and start new Read burst)
LOAD COMMAND REGISTER
10
L
NOTE: 1. This table applies when CKE was HIGH and CKE is HIGH (see Truth Table 3).
n-1
n
2. This table is bank specific, except where noted; i.e., the Current State is for a specific bank and the commands shown
are those allowed to be issued to that bank, when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank is not in read or write mode.
RowActive: A row in the bank has been activated and RCD has been met. No data bursts/accesses and no
t
register accesses are in progress.
Read: A read burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE operation has been initiated to the SyncFlash internal state machine (ISM) and has not
yet completed.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 4, and according to Truth
Table 5.
Active Terminate: Starts with registration of an ACTIVE TERMINATE command and ends on the next clock cycle. The
bank will then be in the idle state.
t
t
RowActivating: Starts with registration of an ACTIVE command and ends when RCD is met. Once RCD is met, the
bank will be in the row active state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
AccessingMode
t
Register: Starts with registration of a LOAD MODE REGISTER command and ends when MRD has been met.
t
Once MRD is met, the SyncFlash memory will be in the all banks idle state.
Initialize Mode: Starts with RP# transitioning from LOW to HIGH and ends after 100µs delay.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. May or may not be bank specific.
9. Not bank specific; BURST TERMINATE affects the most recent read burst, regardless of bank.
10. A READ operation to the bank under ISM control will output the contents of the row activated prior to the LCR/active/
write sequence (see Truth Table 2a).
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SYNCFLASH MEMORY
TRUTH TABLE 5 – CURRENT STATE BANK n; COMMAND TO BANK m
(Notes: 1–6)
CURRENT
STATE
CS# RAS#CAS# WE# COMMAND/ACTION
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start read burst)
WRITE (Select column and start WRITE)
ACTIVE TERMINATE
Idle
Row
Activating,
Active, or
Active
H
H
L
L
H
L
L
Terminate
L
H
H
H
L
LOAD COMMAND REGISTER
L
H
L
ACTIVE (Select and activate row)
READ (Select column and start new read burst)
ACTIVE TERMINATE
Read
H
L
H
L
L
H
H
H
L
LOAD COMMAND REGISTER
L
H
L
ACTIVE (Select and activate row)
READ (Select column and start read burst)
ACTIVE TERMINATE
H
L
Write
H
H
L
H
L
L
BURST TERMINATE
H
LOAD COMMAND REGISTER (HCS)
NOTE: 1. This table applies when CKE was HIGH and CKE is HIGH (see Truth Table 3).
n-1
n
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank is not in initialize, read, write mode.
t
RowActive: A row in the bank has been activated and RCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A read burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE operation has been initiated to the SyncFlash ISM and has not yet completed.
4. LOAD MODE REGISTER command may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
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SYNCFLASH MEMORY
FLASHMEMORY
FUNCTIONALDESCRIPTION
FLASHCOMMANDSEQUENCES
All Flash operations are performed using either a
hardware command sequence (HCS) or a software com-
mand sequence (SCS). The HCS operations are used in
systems that support the LOAD COMMAND REGIS-
TER (LCR) command. In systems that do not have the
ability to generate an LCR command, SCS operations
can be used for Flash operations. A Flash command
sequence (FCS) is used to describe Flash operations
where the actual implementation (HCS or SCS) is not
relevant.
The SyncFlash memory incorporates a number of
features that make it ideally suited for code storage
and execute-in-place applications on an SDRAM bus.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting
data stored in other blocks. These memory blocks are
read, programmed, and erased by issuing commands
to the command execution logic (CEL). The CEL con-
trols the operation of the internal state machine (ISM),
which completely controls all READ DEVICE CONFIGU-
RATION, READ STATUS REGISTER, CLEAR STATUS
REGISTER, RESET DEVICE/CONFIRM, PROGRAM
SETUP/CONFIRM, PROTECT BLOCKS/CONFIRM,
PROTECT DEVICE/CONFIRM, UNPROTECT DEVICE
/CONFIRM, UNPROTECT BLOCKS/CONFIRM, ERASE
NVMODE REGISTER, PROGRAM NVMODE REGISTER,
DISABLE HARDWARE LCR, ERASE SETUP CONFIRM
and CHIP INITIALIZATION operations. The ISM pro-
tects each memory location from overerasure and opti-
mizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for programming the device in-system or in
an external programmer.
HARDWARE COMMAND SEQUENCE (HCS)
All HCS operations are executed with LCR, LCR/
ACTIVE/READ, or LCR/ACTIVE/WRITE commands
and command sequences as defined in Truth Tables 1
and 2a. See PROGRAM/ERASE diagram for timing in-
formation. See the SDRAM Interface Functional De-
scription for information on reading the memory array.
Address pins A0–A7 are used to input 8-bit com-
mands during the LCR command cycle. This command
will identify which Flash operation is initiated.
Certain LCR/active/write command sequences re-
quire an 8-bit confirmation code on the WRITE cycle.
The confirmation code is input on DQ0–DQ7.
The Flash Memory Functional Description provides
detailed information on the operation of the SyncFlash
memory and is organized into these sections:
SOFTWARE COMMAND SEQUENCE (SCS)
Flash operations can also be performed using an
SCS. The SCS uses a series of standard CPU READ and
WRITE op-codes to perform Flash operations. This com-
mand interface is similar to the multistep sequence
common in standard Flash components. Table 3 is an
example of programming data into a particular address
using SCS. See Truth Table 2b for a description of SCS
operations.
•
•
•
•
•
•
•
•
Command Sequences
Memory Architecture
Output (READ) Operations
Input Operations
Command Execution
Reset/Power-Down Mode
Error Handling
PROGRAM/ERASE Cycle Endurance
1
Table 3
Software Code to Program Data Value 1234h to Address 0000h Using SCS
ASSEMBLY CODE EXECUTED
SDRAM COMMANDS ISSUED
OP-CODE
ADDRESS, DATA
COMMAND BANK
ADDRESS
DATA
WRITE
00000055h, 00000000h
ACTIVE
WRITE
0h
0h
000h
55h
XXXX
0000h
WRITE
WRITE
WRITE
0000552Ah, 00000055h
00008040h, 000000A0h
00000000h, 00001234h
ACTIVE
WRITE
0h
0h
055h
2Ah
XXXX
0055h
ACTIVE
WRITE
0h
0h
080h
40h
XXXX
00A0h
ACTIVE
WRITE
0h
0h
000h
00h
XXXX
1234h
NOTE: 1. This is a programming example for the 4 Meg x 16.
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SYNCFLASH MEMORY
When a CPU executes a WRITE op-code to a memory
address configured for SDRAM, the memory controller
issues an ACTIVE command followed by a WRITE com-
mand. A similar ACTIVE/READ pair is also issued dur-
ing a READ operation. By issuing ACTIVE/WRITE and
ACTIVE/READ pairs with predefined address and data
values, any of the Flash commands can be performed.
BLOCK operation has been executed to these blocks,
an UNPROTECT ALL BLOCKS operation will unlock all
blocks except the blocks at locations 0 and 15 unless
RP# = VHH. This provides additional security for critical
code during in-system firmware updates should an
unintentional power disruption or system reset
occur.
A second level of block protection is possible
by completing a hardware DEVICE PROTECT opera-
tion. DEVICE PROTECT prevents block protect bit
modification.
The protection status of any block may be checked
by reading the protect bits with a read device configu-
ration command sequence.
MEMORYARCHITECTURE
The 64Mb SyncFlash memory is a four-bank archi-
tecture with four erasable blocks per bank. By erasing
blocks rather than the entire array, the total device
endurance is enhanced, as is system flexibility. Only
the ERASE and BLOCK PROTECT functions are block
ori-ented. The four banks have simultaneous read-
while-write functionality. An ISM PROGRAM or ERASE
operation to any bank can occur simultaneously to a
READ to any other bank.
COMMAND EXECUTION LOGIC (CEL)
SyncFlash operations are executed by issuing the
appropriate commands to the CEL. The CEL receives
and interprets commands to the device. These com-
mands control the operation of the ISM and the read
path (i.e., memory array, device configuration, or sta-
tus register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more details.
The SyncFlash memory has a single background
operation ISM to control power-up initialization,
ERASE, PROGRAM, and PROTECT operations. ISM op-
erations are initiated with an HCS or SCS. Only one ISM
operation can occur at any time; however, certain other
commands, including READ operations, can be per-
formed while an ISM operation is taking place. A new
HCS or SCS will not be permitted until the current ISM
operation is complete.
INTERNAL STATE MACHINE (ISM)
Power-up initialization, erase, program, and pro-
tect timings are simplified by using an ISM to control all
programming algorithms in the memory array. The ISM
ensures protection against overerasure and optimizes
programming margin to each cell.
During PROGRAM operations, the ISM automati-
cally increments and monitors PROGRAM attempts,
verifies programming margin on each memory cell and
updates the ISM status register. When BLOCK ERASE is
performed, the ISM automatically overwrites the en-
tire addressed block (eliminates overerasure), incre-
ments and monitors ERASE attempts, and sets bits in
the ISM status register.
An operational command controlled by the ISM is
defined as either a bank-level operation or a device-
level operation. PROGRAM and ERASE are bank-level
ISM operations. After an ISM bank-level operation has
been initiated, a READ may be issued to any bank;
however, a READ to the bank under ISM control will
output the contents of the row activated prior to the
HCS or SCS. CHIP INITIALIZE, HARDWARE LCR DIS-
ABLE, ERASE NVMODE REGISTER, PROGRAM
NVMODE REGISTER, BLOCK PROTECT, DEVICE PRO-
TECT, and UNPROTECT ALL BLOCKS are device-level
ISM operations. Once an ISM device-level operation
has been initiated, a READ to any bank will output the
contents of the array. A READ STATUS REGISTER com-
mand sequence may be issued to determine comple-
tion of the ISM operation. When SR7 = 1, the ISM opera-
tion is complete and a new ISM operation may be initi-
ated.
ISM STATUS REGISTER
The 16-bit ISM status register allows an external
processor to monitor the status of the ISM during de-
vice initialization, ERASE NVMODE REGISTER, PRO-
GRAM NVMODE REGISTER, PROGRAM, ERASE,
BLOCK PROTECT, DEVICE PROTECT or UNPROTECT
ALL BLOCKS, and any related errors. ISM operations
and related errors can be monitored by reading status
register bits on DQ0–DQ8.
All of the defined bits are set by the ISM, but only
the ISM status bits (SR0, SR1, SR2, SR7) are cleared by
the ISM. The erase/unprotect block, program/protect
block, and device protection bits must be cleared by
PROTECTED BLOCKS
The 64Mb SyncFlash devices are organized into 16
erasable memory blocks. Each block may be software
protected by issuing the appropriate FCS for a BLOCK
PROTECT operation.
The blocks at locations 0 and 15 have additional
protection to prevent inadvertent PROGRAM or ERASE
operations in 3.3V-only platforms. Once a PROTECT
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SYNCFLASH MEMORY
the host system using the CLEAR STATUS REGISTER
command. This allows the user to choose when to poll
and clear the status register. For example, the host
system may perform multiple PROGRAM operations
before checking the status register instead of checking
after each individual PROGRAM.
A VCC power sequence error is cleared by re-
initializing the device.
Asserting the RP# signal or powering down the de-
vice will also clear the status register.
ter, or one of the device configuration registers.
SyncFlash memory is in the array read mode unless a
status register or device register read is initiated or in
progress.
A READ to the device configuration register or the
status register must be issued as defined by the FCS.
The burst length of data-out is defined by the mode
register settings. Reading the device configuration reg-
ister or status register will not disrupt data in a previ-
ously open (or “activated”) page. When the burst is
complete, a subsequent READ will read the array. How-
ever, several differences exist and are described in the
following section. Moving between modes to perform a
specific READ will be covered in the Command Execu-
tion section.
OUTPUT(READ)OPERATIONS
SyncFlash memory features three different types of
READs. Depending on the mode, a READ operation
will produce data from the memory array, status regis-
Figure 19
2 Meg x 32 Memory Address Map
Figure 20
4 Meg x 16 Memory Address Map
ADDRESS RANGE
ADDRESS RANGE
Bank
Row Column
Bank
Row Column
3 FFF FFh
3 C00 00h
3 BFF FFh
3 800 00h
3 7FF FFh
3 400 00h
3 3FF FFh
3 000 00h
2 FFF FFh
2 C00 00h
2 BFF FFh
2 800 00h
2 7FF FFh
2 400 00h
2 3FF FFh
2 000 00h
1 FFF FFh
1 C00 00h
1 BFF FFh
1 800 00h
1 7FF FFh
1 400 00h
1 3FF FFh
1 000 00h
0 FFF FFh
0 C00 00h
0 BFF FFh
0 800 00h
0 7FF FFh
0 400 00h
0 3FF FFh
0 000 00h
3 7FF FFh
3 600 00h
3 5FF FFh
3 400 00h
3 3FF FFh
3 200 00h
3 1FF FFh
3 000 00h
2 7FF FFh
2 600 00h
2 5FF FFh
2 400 00h
2 3FF FFh
2 200 00h
2 1FF FFh
2 000 00h
1 7FF FFh
1 600 00h
1 5FF FFh
1 400 00h
1 3FF FFh
1 200 00h
1 1FF FFh
1 000 00h
0 7FF FFh
0 600 00h
0 5FF FFh
0 400 00h
0 3FF FFh
0 200 00h
0 1FF FFh
0 000 00h
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
256K-word Block
15
14
13
12
11
10
9
128K-Dword Block 15
128K-Dword Block 14
128K-Dword Block 13
128K-Dword Block 12
128K-Dword Block 11
128K-Dword Block 10
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
128K-Dword Block
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Word-wide (x16)
Dword-wide (x32)
Unlock Blocks
(RP# = VHH
)
Unlock Blocks
(RP# = VHH
)
Unlock Blocks
(RP# = VIH
)
Unlock Blocks
(RP# = VIH
)
NOTE: See block lock and unlock flowchart sequences for
additionalinformation.
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SYNCFLASH MEMORY
MEMORY ARRAY
the array is input on the DQ pins. The data and ad-
dresses are latched on the rising edge of the clock.
Details on how to input data to the array is covered in
the Command Execution section.
A READ command to any bank will output the con-
tents of the memory array. While a PROGRAM or ERASE
ISM operation is in progress, a READ to any location in
the bank under ISM control will output the contents of
the row activated prior to an FCS; a READ to any other
bank will output the contents of the array. All com-
mands and their operations are covered in the SDRAM
Interface Functional Description section.
COMMANDEXECUTION
Commands are issued to bring the device into dif-
ferent operational modes. Each mode has specific op-
erations that can be performed while in that mode. All
HCS modes require that an LCR/active/read or LCR/
active/write sequence be issued, except CLEAR STA-
TUS REGISTER, which is a single LCR command. In-
puts A0–A7 during the FCS determine the operation
being performed. The following section describes the
properties of each mode, and Truth Tables 1, 2a, and
2b list all commands and command sequences re-
quired to perform the desired operation. Read-while-
write functionality allows a background operation pro-
gram or erase to any bank while simultanously reading
any other bank.
STATUS REGISTER
Reading the status register requires an FCS. The
status register contents are latched on the next posi-
tive clock edge subject to CAS latencies. The burst
length of the status register data-out is defined by the
mode register.
All commands and their operations are covered in
the Command Execution section.
DEVICE CONFIGURATION REGISTER
To read the device ID, manufacturer compatibility
ID, device protection status, block protect status, and
the hardware LCR disable bit, the appropriate com-
mand sequence for READ DEVICE CONFIGURATION
must be issued. This is the same input sequencing
used when reading the status register, except that spe-
cific addresses must be issued.
The HCS operations in Truth Table 2a must be com-
pleted on consecutive clock cycles. However, in order
to reduce bus contention issues, an unlimited number
of NOPs or COMMAND INHIBITs can be issued
throughout the LCR/active/write command sequence.
For additional protection, these command sequences
must have the same bank address for the three com-
mand cycles.
INPUTOPERATIONS
The SCS operations described in Truth Table 2b
must also be completed on adjacent clock cycles. The
SCS operation will allow NOP, COMMAND INHIBIT,
REFRESH, and BURST TERMINATE commands to be
issued during the sequence without aborting the se-
quence. All steps in the SCS must access the same bank
or the operation will be aborted and the device will
return to the read array mode.
An FCS is required to program the array, or to per-
form an ERASE, PROTECT, UNPROTECT, or HARD-
WARE LCR DISABLE operation. The first cycle of an
input operation is an FCS operation where inputs A0–
A7 determine the input command being executed to
the CEL. An input operation will not disrupt data in a
previously opened page.
The DQ pins are used either to input data to the
array or to input a command to the CEL during the
WRITE cycle.
More information describing how to program, erase,
protect, or unprotect the device is provided in the Com-
mand Execution section.
If the bank address changes during the FCS or if the
command sequences are not consecutive (other than
NOPs and COMMAND INHIBITs), the program and
erase status bits (SR4 and SR5) will be set and the de-
sired operation will be aborted.
For additional protection, these command se-
quences must have the same bank address during all
command cycles.
MEMORY ARRAY
Programming or erasing the memory array sets the
desired bits to logic 0s but cannot change a given bit to
a logic 1 from a logic 0. Setting any bit to a logic 1 re-
quires that the entire block be erased. Programming a
protected block requires that the RP# pin be brought to
VHH. A0–A10 (x32), A0–A11 (x16) provide the address to
be programmed, while the data to be programmed in
STATUS REGISTER
Reading and clearing the status register requires an
FCS. During status reads, the status register contents
are latched on the next positive clock edge, subject to
CAS latencies, for a burst length defined by the mode
register.
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SYNCFLASH MEMORY
DEVICE CONFIGURATION
three cycles. After the ISM has initiated programming,
it cannot be aborted except by a reset or by powering
down the device. Doing either while programming the
array will corrupt the data being written.
To read the device ID, manufacturer compatibility
ID, device protect bit, and each of the block protect
bits, the appropriate FCS operation for READ DEVICE
CONFIGURATION must be issued. Specific configura-
tion addresses must be issued to read the desired in-
formation. The manufacturer compatibility ID is read
at 000h; the device ID is read at 001h. The manufac-
turer compatibility ID and device ID are output on
DQ0–DQ7. The device protect bit is read at 003h; and
each of the block protect bits is read on the third ad-
dress location within each block (x02h). The device and
block protect bits are output on DQ0. The mode regis-
ter is read from address 004h. The hardware load com-
mand register bit is available on bit 0 of address 005h.
A LOW on bit zero means that HCS operations are
disabled and a HIGH means that HCS operations are
allowed.
ERASE SEQUENCE
Executing an erase sequence will set all bits within a
block to logic 1. The HCS necessary to execute an ERASE
is similar to that of a PROGRAM. To provide added
security against accidental block erasure, three con-
secutive command sequences on consecutive clock
edges are required to initiate an ERASE of a block. See
Table 2a. In the first cycle, LOAD COMMAND REGIS-
TER is issued with ERASE SETUP (20h) on A0–A7, and
the bank address of the block to be erased is issued on
BA0, BA1. The next command is ACTIVE, where A10,
A11, BA0, and BA1 provide the address of the block to
be erased. The third cycle is WRITE, during which
ERASE CONFRIM (D0h) is issued on DQ0–DQ7 and the
bank address is reissued. The ISM status bit will be set
on the following clock edge (subject to CAS latencies).
After ERASE CONFIRM (D0h) is issued, the ISM will
start erasing the addressed block. When the ERASE
operation is complete, the bank will be in the array read
mode and ready for an executable command. Erasing
hardware-protected blocks also requires that the RP#
pin be set to VHH prior to the third cycle (WRITE), and
RP# must be held at VHH until the ERASE operation is
complete (SR7 = 1). If the HCS is not completed on
consecutive cycles (NOP, COMMAND INHIBIT,
PRECHARGE, and REFRESH are permitted between
cycles) or the bank address changes for one or more of
the command cycles, the program and erase status bits
(SR4 and SR5) will be set.
The device configuration register contents are out-
put subject to CAS latencies for a burst length defined
by the mode register.
PROGRAM SEQUENCE
Using an HCS operation, three commands on con-
secutive clock edges are required to input data to the
array (NOPs and COMMAND INHIBITS are permitted
between cycles). See Table 2a. In the first cycle, LOAD
COMMAND REGISTER is issued with PROGRAM SETUP
(40h) on A0–A7, and the bank address is issued on BA0,
BA1. The next command is ACTIVE, which identifies
the row address and confirms the bank address. The
third cycle is WRITE, during which the column address,
the bank address, and data are issued.
To perform a program operation using an SCS op-
eration, the system executes a series of WRITE op-codes
using a predetermined set of address/data values (see
Truth Table 2b). The SCS operation will result in the
command register being loaded with the PROGRAM
command (40h), and the CEL being loaded with the
address and data value to be programmed.
During the SCS operation, eight commands on con-
secutive clock edges are required to input data to the
array (NOP and COMMAND INHIBIT are permitted
between cycles). See Table 2b. After the first five setup
cycles, the next three cycles are identical to the normal
LCR command sequence except the command for the
first of last three cycles is a WRITE instead of an LCR.
The ISM status bit is set on the following clock edge
(subject to CAS latencies), indicating the ERASE op-
eration is in progress.
The ISM status bit will be set on the following clock
edge (subject to CAS latencies).
While the ISM is programming the array, the ISM
status bit (SR7) will be at “0.” When the ISM status bit
(SR7) is set to a logic 1, programming is complete, and
the bank will be in the array read mode and ready for a
new ISM operation.
Programming hardware-protected blocks requires
that the RP# pin be set to VHH during the FCS, and RP#
must be held at VHH until the ISM PROGRAM operation
is complete. The program and erase status bits (SR4
and SR5) will be set and the operation aborted if the
FCS command sequence is not completed on consecu-
tive cycles or the bank address changes for any of the
PROGRAM AND ERASE NVMODE REGISTER
The contents of the mode register may be copied
into the nvmode register with a PROGRAM NVMODE
REGISTER command. Prior to programming the
nvmode register, an erase nvmode register command
sequence must be completed to set all bits in the
nvmode register to logic 1. The command sequence
necessary to execute an ERASE NVMODE REGISTER
and PROGRAM NVMODE REGISTER is similar to that
64Mb: x16, x32 SyncFlash
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SYNCFLASH MEMORY
of a program sequence. See Truth Tables 2a and 2b for
more information on the FCS operations necessary to
complete ERASE NVMODE REGISTER and PROGRAM
NVMODE REGISTER.
If the device protect bit is set, RP# must be brought
to VHH prior to the last FCS cycle and held at VHH until
the BLOCK PROTECT or UNPROTECT ALL BLOCKS op-
eration is complete.
To check a block’s protect status, a read device con-
figuration command sequence may be issued.
BLOCK PROTECT/UNPROTECT SEQUENCE
Executing a block protect sequence enables the first
level of software/hardware protection for a given block.
The command sequence necessary to execute a BLOCK
PROTECT is similar to that of a program sequence. To
provide added security against accidental block pro-
tection, three consecutive command cycles are re-
quired to initiate a BLOCK PROTECT during a normal
HCS. In the first cycle, LOAD COMMAND REGISTER is
issued with PROTECT SETUP (60h) on A0–A7, and the
bank address of the block to be protected is issued on
BA0, BA1. The next cycle is ACTIVE, which identifies a
row in the block to be protected and confirms the bank
address. The third cycle is WRITE, during which BLOCK
PROTECT CONFIRM (01h) is issued on DQ0–DQ7, and
the bank address is reissued. The ISM status bit is set
on the following clock edge (subject to CAS latencies),
indicating the PROTECT operation is in progress.
If the LCR/ACTIVE/WRITE is not completed on con-
secutive cycles (NOP and COMMAND INHIBIT, RE-
FRESH, and PRECHARGE are permitted between
cycles), or the bank address changes, the write and
erase status bits (SR4 and SR5) will be set and the op-
eration will be aborted. When the ISM status bit (SR7) is
set to a logic 1, the PROTECT is complete.
DEVICE PROTECT SEQUENCE
Executing a device protect command sequence sets
the device protect bit to a “1” and prevents block pro-
tect bit modification. The command sequence neces-
sary to execute a DEVICE PROTECT is similar to that of
a PROGRAM sequence. During normal HCS operation,
LOAD COMMAND REGISTER is issued in the first cycle
with protect setup (60h) on A0–A7, and a bank address
is issued on BA0, BA1. The bank address is “Don’t Care,”
but the same bank address must be used for all three
cycles. The next cycle is ACTIVE. The third cycle is
WRITE, during which DEVICE PROTECT (F1h) is is-
sued on DQ0–DQ7. RP# must be brought to VHH prior to
registration of the WRITE command.
During the SCS, eight commands on consecutive
clock edges are required to input data to the array (NOP,
COMMAND INHIBIT, REFRESH, PRECHARGE, and
BURST TERMINATE are permitted between cycles).
After the first five setup cycles, the last three cycles are
indentical to the normal HCS, except the command for
the first of the last three cycles is a WRITE instead of an
LCR. The ISM status bit is set on the following clock
edge (subject to CAS latencies). RP# must be held at
VHH until the PROTECT operation is complete (SR7 = 1).
Once the device protect bit is set, it can be reset by
issuing an UNPROTECT BLOCK command with RP# =
VHH. With the device protect bit set to a “1,” BLOCK
PROTECT or BLOCK UNPROTECT is prevented unless
RP# is at VHH during either operation. The device pro-
tect bit does not affect PROGRAM or ERASE operations.
During the SCS operation, eight commands on con-
secutive clock edges are required to input data to the
array (NOP, COMMAND INHIBIT, REFRESH, and
PRECHARGE are permitted between cycles). After the
first six setup cycles, the last 2 cycles are identical to the
normal HCS. The ISM status bit is set on the following
clock edge (subject to CAS latencies) indicating the
PROTECT operation is in progress.
Once a block protect bit has been set to a “1” (pro-
tected), it can only be reset to a “0” if the UNPROTECT
ALL BLOCKS command is executed. The unprotect all
blocks command sequence is similar to the block pro-
tect sequence; however, in the last FCS cycle, a WRITE
is issued with UNPROTECT ALL BLOCKS CONFIRM
(D0h) and addresses are “Don’t Care.” For additional
information, refer to Truth Tables 2a and 2b.
The blocks at locations 0 and 15 have additional
security. Once the block protect bits at locations 0 and
15 have been set to a “1” (protected), each bit can only
be reset to a “0” if RP# is brought to VHH prior to the third
cycle (WRITE) of the UNPROTECT operation and held
at VHH until the operation is complete (SR7 = 1).
CHIP INITIALIZE SEQUENCE
Executing a chip initialize sequence can be accom-
plished one of two ways. The first option is a hardware
initiated power-up using the RP# transition to initiate a
reset. A successful entry into the reset mode requires
that RP# be held LOW for a minimum of 5µs before
transitioning HIGH.
The second option is called a software initiated
power-up, which requires an INITIALIZE DEVICE FCS
operation for a successful entry into reset mode.
During an HCS INITIALIZE DEVICE operation, the
LOAD COMMAND REGISTER command is issued in
the first cycle with CHIP INITIALIZE (68h) issued on
A0–A7, and a bank address issued on BA0, BA1. The
64Mb: x16, x32 SyncFlash
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SYNCFLASH MEMORY
bank address is “Don’t Care,” but the same bank ad-
dress must be used for all three cycles. The second
cycle is ACTIVE, and the third cycle is WRITE, during
which C0h is issued on DQ0-DQ7. Once the last com-
mand is issued, the initialization sequence will com-
mence.
During an SCS INITIALIZE DEVICE operation, eight
commands on consecutive clock edges are required to
input data to the array (NOP, COMMAND INHIBIT,
REFRESH, PRECHARGE, and BURST TERMINATE are
permitted between cycles). After the first five setup
cycles, the last three cycles are identical to a typical
HCS, except the command for the first of the last
three cycles is a WRITE instead of an LCR. Once the last
command is issued, the initialization sequence will
commence.
To enter this mode, RP# (reset/power-down) is taken
to VSS ±0.2V. To prevent an inadvertent reset, RP# must
be held at VSS for at least 5µs prior to the device entering
the reset/deep power-down mode. After the device
enters the reset/deep power-down mode, a transition
from LOW to HIGH on RP# results in a device power-up
initialization sequence as outlined in the Chip Initial-
ization section. When the device enters the deep power-
down mode, all buffers excluding the RP# buffer are
disabled and the current draw is a maximum of 50µA at
3.3V VCC. The input to RP# must remain at VSS during
deep power-down. Entering the reset mode clears the
status register.
ERRORHANDLING
After the ISM status bit (SR7) has been set, the de-
vice protect (SR3), write/protect block (SR4) and erase/
unprotect (SR5) status bits may be checked. If one or a
combination of SR3, SR4, SR5 status bits has been set,
an error has occurred. SR8 is set when an inadvertent
power failure occurs during device initialization. The
device should be reinitialized to ensure proper device
operation. The ISM cannot reset SR3, SR4, SR5, or SR8.
To clear these bits, CLEAR STATUS REGISTER com-
mand must be given. Table 6 lists the combination of
errors.
The initialization sequence is completed either by
allowing a time period of 100µs to elapse or by checking
for SR7 = 1.
DISABLE LCR SEQUENCE
In some systems the SDRAM controller does not
support the generation of the LCR command. These
systems will likely find that the SCS is more practical for
performing Flash operations. The DISABLE LCR com-
mand can be issued with either an HCS or SCS opera-
tion. Once issued, the DISABLE LCR bit will no longer
allow HCS operations. Note that unless DISABLE LCR
is issued, the device can function in either HCS or SCS
mode.
PROGRAM/ERASECYCLEENDURANCE
SyncFlash memory is designed and fabricated to
meet advanced code and data storage requirements.
Operation outside specification limits may reduce the
number of PROGRAM and ERASE cycles that can be
performed on the device. Each block is designed and
processed for a minimum of 100,000-PROGRAM/
ERASE-cycle endurance.
RESET/DEEPPOWER-DOWNMODE
To allow for maximum power conservation, the de-
vice features a very low current, deep power-down
mode.
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SYNCFLASH MEMORY
Table 4
1
Status Register Bit Definition
R
VPS
ISMS
R
ES
WS
DPS
BISMS
DBS
15–9
8
7
6
5
4
3
2–1
0
STATUS
BIT # STATUS REGISTER BIT
DESCRIPTION
SR15– RESERVED
SR9
Reserved for future use.
SR8
VCC POWER SEQUENCE STATUS (VPS)
1 = Power-up incomplete error
0 = Power-up complete
VPS is set if there has been a power disruption that may result in
undefined device operation. A VPS error is only cleared by
re-initializing the device.
SR7
ISM STATUS (ISMS)
1 = Ready
0 = Busy
The ISMS bit displays the active status of the state machine
when performing PROGRAM, BLOCK ERASE or CHIP INITIALIZE.
The controlling logic polls this bit to determine when the erase
and program status bits are valid. This bit can be monitored to
determine the completion of power-up initialization after CHIP
INITIALIZATION sequence is issued.
SR6
SR5
RESERVED
Reserved for future use.
ERASE/UNPROTECT BLOCK STATUS (ES) ES is set to “1” after the maximum number of ERASE cycles is
1 = BLOCK ERASE or BLOCK
UNPROTECT error
0 = Successful BLOCK ERASE or
UNPROTECT
executed by the ISM without a successful verify. This bit is also set
to “1” if a BLOCK UNPROTECT operation is unsuccessful. ES is
only cleared by a CLEAR STATUS REGISTER command or by a
RESET.
SR4
SR3
PROGRAM/PROTECT BLOCK STATUS (WS) WS is set to “1” after the maximum number of PROGRAM cycles
1 = PROGRAM or BLOCK PROTECT error is executed by the ISM without a successful verify. This bit is also
0 = Successful BLOCK ERASE or
UNPROTECT
set to “1” if a BLOCK or DEVICE PROTECT operation is
unsuccessful. WS is only cleared by a CLEAR STATUS REGISTER
command or by a RESET.
DEVICE PROTECT STATUS (DPS)
1 = Device protected, invalid operation
attempted
0 = Device unprotected or RP#
condition met
DPS is set to “1” if an invalid PROGRAM, ERASE, PROTECT
BLOCK, PROTECT DEVICE or UNPROTECT ALL BLOCKS is met.
After one of these commands is issued, the condition of RP#, the
block protect bit and the device protect bit are compared to
determine if the desired operation is allowed. Must be cleared by
CLEAR STATUS REGISTER or by a RESET.
SR2
SR1
BANKA1 ISM STATUS (BISMS)
BANKA0 ISM STATUS
When SR0 = 0, the bank under ISM control can be decoded from
SR1, SR2: [0,0] Bank 0; [0,1] Bank 1; [1,0] Bank 2; [1,1] Bank 3.
SR1, SR2 is valid when SR7 = 0. When SR7 = 1, SR1, SR2 is reset to
“0.”
SR0
DEVICE/BANK ISM STATUS (DBS)
1 = Device-level ISM operation
0 = Bank-level ISM operation
DBS is set to “1” if the ISM operation is a device-level operation.
A valid READ to any bank can immediately follow the
registration of an ISM PROGRAM operation. When DBS is set to
“0,” the ISM operation is a bank-level operation. A READ to the
bank under ISM control will output the contents of the row
activated prior to the FCS. SR1 and SR2 can be decoded to
determine which bank is under ISM control. SR0 is used in
conjuction with SR7, and is valid when SR7 = 0. When SR7 = 1,
SR0 is reset to “0.”
NOTE: 1. SR3–SR5 must be cleared with CLEAR STATUS REGISTER prior to initiating an ISM WRITE operation for the status bits to
be valid.
2. x32: SR32–SR16 is a copy of SR15–SR0.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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64Mb: x16, x32
SYNCFLASH MEMORY
Table 5
Device Configuration
DEVICE
CONFIGURATION
CONFIGURATION
ADDRESS
DATA
CONDITION
NOTES
Manufacturer
000h
xx2Ch
Manufacturer compatibility ID read
1
Compatibility ID
Device ID
x32: 001h
xxD4h
xxD5h
Device ID read
Device ID read
1
x16: 001h
1
Block Protect Bit
Device Protect Bit
x02h
x02h
DQ0 = 1
DQ0 = 0
Block protected
Block unprotected
2, 3
003h
003h
DQ0 = 1
DQ0 = 0
Block protect modification prevented
Block protect modification enabled
3
Mode Register
004h
Mode register definition data
4
Hardware LCR Disable
005h
005h
DQ0 = 1
DQ0 = 0
Hardware LCR is disabled
Hardware LCR is enabled
3, 5
NOTE: 1. DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0.
2. Address to read block protect bit is always the third location within each block.
x32: X = 0, 2, 4, 6h; BA0, BA1 required.
x16: X = 0, 4, 8, Ch; BA0, BA1 required.
3. DQ1–DQ7 are reserved, DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0.
4. See Figure 1 for more information.
5. Factory preset is “0.”
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
Table 6
Status Register Codes
1
STATUS
REGISTER
CODE
SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 STATE MACHINE DESCRIPTION
000h
001h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Busy – ERASE or PROGRAM cycle for Bank 0
Busy – BLOCK PROTECT or UNPROTECT
cycle
002h
003h
004h
005h
006h
007h
010h
011h
012h
013h
014h
015h
016h
020h
021h
022h
023h
024h
025h
026h
080h
090h
098h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
Busy – ERASE or PROGRAM cycle for Bank 1
Busy – DEVICE PROTECT cycle
Busy – ERASE or PROGRAM cycle for Bank 2
Busy – NVMODE ERASE or PROGRAM cycle
Busy – ERASE or PROGRAM cycle for Bank 3
Busy – INITIALIZATION cycle
Busy – PROGRAM cycle error for Bank 0
Busy – BLOCK PROTECT cycle error
Busy – PROGRAM cycle error for Bank 1
Busy – DEVICE PROTECT cycle error
Busy – PROGRAM cycle error for Bank 2
Busy – NVMODE PROGRAM cycle error
Busy – PROGRAM cycle error for Bank 3
Busy – ERASE cycle error for Bank 0
Busy – BLOCK UNPROTECT cycle error
Busy – ERASE cycle error for Bank 1
Busy – DEVICE UNPROTECT cycle error
Busy – ERASE cycle error for Bank 2
Busy – NVMODE ERASE cycle error
Busy – ERASE cycle error for Bank 3
Ready – No errors
Ready – PROGRAM or PROTECT cycle error
Ready – Program/protect error and device/
block protection error
0A0h
0A8h
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
Ready – ERASE or UNPROTECT cycle error
Ready – Erase/unprotect error and device/
block protection error
0B0h
0B8h
0
0
1
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
Ready – Command sequence error
Ready – Command sequence error and
device/block protection error
1xxh
1
X
X
X
X
X
X
X
X
VCC error (power-up without initialization
error)
NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
64Mb: x16, x32 SyncFlash
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1
SELF-TIMEDPROGRAMSEQUENCE
COMPLETEPROGRAMSTATUS-CHECK
SEQUENCE
Start (PROGRAM completed)
Start
FCS Command
2
YES
Command Sequence Error5
Invalid PROGRAM Error5
Sequence
SR4, SR5 = 1?
NO
SR3 = 1?
NO
Read Status Register
Polling
YES
YES
NO
SR7 = 1?
PROGRAM Error5
SR4 = 1?
NO
YES
Complete Status
PROGRAM Successful
3
Check
4
PROGRAM Complete
NOTE: 1. Sequence may be repeated for multiple PROGRAMs.
2. FCS includes HCS and SCS.
3. Complete status check is not required.
4. The bank will be in array read mode.
5. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SELF-TIMEDBLOCKERASE
COMPLETEBLOCKERASE
STATUS-CHECKSEQUENCE
1
SEQUENCE
Start (BLOCK ERASE completed)
Start
FCS Command
Sequence
YES
Command Sequence Error6
Invalid ERASE or
2, 3
SR4, SR5 = 1?
NO
Read Status Register
YES
YES
SR3 = 1?
NO
6
UNPROTECT Error
NO
BLOCK ERASE or
UNPROTECT Error
SR7 = 1
SR5 = 1?
NO
6
YES
Complete Status
ERASE or BLOCK UNPROTECT Successful
4
Check
5
ERASE Complete
NOTE: 1. Sequence may be repeated to erase multiple blocks.
2. FCS includes HCS and SCS.
3. RP# can be brought to VHH before the last command in the erase sequence is issued.
4. Complete status check is not required.
5. The bank will be in the array read mode.
6. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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64Mb: x16, x32
SYNCFLASH MEMORY
1
BLOCKPROTECTSEQUENCE
COMPLETEBLOCKPROTECT
STATUS-CHECKSEQUENCE
Start (BLOCK PROTECT completed)
Start
YES
BLOCK or DEVICE
PROTECT Error
SR4 = 1?
NO
6
FCS Command
Sequence2, 3
YES
YES
6
SR4, SR5 = 1?
Command Sequence Error
Invalid BLOCK/DEVICE
Read Status Register
NO
SR3 = 1?
NO
6
PROTECT Error
NO
SR7 = 1
YES
BLOCK PROTECT Successful
Complete Status
Check
DEVICE PROTECT Complete4, 5
NOTE: 1. Sequence may be repeated for multiple BLOCK PROTECTs.
2. FCS includes HCS and SCS.
3. RP# can be brought to VHH before the last command in the block protect sequence is issued.
4. Complete status check is not required.
5. The bank will be in array read mode.
6. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
1
DEVICEPROTECTSEQUENCE
COMPLETEBLOCK
STATUS-CHECKSEQUENCE
Start
Start
Device
YES
FCS Command
Sequence2, 3
Protected?
NO
Unprotect
Blocks 1-14?
YES
Read Status Register
NO
NO
RP# = VHH
SR7 = 1
YES
FCS Command
2
Sequence
Complete Status
Check
Read Status Register
SR7 = 1
DEVICE PROTECT Complete4, 5
NO
YES
Complete Status
4, 5
Check
ALL BLOCKS UNPROTECT Complete
NOTE: 1. Once the device protect bit is set, it can be reset.
2. FCS includes HCS and SCS.
3. RP# can be brought to VHH before the last command in the device protect sequence is issued.
4. Complete status check is not required.
5. A subsequent WRITE command may be issued.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
COMPLETEDEVICEPROTECT
STATUS-CHECKSEQUENCE
Start (DEVICE PROTECT completed)
YES
BLOCK or DEVICE
PROTECT Error
SR4 = 1?
NO
1
YES
YES
1
SR4, SR5 = 1?
Command Sequence Error
Invalid BLOCK/DEVICE
NO
SR3 = 1?
NO
1
PROTECT Error
DEVICE PROTECT Successful
NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
ABSOLUTEMAXIMUMRATINGS*
Voltage on RP# Relative to VSS ...................... -1V to +9V
Voltage on VCC, VCCP, or VCCQ Supply, Inputs,
or I/O Pins Relative to VSS ................... -1V to +4.6V
Operating Temperature,
TA (ambient)........................................ 0ºC to +70ºC
Storage Temperature (plastic) ........... -55ºC to +150ºC
Power Dissipation ........................................................ 1W
Short Circuit Output Current................................ 50mA
1,2
DCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS
Commercial Temperature (0ºC £ TA £ +70ºC); VCC = VCCQ
PARAMETER/CONDITION
VCC SUPPLY VOLTAGE
SYMBOL
VCC
MIN
3.0
MAX
3.6
UNIT
V
V
V
VCCQ SUPPLY VOLTAGE
VCCQ
VHH
3.0
3.6
HARDWARE PROTECTION VOLTAGE
(RP# only)
7.0
8.5
INPUT HIGH VOLTAGE:
Logic 1; All Inputs
VIH
2
VCCQ + 0.3
0.8
V
V
INPUT LOW VOLTAGE:
Logic 0; All Inputs
VIL
-0.3
INPUT LEAKAGE CURRENT:
Any input 0V £ VIN £ VCC
(All other pins not under test = 0V)
IL
-5
-5
2.4
–
5
5
µA
µA
V
OUPUT LEAKAGE CURRENT:
DQs are disabled; 0V £ VOUT £ VCCQ
IOZ
OUTPUT HIGH VOLTAGE:
IOUT = -4mA
VOH
VOL
–
OUTPUT LOW VOLTAGE:
IOUT = 4mA
0.4
V
NOTE: 1. All voltages referenced to VSS.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
1,2,3
ICC SPECIFICATIONSANDCONDITIONS
Commercial Temperature (0ºC £ TA £ +70ºC)
PARAMETER/CONDITION
SYMBOL -7E/-75 UNITS NOTES
VCC OPERATING CURRENT: Active Mode
Burst = 2; READ; RC = RC (MIN); CAS latency = 3
ICCR1
ICCR2
ICCS1
140
130
50
mA
mA
mA
4, 5, 6
t
t
VCC OPERATING CURRENT: Burst Mode
Continuous Burst; All banks active; READ; CAS latency = 3
4, 5, 6
VCC STANDBY CURRENT: Active Mode
CS# = HIGH; CKE = HIGH; All banks active;
No burst in progress
VCC STANDBY CURRENT: Power-Down Mode
CKE = LOW; No burst in progress
ICCS2
ICCDP
2
mA
µA
VCC DEEP POWER-DOWN CURRENT:
RP# = VSS ±0.2V
50
PROGRAM CURRENT
ICCW + IPPW
ICCE + IPPE
60
80
mA
mA
VCCP OPERATING CURRENT:
Erase current
VCCP OPERATING CURRENT: Active Mode
Burst = 2; READ; RC = RC (MIN); CAS latency = 3
IPPR1
IPPR2
IPPS1
IPPS2
IPPDP
150
150
150
150
1
µA
µA
µA
µA
µA
t
t
VCCP OPERATING CURRENT: Burst Mode;
Continuous Burst; All banks active; READ; CAS latency = 3
VCCP STANDBY CURRENT: Active Mode
CKE = LOW; Burst in progress
VCCP STANDBY CURRENT: Power-Down Mode
CKE = LOW; No burst in progress
VCCP DEEP POWER-DOWN CURRENT:
RP# = VSS ±0.2V
CAPACITANCE
PARAMETER
SYMBOL MIN MAX UNITS NOTES
Input Capacitance: CLK
CI1
CI2
CIO
2.5
2.5
4.0
6.5
6.5
7.0
pF
pF
pF
7
7
7
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
NOTE: 1. All voltages referenced to VSS
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
3. ICC specifications are tested after the device is properly initialized.
4. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputsopen.
5. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is
slower as the CAS latency is reduced.
6. Address transitions average one transition every 30ns
7. This parameter is sampled. VCC = VCCQ; f = 1 MHz, T = +25ºC
A
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS
(Notes: 1–5); Commercial Temperature (0ºC £ TA £ +70ºC); VCC = VCCQ
ACCHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
-7E
-75
SYMBOL
MIN
MAX
5.4
5.4
MIN
MAX
5.4
6
UNITS NOTES
t
CL = 3
CL = 2
CL = 1
AC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AC
t
AC
AH
17
17
t
Address hold time
Address setup time
CLK HIGH level width
CLK LOW level width
Clock cycle time
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
t
AS
t
CH
t
CL
t
CL = 3
CL = 2
CL = 1
CK
t
CK
7.5
20
t
CK
20
t
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
CKH
CKS
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
t
t
CMH
t
CMS
t
DH
t
Data-in setup time
Data-outHigh-Ztime
DS
t
CL = 3
CL = 2
CL = 1
HZ
5.4
5.4
17
5.4
6
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
t
HZ
t
HZ
t
Data-outLow-Ztime
Data-outholdtime
ACTIVEcommandperiod
ACTIVE to READ or WRITE delay
ACTIVEbankatoACTIVEbankbcommand
Transition time
LZ
1
3
60
22.5
14
0.3
1
3
66
25
15
0.3
t
OH
t
RC
t
RCD
t
RRD
t
T
1.2
1.2
7
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between
VIL and VIH) in a monotonic manner.
4. Outputs measured at 1.5V with equivalent load:
x16
x32
Q
Q
50pF
30pF
5. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to a 1.5V crossover point. If the input
t
transition time is longer than T (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the
1.5V crossover point.
t
6. HZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The
t
last valid data element will meet OH before going High-Z.
t
7. AC characteristics assume T = 1ns.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
ACFUNCTIONALCHARACTERISTICS
(Notes: 1–6); Commercial Temperature (0ºC £ TA £ +70ºC); VCC = VCCQ
PARAMETER
SYMBOL
-7E
1
1
1
0
0
2
0
2
-75
1
1
1
0
0
2
0
2
UNITS NOTES
t
t
READ/WRITEtoREAD/LOADCOMMANDREGISTERcommand
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQMtodatahigh-impedanceduringREADs
WRITE command to input data delay
CCD
CK
7
8
8
7
7
7
7
7
7
7
7
t
t
CKED
CK
t
t
PED
CK
t
t
DQD
DQM
DQZ
DWD
MRD
ROH
ROH
CK
t
t
CK
t
t
CK
t
t
CK
t
t
LOADMODEREGISTERcommandtoACTIVEcommand
Data-outtoHigh-ZfromACTIVETERMINATEcommand
CK
t
t
CL = 3
CL = 2
CL = 1
3
2
1
3
2
1
CK
t
t
CK
t
t
ROH
CK
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
t
3. AC characteristics assume T = 1ns.
4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between
VIL and VIH) in a monotonic manner.
5. Outputs measured at 1.5V with equivalent load:
x16
x32
Q
Q
50pF
30pF
6. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to a 1.5V crossover point. If the input
t
transition time is longer than T (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the
1.5V crossover point.
7. Required clocks specified by JEDEC functionality and not dependent on any timing parameter.
t
8. Timing actually specified by CKS; clock(s) specified as a reference only at minimum cycle rate.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
INITIALIZEANDLOADMODEREGISTER(RP#CONTROL)
Ta
Tm
Tn
Tn + 1
CK
Tn + 2
CL
Tn + 3
( (
) )
( (
) )
t
t
CLK
( (
) )
( (
) )
t
CH
t
t
CKH
CKS
( (
) )
( (
) )
( (
) )
( (
) )
CKE
t
t
CMH
CMS
( (
) )
( (
) )
( (
) )
( (
) )
LOAD MODE
REGISTER
COMMAND
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
DQM
((
))
((
))
V
CC, VCCP,
VCC
Q
((
))
1
RP#
((
))
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ADDRESS
DQ
OPCODE
ROW
High-Z
((
))
((
))
t
MRD
T = 100µs
Load Mode Register3, 4, 5
Power-up:2
DON’T CARE
UNDEFINED
V
CC, VCCP, VCCQ,
CLK stable
TIMING PARAMETERS
-7E
MAX
-75
MAX UNITS
-7E
-75
SYMBOL*
MIN
0.8
1.5
2.5
2.5
7
MIN
0.8
1.5
2.5
2.5
7.5
10
SYMBOL*
MIN
MAX
MIN
0.8
1.5
0.8
1.5
2
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
CKH
0.8
1.5
0.8
1.5
2
ns
ns
ns
ns
clk
t
t
AS
CKS
t
t
CH
CMH
t
t
CL
CMS
t
t
CK (3)
MRD
t
CK (2)
7.5
*CAS latency indicated in parentheses.
NOTE: 1. RP# = VCC or VHH.
2. VCC, VCCP, VCCQ = 3.3V.
3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, and the
LOAD MODE REGISTER cycle is required to enter new mode register values.
4. JEDEC and PC100 specify three clocks.
5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
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SYNCFLASH MEMORY
INITIALIZEANDLOADMODEREGISTER(FCSCONTROL)
Ta
Tm
Tn
Tn + 1
CK
Tn + 2
CL
Tn + 3
( (
) )
( (
) )
t
t
CLK
CKE
( (
) )
( (
) )
t
CH
t
t
CKS
CKH
( (
) )
( (
) )
( (
) )
( (
) )
t
t
CMH
CMS
( (
) )
( (
) )
( (
) )
( (
) )
6
LOAD MODE
REGISTER
COMMAND
WRITE
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
DQM
((
))
((
))
VCC, VCCP,
VCCQ
((
))
((
))
1
RP#
t
t
AS
AH
( (
) )
( (
) )
( (
) )
( (
) )
ADDRESS
DQ
OPCODE
ROW
High-Z
((
))
((
))
C0h
t
MRD
T = 100µs
3, 4, 5
Load Mode Register
2
DON’T CARE
UNDEFINED
Power-up:
V
CC, VCCP, VCCQ,
CLK stable
TIMING PARAMETERS
-7E
MAX
-75
-7E
MAX
-75
SYMBOL*
MIN
0.8
1.5
2.5
2.5
7
MIN
0.8
1.5
2.5
2.5
7.5
10
MAX UNITS
SYMBOL*
MIN
0.8
1.5
0.8
1.5
2
MIN
0.8
1.5
0.8
1.5
2
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
CKH
ns
ns
ns
ns
clk
t
t
AS
CKS
t
t
CH
CMH
t
t
CL
CMS
t
t
CK (3)
MRD
t
CK (2)
7.5
*CAS latency indicated in parentheses.
NOTE: 1. RP# = VCC or VHH.
2. VCC, VCCP, VCCQ = 3.3V.
3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, and the
LOAD MODE REGISTER cycle is required to enter new mode register values.
4. JEDEC and PC100 specify three clocks.
5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”
6. WRITE command preceded by the beginning of the chip initialize sequence. (See Truth Tables 2a/2b.)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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SYNCFLASH MEMORY
1
CLOCKSUSPENDMODE
T0
T1
T2
T3
T4
T5
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS
CKH
t
t
CMS CMH
COMMAND
DQM
READ
NOP
NOP
NOP
NOP
NOP
t
t
CMS CMH
t
AS
t
AH
x32: A0–A10
x16: A0–A11
2
COLUMN m
t
AS
t
AH
BA
BANK
t
AC
t
AC
t
OH
t
HZ
D
OUT
m
DOUT m+1
DQ
t
LZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-7E
MAX
-75
SYMBOL*
MIN
MAX
MIN
MAX UNITS
SYMBOL*
MIN
1.5
MIN
MAX UNITS
t
t
AC (3)
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
0.8
1.5
ns
ns
ns
ns
ns
t
t
AC (2)
CMH
0.8
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
CMS
1.5
t
t
AS
DH
0.8
t
t
CH
DS
1.5
t
t
CL
HZ (3)
5.4
5.4
5.4
6
ns
ns
ns
ns
t
t
CK (3)
HZ (2)
t
t
CK (2)
7.5
0.8
LZ
1
3
1
3
t
t
CKH
0.8
OH
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, CAS latency = 3.
2. A0–A7.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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SYNCFLASH MEMORY
1
READ
T0
T1
CK
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CLK
CKE
t
CH
t
t
t
CKH
CKS
t
CMS CMH
COMMAND
DQM
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS CMH
t
t
t
AS
AH
x32: A0–A10
x16: A0–A11
2
ROW
COLUMN m
ROW
t
AS
AH
BA
BANK
BANK
BANK
t
t
t
AC
OH
AC
OH
AC
OH
t
t
t
t
t
OH
AC
D
OUT
m
DOUT m+1
D
OUT m+2
DOUT m+3
DQ
t
t
LZ
HZ
t
t
RCD
RC
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
MAX UNITS
-7E
-75
SYMBOL*
MIN
MAX
5.4
MIN
SYMBOL*
MIN
MAX
MIN
1.5
MAX UNITS
t
t
AC (3)
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
ns
ns
ns
t
t
AC (2)
5.4
CMH
0.8
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
CMS
1.5
t
t
AS
HZ (3)
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
ns
t
t
CH
HZ (2)
t
t
CL
LZ
1
3
1
3
t
t
CK (3)
OH
t
t
CK (2)
7.5
0.8
RC
60
66
25
t
t
CKH
0.8
ns
RCD
22.5
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, CAS latency = 2.
2. A0–A7.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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SYNCFLASH MEMORY
1
READ – ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
COMMAND
DQM
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS CMH
t
t
AH
AS
x32: A0–A10
x16: A0–A11
2
2
ROW
ROW
ROW
COLUMN m
COLUMN b
BANK 1
t
t
AH
AS
BA
BANK 0
BANK 0
BANK 1
t
BANK 0
t
t
t
t
AC
AC
AC
AC
AC
t
t
t
t
t
t
AC
OH
OH
OH
OH
OH
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
RCD - BANK 0
CAS Latency - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 1
CAS Latency - BANK 1
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-7E
-75
SYMBOL*
MIN
1.5
0.8
1.5
1
MAX
MIN
1.5
0.8
1.5
1
MAX UNITS
SYMBOL*
MIN
MAX
5.4
MIN
MAX UNITS
t
t
AC (3)
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AC (2)
5.4
CMH
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
CMS
t
t
AS
LZ
t
t
CH
OH
3
3
t
t
CL
RC
60
66
t
t
CK (3)
RCD
22.5
14
25
t
t
CK (2)
7.5
0.8
RRD
15
t
CKH
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, CAS latency = 2.
2. A0–A7.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
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53
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
1
READ – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
CMS CMH
( (
) )
DQM
( (
) )
t
t
AH
AS
( (
) )
( (
) )
x32: A0–A10
x16: A0–A11
2
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
BA
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC
AC
( (
) )
t
t
t
t
t
t
OH
AC
OH
OH
OH
OH
OH
( (
) )
( (
) )
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
D
OUT
m
D
OUT m+1
DQ
t
LZ
t
HZ
256 (x16), 128 (x32) locations within
the same row.
Full page completed.
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
MAX UNITS
-7E
-75
SYMBOL*
MIN
MAX
5.4
MIN
SYMBOL*
MIN
1.5
MAX
MIN
1.5
MAX UNITS
t
t
AC (3)
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
ns
ns
ns
t
t
AC (2)
5.4
CMH
0.8
0.8
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
CMS
1.5
1.5
t
t
AS
HZ (3)
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
t
t
CH
HZ (2)
t
t
CL
LZ
1
3
1
3
t
t
CK (3)
OH
t
t
CK (2)
7.5
0.8
RCD
22.5
25
t
CKH
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. A0–A7.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
54
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
1
READ – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM
t
t
AH
AS
x32: A0–A10
x16: A0–A11
2
ROW
COLUMN m
t
t
AH
AS
BA
BANK
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m+2
D
OUT m+3
DQ
t
LZ
t
t
t
LZ
HZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
MAX UNITS
-7E
MAX
-75
SYMBOL*
MIN
MAX
5.4
MIN
SYMBOL*
MIN
1.5
MIN
1.5
MAX UNITS
t
t
AC (3)
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
ns
ns
ns
t
t
AC (2)
5.4
CMH
0.8
0.8
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
CMS
1.5
1.5
t
t
AS
HZ (3)
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
t
t
CH
HZ (2)
t
t
CL
LZ
1
3
1
3
t
t
CK (3)
OH
t
t
CK (2)
7.5
0.8
RCD
22.5
25
t
CKH
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, CAS latency = 2.
2. A0–A7.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
55
1
PROGRAM/ERASE
(Bank a followed by READ to Bank a)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM
LCR
ACTIVE
NOP
WRITE
READ
NOP
NOP
NOP
NOP
NOP
t
t
CMS
CMH
t
t
AS
AH
x32: A0–A10
x16: A0–A11
3
2
COMCODE
ROW
COLUMN
m
COLUMN n
BANK a
BANK a
BANK a
BANK a
BA
t
t
DH
t
t
DS
DS
DH
High-Z
D
IN4 m
Dout n+1
Dout n
DQ
t
RCD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-7E
MAX
-75
SYMBOL*
MIN
0.8
1.5
2.5
2.5
7
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MAX UNITS
SYMBOL*
MIN
1.5
MIN
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
0.8
1.5
25
ns
ns
ns
ns
ns
ns
t
t
AS
CMH
0.8
t
t
CH
CMS
1.5
t
t
CL
DH
0.8
t
t
CK (3)
DS
1.5
t
t
CK (2)
7.5
0.8
RCD
22.5
t
CKH
0.8
*CAS latency indicated in parentheses.
NOTE: 1. ACTIVE/READ or READ will output the contents of the row activated prior to the HCS. For this example, read burst length = 2, CAS latency = 2.
2. Com-code = 40h for PROGRAM, 20h for ERASE (see Truth Table 2a).
3. Column address is “Don’t Care” for ERASE operation.
4. DIN = D0h (ERASE CONFIRM) for ERASE operation.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
1
PROGRAM/ERASE
(Bank a followed by READ to Bank b)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
DQM
LCR
ACTIVE
NOP
WRITE
READ
NOP
NOP
NOP
NOP
NOP
t
t
CMS
CMH
t
t
AH
AS
x32: A0-A10
x16: A0-A11
2
3
COLUMN n
BANK b
COMCODE
ROW
COLUMN
m
BANK a
BANK a
t
BA
BANK a
t
t
t
DH
DS
DH
n
DS
High-Z
IN4 m
D
OUT n + 1
D
OUT
D
DQ
t
RCD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
MAX
-75
-7E
MAX
-75
SYMBOL*
MIN
MIN
0.8
1.5
2.5
2.5
7.5
10
MAX UNITS
SYMBOL*
MIN
1.5
MIN
1.5
0.8
1.5
0.8
1.5
25
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
CKS
ns
ns
ns
ns
ns
ns
t
t
AS
CMH
0.8
t
t
CH
CMS
1.5
t
t
CL
DH
0.8
t
t
CK (3)
DS
1.5
t
t
CK (2)
7.5
0.8
RCD
22.5
t
CKH
0.8
*CAS latency indicated in parentheses.
NOTE: 1. ACTIVE/READ or READ will output the contents of the row activated prior to the HCS. For this example, read burst
length = 2, CAS latency = 3.
2. Com-code = 40h for PROGRAM, 20h for ERASE (see Truth Table 2a).
3. Column address is “Don’t Care” for ERASE operation.
4. DIN = D0h (ERASE CONFIRM) for ERASE operation.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
57
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
86-PIN PLASTIC TSOP (400 MIL)
SEE DETAIL A
22.22 ±.08
.61
.50
TYP
.10 (2X)
+.07
-.03
0.20
2.80 (2X)
11.76 ±.10
10.16 ±.08
R .75 (2X)
PIN #1 ID
+.03
-.02
.15
R 1.00
(2X)
.25
GUAGE
PLANE
+.10
-.05
.10
.10
.50 ±.10
1.20 MAX
.80
TYP
DETAIL A
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
58
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
90-BALLFBGA
.850 ±.075
.10
C
SEATING PLANE
C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb.
Or 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
11.00 ±.10
6.40
.80
SUBSTRATE: PLASTIC LAMINATE
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
90X Ø 0.45
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION.
THE PRE-REFLOW DIAMETER IS Ø 0.40mm
PIN A1 ID
PIN A1 ID
TYP
BALL A9
BALL A1
6.50 ±.05
13.00 ± .10
C
L
11.20
.80
5.60 ±.05
TYP
C
L
3.20 ±.05
1.20 MAX
5.50 ±.05
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
DATASHEETDESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail:prodmktg@micron.com,Internet:http://www.micron.com,CustomerCommentLine:800-932-4992
Micron, the M logo, and SyncFlash are registered trademarks, and the Micron logo is a trademark of Micron Technology, Inc.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
59
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
REVISIONHISTORY
Rev. 2, Advance .................................................................................................................................................... 4/02
• Removed -7 and -8E devices
Original document, Rev. 1, Advance .................................................................................................................. 3/02
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
60
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