MT29C4G48MAZAPAKD-5IT [MICRON]
NAND Flash and Mobile LPDRAM 152-Ball Package-on-Package (PoP) Combination Memory (TI OMAPâ¢) MT29C Family; NAND闪存和移动LPDRAM 152球包上封装（PoP ）的内存组合（ TI OMAPâ ?? ¢ ） MT29C家庭
| 型号： | MT29C4G48MAZAPAKD-5IT |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | NAND Flash and Mobile LPDRAM 152-Ball Package-on-Package (PoP) Combination Memory (TI OMAPâ¢) MT29C Family |
| 文件： | 总15页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
‡
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Fe a t u re s
NAND Fla sh a n d Mo b ile LPDRAM
152-Ba ll Pa cka g e -o n -Pa cka g e (Po P)
Co m b in a t io n Me m o ry (TI OMAP™)
MT29C Fa m ily
Current production part numbers: See Table 1 on page 3
Fig u re 1:
Po P Blo ck Dia g ra m
Fe a t u re s
®
• Micron NAND Flash and Mobile LPDRAM
components
• RoHS-compliant, “green” package
• Separate NAND Flash and Mobile LPDRAM
interfaces
• Space-saving package-on-package combination
• Low-voltage operation (1.70–1.95V)
• Industrial temperature range: –40°C to +85°C
NAND Flash
Device
NAND Flash
Interface
NAND Flash
Power
NAND Fla sh -Sp e cific Fe a t u re s
• Organization
– Page size
x8: 2112 bytes (2048 + 64 bytes)
x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
LP-DRAM
Device
LP-DRAM Power
LP-DRAM Interface
Mo b ile LPDRAM-Sp e cific Fe a t u re s
• No external voltage reference required
• No minimum clock rate requirement
• 1.8V LVCMOS-compatible inputs
• Programmable burst lengths
• Partial-array self refresh (PASR)
• Deep power-down (DPD) mode
• Selectable output drive strength
Op t io n s
Ma rkin g
• LP-DRAM
166 MHz CL32
133 MHz CL3
-6
-75
1
• STATUS REGISTER READ (SRR) supported
Notes: 1. Contact factory for remapped SRR output.
2. CL = CAS (READ) latency.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Pa rt Nu m b e rin g In fo rm a t io n – 152-Ba ll Po P
Pa rt Nu m b e rin g In fo rm a t io n – 152-Ba ll Po P
Micron NAND Flash and LPDRAM devices are available in different configurations and
densities.
Fig u re 2:
152-Ba ll Pa rt Nu m b e r Ch a rt
MT 29C 1G 24M
A
C
J
A
CG –x
IT ES
Production Status
Blank = Production
Micron Technology
ES = Engineering sample
MS = Mechanical sample
Product Family
29C = NAND + LPDRAM MCP
Operating Temperature Range
IT = Industrial (–40° to +85°C)
NAND Density
1G = 1Gb
2G = 2Gb
LPDRAM Self Refresh Current
Blank = Standard
4G = 4Gb
LPDRAM Density
12M = 512Mb
LPDRAM Access Time
–6 166 MHz CL3
24M = 1024Mb
48M = 2048Mb
–75 133 MHz CL3
Operating Voltage Range
A = 1.8V (1.70–1.95V)
Package Codes
CA = 152-ball PoP VFBGA (14 x 14 x 0.9mm)
CG = 152-ball PoP VFBGA (14 x 14 x 1.0mm)
JQ = 152-ball PoP TFBGA (14 x 14 x 1.1mm)
NAND Flash Configuration
Width Density Generation
C
D
J
x8
1Gb
1Gb
2Gb
2Gb
4Gb
4Gb
1Gb
1Gb
First
Chip Count
x16
x8
First
CE#, CS# Chip Count
LPDRAM Configuration
Second
Second
First
Type
DDR
DDR
DDR
DDR
Width Density Generation
A
B
C
D
1, 1
1, 1
1, 2
1, 2
1 NAND, 1 DRAM
2 NAND, 1 DRAM
1 NAND, 2 DRAM
2 NAND, 2 DRAM
K
N
P
x16
x8
J
x16
x32
1Gb
1Gb
First
First
L
x16
x8
First
N
R
x16 512Mb Second
x32 512Mb Second
U
V
Second
Second
x16
Note:
Not all possible combinations are available. Contact factory for availability.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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©2008 Micron Technology, Inc. All rights reserved.
2
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
De vice Ma rkin g
Ta b le 1:
Pro d u ct io n Pa rt Nu m b e rs
Ph ysica l Pa rt
Ma rkin g
Pa rt Nu m b e r
NAND Pro d u ct
LPDDR Pro d u ct
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F1G16ABBHC-ET
MT29F1G16ABBHC-ET
MT29F2G16ABDHC-ET
MT29F2G16ABDHC-ET
MT29F1G08ABCHC-ET
MT29F1G08ABCHC-ET
MT29F1G16ABCHC-ET
MT29F1G16ABCHC-ET
JW399
JW400
JW297
JW296
JW226
JW227
JW188
JW189
JW385
JW384
JW375
JW374
MT29C4G48MAPLCCA-6 IT
MT29C4G48MAPLCCA-75 IT
MT29C4G48MAPLCJQ-6 IT
MT29C4G48MAPLCJQ-75 IT
MT29C1G12MADRACG-6 IT
MT29C1G12MADRACG-75 IT
MT29C2G24MAKLACG-6 IT
MT29C2G24MAKLACG-75 IT
MT29C1G12MAURACA-6 IT
MT29C1G12MAURACA-75 IT
MT29C1G12MAVRACA-6 IT
MT29C1G12MAVRACA-75 IT
De vice Ma rkin g
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/ decoder. To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/ Label,” at www.micron.com/ csn.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
3
©2008 Micron Technology, Inc. All rights reserved.
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ge n e ra l De scrip t io n
Ge n e ra l De scrip t io n
Micron package-on-package (PoP) products combine NAND Flash and Mobile LPDRAM
devices in a single MCP. These products target mobile applications with low-power,
high-performance, and minimal package-footprint design requirements. The NAND
Flash and Mobile LPDRAM devices are also members of the Micron discrete memory
products portfolio.
The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no
shared address, control, data, or power balls). This bus architecture supports an opti-
mized interface to processors with separate NAND Flash and Mobile LPDRAM buses.
The NAND Flash and Mobile LPDRAM devices have separate core power connections
and share a common ground (i.e., V is tied together on the two devices).
SS
The bus architecture of this device also supports separate NAND Flash and Mobile
LPDRAM functionality without concern for device interaction. Operational characteris-
tics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron
data sheets for each of the discrete devices.
For device specifications and complete Micron NAND Flash features documentation,
please refer to the component data sheet at www.micron.com/ products/ nand, or con-
tact your local Micron sales office.
For device specifications and complete Mobile LPDRAM features documentation,
please refer to the component data sheet at www.micron.com/ products/ mobiledram, or
contact your local Micron sales office.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
©2008 Micron Technology, Inc. All rights reserved.
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ba ll Assig n m e n t s a n d De scrip t io n s
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 3:
152-Ba ll VFBGA Ba ll Assig n m e n t s (NAND x8; LPDDR x16)
17
19
NC
NC
20
NC
NC
NC
NC
NC
21
NC
NC
NC
NC
NC
18
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ12
DQ15
A
B
NC
NC
NC
NC
NC
NC
NC
V
DDQ LDM DQ5 DQ7
V
SSQ
DQ2 DQ4 DQ8 DQ11 CK
VSS
UDM
VDDQ DQ13
A
B
DQ14
NC
NC
V
DDQ DQ1 DQ6 LDQS DQ3 DQ0 DQ9 DQ10 CK#
VSSQ UDQS
VDD
C
V
SSQ
NC
NC
C
D
E
D
E
V
SSQ
V
DDQ
V
SSQ
NC
NC
V
DDQ
F
F
A0
NC
NC
G
H
J
G
H
J
V
SS
V
DD
A3
A9
V
SS
A2
A1
V
DD
NC
NC
WE#
NC
NC
NC
NC
NC
NC
K
L
K
L
VDDQ
V
SSQ
RE#
A7
A6
V
SS
M
N
P
M
N
P
A8
A11
V
CC
V
SS
VDD
NC
A5
A12
V
SS
R
R
CS1# CS0#
V
CC
T
T
CAS#
A4
I/O1 I/O0
I/O3 I/O2
CE1# LOCK
U
V
W
Y
AA
U
V
W
Y
AA
BA1 RAS#
VSSQ
VDDQ
V
SS
V
SSQ
NC
NC
20
NC
NC
21
WE#
BA0
18
NC
NC
1
NC
NC
2
I/O6 I/O7 WP#
V
SS
V
CC
NC
NC
R/B#
CLE
10
V
SS
A14 CKE1
VDD CKE0 A10
VDD
VDDQ
I/O4 I/O5
NC
5
VCC
VSS
CE0# ALE
VDD
TQ
12
V
SS
VDDQ A13
VSSQ
17
19
3
4
6
7
8
9
11
13
14
15
16
Top View – Ball Down
NAND
LPDDR
Supply
Ground
Note:
Contact factory for availability of x16 LPDDR configuration.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
5
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 4:
152-Ba ll VFBGA Ba ll Assig n m e n t s (NAND x16; LPDDR x32)
17
19
20
21
NC
NC
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ20
DQ23
DQS3 NC
DQ28 NC
DM3
DQ22
A
B
NC
NC
NC
NC
V
DDQ DM1 DQ13 DQ15
V
SSQ DQ10 DQ12 DQ16 DQ19 CK
VSS
DM2
VDDQ DQ21
A
B
DQ6 DQ7
V
DDQ DQ9 DQ14 DQS1 DQ11 DQ8 DQ17 DQ18 CK#
VSSQ DQS2
VDD
DQ24 DQ26
DQ25 DQ29
DQ27 DQ31
C
V
SSQ DQS0
C
DQ3 DQ5
DQ0 DQ1
D
E
D
E
VSSQ
VDDQ
VSSQ
VDDQ
F
F
A0 DQ30
DQ4 DQ2
G
H
J
G
H
J
VSS
VDD
DM0
VSS
A2
A1
A3
A9
VDD I/O14
WE# I/O15
K
L
K
L
VDDQ
VSSQ
NC
RE#
A7
A6
I/O13
I/O10
VSS
M
N
P
M
N
P
A8
A11
VCC
VSS
VDD
I/O12 I/O11
A5
A12
I/O8
I/O9
VSS
R
R
CS1# CS0#
VCC
T
T
CAS#
A4
I/O1 I/O0
I/O3 I/O2
CE1# LOCK
U
V
W
Y
AA
U
V
W
Y
AA
BA1 RAS#
VSSQ
VDDQ
V
SS
V
SSQ
NC
NC
20
NC
NC
21
WE#
BA0
18
NC
NC
1
NC
NC
2
I/O6 I/O7 WP#
V
SS
V
CC
NC
NC
R/B#
CLE
10
V
SS
RFU CKE1
VDD CKE0 A10
VDD
VDDQ
I/O4 I/O5
NC
5
VCC
VSS
CE0# ALE
VDD
TQ
12
V
SS
VDDQ A13
VSSQ
17
19
3
4
6
7
8
9
11
13
14
15
16
Top View
NAND
LP-DRAM
Supply
Ground
(Ball Down)
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
6
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 2:
x8/x16 NAND Ba ll De scrip t io n s
Sym b o l
Typ e
De scrip t io n
ALE
Input
Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address
register.
CE1#, CE0#
CLE
Input
Input
Chip enable: Gates transfers between the host system and the NAND Flash device.
Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip
command register.
LOCK
Input
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK
LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).
RE#
WE#
WP#
Input
Input
Input
Read enable: Gates information from the NAND device to the host system.
Write enable: Gates information from the host system to the NAND device.
Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.
I/O[7:0]
(x8)
Input/
output
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information.
Data is output only during READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU1 for NAND x8 devices.
I/O[15:0]
(x16)
R/B#
Output
Supply
Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in
progress.
VCC
VCC: NAND power supply.
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
7
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 3:
x16/x32 LPDDR Ba ll De scrip t io n s
Sym b o l
Typ e
De scrip t io n
A[14:0]
Input
Address inputs: Specifies the row or column address. Also used to load the mode registers. The
maximum LPDDR address is determined by density and configuration. Consult the LPDDR
product data sheet for the maximum address for a given density and configuration. Unused
address pins become RFU.
BA1, BA0
CAS#
Input
Input
Input
Bank address inputs: Specifies one of the 4 banks.
Column select: Specifies the command to execute.
CK, CK#
CK is the system clock. CK and CK# are differential clock inputs. All address and control signals
are sampled and referenced on the crossing of the rising edge of CK with the falling edge of
CK#.
CKE0, CKE1
CS1#, CS0#
Input
Input
Input
Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
LDM, UDM
(x16)
Data mask: Determines which bytes are written during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
DM[3:0]
(x32)
RAS#
WE#
Input
Input
Row select: Specifies the command to execute.
Write enable: Specifies the command to execute.
DQ[15:0]
(x16)
Input/
output
Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.
DQ[31:0]
(x32)
LDQS, UDQS
(x16)
Input/
output
Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
DQS[3:0]
(x32)
TQ
Output
Supply
Supply
Supply
Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDD: LPDDR power supply.
VDD
VDDQ
VSSQ
VDDQ: LPDDR I/O power supply.
VSSQ: LPDDR I/O ground.
Ta b le 4:
Sym b o l
No n -De vice -Sp e cific Ba ll De scrip t io n s
Typ e
De scrip t io n
Supply
VSS
VSS: Shared ground.
–
–
NC
RFU1
No connect: Not internally connected.
Reserved for future use.
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
8
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Ele ct rica l Sp e cifica t io n s
Ele ct rica l Sp e cifica t io n s
Ta b le 5: Ab so lu t e Ma xim u m Ra t in g s
Pa ra m e t e rs/Co n d it io n s
Sym b o l
Min
Ma x
Un it
VCC, VDD
VDDQ
,
–1.0
2.4
V
VCC, VDD, VDDQ Supply voltage
relative to VSS
VIN
–
–0.5
–55
2.4 or (supply voltage1 +
0.3V), whichever is less
V
Voltage on any pin
relative to VSS
+150
°C
Storage temperature range
Notes: 1. Supply voltage references either VCC,VDD, or VDDQ
.
Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Ta b le 6: Re co m m e n d e d Op e ra t in g Co n d it io n s
Pa ra m e t e rs
Sym b o l
Min
Typ
Ma x
Un it
VCC, VDD
VDDQ
–
1.70
1.70
–40
1.80
1.80
–
1.95
1.95
+85
V
V
Supply voltage
I/O supply voltage
°C
Operating temperature range
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
9
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
De vice Dia g ra m s
De vice Dia g ra m s
Fig u re 5:
152-Ba ll Fu n ct io n a l Blo ck Dia g ra m (Sin g le LPDDR)
CE0#
VCC
I/O
CLE
ALE
NAND Flash
RE#
WE#
WP#
LOCK
R/B#
VSS
CS0#
CK
VDD
VDDQ
DM
CK#
LPDDR
CKE0
RAS#
CAS#
WE#
DQ
DQS
TQ
Address,
BA0, BA1
VSSQ
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
10
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
De vice Dia g ra m s
Fig u re 6:
152-Ba ll Fu n ct io n a l Blo ck Dia g ra m (Du a l LPDDR)
CE0#
CLE
V
CC
ALE
NAND Flash
RE#
I/O
WE#
WP#
R/B#
V
SS
CS0#, CS1#
CK
V
V
DD
DDQ
CKE0, CKE1
RAS#
DQM
LPDDR
(Die 0 and 1)
CAS#
DQ
WE#
TQ
Address,
BA0, BA1
V
V
SS
SSQ
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
11
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Pa cka g e Dim e n sio n s
Pa cka g e Dim e n sio n s
Fig u re 7:
152-Ba ll VFBGA (Pa cka g e Co d e : CA)
0.46 ±0.1
Seating
plane
A
0.12 A
152X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
14 ±0.1
Ball A1 ID
Ball A1 ID
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
13
14 ±0.1
CTR
M
N
P
R
T
U
V
W
Y
AA
0.65 TYP
0.65 TYP
0.9 MAX
0.35 MIN
13 CTR
Note:
All dimensions are in millimeters.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
12
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Pa cka g e Dim e n sio n s
Fig u re 8:
152-Ba ll VFBGA (Pa cka g e Co d e : CG)
Seating
plane
A
0.6 ±0.1
0.1
A
152X Ø0.46
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
Ball A1 ID
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
Ball A1 ID
G
H
J
K
L
14 ±0.1
13 CTR
M
N
P
R
T
U
V
W
Y
0.65 TYP
AA
0.65 TYP
1.0 MAX
0.35 MIN
13 CTR
14 ±0.1
Note:
All dimensions are in millimeters.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
13
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Pa cka g e Dim e n sio n s
Fig u re 9:
152-Ba ll TFBGA (Pa cka g e Co d e : JQ)
Seating
plane
A
0.75 ±0.1
0.12 A
152X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
Ball A1 ID
21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
Ball A1 ID
G
H
J
K
L
14 ±0.1
13 CTR
M
N
P
Q
R
T
U
V
W
X
0.65 TYP
0.65 TYP
1.1 MAX
0.35 MIN
13 CTR
14 ±0.1
Notes: 1. All dimensions are in millimeters.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production
devices.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
14
Preliminary
152-Ba ll NAND Fla sh a n d Mo b ile LPDRAM Po P (TI OMAP) MCP
Re visio n Hist o ry
Re visio n Hist o ry
Rev. E, Prelim inary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/09
• “NAND Flash-Specific Features” on page 1: Deleted device size bullet.
• Figure 2: “152-Ball Part Number Chart,” on page 2: Added U and V options under
NAND Flash configurations; deleted low-power option under LPDRAM self refresh
current; added dimensions to package codes; added CS# to first column under chip
count; changed CE# from 2 to 1 for B and D under chip count.
• Table 1, “Production Part Numbers,” on page 3: Replaced former table 1.
• Figure 3: “152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16),” on page 5:
Updated figure.
• Figure 4: “152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32),” on page 6:
Updated figure.
• Table 2, “x8/ x16 NAND Ball Descriptions,” on page 7: Updated table.
• Table 3, “x16/ x32 LPDDR Ball Descriptions,” on page 8: Updated table.
• Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Updated table.
• Table 5, “Absolute Maximum Ratings,” on page 9: Updated table.
• Table 6, “Recommended Operating Conditions,” on page 9: Updated table.
• Figure 5: “152-Ball Functional Block Diagram (Single LPDDR),” on page 10: Updated
figure title; updated figure.
• Figure 6: “152-Ball Functional Block Diagram (Dual LPDDR),” on page 11: Added fig-
ure.
Rev. D, Prelim inary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/08
• Updated template; ready for external publication.
Rev. C, Prelim inary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08
• Added part number for JQ package code, page 1.
• Figure 2, Marketing Part Number Example, on page 2: added JQ package code.
• Added JQ package diagram, Figure 9, 152-Ball TFBGA (Package Code: JQ), on page 14.
Rev. B, Prelim inary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08
• On page 1, added part number for CA package code.
• Figure 2: Marketing Part Number Example on page 2: Added CA package code.
• Removed former capacitance tables. See component data sheets for capacitance.
• Figure 7: 152-Ball VFBGA (Package Code: CA) on page 12, and Figure 8: 152-Ball
VFBGA (Package Code: CG) on page 13: Updated figures.
Rev. A, Prelim inary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08
• Initial release.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
15
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