MAX3873A [MAXIM]
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC; 低功耗，结构紧凑的2.5Gbps / 2.7Gbps的时钟恢复和数据再定时IC
| 型号： | MAX3873A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC |
| 文件： | 总12页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2577; Rev 1; 5/03
Low-Power, Compact 2.5Gbps/2.7Gbps
Clock-Recovery and Data-Retiming IC
General Description
Features
♦ Fully Integrated Clock Recovery and Data
The MAX3873A is a compact, low-power 2.488Gbps/
2.67Gbps clock-recovery and data-retiming IC for
SDH/SONET applications. The phase-locked loop (PLL)
recovers a synchronous clock signal from the serial
NRZ data input. The input data is then retimed by this
recovered clock, providing a clean data output. The
MAX3873A meets all SDH/SONET jitter specifications,
does not require an external reference clock to aid in
frequency acquisition, and provides excellent tolerance
to both deterministic and sinusoidal jitter. The
MAX3873A provides a PLL loss-of-lock (LOL) output to
indicate whether the CDR is in lock. The recovered data
and clock outputs are CML with on-chip 50Ω back termi-
nations on each line. The clock output can be powered
down if not used.
Retiming
♦ Power Dissipation: 260mW with +3.3V Supply
♦ Clock Jitter Generation: 5mUI
RMS
♦ Exceeds ANSI, ITU, and Bellcore SDH/SONET
Jitter Specifications
♦ Differential Input Range: 50mV
♦ Single +3.3V Power Supply
to 1.6V
P-P
P-P
♦ PLL Fast Track (FASTRACK) Mode Available
♦ Clock Output Can Be Disabled
♦ Input Data Rate: 2.488Gbps or 2.67Gbps
♦ Selectable Output Amplitude
♦ Tolerates 2000 Consecutive Identical Digits
♦ Loss-of-Lock Indicator
The MAX3873A is implemented in Maxim’s second-
generation SiGe process and consumes only 260mW at
3.3V supply (output clock disabled, low output swing). The
device is available in a 4mm x 4mm 20-pin QFN
exposed-pad package and operates from -40°C to +85°C.
♦ Differential CML Data and Clock Outputs
♦ Operating Temperature Range: -40°C to +85°C
Ordering Information
Applications
Switch Matrix Backplanes
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
20 QFN
(4mm x 4mm)
MAX3873AEGP -40°C to +85°C
G2044
Digital Cross-Connects
SDH/SONET Test Equipment
DWDM Transmission Systems
Pin Configuration
TOP VIEW
Typical Application Circuit appears at end of data sheet.
RATESET
1
2
3
4
5
15 SDO+
V
CC
14 SDO-
SDI+
SDI-
13 VCC_BUF
MAX3873A
12 SCLKO+
V
11 SCLKO-
CC
QFN**
**NOTE: THE EXPOSED PAD MUST BE
SOLDERED TO THE SUPPLY GROUND.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +5.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-50°C to +150°C
Processing Temperature..................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Voltage at SDI .............................. (V
- 1.0V) to (V
+ 0.5V)
CC
CC
CML Output Current at SDO , SCLꢀO ............................22mA
Voltage at LOL, FASTRACꢀ, FIL , SCLꢀEN
MODE, RATESET...................................-0.5V to (V
+ 0.5V)
CC
Continuous Power Dissipation (T = +85°C)
A
20-Lead QFN (derate 20.0mW/°C above +85°C).....1300mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V = 3.0V to 3.6V, T = -40°C to +85°C. Typical values are at 2.488Gbps, V = 3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
CC
A
PARAMETER
Supply Current (Note 2)
CML INPUT SPECIFICATIONS (SDI+, SDI-)
SYMBOL
CONDITIONS
MODE = GND, SCLꢀEN = low
MODE = OPEN, SCLꢀEN = high
MIN
TYP
79
MAX
99
UNITS
I
mA
CC
112
142
Differential Input Voltage
V
Figure 1
50
1600
+ 0.4
mV
P-P
ID
Single-Ended Input
Voltage
V
Figure 1
V
CC
- 0.8
V
CC
V
IS
Input Common-Mode
Voltage
DC-coupled, Figure 1
V
CC
- V /4
V
ID
Input Termination to V
R
IN
40
50
60
Ω
CC
CML OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-)
MODE = open
640
400
200
800
600
400
1000
800
Differential Output Swing
(Note 3)
mV
MODE = V
CC
P-P
MODE = GND
600
Differential Output
Resistance
R
O
80
100
120
Ω
MODE = Open
MODE = V
V
V
V
- 0.17
- 0.13
- 0.08
CC
CC
CC
Output Common-Mode
Voltage (Note 3)
V
CC
MODE = GND
TTL INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET)
Input High Voltage
Input Low Voltage
Input Current
V
2.0
V
V
IH
V
0.8
IL
-30
2.4
+30
µA
V
Output High Voltage
Output Low Voltage
V
I
I
= sourcing 40µA
= sinking 2mA
OH
OH
V
0.4
V
OL
OL
2
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
AC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, C = 0.022µF, T = -40°C to +85°C. Typical values are at V
= 3.3V, 2.488Gbps, T = +25°C, unless otherwise
CC A
CC
A
F
noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.488
2.67
MAX
UNITS
RATESET = low
RATESET = high
Figure 2 (Note 5)
f ≤ 2MHz
Serial Input Data Rate
Gbps
Clock-to-Q Delay
Jitter Peaking
t
-70
+70
0.1
2.0
ps
dB
CLꢀ-Q
J
P
Jitter Transfer Bandwidth
J
RATESET = Low
MHz
BW
f = 70kHz, 0.4UI deterministic jitter
on input data
6.9
4.5
0.6
0.3
6.9
4.5
0.6
0.3
f = 100kHz, 0.4UI deterministic jitter
on input data
2.12
0.33
0.15
(Notes 6, 8)
f = 1MHz, 0.4UI deterministic jitter
on input data
f = 10MHz, 0.4UI deterministic jitter
on input data
Sinusoidal Jitter Tolerance
UI
P-P
f = 70kHz, 0.4UI deterministic jitter
on input data
f = 100kHz, 0.4UI deterministic jitter
on input data
2.12
0.33
0.15
(Notes 6, 9)
f = 1MHz, 0.4UI deterministic jitter
on input data
f = 10MHz, 0.37UI deterministic jitter
on input data
5
45
6
6.8
62
mUI
RMS
(Notes 7, 8)
(Notes 7, 9)
20% to 80%
20% to 80%
mUI
P-P
Jitter Generation
J
GEN
7.65 mUI
RMS
40
86
mUI
P-P
Clock Output Edge
Speed
60
60
110
ps
Data Output Edge
Speed
110
ps
bits
dB
Tolerated Consecutive
Identical Digits
2000
100kHz to 2.5GHz
2.5GHz to 4.0GHz
17
14
SDI Input Return Loss
(-20log(S ))
11
Frequency Acquisition
Time
Figure 4
Figure 4
1
ms
µs
LOL Assert Time
1.6
_______________________________________________________________________________________
3
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, C = 0.022µF, T = -40°C to +85°C. Typical values are at V
= 3.3V, 2.488Gbps, T = +25°C, unless otherwise
CC A
A
F
noted.) (Note 4)
Note 1: At T = -40°C, DC characteristics are guaranteed by design and characterization.
A
Note 2: CML outputs open.
Note 3: R = 50Ω to V
.
L
CC
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the falling edge of SCLꢀO+. See Figure 2.
23
Note 6: Measured with 2 - 1 PRBS.
Note 7: Jitter BW = 12kHz to 20MHz.
Note 8: RATESET = low.
Note 9: RATESET = high.
V
+ 0.4V
CC
t
CLK
25mV
25mV
800mV
V
CC
SCLKO+
SDO
V
CC
- 0.4V
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
800mV
t
CLK-Q
V
CC
V
V
- 0.4V
- 0.8V
CC
Figure 2. Definition of Clock-to-Q Delay
CC
(b) DC-COUPLED SINGLE-ENDED CML INPUT
Figure 1. Definition of Input Voltage Swing
SERIAL DATA
<2µs
1200 BITS OF 1–0 PATTERN
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
FASTRACK
Figure 3. Definition of Phase Acquisition Time
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL ASSERT TIME
LOL OUTPUT
Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time
_______________________________________________________________________________________
4
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
RECOVERED CLOCK AND DATA
(2.67Gbps, 223 - 1 PATTERN,
RECOVERED CLOCK AND DATA
(2.488Gbps, 223 - 1 PATTERN,
V
IN
= 50mV
)
V
IN
= 50mV
)
P-P
P-P
125mV/div
125mV/div
100ps/div
100ps/div
JITTER TOLERANCE
(2.488Gbps, 223 - 1 PATTERN,
RECOVERED CLOCK JITTER
(2.488Gbps)
V
IN
= 50mV
)
P-P
100
WITH 0.2UI OF PWD
WITH 0.4UI OF
DETERMINISTIC
JITTER
10
1
BELLCORE
MASK
23
2
- 1 PATTERN
RMS = 2.0ps
RMS
0.1
10
100
1000
10,000
10ps/div
JITTER FREQUENCY (kHz)
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO DISABLED)
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO ENABLED)
JITTER TRANSFER
200
180
160
140
120
100
80
200
180
160
140
120
100
80
0.5
0
-0.5
-1.0
MAX OUTPUT SWING
MED OUTPUT SWING
MAX OUTPUT SWING
MIN OUTPUT SWING
MED OUTPUT SWING
-1.5
-2.0
-2.5
-3.0
BELLCORE
MASK
60
60
MIN OUTPUT SWING
40
40
20
20
0
0
3
4
5
6
7
-50
-25
0
25
50
75
100
10
10
10
FREQUENCY (Hz)
10
10
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
BIT-ERROR RATIO
vs. INPUT AMPLITUDE
PULLIN RANGE (RATESET = 0)
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
-2
-3
-4
10
10
10
-5
-6
10
10
-7
-8
10
10
-9
10
-10
10
-50
0
50
100
0
1
2
3
4
5
AMBIENT TEMPERATURE (°C)
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE vs. INPUT
DETERMINISTIC JITTER
JITTER TOLERANCE vs. PULSE-WIDTH
DISTORTION
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
23
f
= 1MHz
JITTER
PRBS = 2 - 1
f
= 1MHz
JITTER
f
= 10MHz
JITTER
f
= 10MHz
JITTER
INPUT DATA FILTERED BY
1870MHz 4TH-ORDER
BESSEL FILTER
23
PRBS = 2 - 1
0.05
0.10
0.15
0.20
-40 -30 -20 -10
0
10 20 30 40
DETERMINISTIC JITTER (UI
)
INPUT PULSE-WIDTH DISTORTION (%)
P-P
Pin Description
PIN
NAME
FUNCTION
1
RATESET
Input Rate Select. Connect to TTL low for 2.488Gbps data and to TTL high for 2.67Gbps data.
2, 5, 6
V
3.3V Supply Voltage
CC
3
4
SDI+
SDI-
Positive Serial Data Input
Negative Serial Data Input
PLL Fast Track Control, TTL Input. When FASTRACꢀ is TTL high, the PLL is switched to a fast-
track mode for fast phase acquisition. When FASTRACꢀ is TTL low, the PLL operates normally.
7
8
9
FASTRACꢀ
VCC_VCO
MODE
3.3V VCO Supply Voltage
Output Amplitude Mode Select. MODE = open sets the CML output amplitude to high; MODE =
high sets the output amplitude to medium; MODE = low sets the output amplitude to low.
6
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Pin Description (continued)
PIN
NAME
FUNCTION
Clock Output Enable, TTL Input. When SCLꢀEN = open or SCLꢀEN = high, the clock outputs
(SCLꢀO ) are enabled. When SCLꢀEN = low, the clock outputs are disabled and SCLꢀO = V
10
SCLꢀEN
.
CC
11
12
SCLꢀO-
SCLꢀO+
VCC_BUF
SDO-
Negative Clock Output, CML. This output can be disabled by setting SCLꢀEN to low.
Positive Clock Output, CML. This output can be disabled by setting SCLꢀEN to low.
3.3V CML Output Buffer Supply Voltage
13
14
Negative Data Output, CML
15
SDO+
LOL
Positive Data Output, CML
16
Loss-of-Lock Output, TTL (Active Low). The LOL output indicates a PLL lock failure.
Supply Ground
17, 20
18
GND
FIL-
Negative PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
Positive PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
19
FIL+
Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and
thermal operation.
EP
Exposed Pad
Input Amplifier
Detailed Description
The input amplifier provides internal 50Ω line termina-
The MAX3873A consists of a fully integrated phase-
locked loop (PLL), input amplifier, and CML output
buffers (Figure 5). The PLL consists of a phase/fre-
quency detector, a loop filter, and a voltage-controlled
oscillator (VCO).
tions and can accept a differential input amplitude from
50mV
to 1600mV
. The structure of the input
P-P
P-P
amplifier is shown in Figure 9.
Phase Detector
The phase detector incorporated in the MAX3873A pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during startup conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the VCO outputs on each
edge of the data input signal. The FD drives the VCO
until the frequency difference is reduced to zero. Once
frequency acquisition is complete, the FD returns to a
neutral state.
V
GND
FIL+ FIL-
RATESET
CC
SDO+
SDO-
AMP
AMP
MAX3873A
MODE
SDI+
SDI-
AMP
PHASE AND
FREQUENCY
DETECTOR
SCLKO+
SCLKO-
I
VCO
Q
LOOP
FILTER
Loop Filter and VCO
The phase detector and frequency detector outputs are
SCLKEN
LOL
summed into the loop filter. An external capacitor, C ,
F
is required to set the PLL damping ratio. See the
Design Procedure section for guidelines on selecting
this capacitor.
FASTRACK
Figure 5. Functional Diagram
_______________________________________________________________________________________
7
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
The loop filter output controls the on-chip LC VCO run-
ning at either 2.488GHz or 2.67GHz. The VCO provides
low phase noise and is trimmed to the correct
For example, using C = 2000pF results in jitter peaking
F
of 0.2dB. Reducing C below 500pF might result in PLL
F
instability. The recommended value is C = 0.022µF to
F
frequency. Clock jitter generation is typically 2ps
within a jitter band of 12kHz to 20MHz.
RMS
guarantee a maximum jitter peaking of less than 0.1dB.
C must be a low TC, high-quality capacitor of type X7R
F
or better.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the
MAX3873A to indicate either a loss of frequency lock or
the absence of incoming data. Under loss-of-lock con-
ditions, LOL may momentarily assert high due to noise.
FASTRACK Mode
The MAX3873A has a PLL fast-track (FASTRACꢀ) mode
to decrease locking time in switched data applications.
In applications where the input data is switched from one
source to another, there is a brief period in which there is
no valid data input to the MAX3873A. In the absence of
input data, the PLL phase slowly drifts from the ideal
position. By enabling FASTRACꢀ during reacquisition,
the time required to regain phase alignment is reduced.
This is accomplished by increasing the loop bandwidth
by approximately 50%.
Design Procedure
Setting the Loop Filter
The MAX3873A is designed for both regenerator and
receiver applications. Its fully integrated PLL is a classic
second-order feedback system, with a loop bandwidth
(J ) below 2.0MHz. The external capacitor, C , can be
BW
F
adjusted to set the loop damping. Figures 6 and 7 show
the open-loop and closed-loop transfer functions. The
The bandwidth of the MAX3873A is also linearly depen-
dent upon the transition density of the input data. By using
a preamble of 1200 bits of a 1–0 pattern during switching,
the loop bandwidth is increased by a factor of approxi-
mately 2 (Figure 3). Thus, by using a 1–0 pattern pream-
ble and enabling FASTRACꢀ, the PLL bandwidth is
increased by a factor of approximately 3, resulting in the
fastest possible reacquisition of phase lock.
PLL zero frequency, f , is a function of external capacitor
Z
C and can be approximated according to:
F
1
f
=
z
2π (3000Ω) C
F
with C expressed in F.
F
FASTRACꢀ increases the rate at which the MAX3873A
acquires the proper phase, assuming that the VCO is
already running at the proper frequency. On startup con-
ditions, however, the VCO frequency is significantly differ-
ent from the input data, and the time required to lock to
the incoming data is increased to approximately 1.0ms.
For an overdamped system, the jitter peaking (J ) of a
P
second-order system can be approximated by:
f
z
J
= 20log 1 +
P
J
BW
H (j2πf) (dB)
O
H(j2πf) (dB)
C = 2000pF
F
0
-3
C = 0.022µF
F
C = 0.022µF
F
C = 2000pF
F
f = 2.4kHz
Z
f = 26kHz
Z
f (kHz)
f (kHz)
1
100
10
1000
100
1000
1
10
Figure 6. Open-Loop Transfer Function
Figure 7. Closed-Loop Transfer Function
8
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Sinusoidal Jitter Tolerance and
Input Deterministic Jitter Trade-Offs
Applications Information
Consecutive Identical Digits (CID)
The MAX3873A has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of less than 10-10. The CID tolerance
is tested using a 213 - 1 PRBS, substituting a long run
of zeros to simulate the worst case. A CID tolerance of
2000 bits is typical.
The MAX3873A has excellent jitter tolerance. Adding DJ
to the input will close the eye opening and result in
reduced sinusoidal jitter tolerance. It typically can toler-
ate more than 0.3UI
of 10MHz jitter when measured
P-P
with a 223 - 1 PRBS data stream with 0.4UI of determin-
istic jitter (DJ). This gives a total high-frequency jitter tol-
erance of 0.7UI. Refer to the Jitter Tolerance vs.
Pulse-Width Distortion and Jitter Tolerance vs.
Deterministic Jitter graphs in the Typical Operating
Characteristics section.
Exposed-Pad Package
The exposed-pad (EP), 20-pin QFN incorporates fea-
tures that provide a very low thermal-resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3873A and must be soldered to the circuit
board for proper thermal and electrical performance.
Input and Output Terminations
The MAX3873A’s digital CML outputs (SDO+, SDO-,
SCLꢀO+, SCLꢀO-) have selectable output amplitude
controlled by the MODE input. If the SCLꢀO outputs
are not used, they can be disabled (see the Supply
Current vs. Temperature graph in the Typical Operating
Characteristics section).
Layout
Circuit board layout and design can significantly affect
the MAX3873A’s performance. Use good high-frequency
design techniques, including minimizing ground induc-
tance and using controlled-impedance transmission
lines on the data and clock signals. Place power-supply
The structure of the high-speed digital outputs is shown
in Figure 8. The MODE input sets the current in the cur-
rent source, thereby controlling the output swing. The
SCLꢀEN input sets the current in the SCLꢀO current
source to 0mA, disabling the output.
decoupling as close to the V
pins as possible. Isolate
CC
the input from the output signals to reduce feedthrough.
The structure of the CML inputs (SDI ) is shown in Figure
9. Unless the CML input is DC-coupled to a CML output,
use AC-coupling with the CML inputs to avoid upsetting
the common-mode voltage.
V
CC
MAX3873A
V
CC
V
CC
50Ω
50Ω
50Ω
SDI+
OUT+
OUT-
V
CC
50Ω
SDI-
MODE
SCLKO ONLY
SCLKEN
MAX3873A
Figure 8. CML Output Model
Figure 9. CML Input Model
_______________________________________________________________________________________
9
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Typical Application Circuit
SWITCH CARD
2.5Gbps OPTICAL
TRANSCEIVER
MAX3873A
CDR
CROSSPOINT
SWITCH
FIL+
FIL- LOL
MODE
SDI+
SDI-
SDO+
SDO-
SCLKO+
SCLKO-
SCLKEN
MAX3873A
FASTRACK
20-PIN QFN
RATESET
Chip Information
TRANSISTOR COUNT: 2028
PROCESS: SiGe BiCMOS
10 ______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
1
21-0106
E
2
______________________________________________________________________________________ 11
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
2
21-0106
E
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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