MAX3874 [MAXIM]
2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier ; 2.488Gbps速率/ 2.667Gbps时钟和数据恢复，带限幅放大器\n
| 型号： | MAX3874 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
|
| 文件： | 总13页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
198-2710; Rev 0; 2/03
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
General Description
Features
The MAX3874 is a compact, dual-rate clock and data
recovery with limiting amplifier for OC-48 and OC-48
with FEC SONET/SDH applications. Without using an
external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by this recovered clock, providing a clean data
output. An additional serial input (SLBI ) is available for
system-loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain
a valid clock output in the absence of data transitions.
The device also includes a loss-of-lock (LOL) output.
ꢀ 2.488Gbps and 2.667Gbps Input Data Rates
ꢀ Reference Clock Not Required for Data
Acquisition
ꢀ Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
ꢀ 2.7mUI
Clock Jitter Generation
RMS
ꢀ 10mV
Input Sensitivity Without Threshold
P-P
Adjust
ꢀ 0.65UI
High-Frequency Jitter Tolerance
P-P
ꢀ
170mV Wide Input Threshold Adjust Range
The MAX3874 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all SONET/
SDH specifications. The MAX3874A is the MAX3874
with a voltage-controlled oscillator (VCO) centered at
2.0212GHz.
ꢀ Clock Holdover Capability Using Frequency-
Selectable Reference Clock
ꢀ Serial Loopback Input Available for System
Diagnostic Testing
ꢀ Loss-of-Lock (LOL) Indicator
ꢀ Small 5mm ✕ 5mm 32-Pin QFN Package
The MAX3874 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm ✕
5mm 32-pin QFN with exposed pad package and oper-
ates over the -40°C to +85°C temperature range.
Ordering Information
PIN-
PKG
PART
TEMP RANGE
PACKAGE
CODE
Applications
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
32 QFN-EP*
32 QFN-EP*
MAX3874EGJ
-40°C to +85°C
-40°C to +85°C
G3255-1
G3255-1
MAX3874AEGJ**
*EP = Exposed pad.
Digital Cross-Connects
**Contains a VCO centered at 2.0212GHz.
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
+3.3V
CAZ
0.1µF
C
+3.3V +3.3V
FIL
0.068µF
V
CC
FIL VCC_VCO CAZ- CAZ+ FREFSET V
CC
FILTER
OUT+
SDI+
2.488Gbps DATA
MAX3745*
OUT-
SDO+
SDO-
SDI-
CML
CML
IN
SLBI+
SLBI-
MAX3874
GND
SCLKO+
SCLKO-
+3.3V
V
V
CTRL
REF
2.488Gbps SYSTEM
LOOPBACK DATA
SIS
LREF LOL
+3.3V
RATESET GND
*FUTURE PRODUCT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +5.0V
Continuous Power Dissipation (T = +85°C)
CC
A
Input Voltage Levels (SDI+, SDI-,
SLBI+, SLBI-) ..............................(V
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-).............. 20ꢀA
CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ... 22ꢀA
Voltage at LOL, LREF, SIS, FIL, RATESET, FREFSET,
32-Pin QFN (derate 21.3ꢀW/°C above +85°C) .........1384ꢀW
Operating Junction Teꢀperature ......................-55°C to +150°C
Storage Teꢀperature Range.............................-55°C to +150°C
Processing Teꢀperature (die) .........................................+400°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
- 1.0V) to (V
+ 0.5V)
CC
CC
V
,V
, CAZ+, CAZ-.......................-0.5V to (V
+ 0.5V)
CTRL REF
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
(Note 2)
175
215
ꢀA
CC
INPUT SPECIFICATION (SDI , SLBI )
Single-Ended Input Voltage
Range
V
0.8
-
-
V
+
CC
0.4
CC
V
Figure 1
Figure 1
V
IS
V
0.4
CC
Input Coꢀꢀon-Mode Voltage
V
V
CC
Input Terꢀination to V
R
42.5
50
57.5
Ω
CC
IN
THRESHOLD-SETTING SPECIFICATION (SDI )
Differential Input Voltage Range
(SDI )
Threshold adjust enabled
50
600
ꢀV
P-P
Threshold Adjustꢀent Range
Threshold Control Voltage
Threshold Control Linearity
Threshold Setting Accuracy
V
Figure 2
-170
0.3
+170
2.1
ꢀV
TH
V
%
V
Figure 2 (Note 3)
CTRL
5
Figure 2
-18
-6
+18
+6
ꢀV
15ꢀV ≤ |V | ≤ 80ꢀV
TH
Threshold Setting Stabiliity
ꢀV
80ꢀV < |V | ≤ 170ꢀV
-12
-10
2.14
+12
+10
2.24
TH
Maxiꢀuꢀ Input Current
I
µA
V
CTRL
Reference Voltage Output
V
2.2
REF
CML OUTPUT SPECIFICATION (SDO , SCLKO )
CML Differential Output
Iꢀpedance
R
85
100
115
Ω
O
CML Output Coꢀꢀon-Mode
Voltage
V
0.2
-
CC
(Note 4)
V
2
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LREF, RATESET, FREFSET)
LVTTL Input High Voltage
LVTTL Input Low Voltage
LVTTL Input Current
V
2.0
V
V
IH
V
0.8
IL
-10
2.4
+10
µA
V
LVTTL Output High Voltage
LVTTL Output Low Voltage
V
I
I
= +20µA
= -1ꢀA
OH
OH
OL
V
0.4
V
OL
Note 1: At -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: CML outputs open.
Note 3: Voltage applied to V
pin is froꢀ 0.3V to 2.1V when input threshold is adjusted froꢀ +170ꢀV to -170ꢀV.
CTRL
Note 4: R = 50Ω to V
.
L
CC
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 5)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.488
2.667
2.0212
MAX
UNITS
MAX3874 (RATESET = GND)
MAX3874 (RATESET = VCC)
MAX3874A
Serial Input Data Rate
Gbps
Differential Input Voltage (SDI )
Differential Input Voltage (SLBI )
V
Threshold adjust disabled, Figure 1 (Note 6)
BER ≤ 10-10
10
50
1600
800
2.0
ꢀV
ꢀV
ID
P-P
P-P
MAX3874
1.5
Jitter Transfer Bandwidth
Jitter Peaking
J
MHz
dB
BW
MAX3874A
0.75
J
f ≤ J
0.1
P
BW
f = 100kHz
3.1
8.0
0.93
0.65
>0.5
>0.3
7.1
Sinusoidal Jitter Tolerance
MAX3874
f = 1MHz
0.62
0.44
UI
P-P
P-P
P-P
f = 10MHz
f = 1MHz (Note 7)
f = 10MHz (Note 7)
f = 100kHz
Sinusoidal Jitter Tolerance
(MAX3874A)
UI
UI
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
(Note 8)
f = 1MHz
0.82
0.54
2.7
f = 10MHz
ꢀUI
Jitter Generation
J
(Note 9)
4.0
RMS
GEN
100kHz to 2.5GHz
2.5GHz to 4GHz
16
Differential Input Return Loss
(SDI , SLBI )
-20log
| S
dB
|
11
15
CML OUTPUT SPECIFICATION (SDO , SCLKO )
Output Edge Speed
t , t
20% to 80%
110
1000
+40
ps
ꢀV
r
f
CML Output Differential Swing
Clock-to-Q Delay
R = 100Ω differential
L
600
-40
800
P-P
t
(Note 10)
ps
CLK-Q
_______________________________________________________________________________________
3
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 5)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL ACQUISITION/LOCK SPECIFICATION
Tolerated Consecutive Identical
Digits
BER ≤ 10-10
2000
Bits
Acquisition Tiꢀe
Figure 4 (Note 11)
Figure 4
1.0
ꢀs
µs
LOL Assert Tiꢀe
2.3
10.0
Low-Frequency Cutoff for DC-
Offset Cancellation Loop
CAZ = 0.1µF
4
kHz
CLOCK HOLDOVER SPECIFICATION
Reference Clock Frequency
Table 4
ppꢀ
CTRL
Maxiꢀuꢀ VCO Frequency Drift
(Note 12)
400
Note 5: Miniꢀuꢀ and ꢀaxiꢀuꢀ AC characteristics are guaranteed by design and characterization using the MAX3874.
Specifications apply to the MAX3874A only when noted.
Note 6: Jitter tolerance is guaranteed (BER ≤ 10-10) within this input voltage range. Input threshold adjust is disabled with V
connected to V
.
CC
Note 7: Measureꢀents liꢀited by equipꢀent capability.
Note 8: Measured using a 100ꢀV differential swing with a 20ꢀVDC offset and an edge speed of 145ps (4th-order Bessel filter
P-P
with f
= 1.8GHz).
3dB
Note 9: Measured with 10ꢀV
differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth froꢀ 12kHz to 20MHz.
P-P
Note 10: Relative to the falling edge of the SCLKO+ (Figure 3).
Note 11: Measured at OC-48 data rate using a 0.068µF loop filter capacitor initialized to +3.6V.
Note 12: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock.
Timing Diagrams
V
+ 0.4V
V
(mV)
CC
TH
5mV
5mV
+188
THRESHOLD-SETTING STABILITY
800mV
(OVERTEMPERATURE AND POWER SUPPLY)
+170
+152
V
CC
V
- 0.4V
CC
1.3
(a) AC-COUPLED SINGLE-ENDED INPUT
800mV
V
(V)
CTRL
V
CC
0.3
2.1
1.1
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
V
V
- 0.4V
- 0.8V
CC
CC
-152
-170
-188
(b) DC-COUPLED SINGLE-ENDED INPUT
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
Figure 1. Definition of Input Voltage Swing
4
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Timing Diagrams (continued)
DATA
DATA
t
CLK
INPUT DATA
LOL OUTPUT
SCLKO+
SDO
t
CLK-Q
ACQUISITION TIME
LOL ASSERT TIME
Figure 3. Definition of Clock-to-Q Delay
Figure 4. LOL Assert Time and PLL Acquisition Time
Measurement
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
RECOVERED CLOCK AND DATA
23
RECOVERED CLOCK AND DATA
23
(2.488Gbps, 2 - 1 PATTERN, V = 10mV
)
(2.67Gbps, 2 - 1 PATTERN, V = 10mV
)
P-P
IN
P-P
IN
200mV/
div
200mV/
div
100ps/div
100ps/div
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
JITTER TOLERANCE
23
RECOVERED CLOCK JITTER
(2.488Gbps)
(2.488Gbps, 2 - 1 PATTERN, V = 10mV
)
P-P
IN
100
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
OC-48
PRBS = 2 - 1
23
WITH ADDITIONAL 0.15UI
OF DETERMINISTIC JITTER
10
1
BELLCORE
MASK
0.1
0
5
10
15
20
25
30
10k
100k
1M
10M
10ps/div
WHITE-NOISE AMPLITUDE (mV
)
JITTER FREQUENCY (Hz)
RMS
TOTAL WIDEBAND RMS JITTER = 1.60ps
PEAK-TO-PEAK JITTER = 12.20ps
_______________________________________________________________________________________
5
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
JITTER TOLERANCE
vs. INPUT DETERMINISTIC JITTER
JITTER TOLERANCE
vs. THRESHOLD ADJUST
JITTER TOLERANCE vs. INPUT AMPLITUDE
23
(2.488Gbps, 2 - 1 PATTERN)
1.0
0.9
0.8
0.7
0.6
23
2
- 1 PATTERN
JITTER FREQUENCY = 10MHz
2.488Gbps
= 10mV
P-P
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
JITTER FREQUENCY = 1MHz
0.8
f
= 1MHz
V
JITTER
IN
0.5
0.4
0.3
0.2
0.1
0.7
0.6
0.5
V
= 100mV
P-P
IN
2.488Gbps
23
2
- 1 PATTERN
f
= 10MHz
JITTER
JITTER FREQUENCY = 10MHz
0.4
0.3
0.2
INPUT DATA FILTERED BY
A 1870MHz 4TH-ORDER
BESSEL FILTER
WITH ADDITIONAL 0.15UI
0.1
DETERMINISTIC JITTER
0
0
0
0.05 0.10
0.15 0.20
0.25 0.30
)
1
10
100
1000
10,000
10 20
30 40 50 60
70 80 90
DETERMINISTIC JITTER (UI
INPUT AMPLITUDE (mV
)
P-P
INPUT THRESHOLD (% AMPLITUDE)
P-P
BIT-ERROR RATIO
vs. INPUT AMPLITUDE
SUPPLY CURRENT vs. TEMPERATURE
JITTER TRANSFER
-2
-3
200
195
190
185
180
175
170
165
160
155
150
145
140
10
10
0.5
0
-4
-5
10
10
-0.5
-1.0
-1.5
-2.0
BELLCORE
MASK
-6
10
-7
-8
-9
10
10
10
C
= 0.068µF
FIL
23
PRBS = 2 - 1
2.488Gbps
OC-48
-2.5
-3.0
-10
-11
10
10
23
PRBS = 2 - 1
0
1
2
3
4
5
1k
10k
100k
FREQUENCY (Hz)
1M
10M
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
INPUT VOLTAGE (mV
)
P-P
DIFFERENTIAL S11 vs. FREQUENCY
PULLIN RANGE (RATESET = 0)
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
-5
-10
-15
-20
-25
-30
-35
-40
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FREQUENCY (GHz)
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
6
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Pin Description
PIN
NAME
FUNCTION
1, 4, 27
V
+3.3V Supply Voltage
CC
2
3
5
6
7
SDI+
SDI-
Positive Serial Data Input, CML
Negative Serial Data Input, CML
SLBI+
SLBI-
SIS
Positive Systeꢀ Loopback Input or Reference Clock Input, CML
Negative Systeꢀ Loopback Input or Reference Clock Input, CML
Signal Selection Input, LVTTL. Set low for norꢀal operation, set high for systeꢀ loopback.
Lock-to-Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to
reference clock.
8
9
LREF
LOL
GND
FIL
Loss-of-Lock Output, LVTTL. Active low.
10, 11, 16,
25, 32
Supply Ground
12
13, 18
14, 15
17
PLL Loop-Filter Capacitor Input. Connect a 0.068µF capacitor between FIL and VCC_VCO.
VCC_VCO +3.3V Supply Voltage for the VCO
N.C. Not Connected
RATESET VCO Frequency Select Input, LVTTL (Tables 2, 3, and 4)
SCLKO- Negative Serial Clock Output, CML
19
20
SCLKO+ Positive Serial Clock Output, CML
21, 24
22
VCC_OUT Supply Voltage for the CML Outputs
SDO-
Negative Serial Data Output, CML
Positive Serial Data Output, CML
23
SDO+
26
FREFSET Reference Clock Frequency Select Input, LVTTL (Tables 2, 3, and 4)
Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and
28
29
CAZ+
CAZ-.
Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and
CAZ-.
CAZ-
30
31
V
+2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustꢀent.
Analog Control Input for Threshold Adjustꢀent. Connect to V to disable threshold adjust.
REF
V
CTRL
CC
Exposed Ground. The exposed pad ꢀust be soldered to the circuit board ground for proper therꢀal and electrical
EP
Pad
perforꢀance.
_______________________________________________________________________________________
7
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
SLBI Input Amplifier
Detailed Description
The SLBI input aꢀplifier accepts either NRZ loopback
The MAX3874 consists of a fully integrated PLL liꢀiting
data or a reference clock signal. This aꢀplifier can
aꢀplifier with threshold adjust, DC-offset cancellation
accept a differential input aꢀplitude froꢀ 50ꢀV
to
P-P
loop, data retiꢀing block, and CML output buffers
(Figure 5). The PLL consists of a phase/frequency
detector, a loop filter, and a VCO.
800ꢀV
.
P-P
Phase Detector
The phase detector incorporated in the MAX3874 pro-
duces a voltage proportional to the phase difference
between the incoꢀing data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoꢀing data eye for retiꢀing.
This device is designed to deliver the best coꢀbination
of jitter perforꢀance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
SDI Input Amplifier
The SDI inputs of the MAX3874 accept serial NRZ data
Frequency Detector
The digital frequency detector (FD) acquires frequency
lock without the use of an external reference clock. The
frequency difference between the received data and
the VCO clock is derived by saꢀpling the in-phase and
quadrature VCO outputs on both edges of the data-
input signal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is coꢀplete, the FD returns to a neutral state. False
locking is eliꢀinated by this digital frequency detector.
with a differential input aꢀplitude froꢀ 10ꢀV
to
P-P
1600ꢀV . The input sensitivity is 10ꢀV , at which
P-P
P-P
the jitter tolerance is ꢀet for a BER of 10-10 with thresh-
old adjust disabled. The input sensitivity can be as low
as 4ꢀV
and still ꢀaintain a BER of 10-10. The
P-P
MAX3874 inputs are designed to directly interface with
a transiꢀpedance aꢀplifier such as the MAX3745.
For applications in which vertical threshold adjustꢀent is
needed, the MAX3874 can be connected to the output of
an AGC aꢀplifier such as the MAX3861. When using the
threshold adjust, the input voltage range is 50ꢀV
to
P-P
600ꢀV
(see the Design Procedure section).
P-P
V
REF
LOL
CAZ+
CAZ-
FIL
RATESET
MAX3874
BANDGAP
REFERENCE
THRESHOLD
ADJUST
V
CTRL
SDI+
SDI-
DC-OFFSET
CANCELLATION
LOOP
AMP
AMP
SDO+
SDO-
0
1
D
CML
CML
Q
PHASE/
FREQUENCY
DETECTOR
SCLKO+
SCLKO-
SLBI+
SLBI-
LOOP
FILTER
VCO
SIS
LREF
LOGIC
FREFSET
Figure 5. Functional Diagram
8
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Loop Filter and VCO
Modes of Operation
The MAX3874 has three operational ꢀodes controlled by
the LREF and SIS inputs: norꢀal, systeꢀ loopback, and
clock holdover. Norꢀal operation ꢀode requires a serial
data streaꢀ at the SDI inputs, systeꢀ loopback ꢀode
requires a serial data streaꢀ at the SLBI inputs, and
clock holdover ꢀode requires a reference clock signal at
the SLBI inputs. See Table 1 for the required LREF and
SIS settings. Once an operational ꢀode is chosen, the
reꢀaining logic inputs (RATESET, FREFSET) prograꢀ
the input data rate or reference clock frequency.
The phase detector and frequency detector outputs are
suꢀꢀed into the loop filter. An external capacitor (C
)
FIL
connected froꢀ FIL to VCC_VCO is required to set the
PLL daꢀping ratio. Note that the PLL jitter bandwidth
does not change as the external capacitor changes,
but the jitter peaking, acquisition tiꢀe, and loop stability
are affected. See the Design Procedure section for
guidelines on selecting this capacitor.
The loop filter output controls the two on-chip VCOs.
The VCOs provide low phase noise and are triꢀꢀed to
the 2.488GHz and 2.667GHz frequencies. (The
MAX3874A uses a single VCO triꢀꢀed to 2.0212GHz.)
The RATESET pin is used to select the appropriate
VCO. See Tables 2, 3, and 4 for the proper settings.
Normal and System Loopback Settings
The RATESET pin is available for setting the SDI and
SLBI inputs to receive the appropriate data rate. The
FREFSET pin can be set to a zero or 1 while in norꢀal
or systeꢀ-loopback ꢀode (Tables 2 and 3).
Loss-of-Lock Monitor
The LOL output indicates a PLL lock failure due to
excessive jitter present at the data input or due to loss
of input data. The LOL output is asserted low when the
PLL loses lock.
DC-Offset Cancellation Loop
A DC-offset cancellation loop is iꢀpleꢀented to reꢀove
the DC offset of the liꢀiting aꢀplifier. To ꢀiniꢀize the low-
frequency pattern-dependent jitter associated with this
DC-cancellation loop, the low-frequency cutoff is 10kHz
(typ) with CAZ = 0.1µF, connected froꢀ CAZ+ to CAZ-.
The DC-offset cancellation loop operates only when
threshold adjust is disabled.
Table 1. Operational Modes
MODE
Norꢀal
LREF
SIS
0
1
1
0
Systeꢀ loopback
Clock holdover
1
1 or 0
Design Procedure
Table 2. Data-Rate Settings (MAX3874)
Decision Threshold Adjust
In applications in which the noise density is not bal-
anced between logical zeros and ones (i.e., optical
aꢀplification using EDFA aꢀplifiers), lower bit-error
ratios (BERs) can be achieved by adjusting the input
INPUT DATA RATE
RATESET
FREFSET
(Gbps)
2.667
2.488
1
0
1 or 0
1 or 0
threshold. Varying the voltage at V
froꢀ +0.3V to
CTRL
+2.1V achieves a vertical decision threshold adjust-
ꢀent of +170ꢀV to -170ꢀV, respectively (Figure 2).
Use the provided bandgap reference voltage output
Table 3. Data-Rate Settings (MAX3874A)
(V
) with a voltage-divider circuit or the output of a
REF
INPUT DATA RATE
DAC to set the voltage at V
using V
be used to generate the voltage for V
. See Figure 10 when
RATESET
FREFSET
CTRL
(Gbps)
to generate the voltage for V
. V
can
REF
CTRL REF
2.0212
0
1 or 0
(Figure 10).
CTRL
If threshold adjust is not required, disable it by con-
necting V directly to V and leave V floating.
CTRL
CC
REF
_______________________________________________________________________________________
9
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Table 4. Holdover Frequency Settings
REFERENCE CLOCK
FREQUENCY (MHz)
SCLKO FREQUENCY (GHz)
RATESET
FREFSET
666.51
622.08
166.63
155.52
2.667
2.488
2.667
2.488
1
0
1
0
0
0
1
1
Clock Frequencies in Holdover Mode
Set the incoꢀing reference-clock frequency and outgo-
ing serial-clock frequency by setting RATESET and
FREFSET appropriately (Table 3).
H (j2πf) (dB)
O
Setting the Loop Filter
The MAX3874 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback systeꢀ, with a jitter transfer
C
= 0.068µF
f = 3.6kHz
Z
FIL
C
= 0.01µF
bandwidth (J ) below 2MHz. The external capacitor
BW
FIL
f = 24.5kHz
Z
(C ) connected froꢀ FIL to VCC_VCO sets the PLL
FIL
daꢀping. Note that the PLL jitter transfer bandwidth
does not change as C
changes, but the jitter peak-
FIL
ing, acquisition tiꢀe, and loop stability are affected.
Figures 6 and 7 show the open-loop and closed-loop
transfer functions.
f (kHz)
100
1000
1
10
The PLL zero frequency, f , is a function of external
Z
Figure 6. Open-Loop Transfer Function
capacitor C , and can be approxiꢀated according to:
FIL
1
f =
Z
2π(650Ω)C
FIL
C
= 0.01µF
H(j2πf) (dB)
FIL
For an overdaꢀped systeꢀ (f / J
< 0.25), the jitter
BW
Z
peaking (J ) of a second-order systeꢀ can be approxi-
P
0
ꢀated by:
-3
C
= 0.068µF
FIL
f
Z
J
= 20log 1+
P
J
BW
where J
is the jitter transfer bandwidth for a given
BW
data rate.
f (kHz)
1
10
100
1000
The recoꢀꢀended value of C
= 0.068µF is to guar-
FIL
antee a ꢀaxiꢀuꢀ jitter peaking of less than 0.1dB.
Decreasing C froꢀ the recoꢀꢀended value
FIL
Figure 7. Closed-Loop Transfer Function
decreases acquisition tiꢀe, with the trade-off of
increased peaking. Excessive reduction of C can
FIL
vide internal 50Ω terꢀination to reduce the required
nuꢀber of external coꢀponents. AC-coupling is recoꢀ-
ꢀended. See Figure 8 for the input structure. For addi-
tional inforꢀation about logic interfacing, refer to Maxiꢀ
Application Note HFAN 1.0: Introduction to LVDS,
PECL, and CML.
cause PLL instability. C
ꢀust be a low-TC, high-qual-
FIL
ity capacitor of type X7R or better.
Input Terminations
The SDI and SLBI inputs of the MAX3874 are cur-
rent-ꢀode-logic (CML) coꢀpatible. The inputs all pro-
10 ______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
V
CC
MAX3874
V
CC
50Ω
50Ω
50Ω
50Ω
SDI+
SDI-
SDO+
SDO-
MAX3874
Figure 8. CML Input Model
Output Terminations
The MAX3874 uses CML for its high-speed digital out-
puts (SDO and SCLKO ). The configuration of the
output circuit includes internal 50Ω back terꢀinations
Figure 9. CML Output Model
Consecutive Identical Digits (CIDs)
to V . See Figure 9 for the output structure. CML out-
CC
The MAX3874 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
ꢀaintaining a BER better than 10-10. The CID tolerance
is tested using a 213 - 1 PRBS with long runs of ones
and zeros inserted in the pattern. A CID tolerance of
2000 bits is typical.
puts can be terꢀinated by 50Ω to V , or by 100Ω dif-
CC
ferential iꢀpedance. For additional inforꢀation on logic
interfacing, refer to Maxiꢀ Application Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
Applications Information
Clock Holdover Capability
Clock holdover is required in soꢀe applications in
which a valid clock ꢀust be provided to the upstreaꢀ
device in the absence of data transitions. To provide
this function, an external reference clock signal ꢀust
be applied to the SLBI inputs and the proper control
signals set (see the Modes of Operation section). To
enter holdover ꢀode autoꢀatically when there are no
transitions applied to the SDI+ inputs, LOL or the sys-
teꢀ LOS can be directly connected to LREF.
Exposed Pad (EP) Package
The EP, 32-pin QFN incorporates features that provide
a very low therꢀal-resistance path for heat reꢀoval
froꢀ the IC. The pad is electrical ground on the
MAX3874 and should be soldered to the circuit board
for proper therꢀal and electrical perforꢀance.
Layout Considerations
For best perforꢀance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use ꢀultiple vias where possible.
Use controlled-iꢀpedance transꢀission lines to inter-
face with the MAX3874 high-speed inputs and outputs.
System Loopback
The MAX3874 is designed to allow systeꢀ-loopback
testing. When the device is set for systeꢀ-loopback
ꢀode, the serial output data of a transꢀitter can be
directly connected to the SLBI inputs to run systeꢀ
diagnostics. See Table 1 for selecting systeꢀ loopback
operation ꢀode. While in systeꢀ loopback ꢀode, LREF
should not be connected to LOL.
Place power-supply decoupling as close to V
as
CC
possible. To reduce feedthrough, isolate the input sig-
nals froꢀ the output signals. If a bare die is used,
ꢀount the back of die to ground (GND) potential.
Figure 10 shows interfacing with the MAX3861 AGC
using threshold adjust.
______________________________________________________________________________________ 11
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
+3.3V
+3.3V
0.1µF
+3.3V
0.068µF
+3.3V
VCC
FIL VCC_VCO CAZ- CAZ+
SDI+
FREFSET
TIA OUTPUT
(2.488Gbps)
MAX3861
AGC AMPLIFIER
SDI-
SDO+
CML
CML
SLBI+
SLBI-
SDO-
SCLKO+
SCLKO-
MAX3874
V
CTRL
R1
V
REF
155.52MHz
REFERENCE CLOCK
SIS
LREF
LOL
TTL
RATESET GND
R2
R1 + R2 ≥ 50kΩ
Figure 10. Interfacing with the MAX3861 AGC Using Threshold Adjust
Pin Configuration
Chip Information
TRANSISTOR COUNT: 5142
PROCESS: SiGe BiPOLAR
SUBSTRATE: SOI
TOP VIEW
V
1
2
3
4
5
6
7
8
24 VCC_OUT
CC
SDI+
SDI-
23
22
SDO+
SDO-
V
21 VCC_OUT
CC
MAX3874
20
19
SLBI+
SLBI-
SIS
SCLKO+
SCLKO-
18 VCC_VCO
17
LREF
RATESET
5mm x 5mm
32 QFN
12 ______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and Data Recovery
with Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2003 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
相关型号：
MAX3874AEGJ-T
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.90 MM HEIGHT, MO-220, QFN-32
MAXIM
MAX3874AETJ+
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WHHD-2, TQFN-32
MAXIM
MAX3874AETJ+D
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WHHD-2, TQFN-32
MAXIM
MAX3874AETJ+TD
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WHHD-2, TQFN-32
MAXIM
MAX3874EGJ-T
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.90 MM HEIGHT, MO-220, QFN-32
MAXIM
MAX3875A
Single/Dual/Quad.Ultra-High-Speed.+3V/+5V.Beyond-the-Rails Comparators[MAX961/MAX962/MAX963/MAX964/MAX997/MAX999/MAX961/MAX962/MAX963/MAX964/MAX997/MAX999/MAX961/MAX962/MAX963/MAX964/MAX997/MAX999/MAX961ESA/MAX961ESA-T/MAX961EUA/MAX961EUA-T/MAX962ESA/MAX962ESA-T/MAX962EUA/MAX962EUA-T/MAX963ESD/MAX963ESD-T/MAX964EEE/MAX964EEE-T/MAX964ESD/MAX964ESD-T/MAX964ESE/MAX964ESE-T/MAX997ESA/MAX997ESA-T/MAX997EUA/MAX997EUA-T/MAX999EUK-T ]
MAXIM
©2020 ICPDF网 联系我们和版权申明