MAX17017 [MAXIM]
Quad-Output Controller for Low-Power Architecture; 四输出控制器的低功耗架构
| 型号： | MAX17017 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad-Output Controller for Low-Power Architecture |
| 文件： | 总31页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4121; Rev 2; 6/09
Quad-Output Controller for
Low-Power Architecture
MAX017
General Description
Features
o Fixed-Frequency, Current-Mode Controllers
The MAX17017 is a quad-output controller for ultra-
mobile portable computers (UMPCs) that rely on a low-
power architecture. The MAX17017 provides a compact,
low-cost controller capable of providing four indepen-
o 5.5V to 28V Input Range (Step-Down) or 3V to 5V
Input Range (Step-Up)
o 1x Step-Up or Step-Down Controller
dent regulators—a main stage, a 3A
internal step-
P-P
o 1x Internal 5A
o 1x Internal 3A
Step-Down Regulator
Step-Down Regulator
P-P
P-P
down, a 5A
internal step-down, and a 2A source/sink
P-P
linear regulator.
o 1x 2A Source/Sink Linear Regulator with Dynamic
The main regulator can be configured as either a step-
down converter (for 2 to 4 Li+ cell applications) or as a
step-up converter (for 1 Li+ cell applications). The inter-
nal switching regulators include 5V synchronous
MOSFETs that can be powered directly from a single Li+
cell or from the main 3.3V/5V power stages. Finally, the
linear regulator is capable of sourcing and sinking 2A to
support DDR termination requirements or to generate a
fixed output voltage.
REFIN
o Internal BST Diodes
o Internal 5V, 50mA Linear Regulator
o Fault Protection—Undervoltage, Overvoltage,
Thermal, Peak Current Limit
o Independent Enable Inputs and Power-Good
Outputs
o Voltage-Controlled Soft-Start
o High-Impedance Shutdown
o 10µA (typ) Shutdown Current
The step-down converters use a peak current-mode,
fixed-frequency control scheme—an easy to implement
architecture that does not sacrifice fast-transient
response. This architecture also supports peak current-
limit protection and pulse-skipping operation to maintain
high efficiency under light-load conditions.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Separate enable inputs and independent open-drain
power-good outputs allow flexible power sequencing. A
soft-start function gradually ramps up the output volt-
age to reduce the inrush current. Disabled regulators
enter high-impedance states to avoid negative output
voltage created by rapidly discharging the output
through the low-side MOSFET. The MAX17017 also
includes output undervoltage, output overvoltage, and
thermal-fault protection.
MAX17017GTM+
-40°C to +105°C
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
The MAX17017 is available in a 48-pin, 6mm x 6mm
thin QFN package.
37
ONB
24 CSPA
23 CSNA
22 AGND
21 REF
SYNC 38
ONA 39
INBC 40
INBC 41
INBC 42
INBC 43
Applications
1-to-4 Li+ Cell Battery-Powered Devices
20 FREQ
19 UP/DN
18 INA
Low-Power Architecture
MAX17017
Ultra-Mobile PC (UMPC)
Portable Gaming
V
44
17 V
CC
DD
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
POKD 45
OND 46
ONC 47
FBC 48
16 BYP
15 LDO5
14 INLDO
13 SHDN
EXPOSED PAD = GND
+
1
2
3
4
5
6
7
8
9
10 11 12
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Quad-Output Controller for
Low-Power Architecture
ABSOLUTE MAXIMUM RATINGS
INLDO, SHDN to GND............................................-0.3V to +28V
VTTR to GND.............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 6V)
BYP
LXB, LXC to GND ....................................-1.0V to (V
LDO5, INA, V , V to GND..................................-0.3V to +6V
INBC
DD CC
BSTB to GND ....................................(V
BSTC to GND....................................(V
BSTA to GND ....................................(V
- 0.3V) to (V
- 0.3V) to (V
- 0.3V) to (V
DHA to LXA.............................................-0.3V to (V
ONA, ONB, ONC, OND to GND...............................-0.3V to +6V
POKA, POKB, POKC, POKD to GND.........-0.3V to (V
REF, REFIND, FREQ, UP/DN,
SYNC to GND ........................................-0.3V to (V
FBA, FBB, FBC, FBD to GND.....................-0.3V to (V
BYP to GND ............................................-0.3V to (V
CSPA, CSNA to GND .................................-0.3V to (V
DLA to GND................................................-0.3V to (V
INBC, IND to GND....................................................-0.3V to +6V
OUTD to GND............................................-0.3V to (V + 0.3V)
+ 0.3V)
DD
DD
DD
LXB
BSTA
+ 6V)
+ 6V)
LXC
LXA
+ 0.3V)
CC
REF Short-Circuit Current......................................................1mA
Continuous Power Dissipation (T = +70°C)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
A
CC
CC
LDO5
CC
DD
2
Multilayer PCB: 48-Pin 6mm x 6mm TQFN
(T4866-2 derated 37mW/°C above +70°C) ....................2.9W
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
MAX017
IND
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD CC A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
UP/DN = GND (step-up), INA
3.0
5.0
Input Voltage Range
V
UP/DN = LDO5 (step-down), INLDO,
INA = LDO5
5.5
2.5
24
UP/DN = GND (step-up), INA = INLDO,
rising edge hysteresis = 100mV
2.7
4.2
2.9
INA Undervoltage Threshold
INBC Input Voltage Range
V
V
INA(UVLO)
UP/DN = LDO5 (step-down), INA = V
rising edge, hysteresis = 160mV
,
CC
4.0
2.3
2.9
4.4
5.5
V
V
Minimum Step-Up Startup
Voltage
UP/DN = GND (step-up)
3.0
SUPPLY CURRENTS
V
Shutdown Supply Current
I
V
V
= 5.5V to 26V, SHDN = GND
10
50
15
80
μA
μA
INLDO
IN(SHDN)
IN
= 5.5V to 26V, ON_ = GND,
INLDO
V
Suspend Supply Current
I
INLDO
IN(SUS)
SHDN = INLDO
SHDN = ONA = ONB = ONC = OND =
GND, T = +25°C
A
V
V
Shutdown Supply Current
Shutdown Supply Current
0.1
0.1
7
1
1
μA
μA
μA
CC
DD
SHDN = ONA = ONB = ONC = OND =
GND, T = +25°C
A
SHDN = ONA = ONB = ONC = OND =
INA Shutdown Current
I
10
INA
GND, UP/DN = V
CC
ONA = V , ONB = ONC = OND = GND;
CC
does not include switching losses,
V
Supply Current
CC
210
300
μA
Main Step-Down Only
measured from V
CC
2
_______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
CC
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD
A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
ONA = ONB = V , ONC = OND = GND;
CC
does not include switching losses,
V
Supply Current
CC
280
350
350
3
μA
Main Step-Down and Regulator B
measured from V
CC
ONA = ONC = V , ONB = OND = GND;
CC
does not include switching losses,
V
Supply Current
CC
280
2.2
μA
Main Step-Down and Regulator C
measured from V
CC
ONA = OND = V , ONB = ONC = GND;
CC
does not include switching losses;
V
Supply Current
CC
mA
Main Step-Down and Regulator D
measured from V
CC
INA Supply Current (Step-Down)
I
I
ONA = V , UP/DN = V (step-down)
40
60
μA
μA
INA
CC
CC
INA + V Step-Up Supply Current
CC
ONA = V , UP/DN = GND (step-up)
320
410
INA
CC
5V LINEAR REGULATOR (LDO5)
V
= 5.5V to 26V, I
= 0 to 50mA,
INLDO
LDO5
LDO5 Output Voltage
V
4.8
70
5.0
5.2
V
LDO5
BYP = GND
LDO5 Short-Circuit Current Limit
BYP Switchover Threshold
LDO5-to-BYP Switch Resistance
1.25V REFERENCE
LDO5 = BYP = GND
Rising edge
160
4.65
1.5
250
mA
V
V
BYP
R
LDO5 to BYP, V
= 5V, I = 50mA
LDO5
4
_
BYP
BYP
Reference Output Voltage
Reference Load Regulation
Reference Undervoltage Lockout
OSCILLATOR
V
No load
1.237
1.25
3
1.263
10
V
mV
V
REF
_V
REF
REF(UVLO)
I
= -1μA to +50μA
REF
V
1.0
FREQ = V
500
750
1.0
CC
kHz
Oscillator Frequency
Switching Frequency
f
FREQ = REF
FREQ = GND
OSC
0.9
90
1.1
MHz
f
f
Main step-up/step-down (regulator A)
Regulator B
1/2 f
SWA
SWB
SWC
OSC
MHz
f
OSC
f
Regulator C
1/2 f
OSC
Maximum Duty Cycle
(All Switching Regulators)
D
93.5
%
MAX
FREQ = V
or GND
90
75
CC
Minimum On-Time
(All Switching Regulators)
t
ns
ON(MIN)
FREQ = REF
REGULATOR A (Main Step-Up/Step-Down)
V
V
+
+
CC
0.3
Step-up configuration (UP/DN = GND)
3.0
1.0
Output-Voltage Adjust Range
V
CC
0.3
Step-down configuration (UP/DN = V
)
CC
_______________________________________________________________________________________
3
Quad-Output Controller for
Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD CC A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
Step-up configuration (UP/DN = GND),
V
- V
= 0 to 20mV, 90% duty
0.975
0.99
1.013
CSPA
CSNA
cycle
FBA Regulation Voltage
V
V
V
FBA
FBA
MAX017
Step-down configuration (UP/DN = V ),
CC
0.968
0.959
0.97
1.003
1.013
V
- V
= 0mV, 90% duty cycle
CSPA
CSNA
Step-up configuration (UP/DN = GND),
- V = 0mV, 90% duty cycle
V
CSPA
CSNA
FBA Regulation Voltage
(Overload)
V
Step-down configuration (UP/DN = V ),
CC
V
- V
= 0 to 20mV, 90% duty
0.930
1.003
CSPA
CSNA
cycle
Step-up configuration (UP/DN = GND),
- V = 0 to 20mV
-20
-40
10
16
-5
V
CSPA
CSNA
FBA Load Regulation
ΔV
mV
mV
FBA
Step-down configuration (UP/DN = V ),
CC
V
- V
= 0 to 20mV
CSPA
CSNA
Step-up (UP/DN =
GND)
UP/DN = GND
or V
5
10
16
22
,
CC
FBA Line Regulation
FBA Input Current
0 to 100% duty
cycle
Step-down (UP/DN
= V
)
CC
UP/DN = GND or V
,
CC
I
-100
0
+100
nA
V
FBA
T
A
= +25°C
Current-Sense Input Common-
Mode Range
V
+
CC
0.3V
V
CSA
Current-Sense Input Bias Current
Current-Limit Threshold (Positive)
Idle Mode™ Threshold
I
T
= +25°C
40
20
4
60
μA
mV
mV
mV
Ω
CSA
A
V
18
22
ILIMA
IDLEA
V
Zero-Crossing Threshold
V
1
IZX
DHA Gate Driver On-Resistance
R
DHA forced high and low
DLA forced high
2.5
2.5
1.5
5
5
3
DH
DLA Gate Driver On-Resistance
R
Ω
DL
DLA forced low
DHA Gate Driver Source/Sink
Current
I
DHA forced to 2.5V
0.7
A
DH
I
I
DLA forced to 2.5V
DLA forced to 2.5V
0.7
1.5
5
DL(SRC)
DLA Gate Driver Source/Sink
Current
A
DL(SNK)
BSTA Switch On-Resistance
R
Ω
BSTA
Idle Mode is a trademark of Maxim Integrated Products, Inc.
4
_______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD CC A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
REGULATOR B (Internal 3A Step-Down Converter)
FBB Regulation Voltage
FBB Regulation Voltage (Overload)
FBB Load Regulation
FBB Line Regulation
I
I
= 0% duty cycle (Note 2)
= 0 to 2.5A, 0% duty cycle (Note 2)
= 0 to 2.5A
0.747
0.720
0.755
0.762
0.762
V
V
LXB
V
FBB
LXB
ΔV
/ΔI
I
-5
8
mV/A
mV
nA
FBB LXB LXB
0 to 100% duty cycle
= +25°C
7
10
+100
150
80
FBB Input Current
I
T
-100
-5
FBB
A
High-side n-channel
Low-side n-channel
75
Internal MOSFET On-Resistance
mΩ
40
LXB Peak Current Limit
I
3.0
-20
3.45
0.8
100
4.0
A
A
PKB
LXB Idle-Mode Trip Level
LXB Zero-Crossing Trip Level
I
IDLEB
I
mA
ZXB
ONB = GND, V
= GND or 5V;
LXB
LXB Leakage Current
I
+20
μA
LXB
V
= 5V at T = +25°C
A
INBC
REGULATOR C (Internal 5A Step-Down Converter)
FBC Regulation Voltage
FBC Regulation Voltage (Overload)
FBC Load Regulation
FBC Line Regulation
I
I
= 0A, 0% duty cycle (Note 2)
= 0 to 4A, 0% duty cycle (Note 2)
= 0 to 4A
0.747
0.710
0.755
0.762
0.762
V
V
LXC
LXC
V
FBC
ΔV
/ΔI
I
-7
14
mV/A
mV
nA
FBC LXC LXC
0 to 100% duty cycle
= +25°C
12
16
+100
100
40
FBC Input Current
I
T
-100
-5
FBC
A
High-side n-channel
Low-side n-channel
50
Internal MOSFET On-Resistance
mΩ
25
LXC Peak Current Limit
I
5.0
5.75
1.2
100
6.5
A
A
PKC
LXC Idle-Mode Trip Level
LXC Zero-Crossing Trip Level
I
IDLEC
I
mA
ZXC
ONC = GND, V
= GND or 5V;
LXC
LXC Leakage Current
I
-20
1
+20
μA
LXC
V
= 5V at T = +25°C
A
INBC
REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)
IND Input Voltage Range
IND Supply Current
V
2.8
50
V
μA
μA
V
IND
OND = V
10
CC
IND Shutdown Current
REFIND Input Range
OND = GND, T = +25°C
10
A
0.5
-100
0.5
1.5
+100
1.5
REFIND Input Bias Current
OUTD Output Voltage Range
V
V
= 0 to 1.5V, T = +25°C
nA
V
REFIND
A
V
OUTD
with respect to V
, OUTD =
REFIND
FBD
-10
0
FBD, I
= +50μA (source load)
OUTD
FBD Output Accuracy
FBD Load Regulation
V
mV
FBD
V
with respect to V
,
REFIND
= -50μA (sink load)
FBD
0
+10
OUTD = FBD, I
OUTD
I
=
1A
-17
-13
mV/A
OUTD
_______________________________________________________________________________________
5
Quad-Output Controller for
Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD CC A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
FBD Line Regulation
SYMBOL
CONDITIONS
= 1.0V to 2.8V, I
UNITS
MIN
TYP
1
MAX
V
V
=
OUTD
200mA
mV
μA
IND
FBD Input Current
= 0 to 1.5V, T = +25°C
0.1
0.5
+4
-4
FBD
A
Source load
Sink load
+2
-2
MAX017
OUTD Linear Regulator Current
Limit
A
Current-Limit Soft-Start Time
With respect to internal OND signal
High-side on-resistance
160
120
180
μs
250
450
+10
+20
Internal MOSFET On-Resistance
mΩ
Low-side on-resistance
I
=
=
0.5mA
3mA
-10
-20
VTTR
VTTR
VTTR Output Accuracy
REFIND to VTTR
mV
mA
I
VTTR Maximum Current Rating
5
FAULT PROTECTION
Upper threshold
rising edge, hysteresis = 50mV
9
12
-12
12
-12
5
14
-9
SMPS POK and Fault Thresholds
%
%
Lower threshold
falling edge, hysteresis = 50mV
-14
6
Upper threshold
rising edge, hysteresis = 50mV
16
-6
VTT LDO POKD and Fault
Threshold
Lower threshold
falling edge, hysteresis = 50mV
-16
FB_ forced 50mV beyond POK_ trip
threshold
POK Propagation Delay
t
μs
μs
μs
POK
FB_ forced 50mV above POK_ upper trip
threshold
Overvoltage Fault Latch Delay
t
t
t
5
OVP
UVP
UVP
SMPS Undervoltage Fault
Latch Delay
FBA, FBB, or FBC forced 50mV below
POK_ lower trip threshold
5
VTT LDO Undervoltage Fault
Latch Delay
FBD forced 50mV below POKD lower trip
threshold
5000
μs
V
POK Output Low Voltage
V
I
I
= 3mA
0.4
1
POK
SINK
V
V
= 1.05V, V
= V
= 0.8V, V
=
FBD
FBA
FBB
FBC
POK Leakage Currents
μA
°C
+ 50mV (POK high impedance);
POK
REFIND
POK_ forced to 5V, T = +25°C
A
Thermal-Shutdown Threshold
GENERAL LOGIC LEVELS
SHDN Input Logic Threshold
SHDN Input Bias Current
ON_ Input Logic Threshold
ON_ Input Bias Current
T
Hysteresis = 15°C
160
SHDN
Hysteresis = 20mV
0.5
-1
1.6
+1
1.6
+1
1.6
+1
V
μA
V
T
= +25°C
A
Hysteresis = 170mV
0.5
-1
T
T
= +25°C
= +25°C
μA
V
A
A
UP/DN Input Logic Threshold
UP/DN Input Bias Current
0.5
-1
μA
6
_______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
= I
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
= V
= V
= V
= 5V, I
= I
= no load, FREQ = GND, UP/DN = V , T = 0°C to +85°C, unless other-
ONA
ONB
ONC
OND
REF
LDO5
OUTD CC A
wise noted. Typical values are at T = +25°C.) (Note 1)
A
T
= 0°C to +85°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
High (V
)
CC
V
- 0.4V
CC
FREQ Input Voltage Levels
V
Unconnected/REF
Low (GND)
1.65
3.8
0.5
+2
3.5
+1
FREQ Input Bias Current
SYNC Input Logic Threshold
SYNC Input Bias Current
T
= +25°C
-2
1.5
-1
μA
V
A
T
= +25°C
μA
A
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
ONA
= V
= V
= V
= 5V, I
= I
= I = no load, FREQ = GND, UP/DN = V , T = -40°C to +105°C.) (Note 1)
OUTD CC A
ONB
ONC
OND
REF
LDO5
T
= -40°C to +105°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
UP/DN = GND (step-up), INA
3.0
5.0
Input Voltage Range
V
V
UP/DN = LDO5 (step-down), INLDO,
INA = LDO5
5.5
2.4
3.9
24
UP/DN = GND (step-up), INA = INLDO,
rising edge, hysteresis = 100mV
3.0
V
INA(UVLO
)
INA Undervoltage Threshold
UP/DN = LDO5 (step-down), INA = V
rising edge, hysteresis = 160mV
,
CC
4.5
5.5
INBC Input Voltage Range
Minimum Step-Up Startup Voltage
SUPPLY CURRENTS
2.3
3.0
V
V
UP/DN = GND (step-up)
V
Shutdown Supply Current
I
V
V
= 5.5V to 26V, SHDN = GND
15
80
μA
μA
INLDO
IN(SHDN)
IN
= 5.5V to 26V, ON_ = GND,
INLDO
V
Suspend Supply Current
I
INLDO
IN(SUS)
SHDN = INLDO
SHDN = ONA = ONB = ONC = OND =
GND, UP/DN = V
INA Shutdown Current
Supply Current
I
10
μA
μA
INA
CC
ONA = V , ONB = ONC = OND = GND;
CC
does not include switching losses,
measured from V
V
CC
350
Main Step-Down Only
CC
ONA = ONB = V , ONC = OND = GND;
CC
does not include switching losses,
V
Supply Current
CC
400
400
μA
μA
Main Step-Down and Regulator B
measured from V
CC
ONA = ONC = V , ONB = OND = GND,
CC
does not include switching losses,
V
Supply Current
CC
Main Step-Down and Regulator C
measured from V
CC
_______________________________________________________________________________________
7
Quad-Output Controller for
Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
ONA
= V
= V
= V
= 5V, I
= I
= I = no load, FREQ = GND, UP/DN = V , T = -40°C to +105°C.) (Note 1)
OUTD CC A
ONB
ONC
OND
REF
LDO5
T
= -40°C to +105°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
mA
MIN
TYP
MAX
ONA = OND = V , ONB = ONC = GND,
CC
does not include switching losses,
V
Supply Current
Main Step-Down and Regulator D
CC
3.5
measured from V
CC
INA Supply Current (Step-Down)
I
I
ONA = V , UP/DN = V (step-down)
75
INA
CC
CC
MAX017
μA
INA + V Step-Up Supply Current
CC
ONA = V , UP/DN = GND (step-up)
475
INA
CC
5V LINEAR REGULATOR (LDO5)
V
= 5.5V to 26V, I
= 0 to 50mA,
INLDO
LDO5
LDO5 Output Voltage
V
4.75
55
5.25
V
LDO5
BYP = GND
LDO5 Short-Circuit Current Limit
1.25V REFERENCE
LDO5 = BYP = GND
mA
Reference Output Voltage
Reference Load Regulation
OSCILLATOR
V
No load
1.237
1.263
12
V
REF
ΔV
I
= -1μA to +50μA
mV
REF
REF
Oscillator Frequency
f
FREQ = GND
0.9
89
1.1
MHz
%
OSC
Maximum Duty Cycle
(All Switching Regulators)
D
MAX
REGULATOR A (Main Step-Up/Step-Down)
V
0.3V
+
CC
Step-up configuration (UP/DN = GND)
3.0
Output-Voltage Adjust Range
V
V
V
0.3V
+
CC
Step-down configuration (UP/DN = V
)
1.0
CC
Step-up configuration,
0.970
0.963
0.954
0.925
1.018
1.008
1.018
1.008
V
- V
= 0mV, 90% duty cycle
CSPA
CSNA
FBA Regulation Voltage
FBA Regulation Voltage
Step-down configuration,
- V = 0mV, 90% duty cycle
V
CSPA
CSNA
Step-up configuration (UP/DN = GND),
- V = 0 to 20mV, 90% duty cycle
V
CSPA
CSNA
V
V
FBA
(Overload)
Step-down configuration (UP/DN = V ),
CC
V
- V
CSNA
= 0 to 20mV, 90% duty cycle
CSPA
Step-up (UP/DN = GND)
Step-down (UP/DN = V
5
19
23
FBA Line Regulation
mV
)
CC
10
Current-Sense Input Common-
Mode Range
V
0.3V
+
CC
V
0
V
CSA
Current-Limit Threshold (Positive)
V
17
23
mV
ILIMA
8
_______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
ONA
= V
= V
= V
= 5V, I
= I
= I = no load, FREQ = GND, UP/DN = V , T = -40°C to +105°C.) (Note 1)
OUTD CC A
ONB
ONC
OND
REF
LDO5
T
= -40°C to +105°C
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
REGULATOR B (Internal 3A Step-Down Converter)
FBB Regulation Voltage
I
I
= 0A, 0% duty cycle (Note 2)
0.742
0.715
6
0.766
0.766
12
V
V
LXB
FBB Regulation Voltage (Overload)
FBB Line Regulation
V
= 0 to 2.5A , 0% duty cycle (Note 2)
FBB
LXB
mV
A
LXB Peak Current Limit
I
2.7
4.2
PKB
REGULATOR C (Internal 5A Step-Down Converter)
FBC Regulation Voltage
I
I
= 0A, 0% duty cycle (Note 2)
0.742
0.705
11
0.766
0.766
20
V
V
LXC
LXC
FBC Regulation Voltage (Overload)
FBC Line Regulation
V
= 0 to 4A, 0% duty cycle (Note 2)
FBC
mV
A
LXC Peak Current Limit
I
5.0
6.5
PKC
REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)
IND Input Voltage Range
IND Supply Current
V
1
2.8
70
V
μA
V
IND
OND = V
CC
REFIND Input Range
0.5
0.5
1.5
1.5
OUTD Output Voltage Range
V
V
OUTD
V
with respect to V
,
FBD
REFIND
-12
0
0
OUTD = FBD, I
= +50μA (source load)
OUTD
FBD Output Accuracy
V
mV
FBD
V
with respect to V
,
REFIND
FBD
+12
OUTD = FBD, I
= -50μA (sink load)
OUTD
FBD Load Regulation
I
=
1A
-20
+2
-2
mV/A
A
OUTD
Source load
Sink load
+4
-4
OUTD Linear Regulator Current
Limit
High-side on-resistance
Low-side on-resistance
300
475
+20
Internal MOSFET On-Resistance
VTTR Output Accuracy
mΩ
REFIND to VTTR
I
=
3mA
-20
mV
VTTR
_______________________________________________________________________________________
9
Quad-Output Controller for
Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), V
= 12V, V
= V
= V
= V
= V
= V
= V
= 5V, V
= 1.8V, V
=
SHDN
INLDO
INA
INBC
DD
CC
BYP
CSPA
CSNA
IND
V
ONA
= V
= V
= V
= 5V, I
= I
= I = no load, FREQ = GND, UP/DN = V , T = -40°C to +105°C.) (Note 1)
OUTD CC A
ONB
ONC
OND
REF
LDO5
T
= -40°C to +105°C
A
PARAMETER
FAULT PROTECTION
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
Upper threshold rising edge,
hysteresis = 50mV
8
16
-8
SMPS POK and Fault Thresholds
%
MAX017
Lower threshold falling edge,
hysteresis = 50mV
-16
6
Upper threshold rising edge,
hysteresis = 50mV
16
VTT LDO POKD and Fault
Threshold
%
V
Lower threshold falling edge,
hysteresis = 50mV
-16
-6
POK Output Low Voltage
V
I
= 3mA
SINK
0.4
POK
GENERAL LOGIC LEVELS
SHDN Input Logic Threshold
ON_ Input Logic Threshold
UP/DN Input Logic Threshold
Hysteresis = 20mV
Hysteresis = 170mV
0.5
0.5
0.5
1.6
1.6
1.6
V
V
V
High (V )
CC
V
CC
- 0.4V
FREQ Input Voltage Levels
SYNC Input Logic Threshold
V
V
Unconnected/REF
Low (GND)
1.65
3.8
0.5
3.5
1.5
Note 1: Limits are 100% production tested at T = +25°C. Maximum and minimum limits are guaranteed by design and
A
characterization.
Note 2: Regulation voltage tested with slope compensation. The typical value is equivalent to 0% duty cycle. In real application, the
regulation voltage is higher due to the line regulation times the duty cycle.
10 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
Typical Operating Characteristics
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
SMPS REGULATOR B EFFICIENCY
vs. LOAD CURRENT
SMPS REGULATOR A EFFICIENCY
vs. LOAD CURRENT
SMPS REGULATOR A OUTPUT VOLTAGE
vs. LOAD CURRENT
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5.05
5.00
4.95
4.90
4.85
4.80
4.75
V
= 8V
IN
V
= 20V
V = 2.5V
IN
IN
V
= 12V
V = 3.3V
IN
IN
V
= 20V
IN
V
= 12V
IN
V
= 5V
IN
V
= 8V
IN
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
SMPS REGULATOR B OUTPUT VOLTAGE
vs. LOAD CURRENT
SMPS REGULATOR C EFFICIENCY
vs. LOAD CURRENT
1.82
1.77
1.72
90
85
80
75
70
65
60
55
50
V
= 2.5V
IN
V
= 5V
IN
V
= 3.3V
IN
V
= 2.5V
IN
V
= 5V
IN
V
= 3.3V
IN
0
0.5
1.0
1.5
2.0
2.5
3.0
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
LOAD CURRENT (A)
REGULATOR D VOLTAGE
vs. SOURCE/SINK LOAD CURRENT
SMPS REGULATOR C OUTPUT VOLTAGE
vs. LOAD CURRENT
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.930
0.925
0.920
0.915
0.910
0.905
0.900
0.895
0.890
0.885
0.880
V
= 5V
IN
V
= 2.5V
IN
V
= 3.3V
IN
-2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
LOAD CURRENT (A)
______________________________________________________________________________________ 11
Quad-Output Controller for
Low-Power Architecture
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
REG B STARTUP WAVEFORM
(HEAVY LOAD)
REG A STARTUP WAVEFORM
REG A SHUTDOWN WAVEFORM
(HEAVY LOAD)
MAX17017 toc09
MAX17017 toc10
MAX17017 toc08
ONA
OUTA
POKA
ONB
OUTB
POKB
ONA
MAX017
OUTA
POKA
I
LA
I
I
LA
LB
LXA
LXB
LXA
400μs/div
400μs/div
400μs/div
ONA: 5V/div
OUTA: 5V/div
POKA: 5V/div
R
= 2.5Ω
LOAD
ONB: 5V/div
OUTB: 2V/div
POKB: 5V/div
R
= 1.01Ω
LOAD
ONA: 5V/div
OUTA: 5V/div
POKA: 5V/div
R
= 1.6Ω
LOAD
I
: 5A/div
I
: 2A/div
I
: 5A/div
LA
LB
LA
LXA: 10V/div
LXB: 5V/div
LXA: 10V/div
REG C STARTUP WAVEFORM
(HEAVY LOAD)
REG B SHUTDOWN WAVEFORM
REG C SHUTDOWN
MAX17017 toc12
MAX17017 toc11
MAX17017 toc13
ONC
ONB
ONC
OUTC
POKC
OUTB
POKB
OUTC
POKC
I
LB
I
LC
I
LC
LXB
LXC
LXC
400μs/div
400μs/div
100μs/div
ONC: 5V/div
OUTC: 1V/div
POKC: 5V/div
R
= 0.25Ω
LOAD
ONB: 5V/div
OUTB: 2V/div
POKB: 5V/div
R
= 0.8Ω
LOAD
ONC: 5V/div
OUTC: 1V/div
POKC: 5V/div
R
= 0.25Ω
LOAD
I
: 5A/div
I
: 2A/div
LC
I : 5A/div
LB
LC
LXC: 5V/div
LXB: 5V/div
LXC: 5V/div
12 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
REG A LOAD TRANSIENT (1A TO 3.2A)
REG B LOAD TRANSIENT (0.4A TO 2A)
REG C LOAD TRANSIENT (0.8A TO 3A)
MAX17017 toc14
MAX17017 toc15
MAX17017 toc16
OUTB
LXB
OUTC
LXC
OUTA
LXA
I
LA
I
LC
I
LB
I
I
OUTC
OUTA
I
OUTB
20μs/div
20μs/div
20μs/div
OUTA: 100mV/div
LXA: 10V/div
V
= 12V, LOAD TRANSIENT
IS FROM 1A TO 3.2A
OUTB: 50mV/div
LXB: 5V/div
V
= 5V, 0.4A TO 2.0A
LOAD TRANSIENT
INA
INBC
OUTC: 50mV/div
LXC: 5V/div
V
= 5V, 0.8A TO 3.0A
LOAD TRANSIENT
INBC
I
I
: 2A/div
: 2A/div
I
I
: 1A/div
: 2A/div
LA
OUTA
LB
OUTB
I
I
: 2A/div
: 2A/div
LC
OUTC
REG D LOAD TRANSIENT (SOURCE/SINK)
REG D LOAD TRANSIENT (SINK)
REG D LOAD TRANSIENT (SOURCE)
MAX17017 toc17
MAX17017 toc18
MAX17017 toc19
OUTD
OUTD
OUTD
I
I
OUTD
OUTD
I
OUTD
20μs/div
20μs/div
OUTD: 10mV/div IND = 1.8V, REFIND = 0.9V,
: 1A/div = 2 x 10μF, LOAD TRANSIENT
20μs/div
OUTD: 10mV/div IND = 1.8V, REFIND = 0.9V,
: 1A/div = 2 x 10μF, LOAD TRANSIENT
OUTD: 20mV/div IND = 1.8V, REFIND = 0.9V,
I
: 1A/div
C
= 2 x 10μF, LOAD TRANSIENT
OUTD
OUT
I
C
OUT
I
C
OUT
OUTD
OUTD
IS FROM 1A SOURCING TO 1A SINKING
IS FROM 0 TO 1A SINKING
IS FROM 0 TO 1A SOURCING
______________________________________________________________________________________ 13
Quad-Output Controller for
Low-Power Architecture
Pin Description
PIN
NAME
FUNCTION
Open-Drain Power-Good Output for the Internal 5A Step-Down Converter. POKC is low if FBC is more than
12% (typ) above or below the nominal 0.75V feedback regulation threshold. POKC is held low during
startup and in shutdown. POKC becomes high impedance when FBC is in regulation.
1
POKC
Boost Flying Capacitor Connection for the Internal 5A Step-Down Converter. The MAX17017 includes an
internal boost switch/diode connected between V
in Figure 1.
and BSTC. Connect to an external capacitor as shown
2
BSTC
LXC
DD
MAX017
Inductor Connection for the Internal 5A Step-Down Converter. Connect LXC to the switched side of the
inductor.
3–6
7, 8
Source/Sink Linear Regulator Output. Bypass OUTD with 2x 10μF or greater ceramic capacitors to ground.
Dropout needs additional output capacitance (see the VTT LDO Output Capacitor Selection (C
OUTD
)
OUTD
section).
9
IND
FBD
Source/Sink Linear Regulator Input. Bypass IND with a 10μF or greater ceramic capacitor to ground.
Feedback Input for the Internal Source/Sink Linear Regulator. FBD tracks and regulates to the REFIND
voltage.
10
11
12
VTTR
REFIND
Ouput of Reference Buffer. Bypass with 0.22μF for 3mA of output current.
Dynamic Reference Input Voltage for the Source/Sink Linear Regulator and the Reference Buffer. The linear
regulator feedback threshold (FBD) tracks the REFIND voltage.
Shutdown Control Input. The device enters its 5μA supply current shutdown mode if V
is less than the
SHDN
SHDN input falling edge trip level and does not restart until V
is greater than the SHDN input rising
13
14
SHDN
SHDN
edge trip level. Connect SHDN to V
for automatic startup of LDO5.
INLDO
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to GND with a 0.1μF or
greater ceramic capacitor close to the controller.
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Connect BYP and INLDO to the system’s 5V supply to effectively disable the linear regulator.
INLDO
5V Internal Linear Regulator Output. Bypass with a 4.7μF or greater ceramic capacitor. The 5V linear
regulator provides the bias power for the gate drivers (V ) and analog control circuitry (V ). The linear
DD
CC
regulator sources up to 50mA (max guaranteed). When BYP exceeds 4.65V (typ), the MAX17017 bypasses
the linear regulator through a 1.5_ bypass switch. When the linear regulator is bypassed, LDO5 supports
loads up to 100mA.
15
LDO5
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Bypass SHDN to ground and leave LDO5 unconnected. Connect BYP and INLDO to effectively disable the
linear regulator.
Linear Regulator Bypass Input. When BYP exceeds 4.65V, the controller shorts LDO5 to BYP through a 1.5_
bypass switch and disables the linear regulator. When BYP is low, the linear regulator remains active.
The BYP input also serves as the VTTR buffer supply, allowing VTTR to remain active even when the
source/sink linear regulator (OUTD) has been disabled under system standby/suspend conditions.
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Bypass LDO5 to ground with a 1μF capacitor and leave this output unconnected. Connect BYP and INLDO
to the system’s 5V supply to effectively disable the linear regulator.
16
BYP
14 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
Pin Description (continued)
PIN
NAME
FUNCTION
5V Analog Bias Supply. V
powers all the analog control blocks (error amplifiers, current-sense amplifiers,
CC
17
V
fault comparators, etc.) and control logic. Connect V
to the 5V system supply with a series 10_ resistor,
CC
CC
and bypass to analog ground using a 1μF or greater ceramic capacitor.
Input to the Circuit in Reg A in Boost Mode. Connect INA to the input in step-up mode (UP/DN = GND) and
18
19
INA
connect INA to LDO5 in step-down mode (UP/DN = V ).
CC
Converter Configuration Selection Input for Regulator A. When UP/DN is pulled high (UP/DN = V ),
CC
regulator A operates as a step-down converter (Figure 1). When UP/DN is pulled low (UP/DN = GND),
UP/DN
regulator A operates as a step-up converter.
Trilevel Oscillator Frequency Selection Input.
FREQ = V : RegA = 250kHz, RegB = 500kHz, RegC = 250kHz
CC
FREQ = REF: RegA = 375kHz, RegB = 750kHz, RegC = 375kHz
FREQ = GND: RegA = 500kHz, RegB = 1MHz, RegC = 500kHz
20
21
FREQ
REF
1.25V Reference-Voltage Output. Bypass REF to analog ground with a 0.1μF ceramic capacitor. The
reference sources up to 50μA for external loads. Loading REF degrades output voltage accuracy according
to the REF load-regulation error. The reference shuts down when the system pulls SHDN low in buck mode
(UP/DN = GND) or when the system pulls ONA low in boost mode (UP/DN = V ).
CC
22
23
AGND
CSNA
Analog Ground
Negative Current-Sense Input for the Main Switching Regulator. Connect to the negative terminal of the current-
sense resistor. Due to the CSNA bias current requirements, limit the series impedance to less than 10Ω.
Positive Current-Sense Input for the Main Switching Regulator. Connect to the positive terminal of the current-
sense resistor. Due to the CSPA bias current requirements, limit the series impedance to less than 10Ω.
24
25
CSPA
FBA
Feedback Input for the Main Switching Regulator. FBA regulates to 1.0V.
Open-Drain Power-Good Output for the Main Switching Regulator. POKA is low if FBA is more than 12% (typ)
above or below the nominal 1.0V feedback regulation point. POKA is held low during soft-start and in
shutdown. POKA becomes high impedance when FBA is in regulation.
26
POKA
27
28
DHA
LXA
High-Side Gate-Driver Output for the Main Switching Regulator. DHA swings from LXA to BSTA.
Inductor Connection of Converter A. Connect LXA to the switched side of the inductor.
Boost Flying Capacitor Connection of Converter A. The MAX17017 includes an internal boost switch/diode
29
BSTA
DLA
LXB
connected between V
and BSTA. Connect to an external capacitor as shown in Figure 1.
DD
30
Low-Side Gate-Driver Output for the Main Switching Regulator. DLA swings from GND to V
.
DD
31, 32,
33
Inductor Connection for the Internal 3A Step-Down Converter. Connect LXB to the switched side of the
inductor.
Boost Flying Capacitor Connection for the Internal 3A Step-Down Converter. The MAX17017 includes an
34
35
BSTB
POKB
internal boost switch/diode connected between V
in Figure 1.
and BSTB. Connect to an external capacitor as shown
DD
Open-Drain Power-Good Output for the Internal 3A Step-Down Converter. POKB is low if FBB is more than
12% (typ) above or below the nominal 0.75V feedback-regulation threshold. POKB is held low during soft-
start and in shutdown. POKB becomes high impedance when FBB is in regulation.
______________________________________________________________________________________ 15
Quad-Output Controller for
Low-Power Architecture
Pin Description (continued)
PIN
NAME
FUNCTION
36
FBB
Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V.
Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven
high, the controller enables the 3A internal switching regulator.
37
38
39
ONB
SYNC
ONA
External Synchronization Input. Used to override the internal switching frequency.
Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is
driven high, the controller enables the step-up/step-down converter.
MAX017
Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of
the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10μF or greater
ceramic capacitors to support the RMS current.
40–43
44
INBC
5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1μF or greater ceramic
capacitor. Provides power for the BSTB and BSTC driver supplies.
V
DD
Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more
than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in
shutdown. POKD becomes high impedance when FBD is in regulation.
45
POKD
OND
Source/Sink Linear Regulator (Regulator D) and Reference Buffer Enable Input. When OND is pulled low, OUTD
is high impedance. When OND is driven high, the controller enables the source/sink linear regulator.
46
Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven
high, the controller enables the 5A internal switching regulator.
47
48
ONC
FBC
Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V.
Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching
regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad.
Connect the exposed backside pad to system power ground planes through multiple vias.
EP
PGND
supply required for the SMPS analog controller, refer-
Detailed Description
ence, and logic blocks. LDO5 supplies at least 50mA
The MAX17017 standard application circuit (Figure 1)
for external and internal loads, including the MOSFET
gate drive, which typically varies from 5mA to 15mA
per switching regulator, depending on the switching
frequency. Bypass LDO5 with a 4.7μF or greater
ceramic capacitor to guarantee stability under the full-
load conditions.
provides a 5V/5A
main stage, a 1.8V/3A
VDDQ
P-P
P-P
and 0.9A/2A VTT outputs for DDR, and a 1.05V/5A
chipset supply.
P-P
The MAX17017 supports four power outputs—one high-
voltage step-down controller, two internal MOSFET
step-down switching regulators, and one high-current
source/sink linear regulator. The step-down switching
regulators use a current-mode fixed-frequency architec-
ture compensated by the output capacitance. An inter-
nal 50mA 5V linear regulator provides the bias supply
and driver supplies, allowing the controller to power up
from input supplies greater than 5.5V.
The MAX17017 switch-mode step-down switching reg-
ulators require a 5V bias supply in addition to the main-
power input supply. This 5V bias supply is generated
by the controller’s internal 5V linear regulator (LDO5).
This boot-strappable LDO allows the controller to
power up independently. The gate-driver V
input
DD
supply is typically connected to the fixed 5V linear reg-
ulator output (LDO5). Therefore, the 5V LDO supply
must provide LDO5 (PWM controller) and the gate-
drive power during power-up.
Fixed 5V Linear Regulator (LDO5)
An internal linear regulator produces a preset 5V low-
current output from INLDO. LDO5 powers the gate dri-
vers for the external MOSFETs, and provides the bias
16 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
13
14
SHDN
LDO5
INLDO
6V TO 16V
C7
C8
C9
C10
1μF, 16V
0603
4.7μF, 16V
1206
4.7μF, 16V
1206
22μF, 16V
C-CASE
16TQC22M
C1
4.7μF, 6V
0603
PWR
PWR
PWR
PWR
24
C4
0.1μF, 6V
0402
15
44
19
BSTA
L1
3.3μH, 6A, 30mΩ
6.7mm x 7.7mm x 3.0mm
(NEC/TOKIN:
R15
4mΩ
1%
23
28
DHA
LXA
N
PWR
V
DD
H1
MPLC0730L3R3)
5V,
4A
UP/DN
C14
30
150μF, 35mΩ, 6V
R1
10Ω
C2
1.0μF, 6V
0402
DLA
N
L1
B2 CASE
C16
OPEN
0402
5%, 0402
PWR
17
18
V
29
27
PWR
CC
CSPA
CSNA
AGND
R3
INA
C21
OPEN
0402
40kΩ
AGND
1%, 0402
39
37
47
46
AGND
25
16
ONA
ON OFF
ON OFF
ON OFF
ON OFF
FBA
C21
680pF, 6V
0402
R4
ONB
ONC
10kΩ
BYP
AGND
1%, 0402
AGND
4x INBC
OND
40-43
34
C12
1μF, 16V
0402
C13
10μF, 6V
0805
MAX17017
PWR
PWR
5V SMPS
OUTPUT
C5
L2
0.1μF, 6V
R9
100kΩ
5%,
R10
R11
100kΩ
5%,
R12
100kΩ
5%,
1.0μH, 6.8A, 14.2mΩ
BSTB
0402
100kΩ
5%,
5.8mm x 6.2mm x 3.0mm
(NEC/TOKIN: MPLC0525L1RO)
1.8V,
2.5A
0402
0402
0402
0402
3x LXB
26
35
31, 32, 33
36
C14
330μF
POKA
POKB
R5
R6
10.0kΩ
1%, 0402
14kΩ
18mΩ, 2.5V, B2 CASE
1%, 0402
1
PWR
FBB
POKC
C22
1000pF, 6V
0402
45
38
POKD
SYNC
AGND
AGND
L3
C6
2
1.0μH, H6.8A, 14.2mΩ
AGND
BSTC
0.1μF,
6V
R2
5.8mm x 8.2mm x 3.0mm
0Ω
(NEC/TOKIN: MPLC0525L1R0)
0402
1.05V,
4A
1%, 0402
4x LXC
20
FREQ
3-6
48
C16
R7
330μF
R8
C3
3.01kΩ
18mΩ, 2.5V,
B2 CASE
10.0kΩ
0.1μF, 6V
1%, 0402
AGND
1%, 0402
0402
PWR
FBC
21
C23
2200pF, 6V
0402
REF
AGND
AGND
AGND
AGND
11
VTTR
9
IND
C23
0.1μF,
6V
C17
1μF, 6V
0402
C18
10μF, 6V
0805
0402
R13
15kΩ
PWR
PWR
7, 8
0.9A,
1A
2x OUTD
1%, 0402
C19
C20
12
1.8V SMPS
OUTPUT
10
22
10μF, 6V
0805
10μF, 6V
FBD
REFIND
0805
R14
15.0kΩ
1%, 0402
AGND
PWR
PWR
PGND
PWR
AGND
AGND
Figure 1. Standard Application Circuit
______________________________________________________________________________________ 17
Quad-Output Controller for
Low-Power Architecture
UP/DN
UP/DN = V [BUCK],
CC
LOW BUCK MODE
BYP
V
CC
LDO5
INLDO
V
DD
MAX17017
INA
TSDN
TSDN
MAX017
SHDN
V
CC
BYP_OK
V
BSTA
_OK
CC
CSPA
CSNA
EN
SW
DRV
REF_OK
ONLDO
FB
ONA
EN
DHA
LXA
LDO5
V
REG A
ANALOG
CC
V
OK
CC
UVLO
V
DD
*ONA (SHDN)
DLA
BIAS
EN
V
V
CC
CC
SSDA+
FBA
EN
SYNC
OND
REF
BSTB
INBC
REF
OSC
REFOK
EN
IND
V
CC
V
CC
CSB
EN
REG D
ANALOG
OUTD
REG B
ANALOG
LXB
V
DD
ONB
EN
INBC_OK
FBB
PGND
FBD
REG D PWR
BSTC
INBC
BYP
INBC_OK
INBC
UVLO
-
VTTR
REFIND
+
V
CC
ONA
ON_VTTR
ONB
ONC
OND
CSC
REFIND
POKX
REG C
LXC
ANALOG
V
DD
PGOOD AND
FAULT
PROTECTION
FAULTX
ONX
ONC
INBC_OK
EN
FBC
*BUCK REF ENABLED BY SHDN;
BOOST REF ENABLED BY ONA.
+SSDA ONLY USED IN STEP-UP MODE. SSDA = HIGH IN STEP-DOWN MODE.
Figure 2. MAX17017 Block Diagram
18 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
LDO5 Bootstrap Switchover
SMPS Detailed Description
When the bypass input (BYP) exceeds the LDO5 boot-
strap switchover threshold for more than 500μs, an
internal 1.5Ω (typ) p-channel MOSFET shorts BYP to
LDO5, while simultaneously disabling the LDO5 linear
regulator. This bootstraps the controller, allowing power
for the internal circuitry and external LDO5 loading to
be generated by the output of a 5V switching regulator.
Bootstrapping reduces power dissipation due to driver
and quiescent losses by providing power from a
switch-mode source, rather than from a much-less-effi-
cient linear regulator. The current capability increases
from 50mA to 100mA when the LDO5 output is
switched over to BYP. When BYP drops below the boot-
strap threshold, the controller immediately disables the
bootstrap switch and reenables the 5V LDO.
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums multiple
signals: the output-voltage error signal with respect to
the reference voltage, the current-sense signal, and the
slope compensation ramp (Figure 3). The MAX17017
uses a direct-summing configuration, approaching
ideal cycle-to-cycle control over the output voltage
without a traditional error amplifier and the phase shift
associated with it.
Frequency Selection (FREQ)
The FREQ input selects the PWM mode switching fre-
quency. Table 1 shows the switching frequency based
on the FREQ connection. High-frequency (FREQ =
GND) operation optimizes the application for the small-
est component size, trading off efficiency due to higher
switching losses. This might be acceptable in ultra-
portable devices where the load currents are lower.
Low-frequency (FREQ = 5V) operation offers the best
overall efficiency at the expense of component size and
board space.
Reference (REF)
The 1.25V reference is accurate to 1% over temperature
and load, making REF useful as a precision system refer-
ence. Bypass REF to GND with a 0.1μF or greater ceram-
ic capacitor. The reference sources up to 50μA and sinks
5μA to support external loads. If highly accurate specifi-
cations are required for the main SMPS output voltages,
the reference should not be loaded. Loading the refer-
ence slightly reduces the output voltage accuracy
because of the reference load-regulation error.
V
L
R1
R2
TO PWM
LOGIC
UNCOMPENSATED
HIGH-SPEED
FB_
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
I1
I2
I3
V
BIAS
REF
CSH_
CSL_
SLOPE COMPENSATION
Figure 3. PWM Comparator Functional Diagram
______________________________________________________________________________________ 19
Quad-Output Controller for
Low-Power Architecture
Table 1. FREQ Table
REG A AND REG C
REG B
STARTUP
BLANKING
TIME
STARTUP
BLANKING
TIME
SWITCHING
FREQUENCY
SWITCHING
FREQUENCY
SOFT-START
TIME
SOFT-START TIME
PIN
SELECT
REG A: 1200/f
REG C: 900/f
SWA
SWC
f
AND f
1500/f
f
1800/f
3000/f
SWB
SWA
SWC
SWA
SWB
SWB
REG A: 4.8ms
REG C: 3.6ms
MAX017
LDO5
REF
250kHz
375kHz
500kHz
6ms
500kHz
750kHz
1MHz
3.6ms
6ms
REG A: 3.2ms
REG C: 2.4ms
4ms
2.4ms
4ms
REG A: 2.4ms
REG C: 1.8ms
GND
3ms
—
1.8ms
—
3ms
—
SYNC
0.5 x f
—
f
SYNC
SYNC
comparator senses the inductor current during the off-
time. For regulator A, once V - V drops below
the 1mV zero-crossing current-sense threshold, the com-
parator turns off the low-side MOSFET (DLA pulled low).
For regulators B and C, once the current through the low-
side MOSFET drops below 100mA, the zero-crossing
comparator turns off the low-side MOSFET.
Light-Load Operation Control
The MAX17017 uses a light-load pulse-skipping operat-
ing mode for all switching regulators. The switching
regulators turn off the low-side MOSFETs when the cur-
rent sense detects zero inductor current. This keeps the
inductor from discharging the output capacitors and
forces the switching regulator to skip pulses under
light-load conditions to avoid overcharging the output.
CSPA
CSNA
The minimum idle-mode current requirement causes
the threshold between pulse-skipping PFM operation
and constant PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point). The load-current level at which
Idle-Mode Current-Sense Threshold
When pulse-skipping mode is enabled, the on-time of
the step-down controller terminates when the output
voltage exceeds the feedback threshold and when the
current-sense voltage exceeds the idle-mode current-
sense threshold. Under light-load conditions, the on-
time duration depends solely on the idle-mode
current-sense threshold. This forces the controller to
source a minimum amount of power with each cycle. To
avoid overcharging the output, another on-time cannot
begin until the output voltage drops below the feed-
back threshold. Since the zero-crossing comparator
prevents the switching regulator from sinking current,
the MAX17017 switching regulators must skip pulses.
Therefore, the controller regulates the valley of the out-
put ripple under light-load conditions.
PFM/PWM crossover occurs (I ) is equivalent
LOAD(SKIP)
to half the idle-mode current threshold (see the
Electrical Characteristics table for the idle-mode thresh-
olds of each regulator). The switching waveforms can
appear noisy and asynchronous when light loading
causes pulse-skipping operation, but this is a normal
operating condition that results in high light-load effi-
ciency. Trade-offs in PFM noise vs. light-load efficiency
are made by varying the inductor value. Generally, low
inductor values produce a broader efficiency vs. load
curve, while higher values result in higher full-load effi-
ciency (assuming that the coil resistance remains fixed)
and less output voltage ripple. Penalties for using high-
er inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads. This switchover is affected by
a comparator that truncates the low-side switch on-time
at the inductor current’s zero crossing. The zero-crossing
20 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
becomes high impedance as long as the output remains
within 8% (min) of the nominal regulation voltage set
by FB_. POK_ goes low once its corresponding output
drops 12% (typ) below its nominal regulation point, an
output overvoltage fault occurs, or the output is shut
down. For a logic-level POK_ output voltage, connect an
external pullup resistor between POK_ and LDO5. A
100kΩ pullup resistor works well in most applications.
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V rises above
CC
approximately 1.9V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled low
until the SMPS controllers are activated. The V
input
CC
undervoltage lockout (UVLO) circuitry prevents the
switching regulators from operating if the 5V bias supply
(V
CC
and V ) is below its 4.2V UVLO threshold.
DD
SMPS Fault Protection
Regulator A Startup
Output Overvoltage Protection (OVP)
If the output voltage rises above 112% (typ) of its nomi-
nal regulation voltage, the controller sets the fault latch,
pulls POK_ low, shuts down the respective regulator,
and immediately pulls the output to ground through its
low-side MOSFET. Turning on the low-side MOSFET
with 100% duty cycle rapidly discharges the output
capacitors and clamps the output to ground. However,
this commonly undamped response causes negative
output voltages due to the energy stored in the output
LC at the instant the OVP occurs. If the load cannot tol-
erate a negative voltage, place a power Schottky diode
across the output to act as a reverse-polarity clamp. If
the condition that caused the overvoltage persists
(such as a shorted high-side MOSFET), the input
Once the 5V bias supply rises above this input UVLO
threshold and ONA is pulled high, the main step-down
controller (regulator A) is enabled and begins switch-
ing. The internal voltage soft-start gradually increments
the feedback voltage by 10mV every 12 switching
cycles. Therefore, OUTA reaches its nominal regulation
voltage 1200/f
after regulator A is enabled (see the
SWA
REG A Startup Waveform (Heavy Load) graph in the
Typical Operating Characteristics).
Regulator B and C Startup
The internal step-down controllers start switching and the
output voltages ramp up using soft-start. If the bias sup-
ply voltage drops below the UVLO threshold, the controller
stops switching and disables the drivers (LX_ becomes
high impedance) until the bias supply voltage recovers.
source also fails (short-circuit fault). Cycle V
below
CC
1V or toggle the respective enable input to clear the
fault latch and restart the regulator.
Once the 5V bias supply and INBC rise above their
respective input UVLO thresholds (SHDN must be
pulled high to enable the reference), and ONB or ONC
is pulled high, the respective internal step-down con-
troller (regulator B or C) becomes enabled and begins
switching. The internal voltage soft-start gradually
increments the feedback voltage by 10mV every 24
switching cycles for regulator B or every 12 switching
cycles for regulator C. Therefore, OUTB reaches its
Output Undervoltage Protection (UVP)
Each MAX17017 includes an output undervoltage
(UVP)-protection circuit that begins to monitor the out-
put once the startup blanking period has ended. If any
output voltage drops below 88% (typ) of its nominal
regulation voltage, the UVP protection immediately sets
the fault latch, pulls the respective POK output low,
forces the high-side and low-side MOSFETs into high-
impedance states (DH = DL = low), and shuts down the
nominal regulation voltage 1800/f
after regulator B
SWB
is enabled, and OUTC reaches its nominal regulation
voltage 900/f after regulator C is enabled (see the
respective regulator. Cycle V
below 1V or toggle the
SWC
CC
REG B Startup Waveform (Heavy Load) and REG C
Startup Waveform (Heavy Load) graphs in the Typical
Operating Characteristics).
respective enable input to clear the fault latch and
restart the regulator.
Thermal-Fault Protection
The MAX17017 features a thermal-fault-protection cir-
cuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
all POK outputs low, and shuts down all regulators.
Toggle SHDN to clear the fault latch and restart the
controllers after the junction temperature cools by 15°C.
SMPS Power-Good Outputs (POK)
POKA, POKB, and POKC are the open-drain outputs of
window comparators that continuously monitor each
output for undervoltage and overvoltage conditions.
POK_ is actively held low in shutdown (SHDN = GND),
standby (ONA = ONB = ONC = GND), and soft-start.
Once the soft-start sequence terminates, POK_
______________________________________________________________________________________ 21
Quad-Output Controller for
Low-Power Architecture
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
VTT LDO Detailed Description
VTT LDO Power-Good Output (POKD)
POKD is the open-drain output of a window comparator
• Maximum load current. There are two values to
consider. The peak load current (I ) deter-
that continuously monitors the VTT LDO output for
undervoltage and overvoltage conditions. POKD is
actively held low when the VTT LDO is disabled (OND
= GND) and soft-start. Once the startup blanking time
expires, POKD becomes high impedance as long as
the output remains within 6% (min) of the nominal reg-
ulation voltage set by REFIND. POKD goes low once its
corresponding output drops or rises 12% (typ) beyond
its nominal regulation point or the output is shut down.
For a logic-level POKD output voltage, connect an
external pullup resistor between POKD and LDO5. A
100kΩ pullup resistor works well in most applications.
LOAD(MAX)
mines the instantaneous component stresses and fil-
tering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I
) determines the thermal stresses and
LOAD
MAX017
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
• Switching frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
VTT LDO Fault Protection
LDO Output Overvoltage Protection (OVP)
input voltage, due to MOSFET switching losses that
2
are proportional to frequency and V
.
IN
If the output voltage rises above 112% (typ) of its nomi-
nal regulation voltage, the controller sets the fault latch,
pulls POKD low, shuts down the source/sink linear reg-
ulator, and immediately pulls the output to ground
through its low-side MOSFET. Turning on the low-side
MOSFET with 100% duty cycle rapidly discharges the
output capacitors and clamps the output to ground.
• Inductor operating point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency, higher output
ripple, and lower maximum load current, and due to
increased ripple currents. The minimum practical
inductor value is one that causes the circuit to oper-
ate at the edge of critical conduction (where the
inductor current just touches zero with every cycle at
maximum load). Inductor values lower than this
grant no further size-reduction benefit. The optimum
operating point is usually found between 20% and
50% ripple current. When pulse skipping (light
loads), the inductor value also determines the load-
current value at which PFM/PWM switchover occurs.
Cycle V
below 1V or toggle OND to clear the fault
CC
latch and restart the linear regulator.
LDO Output Undervoltage Protection (UVP)
Each MAX17017 includes an output undervoltage pro-
tection (UVP) circuit that begins to monitor the output
once the startup blanking period has ended. If the
source/sink LDO output voltage drops below 88% (typ)
of its nominal REFIND regulation voltage for 5ms, the
UVP protection sets the fault latch, pulls the POKD out-
put low, forces the output into a high-impedance state,
Step-Down Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
and shuts down the linear regulator. Cycle V
below
CC
1V or toggle OND to clear the fault latch and restart the
regulator.
V
V
− V
OUT
(
)
OUT IN
SMPS Design Procedure
(Step Down Regulators)
L =
V f
I
LIR
IN SW LOAD(MAX)
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0μH, 1.5μH, 2.2μH, 3.3μH, etc. Also
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
• Input voltage range. The maximum value (V
)
IN(MAX)
must accommodate the worst-case, high AC-
adapter voltage. The minimum value (V ) must
IN(MIN)
account for the lowest battery voltage after drops
22 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
the selected inductance value, the actual peak-to-peak
Electrical Characteristics table, and f
is the switching
SW
inductor ripple current (ΔI
) is defined by:
frequency selected by the FREQ setting (see Table 1).
INDUCTOR
When using only polymer capacitors on the output, the
V
V
− V
)
(
OUT IN
OUT
additional ESR of the output (R
consideration.
) must be taken into
ESR
ΔI
=
INDUCTOR
V f
L
IN SW
For duty cycles less than 40% using polymer capacitors:
Ferrite cores are often the best choice, although soft sat-
urating molded core inductors are inexpensive and can
work well at 500kHz. The core must be large enough not
⎛
⎞
⎟
⎛
⎞⎛
⎞
V
V
OUT
1
FB
C
>
1 +
OUT
⎜
⎜
⎟⎜
⎟
V
V
IN
2f
R
+ R
x V / V
FB OUT
⎝
⎠⎝
⎠
(
)
ESR
⎝
⎠
OUT
SW DROOP
to saturate at the peak inductor current (I
):
PEAK
For duty cycles above 40% using polymer capacitors, the
ESR and C must meet the conditions listed below:
ΔI
⎛
⎞
⎠
INDUCTOR
2
I
= I
+
⎜
⎝
⎟
OUT
PEAK LOAD(MAX)
⎛
⎜
⎞
V
⎝ V
OUT
R
< R
ESR
DROOP
1
⎟
SMPS Output Capacitor Selection
The output filter capacitor selection requires careful
evaluation of several different design requirements—
stability, transient response, and output ripple volt-
age—that place limits on the output capacitance and
ESR. Based on these requirements, the typical applica-
tion requires a low-ESR polymer capacitor (lower cost
but higher output-ripple voltage) or bulk ceramic
capacitors (higher cost but low output-ripple voltage).
⎠
FB
⎛
⎞⎛
⎞⎛
⎞
V
V
OUT
V
IN
FB
C
>
1 +
OUT
⎜
⎟⎜
⎟⎜
⎟
2f
R
V
⎝
⎠⎝
⎠⎝
⎠
SW DROOP
OUT
When the ESR condition described above is not satis-
fied, or when using a mix of ceramic and polymer
capacitors on the output, an additional feedback pole-
capacitor from FB to analog ground (C ) is necessary
FB
to cancel the output capacitor ESR zero:
SMPS Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the loop
gain. This reduces the output capacitance requirement
(stability and transient) and output power dissipation
requirements as well. The load-line is generated by sens-
ing the inductor current through the high-side MOSFET
on-resistance, and is internally preset to -5mV/A (typ) for
regulator B and -7mV/A (typ) for regulator C. The load-
line ensures that the output voltage remains within the
regulation window over the full-load conditions.
⎛
⎞
C
R
OUT ESR
R
C
>
FB
⎜
⎟
⎝
⎠
FB
where R is the parallel impedance of the FB resistive
FB
divider.
SMPS Output Ripple Voltage
With polymer capacitors, the effective series resistance
(ESR) dominates and determines the output ripple volt-
age. The step-down regulator’s output ripple voltage
) equals the total inductor ripple current
) multiplied by the output capacitor’s ESR.
Therefore, the maximum ESR to meet the output ripple
voltage requirement is:
(V
The load line of the internal SMPS regulators also pro-
vides the AC ripple voltage required for stability. To
maintain stability, the output capacitive ripple must be
kept smaller than the internal AC ripple voltage, and
crossover must occur before the Nyquist pole—
(2f )/(1+D) occurs. Based on these loop requirements,
SW
a minimum output capacitance can be determined from
the following:
RIPPLE
(ΔI
INDUCTOR
⎡
⎢
V f
L
⎤
⎥
IN SW
− V
R
≤
V
RIPPLE
ESR
V
V
)
(
⎢
⎣
⎥
⎦
IN
OUT OUT
where f
is the switching frequency. The actual capa-
When using only ceramic capacitors on the output, the
required output capacitance is:
SW
citance value required relates to the physical case size
needed to achieve the ESR requirement, as well as to
the capacitor chemistry. Thus, polymer capacitor selec-
tion is usually limited by ESR and voltage rating rather
than by capacitance value. Alternatively, combining
ceramics (for the low ESR) and polymers (for the bulk
capacitance) helps balance the output capacitance vs.
output ripple voltage requirements.
⎛
⎞⎛
⎞⎛
⎞
V
V
OUT
V
IN
1
FB
C
>
1 +
OUT
⎜
⎟⎜
⎟⎜
⎟
2f
R
V
⎝
⎠⎝
⎠⎝
⎠
SW DROOP
OUT
where R
is 2R
for regulator A, 5mV/A for
SENSE
DROOP
regulator B, or 7mV/A for regulator C as defined in the
______________________________________________________________________________________ 23
Quad-Output Controller for
Low-Power Architecture
Internal SMPS Transient Response
Input Capacitor Selection
The load-transient response depends on the overall
output impedance over frequency, and the overall
amplitude and slew rate of the load step. In applica-
tions with large, fast load transients (load step > 80% of
full load and slew rate > 10A/μs), the output capacitor’s
high-frequency response—ESL and ESR—needs to be
considered. To prevent the output voltage from spiking
too low under a load-transient event, the ESR is limited
by the following equation (ignoring the sag due to finite
capacitance):
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
requirements of an individual regulator can be
determined by the following equation:
RMS
The I
RMS
⎛
⎞
I
LOAD
I
=
V
V − V
(
)
RMS
OUT IN OUT
⎜
⎟
V
⎝
⎠
IN
The worst-case RMS current requirement occurs when
operating with V = 2V . At this point, the above
MAX017
IN
OUT
equation simplifies to I
= 0.5 x I
However, the
RMS
LOAD.
⎛
⎞
V
STEP
LOAD(MAX)
MAX17017 uses an interleaved fixed-frequency archi-
tecture, which helps reduce the overall input RMS cur-
rent on the INBC input supply.
R
≤
− R
ESR
⎜
PCB⎟
ΔI
⎝
⎠
where V
is the allowed voltage drop, ΔI
is
STEP
LOAD(MAX)
is the parasitic board
For the MAX17017 system (INA) supply, nontantalum
chemistries (ceramic, aluminum, or OS-CON) are pre-
ferred due to their resistance to inrush surge currents
typical of systems with a mechanical switch or connector
in series with the input. For the MAX17017 INBC input
supply, ceramic capacitors are preferred on input due to
their low parasitic inductance, which helps reduce the
high-frequency ringing on the INBC supply when the
internal MOSFETs are turned off. Choose an input
capacitor that exhibits less than +10°C temperature rise
at the RMS input current for optimal circuit longevity.
the maximum load step, and R
PCB
resistance between the load and output capacitor.
The capacitance value dominates the midfrequency
output impedance and dominates the load-transient
response as long as the load transient’s slew rate is
less than two switching cycles. Under these conditions,
the sag and soar voltages depend on the output
capacitance, inductance value, and delays in the tran-
sient response. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from or added to the output filter capacitors by a sud-
den load step, especially with low differential voltages
BST Capacitors
) must be selected large
The boost capacitors (C
BST
across the inductor. The sag voltage (V
) that occurs
SAG
enough to handle the gate charging requirements of
the high-side MOSFETs. For these low-power applica-
tions, 0.1μF ceramic capacitors work well.
after applying the load current can be estimated by the
following:
2
L ΔI
(
ΔI
T − ΔT
)
(
)
LOAD(MAX)
LOAD(MAX)
Regulator A Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
V
=
+
SAG
2C
V
×D
− V
C
OUT
(
)
OUT IN
MAX
OUT
where D
is the maximum duty factor (see the
MAX
Electrical Characteristics table), T is the switching peri-
od (1/f ), and ΔT equals V /V x T when in PWM
OSC
OUT IN
The high-side MOSFET (N ) must be able to dissipate
H
mode, or L x I
/(V - V
) when in pulse-skipping
IDLE IN
OUT
the resistive losses plus the switching losses at both
mode. The amount of overshoot voltage (V
) that
SOAR
V
and V
. Ideally, the losses at V
IN(MAX) IN(MIN)
IN(MIN)
occurs after load removal (due to stored inductor ener-
gy) can be calculated as:
should be roughly equal to the losses at V
, with
IN(MIN)
IN(MAX)
lower losses in between. If the losses at V
are
2
significantly higher, consider increasing the size of N .
H
ΔI
L
(
)
LOAD(MAX)
Conversely, if the losses at V
are significantly
H
IN(MAX)
V
≈
SOAR
higher, consider reducing the size of N . If V does
2C
V
IN
OUT OUT
not vary over a wide range, maximum efficiency is
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
achieved by selecting a high-side MOSFET (N ) that
H
has conduction losses equal to the switching losses.
needed to prevent V
from causing problems during
SOAR
Choose a low-side MOSFET (N ) that has the lowest
L
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
possible on-resistance (R
), comes in a moder-
DS(ON)
ate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
24 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
and is reasonably priced. Ensure that the MAX17017
DLA gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems might occur. Switching losses are not an issue for
the low-side MOSFET since it is a zero-voltage
switched device when used in the step-down topology.
For the low-side MOSFET (N ) the worst-case power
L
dissipation always occurs at maximum battery voltage:
⎡
⎤
⎥
⎛
⎜
⎞
⎟
V
2
OUT
⎢
PD N Resistive = 1−
I
(
R
DS(ON)
(
)
)
L
LOAD
V
⎢
⎥
⎦
⎝ IN(MAX) ⎠
⎣
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
Power-MOSFET Dissipation
greater than I
, but are not high enough to
LOAD(MAX)
Worst-case conduction losses occur at the duty factor
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at
minimum input voltage:
ΔI
⎛
⎞
INDUCTOR
I
= I
−
⎛
⎞
⎜
⎝
⎟
⎠
V
V
2
LOAD LIMIT
OUT
2
PD N Resistive =
I
(
R
DS(ON)
(
)
)
H
LOAD
⎜
⎟
⎝
⎠
IN
where I
is the peak current allowed by the current-
LIMIT
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
DS(ON)
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a relatively
large heatsink to handle the overload power dissipation.
R
required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
Choose a Schottky diode (D ) with a forward voltage
L
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
the conduction (R
) losses. High-side switching
DS(ON)
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N ) due to switching losses is difficult, since
H
it must allow for difficult-to-quantify factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PC board (PCB) layout charac-
teristics. The following switching loss calculation pro-
vides only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
Regulator A Step-Up
Converter Configuration
Regulator A can be configured as a step-up converter
(Figure 4). When UP/DN is pulled low, regulator A oper-
ates as a step-up converter (for 1 Li+ cell applications). It
typically generates a 5V output voltage from a 3V to 5V
battery input voltage. The step-up converter uses a cur-
rent-mode architecture; the difference between the feed-
back voltage and a 1V reference signal generates an error
signal that programs the peak inductor current to regulate
the output voltage. The step-up converter is internally com-
pensated, reducing external component requirements.
using a thermocouple mounted on N :
H
PD N Switching =
(
)
H
I
Q
C
V
⎛
⎞
LOAD G(SW)
OSS IN(MAX)
2
+
V
f
IN(MAX) SW
⎜
⎟
I
⎝
⎠
GATE
When regulator A is configured as a step-up converter,
SHDN should be connected to GND. ONA is the master
enable switch. ONA rising enables REF and the bias
block. Connect LDO5 and INLDO together with OUTA
and connect BYP to either OUTA or INA.
where C
is the output capacitance of N , Q
is
OSS
H
G(SW)
the charge needed to turn on the N MOSFET, and
H
I
is the peak gate-drive source/sink current (1A typ).
GATE
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switching-
At light loads, efficiency is enhanced by an idle mode
in which switching occurs only as needed to service the
load. This idle-mode threshold is determined by com-
paring the current-sense signal to an internal reference.
In idle mode, the synchronous rectifier shuts off once
the current-sense voltage (CSPA - CSNA) drops below
1mV, preventing negative inductor current.
2
loss equation (C x V
x f ). If the high-side MOSFET
IN
SW
DS(ON)
chosen for adequate R
becomes extraordinarily hot when subjected to
, consider choosing another MOSFET with
at low battery voltages
V
IN(MAX)
lower parasitic capacitance.
______________________________________________________________________________________ 25
Quad-Output Controller for
Low-Power Architecture
18
13
38
INA
3V TO 4.5V
SHDN
SYNC
C7
C8
C9
1μF, 16V
0603
4.7μF, 16V
1206
150μF, 35mΩ
6V
B2 CASE
PWR
19
15
PWR
R15
PWR
UP/DN
LDO5
24
23
0.01Ω
1%, 0612
CSPA
CSNA
AGND
14
L1
INLDO
3.3μH, 6.8A, 14.2mΩ
5.8mm x 6.2mm x 3.0mm
(NEC/TOKIN:
5V SMPS
OUTPUT
MPLC0525L1R0)
28
30
MAX017
5V,
1A
44
LXA
DLA
V
DD
CC
C11
N
L1
C1
R1
220μF,
35mΩ 6V
B2 C4SE
R3
C10
0.1μF,
6V, 0402
N
H1
4.7μF, 6V
10Ω
PWR
40kΩ
1%, 0402
0603 5%, 0402
PWR
17
V
29
27
25
PWR
R4
BSTA
DHA
FBA
10kΩ
C2
1%, 0402
1.0μF, 6V
0402
AGND
39
37
47
46
C11
680pF, 6V
0402
ONA
ON OFF
ON OFF
ON OFF
ON OFF
16
AGND
BYP
ONB
ONC
AGND
4x INBC
40-43
C12
C13
10μF, 6V
0805
1μF, 16V
OND
0402
PWR
PWR
5V SMPS
OUTPUT
C5
MAX17017
L2
34
0.1μF, 6V
R9
100kΩ
5%,
R10
R11
100kΩ
5%,
R12
100kΩ
5%,
1.0μH, 6.8A, 14.2mΩ
BSTB
0402
100kΩ
6.7mm x 7.7mm x 3.0mm
5%,
0402
(NEC/TOKIN: MPLC0730L3R3)
1.8V,
2.5A
0402
0402
0402
3x LXB
26
35
C14
31, 32, 33
36
POKA
POKB
R5
R6
220μF
21.0kΩ
1%, 0402
15.0kΩ
1%, 0402
18mΩ, 2.5V, B2 CASE
1
PWR
FBB
POKC
POKD
C15
1000pF, 6V
0402
45
R2
AGND
0Ω
AGND
L3
1%, 0402
C6
0.1μF, 6V
0402
20
2
1.0μH, 6.8A, 14.2mΩ
FREQ
BSTC
5.8mm x 8.2mm x 3.0mm
(NEC/TOKIN: MPLC0525L1R0)
1.05V,
4A
4x LXC
AGND
3-6
48
C16
C17
C3
R7
6.04kΩ
R8
220μF
10μF, 6V
0805
10nF , 6V
0402
15.0kΩ
1%, 0402
18mΩ,
2.5V, B2
CASE
1%, 0402
21
PWR
PWR
REF
FBC
IND
C18
2200pF, 6V
0402
AGND
AGND
AGND
AGND
11
12
VTTR
9
C4
0.1μF,
6V
0402
C19
1μF, 6V
0402
C20
10μF, 6V
0805
R13
PWR
PWR
7, 8
0.9A,
1A
15kΩ
2x OUTD
FBD
1%, 0402
C21
10μF, 6V
0805
C22
1.8V SMPS
OUTPUT
10
22
10μF, 6V
REFIND
0805
R14
AGND
15.0kΩ
PWR
PWR
1%, 0402
PGND
PWR
AGND
AGND
Figure 4. Standard Application Circuit 2, Regulator A Configured as Step-Up Converter
26 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
Step-Up Configuration Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
V
= V
+ V
RIPPLE
RIPPLE(C) RIPPLE(ESR)
⎛
⎞
I
C
V
V
- V
OUT
OUT IN
2
V ≈
RIPPLE(C)
⎛
⎞
⎛
⎞
V
V
- V
f
⎜
⎟
OUT
LIR
LOAD(MAX) SW
VIN
IN
f
⎝
⎠
L =
OUT
OUT SW
⎜
⎟
⎜
⎟
V
I
⎝
⎠
⎝
⎠
OUT
and:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
V
≈ I
R
RIPPLE(ESR) PEAK ESR
rent at the minimum input voltage V
servation of energy:
using con-
IN(MIN)
where I
is the peak inductor current. For polymer
PEAK
capacitors, the output voltage ripple is typically domi-
nated by resistive ripple voltage. The voltage rating and
temperature characteristics of the output capacitor
must also be considered. The output ripple voltage due
to the frequency-dependent term can be compensated
by using capacitors of very low ESR to maintain low rip-
ple voltage. Note that all ceramic capacitors typically
have large temperature coefficient and bias voltage
coefficients. The actual capacitor value in circuit is typi-
cally significantly less than the stated value.
I
V
LOAD(MAX) OUT
I
=
VIN(DC,MAX)
V
IN(MIN)
Calculate the ripple current at that operating point and
the peak current required for the inductor:
V
V
- V
(
)
IN OUT IN
ΔI
=
INDUCTOR
V
f
L
OUT SW
Step-Up Configuration Loop Compensation
The boost converter small-signal model contains a right
half-plane (RHP) zero. The presence of an RHP zero
tends to destabilize wide-bandwidth feedback loop
because during a transient, the output initially changes
in the wrong direction. Also when an RHP zero is pre-
sent, it is difficult to obtain an adequate phase margin.
⎛
⎞
ΔI
INDUCTOR
2
I
= I
+
⎜
⎝
⎟
⎠
PEAK LOAD(MAX)
The inductor’s saturation current rating and the
MAX17017’s LXA current limit should exceed I and
the inductor’s DC current rating should exceed
. For good efficiency, choose an inductor
with less than 0.1Ω series resistance.
PEAK
RHP is determined by inductance L, duty cycle D
and load R. The RHP is:
,
up
I
VIN(DC,MAX)
2
(1 - D ) R
UP
f
=
Step-Up Configuration Output
RHP
2πL
Capacitor Selection
For boost converter, during continuous operation, the
output capacitor has a trapezoidal current profile. The
large RMS ripple current in the output capacitor must
be rated to handle the current. The RMS current is
To maintain stability, crossover must occur before the
RHP. To make sure the phase margin is big enough to
stabilize the circuit, the converter crossover must be
kept 4 ~ 10 times slower than the RHP zero. A minimum
output capacitance is determined from the following:
greatest at I
and minimum input working volt-
LOAD(MAX)
age. Therefore, the output capacitor should be chosen
with a rating at least I The RMS current into
COUT(RMS).
⎛
⎞ ⎛
⎞
A
V
REF
the capacitor is then given by:
STEP-UP
C
> 4
L
OUT
⎜
⎟ ⎜
⎟
R
V
(1 - D )R
⎝
⎠ ⎝
⎠
CS
OUT UP
V
- V
IN
OUT
I
≅ I
COUT(RMS) LOAD
where A
is equal to 1.25, which is the error amplifi-
STEP-UP
V
IN
er gain divided by the current-sense gain; R is the cur-
CS
rent-sensing resistor.
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the resistive ripple
due to the capacitor’s equivalent series resistance (ESR):
Additionally, an additional feedback pole—capacitor
from FB to analog ground (C )—might be necessary to
FB
cancel the unwanted ESR zero of the output capacitor.
______________________________________________________________________________________ 27
Quad-Output Controller for
Low-Power Architecture
In general, if the ESR zero occurs before the Nyquist
pole, then canceling the ESR zero is recommended:
feature makes the MAX17017 ideal for memory applica-
tions in which the termination supply must track the
supply voltage.
If:
VTT LDO Output Capacitor
⎛
⎞
G
V
Selection (C
)
CS OUT
OUTD
ESR >
⎜
⎟
A minimum value of 20μF or greater ceramic is needed
to stabilize the VTT output (OUTD). This value of capac-
itance limits the switching regulator’s unity-gain band-
width frequency to approximately 1.2MHz (typ) to allow
adequate phase margin for stability. To keep the
capacitor acting as a capacitor within the switching
regulator’s bandwidth, it is important that ceramic
capacitors with low ESR and ESL be used.
(1 - D)AV
⎝
⎠
REF
then:
MAX017
⎛
⎜
⎝
⎞
⎟
⎠
C
ESR
OUT
R
C
>
FB
FB
where R is the parallel impedance of the FB resistive
FB
Since the gain bandwidth is also determined by the
transconductance of the output MOSFETs, which
increases with load current, the output capacitor might
need to be greater than 20μF if the load current
exceeds 1.5A, but can be smaller than 20μF if the maxi-
mum load current is less than 1.5A. As a guideline,
choose the minimum capacitance and maximum ESR
for the output capacitor using the following:
divider.
Step-Up Configuration Input
Capacitor Selection
The current in the boost converter input capacitor does
not contain large square-wave currents as found in the
output capacitor. Therefore, the input capacitor selec-
tion is less critical due to the output capacitor. However,
a low ESR is recommended.
I
LOAD
The RMS input ripple current for a boost converter is:
C
= 20μF ×
OUT _MIN
1.5A
0.3V
D
IN(MIN) MAX
and:
I
≈
CIN(RMS)
Lf
SW
I
LOAD
1.5A
R
= 5mΩ ×
ESR_MAX
VTT LDO Design Procedure
R
value is measured at the unity-gain-bandwidth
IND Input Capacitor Selection (C
)
ESR
IND
frequency given by approximately:
The value of the IND bypass capacitor is chosen to limit
the amount of ripple and noise at IND, and the amount of
voltage sag during a load transient. Typically, IND con-
nects to the output of a step-down switching regulator,
which already has a large bulk output capacitor.
Nevertheless, a ceramic capacitor equivalent to half the
VTT output capacitance should be added and placed as
close as possible to IND. The necessary capacitance
value must be increased with larger load current, or if the
trace from IND to the power source is long and results in
relatively high input impedance.
36
I
LOAD
f
=
×
GBW
C
1.5A
OUT
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
capacitor (if desired) to further suppress noise or volt-
age ripple at the output.
VTTR Output Capacitor Selection
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Therefore, the VTTR compensation requirements also
scale. For typical applications requiring load currents
up to 3mA, a 0.22μF or greater ceramic capacitor is
VTT LDO Output Voltage (FBD)
The VTT output stage is powered from the IND input.
The VTT output voltage is set by the REFIND input.
REFIND sets the VTT LDO feedback regulation voltage
(V
= V
) and the VTTR output voltage. The
REFIND
FBD
VTT LDO (FBD voltage) and VTTR track the REFIND
voltage over a 0.5V to 1.5V range. This reference input
recommended (R
< 0.3Ω).
ESR
28 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
above the feedback threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
VTT LDO Power Dissipation
Power loss in the MAX17017 VTT LDO is significant and
can become a limiting design factor in the overall
MAX17017 design:
PD
= 2A x 0.9V = 1.8W
VTT
The 1.8W total power dissipation is within the 40-pin
TQFN multilayer board power-dissipation specification
of 2.9W. The typical DDR termination application does
not actually continuously source or sink high currents.
The actual VTT current typically remains around 100mA
to 200mA under steady-state conditions. VTTR is down
in the microampere range, though the Intel specifica-
tion requires 3mA for DDR1 and 1mA for DDR2. True
worst-case power dissipation occurs on an output
short-circuit condition with worst-case current limit.
MAX17017 does not employ any foldback current limit-
ing, and relies on the internal thermal shutdown for pro-
tection. Both the VTT and VTTR output voltages are
referenced to the same REFIND input.
which the controller begins to skip pulses (V
):
IN(SKIP)
⎛
⎞
⎟
1
V
= V
OUT⎜
IN(SKIP)
f
t
⎝ OSC ON(MIN) ⎠
where f
FREQ.
is the switching frequency selected by
OSC
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
the power components on the top side of the board,
with their ground terminals flush against one another.
Follow the MAX17017 Evaluation Kit layout and use the
following guidelines for good PCB layout:
Applications Information
Minimum Input Voltage
The minimum input operating voltage (dropout voltage) is
restricted by the maximum duty-cycle specification (see
the Electrical Characteristics table). For the best dropout
performance, use the slowest switching frequency setting
(FREQ = GND). However, keep in mind that the transient
performance gets worse as the step-down regulators
approach the dropout voltage, so bulk output capaci-
tance must be added (see the voltage sag and soar
equations in the Design Procedure section). The absolute
point of dropout occurs when the inductor current ramps
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mil-
liohm of excess trace resistance causes a measur-
able efficiency penalty.
down during the off-time (ΔI
) as much as it ramps
DOWN
up during the on-time (ΔI ). This results in a minimum
UP
• Minimize current-sensing errors by connecting
CSPA and CSNA directly across the current-sense
operating voltage defined by the following equation:
resistor (R
).
SENSE_
⎛
⎞
1
V
= V
+ V
+ h
−1 V
+ V
(
)
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
IN(MIN)
OUT
CHG
OUT DIS
⎜
⎟
D
⎝
⎠
MAX
where V
and V
are the parasitic voltage drops in
DIS
CHG
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX17017 controller includes a minimum on-time
specification, which determines the maximum input
operating voltage that maintains the selected switching
frequency (see the Electrical Characteristics table).
Operation above this maximum input voltage results in
pulse skipping to avoid overcharging the output. At the
beginning of each cycle, if the output voltage is still
• Route high-speed switching nodes (BST_, LX_,
DHA, and DLA) away from sensitive analog areas
(REF, REFIND, FB_, CSPA, CSNA).
______________________________________________________________________________________ 29
Quad-Output Controller for
Low-Power Architecture
Chip Information
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFN T4866-2
21-0141
MAX017
30 ______________________________________________________________________________________
Quad-Output Controller for
Low-Power Architecture
MAX017
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
5/08
Initial release
—
Updated Electrical Characteristics and added Regulator Step-Up Converter Configuration 4, 5, 8, 9, 23,
1
9/08
section
25–29
Status changed from silent to public; added leakage current specification and updated
Note 2 in Electrical Characteristics; updated Figures 1, 2, and 4; updated SMPS Loop
Compensation section
1–6, 8–23,
25, 26, 29,
30
2
6/09
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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