MAX17021 [MAXIM]
Dual-Phase, Quick-PWM Controllers for IMVP-6+/IMVP-6.5 CPU Core Power Supplies; 双相， Quick-PWM控制器用于IMVP - 6 + / IMVP- 6.5 CPU核电源
| 型号： | MAX17021 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Phase, Quick-PWM Controllers for IMVP-6+/IMVP-6.5 CPU Core Power Supplies |
| 文件： | 总48页 (文件大小：878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4372; Rev 2; 7/09
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
General Description
Features
o Single-/Dual-Phase, Quick-PWM Controllers
The MAX17021/MAX17082/MAX17482 are 2/1-phase-
interleaved Quick-PWM™ step-down VID power-supply
controllers for notebook CPUs. True out-of-phase oper-
ation reduces input ripple current requirements and
output- voltage ripple, while easing component selec-
tion and layout difficulties. The Quick-PWM control pro-
vides instantaneous response to fast load-current
steps. Active voltage positioning reduces power dissi-
pation and bulk output capacitance requirements and
allows ideal positioning compensation for tantalum,
polymer, or ceramic bulk output capacitors.
o MAX17021 IMVP-6+ (Montevina)
o MAX17082/MAX17482 IMVP-6.5 (Calpella)
o
0.5ꢀ V
Accuracy Over Line, Load, and
OUT
Temperature
o 7-Bit 0 to 1.50V VID Control
o Dynamic Phase Selection Optimizes Active/Sleep
Efficiency
o Transient Phase Overlap Reduces Output
Capacitance
o Integrated Boost Switches
o Active Voltage Positioning with Adjustable Gain
A slew-rate controller allows controlled transitions between
VID codes, controlled soft-start and shutdown, and con-
trolled exit from suspend. A thermistor-based temperature
sensor provides a programmable thermal-fault output
(VRHOT). A current monitor output (IMON) provides an
analog current output proportional to the power consumed
by the CPU (MAX17082/MAX17482 only). Output under-
voltage, overvoltage (MAX17021/MAX17082 only), and
thermal protection shut the controller down when any of
these faults are detected. A voltage-regulator power-OK
(PWRGD) output indicates the output is in regulation.
Additionally, the MAX17021/MAX17082/MAX17482 fea-
ture true differential current sense and a phase-good
(PHASEGD) output that indicates a phase imbalance
fault condition.
o Programmable 200kHz to 800kHz Switching
Frequency
o Accurate Current Balance and Current Limit
o Adjustable Slew-Rate Control
o Power-Good, Clock Enable, and Thermal-Fault
Outputs
o Phase Current Imbalance Fault Output
o Drives Large Synchronous Rectifier MOSFETs
o 4V to 26V Battery Input-Voltage Range
o Undervoltage and Thermal-Fault Protection
o Overvoltage Protection (MAX17021/MAX17082)
o Soft-Startup and Soft-Shutdown
The MAX17021 supports the IMVP-6+ specification
while the MAX17082/MAX17482 support the IMVP-6.5
requirements. The MAX17021/MAX17082/MAX17482
are available in a 5mm x 5mm, 40-pin TQFN package.
Pin Configuration
TOP VIEW
Applications
IMVP-6+/IMVP-6.5 Core Supply
Multiphase CPU Core Supply
Voltage-Positioned, Step-Down Converters
Notebook/Desktop Computers
Blade Servers
30 29 28 27 26 25 24 23 22 21
20 PHASEGD
31
32
33
34
35
36
37
38
DPRSTP (SLOW)
19
18
PWRGD
CLKEN
D0
D1
17 V3P3
D2
D3
16
15
14
13
12
11
TON
MAX17021
(MAX17082)
MAX17482
D4
D5
PSI
DPRSLPVR
SHDN
CSP2
Ordering Information
D6
*EP
8
39
40
+
CSP1
CSN1
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
40 TQFN-EP*
CSN2
MAX17021GTL+
MAX17082GTL+
MAX17482GTL+
1
2
3
4
5
6
7
9
10
+Denotes a lead-free(Pb)/RoHS-compliant package.
*EP = Exposed pad.
THIN QFN
() DESIGNATES MAX17082/MAX17482 PIN NAME.
*EXPOSED PAD. CONNECTED TO GND.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGS
CC DD,
V
, V
V3P3 to GND ...........................................-0.3V to +6V
DL1, DL2 to GND..........................................-0.3V to V + 0.3V
DD
D0–D6 to GND..........................................................-0.3V to +6V
PGDIN, DPRSLPVR, PSI to GND..............................-0.3V to +6V
DPRSTP (MAX17021) to GND..................................-0.3V to +6V
SLOW (MAX17082/MAX17482) to GND...................-0.3V to +6V
CSP1, CSP2, CSN1, CSN2 to GND..........................-0.3V to +6V
THRM, ILIM, PHASEGD to GND...............................-0.3V to +6V
PWRGD, VRHOT to GND .........................................-0.3V to +6V
CLKEN to GND ...........................................-0.3V to V3P3 + 0.3V
BST1, BST2 to GND ...............................................-0.3V to +36V
BST1, BST2 to V .................................................-0.3V to +30V
DD
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................(-0.3V to V
DH2 to LX2 ..............................................(-0.3V to V
Continuous Power Dissipation
) + 0.3V
BST1
) + 0.3V
BST2
40-Pin 5mm x 5mm TQFN Up to +70°C.....................1778mW
(derate above +70°C)............................................22.2mW/°C
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
FB, FBAC to GND .........................................-0.3V to V + 0.3V
CC
TIME, CCI to GND.........................................-0.3V to V + 0.3V
CC
CC
IMON to GND (MAX17021/MAX17082)........-0.3V to V
+ 0.3V
GNDS to GND .......................................................-0.3V to +0.3V
SHDN to GND (Note 1)...........................................-0.3V to +16V
TON to GND ...........................................................-0.3V to +30V
Note 1: SHDN might be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and overlapping operation.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
V
, V
4.5
3.0
5.5
3.6
CC DD
Input-Voltage Range
V
V3P3
0/MAX17482
DAC codes from 0.8125V
to 1.5000V
Measured at FB
with respect to
GNDS;
includes load-
regulation error
(Note 2)
-0.5
-7
+0.5
+7
%
DC Output-Voltage
Accuracy
DAC codes from 0.3750V
to 0.8000V
V
OUT
mV
V
DAC codes from 0 to
0.3625V
-20
+20
MAX17021 IMVP-6+
1.194 1.200 1.206
1.094 1.100 1.106
0.1
Boot Voltage
V
BOOT
MAX17082/MAX17482 IMVP-6.5
Line Regulation Error
FB Input Bias Current
GNDS Input Range
GNDS Gain
V
CC
= 4.5V to 5.5V, V = 4.5V to 26V
IN
%
μA
mV
V/V
μA
V
T
A
= +25°C
-0.1
-200
0.97
-0.5
+0.1
+200
1.03
A
ꢀV
/ꢀV
GNDS
1.00
GNDS
GNDS
OUT
GNDS Input Bias Current
TIME Regulation Voltage
I
T
A
= +25°C
+0.5
V
R
TIME
= 71.5kꢀ
1.985 2.000 2.015
TIME
2
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R
TIME
= 71.5kꢀ (12.5mV/μs nominal)
-10
+10
R
= 35.7kꢀ (25mV/μs nominal) to 178kꢀ
TIME
-15
+15
(5mV/μs nominal)
Soft-start and soft-shutdown:
R
TIME
= 35.7kꢀ (3.125mV/μs nominal) to 178kꢀ
-25
+25
(0.625mV/μs nominal)
Slow:
IMVP-6.5 (MAX17082/MAX17482): V
= 0V,
SLOW
1/2 of nominal slew rate, R
(6.25mV/μs nominal);
= 71.5kꢀ
TIME
-15
-15
+15
TIME Slew-Rate Accuracy
%
IMVP-6+ (MAX17021): V
= V
= 5V,
DPRSTP
DPRSLPVR
1/4 of nominal slew rate, R
(3.125mV/μs nominal)
Slow:
= 71.5kꢀ
TIME
IMVP-6.5 (MAX17082/MAX17482): V
1/2 of nominal slew rate, R
(12.5mV/μs nominal) to 178kꢀ (2.5mV/μs
nominal);
= 0V,
SLOW
= 35.7kꢀ
TIME
+15
IMVP-6+ (MAX17021): V
= V
= 5V
DPRSTP
DPRSLPVR
1/4 of nominal slew rate, R
= 35.7kꢀ
TIME
(6.25mV/μs nominal) to 178kꢀ (1.25mV/μs
nominal)
R
= 96.75kꢀ (600kHz per phase),
TON
-15
-10
-15
+15
+10
167ns nominal
Measured
at DH_
(Note 3)
R
TON
= 200kꢀ (300kHz per phase),
On-Time
t
%
ON
333ns nominal
R
TON
= 303.25kꢀ (200kHz per phase),
+15
350
0.1
500ns nominal
Minimum Off-Time
t
Measured at DH_ (Note 3)
300
ns
OFF(MIN)
TON Shutdown Input
Current
SHDN = GND, V = 26V, V = V = 0V or 5V,
IN CC DD
I
0.01
μA
RTON,SDN
T
A
= +25°C
BIAS CURRENTS
Quiescent Supply Current
Measured at V , V
above the regulation point
= 5V, FB forced
= 0V, FB forced
CC DPRSLPVR
I
I
2.5
5
1
mA
μA
CC
(V )
CC
Quiescent Supply Current
(V
Measured at V , V
DD DPRSLPVR
0.02
DD
)
DD
above the regulation point, T = +25°C
A
_______________________________________________________________________________________
3
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Supply Current
(V3P3)
Measured at V3P3, FB forced within the CLKEN
power-good window
I
2
4
μA
3P3
Shutdown Supply Current
I
I
Measured at V , SHDN = GND, T = +25°C
0.01
0.01
0.01
1
1
1
μA
μA
μA
CC,SDN
DD,SDN
CC
A
(V )
CC
Shutdown Supply Current
(V
Measured at V , SHDN = GND, T = +25°C
DD
A
)
DD
Shutdown Supply Current
(V3P3)
I
Measured at V3P3, SHDN = GND, T = +25°C
3P3,SDN
A
FAULT PROTECTION
Skip mode after output reaches the regulation
voltage or PWM mode; measured at FB with
respect to the voltage target set by the VID code;
see Table 4.
250
300
350
mV
Output Overvoltage-
IMVP-6.5
(MAX17082)
V
Protection Threshold
(MAX17021/MAX17082 Only)
OVP
Soft-start, soft-shutdown, skip
mode, and output have not
reached the regulation
1.45
1.75
1.50
1.55
1.85
V
IMVP-6+
1.80
0.8
voltage; measured at FB
(MAX17021)
Minimum OVP threshold; measured at FB
Output Overvoltage-
Propagation Delay
t
FB forced 25mV above trip threshold
10
μs
OVP
(MAX17021/MAX17082 Only)
0/MAX17482
Output Undervoltage-
Protection Threshold
Measured at FB with respect to the voltage target
set by the VID code; see Table 4
V
UVP
-450
-400
10
-350
mV
μs
Output Undervoltage-
Propagation Delay
t
FB forced 25mV below trip threshold
UVP
CLKEN Startup Delay and
Boot Time Period
Measured from the time when FB reaches the
boot target voltage (Note 2)
t
20
3
60
100
10
μs
BOOT
Measured at startup from the time when CLKEN
goes low
PWRGD Startup Delay
6.5
ms
Lower threshold,
falling edge
(undervoltage)
-350
-300
-250
Measured at FB with respect
to the voltage target set by
CLKEN and PWRGD
Threshold
mV
the VID code; see Table 4,
20mV hysteresis (typ)
rising edge
Upper threshold,
+150
+200
+250
(overvoltage)
FB forced 25mV outside the PWRGD trip
thresholds
CLKEN and PWRGD Delay
10
10
μs
μs
PHASEGD Delay
V
forced 25mV outside trip thresholds
(CCI,FB)
4
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLKEN, PWRGD, and
PHASEGD Transition
Blanking Time
Measured from the time when FB reaches the
target voltage (Note 2)
t
20
32
μs
BLANK
(VID Transitions)
PHASEGD Transition
Blanking Time (Phase 2
Enable Transitions)
Number of DH2 pulses for which PHASEGD is
blanked after phase 2 is enabled
Pulses
CLKEN Output Low Voltage
Low state, I
= 3mA
0.4
V
V
SINK
CLKEN Output High
Voltage
V3P3 -
0.4
High state, I
= 3mA
SOURCE
PWRGD, PHASEGD Output
Low Voltage
Low state, I
= 3mA
0.4
1
V
μA
ꢀ
SINK
PWRGD, PHASEGD
Leakage Current
High-impedance state, PWRGD, PHASEGD forced
to 5V, T = +25°C
A
CSN1 Pulldown Resistance
in Shutdown
SHDN = 0, measured after soft-shutdown
completed (DL_ = low)
10
V
Undervoltage Lockout
Rising edge, 65mV typical hysteresis,
controller disabled below this level
CC
V
4.05
29
4.27
4.48
31
V
UVLO(VCC)
(UVLO) Threshold
THERMAL PROTECTION
Measured at THRM as a percentage of V
falling edge, typical hysteresis = 75mV
,
CC
VRHOT Trip Threshold
VRHOT Delay
30
10
2
%
μs
ꢀ
THRM forced 25mV below the VRHOT trip
threshold, falling edge
t
VRHOT
VRHOT Output
On-Resistance
R
Low state
10
ON(VRHOT)
High-impedance state, VRHOT forced to 5V,
= +25°C
VRHOT Leakage Current
1
μA
T
A
THRM Input Leakage
I
V
= 0 to 5V, T = +25°C
-0.1
+0.1
μA
°C
THRM
THRM
A
Thermal-Shutdown Threshold
T
Typical hysteresis = 15°C
160
SHDN
VALLEY CURRENT LIMIT, DROOP, AND CURRENT BALANCE
V
V
- V
- V
= 100mV
= 500mV
7
10
50
13
55
25
TIME
ILIM
ILIM
CC
Current-Limit Threshold
Voltage (Positive)
V
V
- V
- V
mV
45
20
LIMIT
CSP_
CSN_
TIME
ILIM = V
22.5
Current-Limit Threshold
Voltage (Negative)
Accuracy
V
V
V
, nominally -125% of V
LIMIT
-4
+4
mV
mV
LIMIT(NEG)
CSP_
CSN_
Current-Limit Threshold
Voltage (Zero Crossing)
V
- V , DPRSLPVR = 5V
1
ZERO
GND
LX_
_______________________________________________________________________________________
5
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CSP_, CSN_ Common-
Mode Input Range
0
2
V
V
CC
1
-
V
0.4
-
CC
Phase 2 Disable Threshold
Measured at CSP2
3
V
CSP_, CSN_ Input Current
ILIM Input Current
I
, I
T
= +25°C
= +25°C
-0.2
-0.1
+0.2
+0.1
μA
μA
CSP_ CSN_
A
I
T
A
ILIM
= +25oC
-0.5
+0.5
(1/N) x ꢁ (V
- V
) at
CSP_
CSN_
T
T
A
I
= 0;
mV/
phase
FBAC
Droop Amplifier Offset
ꢁ indicates summation over
all phases from 1 to N, N = 2
= 0oC to +85oC -0.75
+0.75
A
ꢀI
/ꢀ[ꢁ (V
- V
)];
FBAC
CSP_
CSN_
Droop Amplifier
Transconductance
ꢁ indicates summation over all phases from 1 to
N, N = 2, V
G
590
-1.0
600
200
608
μS
m(FBAC)
= V
= 0.45V to 2V
FBAC
CSN-
Current-Balance Amplifier
Offset
(V
- V
) - (V
- V
) at I = 0
CCI
+1.0
mV
μS
CSP1
CSN1
CSP2
CSN2
Current-Balance Amplifier
Transconductance
G
m(CCI)
I
/[(V
- V
CSN1
) - (V
- V )]
CSN2
CCI
CSP1
CSP2
CURRENT MONITOR (MAX17082/MAX17482 Only)
Current-Monitor Output
Current at Full Load
Condition
V
V
- V
= V
- V
= 20mV,
CSP1
CSN1
CSP2
CSN2
I
93.12
96
98.88
μA
IMON
= 0.45V to 2.0V
/ꢀ[ꢁ (V - V )];
CSN_
CSN_
ꢀI
IMON
CSP_
0/MAX17482
Current-Monitor
Transconductance
G
ꢁ indicates summation over all phases from 1 to
N, N = 2, CSN_ = 0.45V to 2V
2.2
2.4
2.6
mS
m(IMON)
IMON Clamp Voltage
V
I
= 10mA
SINK
1.05
1.10
10
1.15
V
IMON,max
IMON Pulldown Resistance
in Shutdown
SHDN = 0, measured after soft-shutdown
completed (DL_ = low)
ꢀ
GATE DRIVERS
High state (pullup)
BST_ - LX_ forced to 5V
0.9
0.7
2.5
2.0
2.0
0.7
DH_ Gate Driver
On-Resistance
R
ꢀ
ꢀ
A
A
A
ON(DH_)
ON(DL_)
Low state (pulldown)
High state (pullup)
0.7
DL_ Gate Driver
On-Resistance
R
Low state (pulldown)
0.25
DH_ Gate Driver Source
Current
I
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
DL_ forced to 2.5V
2.2
2.7
2.7
DH_(SOURCE)
DH_ Gate Driver Sink
Current
I
DH_(SINK)
DL_ Gate Driver Source
Current
I
DL_(SOURCE)
6
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V
= V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN1
= 5V; MAX17021: DPRSTP = GND; T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
DL_ forced to 2.5V
MIN
TYP
MAX
UNITS
DL_ Gate Driver Sink
Current
I
8
A
DL_(SINK)
Internal BST_ Switch
On-Resistance
R
10
20
ꢀ
ON(BST_)
LOGIC AND I/O
SHDN, PGDIN
MAX17021: DPRSLPVR
Logic Input High Voltage
V
2.3
V
IH
SHDN, PGDIN
MAX17021: DPRSLPVR
Logic Input Low Voltage
V
1.0
13
V
V
IL
SHDN No-Fault Level
To enable no-fault mode
11
PSI, D0–D6;
MAX17082/MAX17482: DPRSLPVR, SLOW,
MAX17021: DPRSTP
Low-Voltage Logic Input
High Voltage
V
0.67
V
IHLV
PSI, D0–D6;
MAX17082/MAX17482: DPRSLPVR, SLOW,
MAX17021: DPRSTP
Low-Voltage Logic Input
Low Voltage
V
0.33
+1
V
ILLV
T
= +25°C, SHDN, DPRSLPVR, PGDIN, PSI,
A
Logic Input Current
-1
μA
DPRSTP, SLOW, D0–D6 = 0 or 5V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 10V, V
= V
= V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN2
= 5V; MAX17021: DPRSTP = GND; T = -40°C to +105°C, unless otherwise noted.) (Note 4)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
V
, V
4.5
3.0
5.5
3.6
CC DD
Input-Voltage Range
V
V3P3
DAC codes from
0.8125V to 1.5000V
-0.75
-10
+0.75
+10
%
Measured at FB with
respect to GNDS;
includes load-
DC Output-Voltage
Accuracy
DAC codes from
0.3750V to 0.8000V
V
OUT
mV
V
regulation error (Note 2)
DAC codes from 0 to
0.3625V
-25
+25
MAX17021: IMVP-6+
1.19
1.09
1.21
1.11
Boot Voltage
V
BOOT
MAX17082/MAX17482: IMVP-6.5
_______________________________________________________________________________________
7
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V
= V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN2
= 5V; MAX17021: DPRSTP = GND; T = -40°C to +105°C, unless otherwise noted.) (Note 4)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-200
0.97
1.985
-10
TYP
MAX
+200
1.03
UNITS
mV
GNDS Input Range
GNDS Gain
A
ꢀV
/ꢀV
GNDS
V/V
GNDS
OUT
TIME
TIME
TIME Regulation Voltage
V
TIME
R
R
= 71.5kꢀ
2.015
+10
V
= 71.5kꢀ (12.5mV/μs nominal)
R
= 35.7kꢀ (25mV/μs nominal) to 178kꢀ
TIME
-15
+15
(5mV/μs nominal)
Soft-start and soft-shutdown:
R
TIME
= 35.7kꢀ (3.125mV/μs nominal) to 178kꢀ
-25
+25
(0.625mV/μs nominal)
Slow:
IMVP-6.5 (MAX17082/MAX17482): V
= 0V,
SLOW
1/2 of nominal slew rate, R
(6.25mV/μs nominal);
= 71.5kꢀ
TIME
-15
-17
+15
+17
TIME Slew-Rate Accuracy
%
IMVP-6+ (MAX17021): V
= V
= 5V,
DPRSLPVR
DPRSTP
1/4 of nominal slew rate, R
(3.125mV/μs nominal)
= 71.5kꢀ
TIME
Slow:
IMVP-6.5 (MAX17082/MAX17482): V
= 0V,
SLOW
1/2 of nominal slew rate, R
= 35.7kꢀ
TIME
(12.5mV/μs nominal) to 178kꢀ (2.5mV/μs nominal);
IMVP-6+ (MAX17021): V = V = 5V,
DPRSTP
DPRSLPVR
1/4 of nominal slew rate, R
= 35.7kꢀ
TIME
(6.25mV/μs nominal) to 178kꢀ (1.25mV/μs nominal)
R
= 96.75kꢀ (600kHz per phase),
TON
0/MAX17482
-15
-15
-15
+15
+15
167ns nominal
Measured
at DH_
(Note 3)
R
TON
= 200kꢀ (300kHz per phase),
On-Time
t
%
ON
333ns nominal
R
TON
= 303.25kꢀ (200kHz per phase),
+15
350
500ns nominal
Minimum Off-Time
t
Measured at DH_ (Note 3)
ns
OFF(MIN)
BIAS CURRENTS
Quiescent Supply Current
Measured at V , V
above the regulation point
= 5V, FB forced
CC DPRSLPVR
I
5
4
mA
μA
CC
(V )
CC
Quiescent Supply Current
(V3P3)
Measured at V3P3, FB forced within the CLKEN
power-good window
I
3P3
8
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V
= V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN2
= 5V; MAX17021: DPRSTP = GND; T = -40°C to +105°C, unless otherwise noted.) (Note 4)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT PROTECTION
Skip mode after output reaches the regulation
voltage or PWM mode, measured at FB with
respect to the voltage target set by the VID code
(see Table 4)
250
350
mV
Output Overvoltage-
Protection Threshold
(MAX17021/MAX7082
Only)
V
OVP
IMVP-6.5
(MAX17082)
Soft-start, soft-shutdown, skip
mode, and output have not
reached the regulation voltage,
measured at FB
1.45
1.75
-450
20
1.55
1.85
-350
100
10
V
IMVP-6+
(MAX17021)
Output Undervoltage-
Protection Threshold
Measured at FB with respect to the voltage target
set by the VID code (see Table 4)
V
mV
μs
UVP
CLKEN Startup Delay and
Boot Time Period
Measured from the time when FB reaches the
boot target voltage (Note 3)
t
BOOT
Measured at startup from the time when CLKEN
goes low
PWRGD Startup Delay
3
ms
Lower
threshold,
falling edge
-350
-250
Measured at FB with respect to
the voltage target set by the VID
(undervoltage)
CLKEN and PWRGD
Threshold
mV
code (see Table 4), 20mV
hysteresis (typ)
threshold,
Upper
+150
+250
0.4
rising edge
(overvoltage)
CLKEN Output Low Voltage
Low state, I
= 3mA
V
V
SINK
CLKEN Output High
Voltage
V3P3 -
0.4
High state, I
= 3mA
SOURCE
PWRGD, PHASEGD Output
Low Voltage
Low state, I
= 3mA
0.4
4.5
V
V
SINK
V
CC
Undervoltage-Lockout
Rising edge, 65mV typical hysteresis, controller
disabled below this level
V
R
4.0
28
UVLO(VCC)
Threshold (UVLO)
THERMAL PROTECTION
Measured at THRM as a percentage of V
falling edge, typical hysteresis = 75mV
,
CC
VRHOT Trip Threshold
32
10
%
VRHOT Output
On-Resistance
Low state
ꢀ
ON(VRHOT)
_______________________________________________________________________________________
9
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V
= V
= V
= V
= V
= 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V
ILIM CSP1
IN
CC
DD
SHDN
PGDIN
PSI
= V
V
= V
= V = 1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
FBAC
CSN1
SLOW
CSP2
CSN2
= 5V; MAX17021: DPRSTP = GND; T = -40°C to +105°C, unless otherwise noted.) (Note 4)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VALLEY CURRENT LIMIT, DROOP, AND CURRENT BALANCE
V
V
- V
- V
= 100mV
= 500mV
7
13
60
26
TIME
ILIM
ILIM
CC
Current-Limit Threshold
Voltage (Positive)
V
LIMIT
V
CSP_
- V
CSN_
mV
V
40
19
TIME
ILIM = V
CSP_, CSN_ Common-Mode
Input Range
0
2
ꢀI
/ꢀ[ꢁ(V
- V
)],
FBAC
CSP_
CSN_
Droop Amplifier
Transconductance
ꢁ indicates summation over all phases from 1 to
N, N = 2, V
G
585
-1.25
610
μS
mV
m(FBAC)
= V
= 0.45V to 2V
FBAC
CSN-
Current-Balance Amplifier
Offset
(V
CSP1
- V
CSN1
) - (V
- V ) at I = 0
CSN2 CCI
+1.25
CSP2
CURRENT MONITOR (MAX17082/MAX17482 Only)
ꢀI
/ꢀ[ꢁ(V
- V
)],
IMON
CSP_
CSN_
Current-Monitor
Transconductance
ꢁ indicates summation over all phases from 1 to
N, N = 2, V = 0.45V to 2V
G
2.2
2.6
mS
V
m(IMON)
CSN_
IMON Clamp Voltage
V
I
= 10mA
SINK
1.05
1.15
IMON,max
GATE DRIVERS
High state (pullup)
Low state (pulldown)
High state (pullup)
Low state (pulldown)
2.5
2.0
2.0
0.7
DH_ Gate Driver
On-Resistance
R
BST_ - LX_ forced to 5V
ꢀ
ꢀ
ON(DH_)
ON(DL_)
DL_ Gate Driver
On-Resistance
R
0/MAX17482
LOGIC AND I/O
SHDN, PGDIN:
MAX17021: DPRSLPVR
Logic Input High Voltage
V
2.3
V
V
IH
SHDN, PGDIN:
MAX17021: DPRSLPVR
Logic Input Low Voltage
V
1.0
IL
PSI, D0–D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
Low-Voltage Logic Input
High Voltage
V
0.67
V
V
IHLV
PSI, D0–D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
Low-Voltage Logic Input
Low Voltage
V
0.33
ILLV
Note 2: When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DL_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times might be different due to MOSFET switching speeds.
Note 4: Specifications to T = -40°C and +105°C are guaranteed by design and are not production tested.
A
10 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Typical Operating Characteristics
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 1.075V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
OUTPUT VOLTAGE vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
(V = 0.875V)
(V
= 1.075V)
(V
= 1.075V)
OUT(HFM)
OUT(HFM)
OUT(LFM)
1.15
1.10
1.05
1.00
0.95
100
90
0.90
0.89
0.88
0.87
0.86
0.85
0.84
0.83
7V
SKIP MODE
PWM MODE
80
12V
20V
70
60
50
0
0.1
0
10
20
30
40
50
0.1
1.0
10.0
100.0
0
5
10
LOAD CURRENT (A)
15
20
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V
= 0.875V)
(V
OUT(C4)
= 0.4V)
(V
OUT(C4)
= 0.4V)
OUT(LFM)
90
80
70
60
0.41
0.40
0.39
90
7V
7V
80
70
60
50
40
12V
12V
20V
20V
SKIP MODE
PWM MODE
DPRSLPVR = V
CC
50
30
1.0
10.0
100.0
0
1
2
3
4
5
0.01
0.10
1.00
10.00
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
(V
) = 1.075V)
AT SKIP MODE (V
) = 1.075V)
OUT(HFM
OUT(HFM
400
100
75
50
25
0
10.0
1.0
0.1
0
350
300
250
200
150
100
50
V
= 0.875V
OUT(LFM)
I + I
CC DD
V
= 1.075V
OUT(HFM)
I
IN
I
+ I
CC DD
I
IN
DPRSLPVR = V
CC
DPRSLPVR = GND
18 21 24
INPUT VOLTAGE (V)
DPRSLPVR = V
CC
DPRSLPVR = GND
30 40 50
LOAD CURRENT (A)
0
10
20
6
9
12
15
6
9
12
15
18
21
24
INPUT VOLTAGE AT SKIP MODE (V)
______________________________________________________________________________________ 11
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 1.075V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
0.8125V OUTPUT-VOLTAGE DISTRIBUTION
G
60
TRANSCONDUCTANCE DISTRIBUTION
CURRENT BALANCE vs. LOAD CURRENT
MAX17021 toc12
m(FB)
70
60
50
40
30
20
10
0
60
0.6
V
OUT
= 1.075V
SAMPLE SIZE = 100
SAMPLE SIZE = 100
+85°C
+25°C
+85°C
+25°C
50
40
30
20
10
0
50
40
30
20
10
0.5
0.4
0.3
0.2
0.1
0
0
0
5
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
TRANSCONDUCTANCE (µs)
OUTPUT VOLTAGE (V)
SOFT-START WAVEFORM (UP TO CLKEN)
SOFT-START WAVEFORM (UP TO PWRGD)
SHUTDOWN WAVEFORM
MAX17021 toc13
MAX17021 toc14
MAX17021 toc15
5V
5V
0
5V
5V
0
A
B
A
B
C
A
0
5V
5V
0
B
C
0
0
5V
5V
0
5V
0
1.075V
0
5V
D
E
F
D
0
C
D
1.075V
1.075V
0
0
E
0
0
0
0
0
F
0/MAX17482
E
G
0
0
G
200µs/div
1ms/div
100µs/div
A. SHDN, 10V/div
B. CLKEN, 10V/div
D. I , 10A/div
A. SHDN, 10V/div
E. V , 1V/div
A. SHDN, 10V/div
B. CLKEN, 10V/div
C. PWRGD, 10V/div
D. DL_, 10V/div
E. V , 500mV/div
OUT
LX1
OUT
E. I , 10A/div
B. PWRGD, 10V/div
C. PHASEGD, 10V/div
D. CLKEN, 10V/div
F. I , 10A/div
F. I , 10A/div
LX2
LX1
LX1
C. V , 500mV/div
I
= 15A
G. I , 10A/div
G. I , 10A/div
LX2
OUT
OUT
LX2
I
= 15A
OUT
12 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 1.075V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
LOAD TRANSIENT RESPONSE (HFM MODE)
LOAD-TRANSIENT RESPONSE (LFM MODE)
VID CODE CHANGE (SLOW = GND)
MAX17021 toc18
MAX17021 toc16
MAX17021 toc17
50A
10A
20A
5A
5V
A
A
B
A
0
1.075V
1.075V
B
C
D
1V
0.875V
B
0.975V
25A
C
D
0
0
20A
5A
5A
5A
C
20μs/div
= 10A TO 50A
B. V , 50mV/div
OUT
20µs/div
20µs/div
A. I
C. I , 10A/div
D. I , 10A/div
LX2
A. I
= 5A TO 20A
OUT
C. INDUCTOR CURRENT,
10A/div
A. VID3, 5V/div
B. V , 50mV/div
C. I , 10A/div
LX1
D. I , 10A/div
LX2
OUT
LX1
OUT
B. V , 50mV/div
OUT
DYNAMIC VID CODE CHANGE
(D0 = 12.5mV)
VID CODE CHANGE (SLOW = V
)
DD
MAX17021 toc19
MAX17021 toc20
5V
A
B
5V
A
B
0
0
1.075V
1.075V
0.975V
1.0625V
C
D
C
D
0
0
5A
5A
20µs/div
20µs/div
A. VID3, 5V/div
B. V , 50mV/div
C. I , 10A/div
D. I , 10A/div
LX2
A. D0, 5V/div
B. V , 20mV/div
C. I , 10A/div
LX1
D. I , 10A/div
LX2
LX1
OUT
OUT
I
= 10A
OUT
V
vs. LOAD CURRENT
OUTPUT UNDERVOLTAGE FAULT
IMON
MAX17021 toc21
180
160
V
= 1.075V
OUT
1.075V
0
A
B
C
140
120
100
80
5V
0
5V
0
60
30A
D
40
20
DPRSLPVR = V
CC
0
DPRSLPVR = GND
10 20 30 40 50 60 70 80
+ V (mV)
0
0
100μs/div
V
A. V , 500mV/div
OUT
B. PWRGD, 10V/div
C. DL_, 10V/div
D. I , 15A/div
CSPN1
CSPN2
LX1
______________________________________________________________________________________ 13
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 1.075V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
BIAS SUPPLY REMOVAL
(UVLO RESPONSE)
OUTPUT OVERVOLTAGE WAVEFORM
MAX17021 toc23
MAX17021 toc24
5V
A
B
A
0.875V
0.875V
0
5V
0
0
5V
B
C
D
E
0
5V
0
5V
0
C
10A
0
100μs/div
40μs/div
A. 5V BIAS SUPPLY, 5V/div
A. V , 500mV/div
OUT
B. DL_, 5V/div
C. PWRGD, 5V/div
D. DL_, 5V/div
E. I , 10A/div
B. V , 500mV/div
OUT
LX1
C. PWRGD, 5V/div
I
= 10A
OUT
Pin Description
PIN
NAME
FUNCTION
System Power-Good Logic Input. PGDIN indicates the power status of other system rails and is used for
power-supply sequencing. After power-up to the boot voltage, the output voltage remains at V , CLKEN
BOOT
remains high, and PWRGD remains low as long as the PGDIN stays low. When PGDIN is pulled high, the
output transitions to selected VID voltage, and CLKEN is pulled low. If the system pulls PGDIN low during
normal operation, the MAX17021/MAX17082/MAX17482 immediately drive CLKEN high, pull PWRGD low,
and slew the output to the boot voltage (using two-phase pulse-skipping mode). The controller remains at
1
PGDIN
THRM
the boot voltage until PGDIN goes high again, SHDN is toggled, or the V input power supply is cycled.
CC
0/MAX17482
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V
and
CC
GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of V ) at
CC
2
the desired high temperature.
Current-Monitor Output. The MAX17082/MAX17482 IMON output source a current that is directly
proportional to the current-sense voltage as defined by:
I
= G
x (V
- V
)
IMON
m(IMON)
CSP_
CSN_
where G
= 2.4mS (typ).
m(IMON)
The IMON current is unidirectional (sources current out of IMON only) for positive current-sense values.
For negative current-sense voltages, the IMON current is zero.
Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain based on
the following equation:
IMON
(MAX17082/
MAX17482 where IMAX is defined in the Current Monitor section of the Intel IMVP-6.5 specification and based on
only)
R
= 0.999V/(IMAX x R
x G
)
m(IMON)
IMON
SENSE
3
discrete increments (20A, 30A, 40A, etc.), R
is the typical effective value of the current-sense
SENSE
element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and
is the typical transconductance amplifier gain as defined in the Electrical Characteristics
G
m(IMON)
table.
The IMON voltage is internally clamped to a maximum of 1.1V (typ).
The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly
drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 2.
IMON is pulled to ground when MAX17082/MAX17482 are in shutdown.
14 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Pin Description (continued)
PIN
NAME
FUNCTION
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP_ to CSN_
equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
4
ILIM
valley current-limit threshold. Connect ILIM directly to V to set the default current-limit threshold
CC
setting of 22.5mV (typ) nominal.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of the
internal error-amplifier target. The sum of the resistance between TIME and GND (R
nominal slew-rate:
) determines the
TIME
SLEW RATE = (12.5mV/μs) x (71.5kꢀ/RTIME)
The guaranteed R
range is between 35.7kꢀ and 178kꢀ. This “nominal” slew rate applies to VID
TIME
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew rate for
all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to
the nominal slew rate defined above.
5
TIME
The startup and shutdown slew rates are always 1/8 of nominal slew rate in order to minimize surge
currents.
MAX17021: If both DPRSLPVR and DPRSTP are pulled high, then the slew rate is reduced to 1/4 of nominal.
MAX17082/MAX17482: If SLOW is low, then the slew rate is reduced to 1/2 of nominal.
6
7
V
Controller Analog Bias Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
CC
Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the
feedback remote sense. CCI is internally forced low in shutdown.
CCI
FB
Remote Feedback-Sense Input. Normally shorted to FBAC and connected to the VCC_SENSE pin of the
CPU socket through the load-line gain resistor (see the FBAC pin description). FB internally connects
to the error amplifier and integrator.
8
Voltage-Positioning Transconductance Amplifier Output. Connect a resistor R between FBAC and the
FB
positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-
positioning gain requirement:
R
FB
= R
/(R
x G
)
DROOP
SENSE
m(FBAC)
9
FBAC
where R
is the desired voltage-positioning slope and G
= 600μS (typ). R
is the
SENSE
DROOP
m(FBAC)
value of the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If
lossless sensing is used, R = R . In this case, consider making R a resistor network that
SENSE
L
FB
includes an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Remote Ground-Sense Input. Normally connected to the VSS_SENSE pin of the CPU socket. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage—compensating
for voltage drops from the regulator ground to the load ground.
10
11
12
GNDS
CSN2
CSP2
Negative Current-Sense Input for Phase 2. Connect CSN2 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
Positive Current-Sense Input for Phase 2. Connect CSP2 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4). Short CSP2 to V for dedicated one-phase operation.
CC
______________________________________________________________________________________ 15
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V for normal
CC
operation. Connect to ground to put the IC into its 1μA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at
the same slow slew rate. Forcing SHDN to 11V~13V disables both overvoltage-protection and
undervoltage-protection circuits, clears the fault latch, disables transient phase overlap, and disables
the BST_ charging switches. Do not connect SHDN to > 13V.
13
SHDN
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the operating
mode of MAX17021/MAX17082/MAX17482. When DPRSLPVR is forced high, the controller immediately
enters the automatic pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is
forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward
output-voltage transition that occurs when the controller is in pulse-skipping mode, and stays blanked until
the transition-related PWRGD blanking period is complete and the output reaches regulation. The output
overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed-default
transitional OVP threshold during the period for which the PWRGD upper threshold is blanked.
The MAX17082 is in two-phase pulse-skipping mode during startup and while in boot mode, but is in
forced-PWM mode during the transition from boot mode to VID mode plus 20μs, and during soft-
shutdown, irrespective of the DRPSLPVR logic level.
14
DPRSLPVR
DPRSLPVR and PSI together determine the operating mode and the number of active phases as shown
in the following truth table:
DPRSLPVR
PSI
0
1
0
1
MODE AND PHASES
1
1
0
0
Very low current (one-phase pulse skipping)
Low current (approx 3A) (one-phase pulse skipping)
Intermediate power potential (one-phase PWM)
Max power potential ( two- or one-phase PWM as configured at CSP2)
Power-State Indicator Input. DPRSLPVR and PSI together determine the operating mode and the number
of active phases as shown in the truth table included under the PSI pin description above.
15
PSI
Switching Frequency Setting Input. An external resistor between the input power source and TON sets
0/MAX17482
the switching period (T
= 1/f ) per phase according to the following equation:
SW
SW
T
= 16.3pF x (R
+ 6.5kꢀ)
SW
TON
16
17
18
TON
V3P3
TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON current is
less than 10μA, the MAX17021/MAX17082/MAX17482 disable the controller, set the TON open fault
latch, and pull DL_ and DH_ low.
3.3V CLKEN Input Supply. V3P3 input supplies the CLKEN CMOS push-pull logic output. Connect to
the system’s standard 3.3V supply voltage before SHDN is pulled high for proper IMVP-6.5 operation.
Clock Enable Push-Pull Logic Output. This inverted logic output indicates when the output voltage
sensed at FB is in regulation. During soft-start, shutdown, and when the FB is out of regulation, the
MAX17021/MAX17082/MAX17482 pull CLKEN up to V3P3. During VID transitions, the controller forces
CLKEN low. Except during the power-up sequence, CLKEN is the inverse of PWRGD. See the Startup
Timing Diagram (Figure 10). When in pulse-skipping mode (DPRSLPVR high), the upper CLKEN threshold
is disabled.
CLKEN
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down; if FB is in regulation then PWRGD is high impedance.
During startup, PWRGD is held low and continues to be low while the part is in boot mode and until
5ms (typ) after CLKEN goes low.
19
PWRGD
PWRGD is forced low in shutdown.
PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions).
When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked
during downward transitions.
A pullup resistor on PWRGD causes additional finite shutdown current.
16 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Pin Description (continued)
PIN
NAME
FUNCTION
Phase-Good Current-Balance Open-Drain Output. Used to signal the system that one of the two
phases either has a fault condition or is not matched with the other. Detection is done by identifying
the need for a large on-time difference between phases in order to achieve or move towards current
20
PHASEGD balance. PHASEGD is low in shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in one-phase operation (DPRSLPVR = high or PSI = low).
Boost Flying-Capacitor Connection for Phase 2. BST2 provides the upper supply rail for the DH2 high-
21
BST2
side gate driver. An internal switch between V and BST2 charges the flying capacitor while the low-
DD
side MOSFET is on (DL2 pulled high and LX2 pulled to ground).
Inductor Connection for Phase 2. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to the controller’s zero-crossing comparator for phase 2.
High-Side Gate-Driver Output for Phase 2. DH2 swings from LX2 to BST2. The controller pulls DH2 low
in shutdown.
22
23
LX2
DH2
Low-Side Gate-Driver Output for Phase 2. DL2 swings from GND to V . DL2 is forced low in skip mode
DD
24
25
DL2
after detecting an inductor current zero crossing. DL2 is forced low during one-phase operation (PSI =
GND or CSP2 = V ).
CC
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
VRHOT
1.5V (30% of V ). VRHOT is high impedance in shutdown.
CC
Driver Supply Voltage Input. V is the supply voltage used to internally power the low-side gate
DD
drivers and refresh the BST_ flying capacitors during the off-times. Connect V to the 4.5V to 5.5V
system supply voltage. Bypass V to the system power ground with a 1μF each or greater ceramic
DD
capacitor.
DD
26
27
V
DD
Low-Side Gate-Driver Output for Phase 1. DL1 swings from GND to V . DL1 is forced high when an output
DD
DL1
overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is
forced low after soft-shutdown or in skip mode after detecting an inductor current zero crossing.
High-Side Gate-Driver Output for Phase 1. DH1 swings from LX1 to BST1. The controller pulls DH1 low
in shutdown.
Inductor Connection for Phase 1. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to the controller’s zero-crossing comparator for phase 1.
Boost Flying-Capacitor Connection for Phase 1. BST1 provides the upper supply rail for the DH1 high-
28
29
DH1
LX1
30
BST1
side gate driver. An internal switch between V and BST1 charges the flying capacitor while the low-
DD
side MOSFET is on (DL1 is pulled high and LX1 is pulled to ground).
IMVP-6+ Slew-Rate Select Input. This 1.0V logic input signal from the IMVP-6+ system is usually the
logical complement of the DPRSLPVR signal. However, the IMVP-6+ specification supports a special
slow C4 exit condition that allows both DPRSTP and DPRSLPVR to be pulled high simultaneously.
When this occurs, the voltage-transition slew rate reduces to 1/4 the nominal (R
-based) slew rate
TIME
for the duration of this logic condition. The slew rate returns to normal when either DPRSLPVR or
DPRSTP is pulled low:
DPRSTP
(MAX17021)
DPRSLPVR DPRSTP
SLEW RATE
31
0
0
1
1
0
1
0
1
Nominal slew rate
Nominal slew rate
Nominal slew rate
Slew rate reduced to 1/4 of nominal
IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and “slow”
(half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is set by
the TIME resistance as defined above. When SLOW is forced low, the slew rate is reduced to half the
nominal slew rate.
SLOW
(MAX17082/
MAX17482)
______________________________________________________________________________________ 17
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Low-Voltage VID DAC Code Input. The D0–D6 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. The output voltage is set by the VID code
indicated by the logic-level voltages on D0–D6 (see Table 4).
32–38
D0–D6
Positive Current-Sense Input for Phase 1. Connect CSP1 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4).
Negative Current-Sense Input for Phase 1. Connect CSN1 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
Under V UVLO conditions and after soft-shutdown is completed, CSN1 is internally pulled to GND
CC
through a 10ꢀ FET to discharge the output.
Exposed Pad. Internally connected to GND. Connect to the ground plane through a thermally
enhanced via. For the MAX17021/MAX17082/MAX17482, the exposed pad is the only GND
connection and must be properly soldered.
39
40
—
CSP1
CSN1
EP
0/MAX17482
18 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
R19
10Ω
13
31
14
15
1
6
5V BIAS
INPUT
ON OFF (VRON)
SHDN
V
CC
DD
C1
DPRSTP
DPRSLPVR
PSI
1.0μF
C2
1.0μF
AGND
26
V
PWR
PGDIN
R
SWITCHING FREQUENCY (f = 1/T ):
TON
SW
SW
32
33
34
35
36
37
38
200kΩ
T
= 16.3pF x (R
+ 6.5kΩ)
SW
TON
D0
D1
D2
D3
D4
D5
D6
16
INPUT
7V TO 24V
TON
R9
C
IN
0Ω
30
28
BST1
DH1
VID INPUTS
PWR
N
HI
C4
0.22μF
L1
29
27
LX1
DL1
R10
1.21kΩ
R11
1.50kΩ
R12
20kΩ
C
OUT
D1
VALLEY CURRENT LIMIT SET TO ILIM
N
LO
V
= 0.2V x R1/(R1 + R2)
LIMIT
SLEW RATE SET BY TIME BIAS CURRENT
dV/dt = 12.5mV/μs x 71.5kΩ/(R1 + R2)
MAX17021
PWR
PWR
39
40
NTC1
10kΩ
CSP1
CSN1
C7
0.22μF
C5
0.22μF
4
5
ILIM
B = 3380
R2
R1
59.0kΩ
12.1kΩ
C6
OPEN
DCR THERMAL
COMPENSATION
7
CORE
OUTPUT
TIME
CCI
CSN2
CSP2
AGND
C10
1000pF
AGND
11
12
C9
C11
0.22μF
17
NTC2
3.3V
1.1V
V3P3
0.22μF
10kΩ
B = 3380
C12
OPEN
AGND
R15
1.50kΩ
R4
1.9kΩ
R5
10kΩ
R3
56Ω
C
OUT
R13
0Ω
20
19
25
18
PHASEGD
PWRGD
VRHOT
R16
20kΩ
21
23
BST2
DH2
R14
1.21kΩ
PWR
N
HI
C8
0.22μF
L2
22
24
LX2
DL2
CLKEN
R6
13kΩ
D1
2
N
LO
V
CC
THRM
NTC3
PWR
100kΩ
LOAD-LINE ADJUSTMENT:
B = 4250
R
FB
= R
/(R
x 600μs)
DROOP SENSE
AGND
3
R
R22
25Ω
FB
9
8
4.32kΩ
R20
FBAC
FB
1%
10Ω
N.C.
VCC_SENSE
C13
REMOTE-SENSE
INPUTS
1000pF
10
R21
10Ω
GNDS
AGND
VSS_SENSE
GND (EP)
C14
1000pF
R23
CATCH RESISTORS
REQUIRED WHEN CPU NOT
POPULATED
AGND
25Ω
AGND
PWR
REMOTE-SENSE FILTERS
PWR
Figure 1. Standard 2-Phase IMVP-6+ Application Circuit
______________________________________________________________________________________ 19
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
simple: the high-side switch on-time is determined sole-
Detailed Description
ly by a one-shot whose period is inversely proportional
Table 1 lists the component selection for standard
to input voltage, and directly proportional to output volt-
applications. Table 2 lists component suppliers for the
MAX17021/MAX17082/MAX17482/MAX17482.
age or the difference between the main and secondary
inductor currents (see the On-Time One-Shot section).
Another one-shot sets a minimum off-time. The on-time
Free-Running, Constant-On-Time PWM
one-shot triggers when the error comparator goes low,
Controller with Input Feed-Forward
the inductor current of the selected phase is below the
The Quick-PWM control architecture is a pseudo-fixed-
valley current-limit threshold, and the minimum off-time
frequency, constant-on-time, current-mode regulator
one-shot times out. The controller maintains 180° out-of-
with voltage feed-forward (Figure 3). This architecture
phase operation by alternately triggering the main and
relies on the output filter capacitor’s ESR to act as the
secondary phases after the error comparator drops
current-sense resistor, so the output ripple voltage pro-
below the output-voltage set point.
vides the PWM ramp signal. The control algorithm is
Table 1. Component Selection for Standard Applications
IMVP-6.5
AUBURNDALE SV
CORE
IMVP-6.5
AUBURNDALE LV
CORE
DESIGN
PARAMETERS
IMVP-6+ SV
IMVP-6+ LV
CIRCUIT
FIGURE 1
FIGURE 1
FIGURE 2
FIGURE 2
Input-Voltage Range
7V to 20V
7V to 20V
7V to 20V
7V to 20V
Maximum Load Current
(TDC Current)
44A
(34A)
23A
(19A)
50A
(37A)
28A
(19A)
35A
(10A/μs)
18A
(10A/μs)
35A
(10A/μs)
23A
(10A/μs)
Transient Load Current
Load Line
-2.1mV/A
-4mV/A
-1.9mV/A
-3mV/A
COMPONENTS
TON Resistance (R
)
200kꢀ (f
= 300kHz)
200kꢀ (f
= 300kHz)
200kꢀ (f
= 300kHz)
200kꢀ (f
= 300kHz)
SW
TON
SW
SW
SW
NEC/TOKIN
NEC/TOKIN
NEC/TOKIN
NEC/TOKIN
0/MAX17482
Inductance (L)
MPC1055LR36 0.36μH, MPC1055LR36 0.36μH, MPC1055LR36 0.36μH, MPC1055LR36 0.36μH,
32A, 0.8mꢀ
32A, 0.8mꢀ
32A, 0.8mꢀ
32A, 0.8mꢀ
Siliconix 1x Si4386DY Siliconix 1x Si4386DY Siliconix 1x Si4386DY
7.8m /9.5mꢀ (typ/max) 7.8m /9.5mꢀ (typ/max) 7.8m /9.5mꢀ (typ/max)
Siliconix 1x Si4386DY
7.8m /9.5mꢀ (typ/max)
High-Side MOSFET (N )
H
Siliconix 2x Si4642DY Siliconix 2x Si4642DY Siliconix 2x Si4642DY
3.9m /4.7mꢀ (typ/max) 3.9m /4.7mꢀ (typ/max) 3.9m /4.7mꢀ (typ/max)
Siliconix 2x Si4642DY
3.9m /4.7mꢀ (typ/max)
Low-Side MOSFET (N )
L
4x 330μF, 6mꢀ, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
3x 330μF, 6mꢀ, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
4x 330μF, 6mꢀ, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
3x 330μF, 6mꢀ, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
Output Capacitors
(C
)
OUT
4x 10μF, 25V ceramic
(1210)
4x 10μF, 25V ceramic
(1210)
4x 10μF, 25V ceramic
(1210)
4x 10μF, 25V ceramic
(1210)
Input Capacitors (C
)
IN
20 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Table 1. Component Selection for Standard Applications (continued)
IMVP-6.5
AUBURNDALE SV
CORE
IMVP-6.5
AUBURNDALE LV
CORE
DESIGN
PARAMETERS
IMVP-6+ SV
IMVP-6+ LV
TIME-ILIM Resistance
(R1)
10kꢀ
59kꢀ
10kꢀ
59kꢀ
10kꢀ
59kꢀ
10kꢀ
59kꢀ
ILIM-GND Resistance
(R2)
FB Resistance (R
IMON Resistance
)
4.32kꢀ
N/A
8.45kꢀ
N/A
4.02kꢀ
9.09kꢀ
1.21kꢀ
6.34kꢀ
18.2kꢀ
1.21kꢀ
FB
LX_-CSP_ Resistance
1.21kꢀ
1.21kꢀ
CSP_-CSN_ Series
Resistance (R6)
1.50kꢀ
20kꢀ
1.50kꢀ
20kꢀ
1.50kꢀ
20kꢀ
1.50kꢀ
20kꢀ
Parallel NTC
Resistance
10kꢀ NTC B = 3380
TDK NTCG163JH103F
10kꢀ NTC B = 3380
TDK NTCG163JH103F
10kꢀ NTC B = 3380
TDK NTCG163JH103F
10kꢀ NTC B = 3380
TDK NTCG163JH103F
DCR Sense NTC (NTC1)
DCR Sense
Capacitance (C
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
)
SENSE
Table 2. Component Suppliers
SUPPLIER
WEBSITE
SUPPLIER
WEBSITE
Pulse Engineering
www.pulseeng.com
AVX Corp.
www.avxcorp.com
BI Technologies
www.bitechnologies.com
Renesas Technology
Corp.
www.renesas.com
Central
Semiconductor Corp.
www.centralsemi.com
www.fairchildsemi.com
SANYO Electric Co,
Ltd.
www.sanyodevice.com
Fairchild
Semiconductor
Siliconix (Vishay)
Sumida
www.vishay.com
www.sumida.com
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
International Rectifier
KEMET Corp
www.irf.com
Taiyo Yuden
TDK Corp.
www.kemet.com
www.nec-tokin.com
www.panasonic.com
NEC/TOKIN Corp.
Panasonic Corp.
TOKO America, Inc.
______________________________________________________________________________________ 21
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
R19
10Ω
6
13
14
31
5V BIAS
INPUT
ON OFF (VRON)
SHDN
V
CC
DD
C1
DPRSLPVR
SLOW
1.0μF
C2
1.0μF
AGND
26
AGND
15
1
V
PSI
PWR
PGDIN
R
SWITCHING FREQUENCY (f = 1/T ):
TON
SW
SW
32
33
34
35
36
37
38
200kΩ
T
= 16.3pF x (R
+ 6.5kΩ)
SW
TON
D0
D1
D2
D3
D4
D5
D6
16
INPUT
7V TO 24V
TON
R9
C
IN
0Ω
30
28
BST1
DH1
VID INPUTS
PWR
N
HI
C4
0.22μF
L1
29
27
LX1
DL1
R10
1.21kΩ
R11
1.50kΩ
R12
20kΩ
C
OUT
D1
VALLEY CURRENT LIMIT SET TO ILIM
N
LO
V
= 0.2V x R1/(R1 + R2)
LIMIT
SLEW RATE SET BY TIME BIAS CURRENT
MAX17082
MAX17482
dV/dt = 12.5mV/μs x 71.5kΩ/(R1 + R2)
PWR
PWR
39
40
4
5
NTC1
10kΩ
CSP1
CSN1
ILIM
C7
0.22μF
C5
0.22μF
R2
59.0kΩ
R1
12.1kΩ
B = 3380
TIME
C6
OPEN
DCR THERMAL
COMPENSATION
7
CORE
OUTPUT
AGND
CCI
CSN2
CSP2
AGND
C10
1000pF
11
12
17
3.3V
1.1V
V3P3
C9
C11
0.22μF
NTC2
0.22μF
10kΩ
B = 3380
R4
1.9kΩ
R5
10kΩ
C12
OPEN
AGND
R3
56Ω
R15
1.50kΩ
C
OUT
20
19
25
18
R13
0Ω
PHASEGD
PWRGD
VRHOT
R16
20kΩ
21
23
BST2
DH2
R14
1.21kΩ
PWR
0/MAX17482
N
HI
C8
0.22μF
L2
22
24
CLKEN
LX2
DL2
R6
13kΩ
2
V
CC
THRM
D1
N
LO
NTC3
100kΩ
B = 4250
PWR
LOAD-LINE ADJUSTMENT:
AGND
3
R
= R
/(R
x 600μs)
FB
DROOP SENSE
R7
4.7kΩ
R
R22
25Ω
FB
9
8
4.02kΩ
R20
10Ω
IMON
FBAC
FB
1%
VCC_SENSE
C15
0.022μF
R8
9.09kΩ
C13
1000pF
REMOTE-SENSE
INPUTS
10
R21
GNDS
AGND
10Ω
VSS_SENSE
VSS_SENSE
GND (EP)
C14
1000pF
R23
CATCH RESISTORS
REQUIRED WHEN CPU NOT
POPULATED
AGND
25Ω
AGND
PWR
REMOTE-SENSE FILTERS
PWR
Figure 2. Standard 2-Phase IMVP-6.5 (Calpella) Application Circuit
22 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
BST2
DH2
LX2
THRM
MAX17021
(MAX17082/MAX17482)
VRHOT
EN2
SECONDARY
PHASE DRIVERS
DL2
GND
0.3 x V
CC
BLANK
CSP2
CSN2
PHASEGD
CCI
10x
5ms
STARTUP
DELAY
CURRENT-
BALANCE
FAULT
TRIG
Q
CSP1
CSN1
ONE-SHOT
PHASE 2
ON-TIME
10x
MINIMUM
OFF-TIME
200kΩ
ILIM
CSN2
TRIG
Q
TIME
CSP2
CSP1
CSN1
ONE-SHOT
G
(CCI)
(CCI)
m
m
PHASE 1
ON-TIME
V
CC
FB
ONE-SHOT
TRIG
G
REF
(2.0V)
Q
TON
GND
D0–D6
BST1
DH1
LX1
MAIN PHASE
DRIVERS
SLEW
R
S
R-TO-I
CONVERTER
Q
DAC
PGDIN
SHDN
S
R
Q
Q
Q
GND
LX1
T
FAULT
1mV
V
DD
DL1
GND
TARGET
+ 200mV
TARGET
- 300mV
PWRGD
5ms
STARTUP
DELAY
FB
GNDS
V3P3
60μs
STARTUP
DELAY
CLKEN
MODE/PHASE/
SLEW-RATE
CONTROL
BLANK
(MAX17082/
MAX17482)
CSP_
CSN_
CSP_
CSN_
x2
x2
FBAC
IMON
G
G
m(IMON)
m(FB)
Figure 3. Functional Diagram
______________________________________________________________________________________ 23
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Dual 180° Out-of-Phase Operation
The two phases in the MAX17021/MAX17082/
MAX17482 operate 180° out-of-phase to minimize input
and output filtering requirements, reduce electromagnetic
interference (EMI), and improve efficiency. This effectively
lowers component count—reducing cost, board space,
and component power requirements—making the
MAX17021/MAX17082/MAX17482 ideal for high-power,
cost-sensitive applications.
enable signal (SHDN going from low to high) must be
delayed until the battery voltage is present to ensure
startup.
Switching Frequency (TON)
Connect a resistor (R
) between TON and V to set
IN
= 1/f , per phase:
SW
TON
the switching period T
SW
T
SW
= 16.3pF x (R
+ 6.5kΩ)
TON
A 96.75kΩ to 303.25kΩ corresponds to switching peri-
ods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the appli-
cation for the smallest component size, trading off effi-
ciency due to higher switching losses. This might be
acceptable in ultra-portable devices where the load
currents are lower and the controller is powered from a
lower voltage supply. Low-frequency (200kHz) opera-
tion offers the best overall efficiency at the expense of
component size and board space.
Typically, switching regulators provide power using
only one phase instead of dividing the power among
several phases. In these applications, the input capaci-
tors must support high instantaneous current require-
ments. The high RMS ripple current can lower
efficiency due to I2R power loss associated with the
input capacitor’s effective series resistance (ESR).
Therefore, the system typically requires several low-
ESR input capacitors in parallel to minimize input-volt-
age ripple, to reduce ESR-related power losses, and to
meet the necessary RMS ripple current rating.
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an over-
voltage condition on the output. The MAX17021/
MAX17082/MAX17482 detect an open-circuit fault if the
TON current drops below 10μA for any reason—the
With the MAX17021/MAX17082/MAX17482, the con-
troller shares the current between two phases that
operate 180° out-of-phase, so the high-side MOSFETs
never turn on simultaneously during normal operation.
The instantaneous input current of either phase is effec-
tively halved, resulting in reduced input-voltage ripple,
ESR power loss, and RMS ripple current (see the Input
Capacitor Selection section). Therefore, the same per-
formance can be achieved with fewer or less-expensive
input capacitors.
TON resistor (R
) is unpopulated, a high resistance
TON
value is used, the input voltage is low, etc. Under these
conditions, the MAX17021/MAX17082/MAX17482 stop
switching (DH_ and DL_ pulled low) and immediately
set the fault latch. Toggle SHDN or cycle the V
CC
power supply below 0.5V to clear the fault latch and
reactivate the controller.
+5V Bias Supply (V
and V )
DD
CC
0/MAX17482
The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
system supply. Keeping the bias supply external to the
IC improves efficiency and eliminates the cost associat-
ed with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
On-Time One-Shot
The core of each phase contains a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. The one-shot for the main phase varies the on-
time in response to the input and feedback voltages.
The main high-side switch on-time is inversely propor-
tional to the input voltage as measured by the TON
input, and proportional to the feedback voltage (V ):
FB
T
V
+ 0.075V
The +5V bias supply must provide V
(PWM con-
(
)
CC
SW FB
t
=
ON(MAIN)
troller) and V
(gate-drive power), so the maximum
DD
V
IN
current drawn is:
I
= I
+ f
(Q
+ Q
)
BIAS
CC
SW
G(LOW)
G(HIGH)
where the switching period (T = 1/f ) is set by the
SW SW
resistor at the TON pin, and 0.075V is an approximation
to accommodate the expected drop across the low-
side MOSFET switch.
where I
is provided in the Electrical Characteristics
CC
SW
table, f
is the switching frequency, and Q
and
G(LOW)
Q
are the MOSFET data sheet’s total gate-
G(HIGH)
charge specification limits at V = 5V.
GS
The one-shot for the secondary phase varies the on-
time in response to the input voltage and the difference
between the main and secondary inductor currents.
Two identical transconductance amplifiers integrate the
V
and V
can be tied together if the input power
DD
IN
source is a fixed +4.5V to +5.5V supply. If the +5V bias
supply is powered-up prior to the battery supply, the
24 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
difference between the master and slave current-sense
signals. The summed output is internally connected to
CCI, allowing adjustment of the integration time con-
stant with a compensation network connected between
CCI and FB. The resulting compensation current and
voltage are determined by the following equations:
tor current reverses at light- or negative-load currents.
With reversed inductor current, the inductor’s EMF
causes LX_ to go high earlier than normal, extending
the on-time by a period equal to the DH_-rising dead
time. For loads above the critical conduction point,
where the dead-time effect is no longer a factor, the
actual switching frequency (per phase) is:
I
= G (V
- V
) - G (V
- V
)
CSN2
CCI
m
CSP1
CSN1
m
CSP2
V
= V + I Z
CCI CCI
V
+ V
DIS
CCI
FB
(
)
OUT
f
=
SW
where Z
is the impedance at the CCI output. The
secondary on-time one-shot uses this integrated signal
(V ) to set the secondary high-side MOSFETs on-
t
V
+ V
- V
CCI
(
)
ON IN
DIS CHG
CCI
where V
is the sum of the parasitic voltage drops in the
inductor discharge path, including synchronous rectifier,
inductor, and PCB resistances; V is the sum of the
DIS
time. When the main and secondary current-sense sig-
nals (V = V - V and V = V - V
)
CSN2
CM
CSP1
CSN1
CS
CSP2
CHG
become unbalanced, the transconductance amplifiers
adjust the secondary on-time, which increases or
decreases the secondary inductor current until the cur-
rent-sense signals are properly balanced:
parasitic voltage drops in the inductor charge path,
including high-side switch, inductor, and PCB resis-
tances; and t
is the on-time as determined above.
ON
Current Sense
The output current of each phase is sensed. Low-offset
amplifiers are used for current balance, voltage-posi-
tioning gain, and current limit. Sensing the current at
the output of each phase offers advantages, including
less noise sensitivity, more accurate current sharing
between phases, and the flexibility of using either a cur-
rent-sense resistor or the DC resistance of the output
inductor.
⎛
⎝
⎞
⎠
V
+ 0.075V
CCI
t
= T
SW
ON(SEC)
⎜
⎟
V
IN
⎛
⎞
⎠
⎛
⎝
⎞
⎠
V
+ 0.075V
I
Z
FB
CCI CCI
= T
SW
+ T
SW
⎜
⎟
⎜
⎟
V
V
⎝
IN
IN
= Main On-time + Secondary Current Balance Correction
(
)
(
)
This algorithm results in a nearly constant switching fre-
quency and balanced inductor currents despite the
lack of a fixed-frequency clock generator. The benefits
of a constant switching frequency are twofold: first, the
frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band; second, the
inductor ripple-current operating point remains relative-
ly constant, resulting in easy design methodology and
predictable output-voltage ripple. The on-time one-
shots have good accuracy at the operating points
specified in the Electrical Characteristics table. On-
times at operating points far removed from the condi-
tions specified in the Electrical Characteristics table
can vary over a wider range.
Using the DC resistance (R
) of the output inductor
DCR
allows higher efficiency. In this configuration, the initial
tolerance and temperature coefficient of the inductor’s
DCR must be accounted for in the output-voltage
droop-error budget and power monitor. This current-
sense method uses an RC filtering network to extract
the current information from the output inductor (see
Figure 4). The resistive divider used should provide a
current-sense resistance (R ) low enough to meet the
CS
current-limit requirements, and the time constant of the
RC network should match the inductor’s time constant
(L/R ):
CS
R2
R1+ R2
⎛
⎞
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the Electrical
Characteristics table are influenced by switching
delays in the external high-side MOSFET. Resistive
losses, including the inductor, both MOSFETs, output
capacitor ESR, and PCB copper losses in the output
and ground tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only during forced-PWM operation
and dynamic output-voltage transitions when the induc-
R
=
R
DCR
⎜
⎝
⎟
⎠
CS
and:
L
1
1
⎡
⎤
R
=
+
CS
⎢
⎣
⎥
⎦
C
R1 R2
EQ
where R is the required current-sense resistance and
CS
R
DCR
is the inductor’s series DC resistance.
______________________________________________________________________________________ 25
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Use the worst-case inductance and R
values pro-
resistor (see Figure 4). The ESL induced-voltage step
does not affect the average current-sense voltage, but
results in a significant peak current-sense voltage error
that results in unwanted offsets in the regulation voltage
and results in early current-limit detection. Similar to the
inductor DCR sensing method above, the RC filter’s time
constant should match the L/R time constant formed by
the current-sense resistor’s parasitic inductance:
DCR
vided by the inductor manufacturer, adding some mar-
gin for the inductance drop over temperature and load.
To minimize the current-sense error due to the current-
sense inputs’ bias current (I
_ and I
_), choose
CSN
CSP
R1||R2 to be less than 2kΩ and use the previous equa-
tion to determine the sense capacitance (C ). Choose
EQ
capacitors with 5% tolerance and resistors with 1% tol-
erance specifications. Temperature compensation is
recommended for this current-sense method. See the
Voltage Positioning and Loop Compensation section for
detailed information.
L
ESL
= C R1
EQ
R
SENSE
When using a current-sense resistor for accurate output-
voltage positioning, the circuit requires a differential RC
filter to eliminate the AC voltage step caused by the
where L
is the equivalent series inductance of the
ESL
current-sense resistor, R
is current-sense resis-
SENSE
tance value, and C
matching components.
and R1 are the time-constant
EQ
equivalent series inductance (L ) of the current-sense
ESL
INPUT (V
)
IN
C
IN
N
H
DH_
SENSE RESISTOR
LX_
L
R
SENSE
L
ESL
MAX17021
MAX17082
MAX17482
L
C
DL_
SENSE
D
OUT
L
C
R1 =
N
EQ
L
R
SENSE
PGND
R1
C
EQ
CSP_
CSN_
0/MAX17482
A) OUTPUT SERIES RESISTOR SENSING
INPUT (V
)
IN
C
IN
N
H
DH_
LX_
INDUCTOR
R
L
DCR
R2
R
=
=
R
DCR
CS
( R1 + R2 )
MAX17021
MAX17082
MAX17482
C
OUT
DL_
D
L
N
R1
R2
L
L
1
1
+
R
DCR
C
R1 R2
[ ]
EQ
PGND
C
EQ
CSP_
CSN_
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR.
B) LOSSLESS INDUCTOR SENSING
Figure 4. Current-Sense Methods
26 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Current Balance
The MAX17021/MAX17082/MAX17482 integrate the dif-
ference between the current-sense voltages and adjust
the on-time of the secondary phase to maintain current
balance. The current balance now relies on the accura-
cy of the current-sense resistors instead of the inaccu-
rate, thermally sensitive on-resistance of the low-side
MOSFETs. With active current balancing, the current mis-
match is determined by the current-sense resistor values
and the offset voltage of the transconductance amplifiers:
cuit, this current-limit method is effective in almost
every circumstance.
The positive valley current-limit threshold voltage at
CSP_ to CSN_ equals precisely 1/10 of the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
V
to set the default current-limit threshold setting of
CC
22.5mV (typ).
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immedi-
ately activates an on-time pulse—DL_ turns off, and
DH_ turns on—allowing the inductor current to remain
above the negative-current threshold.
V
OS(IBAL)
I
= I
-I
=
OS(IBAL) LMAIN LSEC
R
SENSE
where R
is the effective sense resistance seen at
SENSE
the current-sense pins and V
is the current-bal-
OS(IBAL)
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP_, CSN_).
ance offset specification in the Electrical
Characteristics table.
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop)
The MAX17021/MAX17082/MAX17482 include a
transconductance amplifier for adding gain to the volt-
age-positioning sense path. The amplifier’s input is gen-
erated by summing the current-sense inputs, which
differentially sense the voltage across either current-
sense resistors or the inductor’s DCR. The amplifier’s
output connects directly to the regulator’s voltage-posi-
tioned feedback input (FB), so the resistance between
FB and the output-voltage sense point determines the
voltage-positioning gain:
Current Limit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses current-sense resistors
between the current-sense inputs (CSP_ to CSN_) as
the current-sensing elements. If the current-sense sig-
nal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
either phase trips the current limit, both phases are
effectively current limited since the interleaved con-
troller does not initiate a cycle with either phase.
V
OUT
= V
- R |
FB FB
TARGET
where the target voltage (V
) is defined in the
TARGET
Nominal Output-Voltage Selection section, and the FB
amplifier’s output current (I ) is determined by the
FB
sum of the current-sense voltages:
Since only the valley current is actively limited, the actu-
al peak current is greater than the current-limit thresh-
old by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the current-
sense resistance, inductor value, and battery voltage.
When combined with the undervoltage-protection cir-
η
I
= G
PH V
∑
FB
m(FB)
CSX
X=1
where V
= V
- V
is the differential current-
CSN_
m(FB)
CS
CSP_
sense voltage, and G
is typically 600μS as
defined in the Electrical Characteristics table.
______________________________________________________________________________________ 27
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Differential Remote Sense
The MAX17021/MAX17082/MAX17482 include differen-
tial, remote-sense inputs to eliminate the effects of volt-
age drops along the PCB traces and through the
processor’s power pins. The feedback-sense node con-
the response time. After either high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the con-
troller simultaneously turns on both high-side MOSFETs
during the next on-time cycle. This maximizes the total
inductor current slew rate. The phases remain over-
lapped until the output voltage exceeds the regulation
voltage after the minimum off-time expires.
nects to the voltage-positioning resistor (R ). The
FB
ground-sense (GNDS) input connects to an amplifier
that adds an offset directly to the target voltage, effec-
tively adjusting the output voltage to counteract the volt-
age drop in the ground path. Connect the
voltage-positioning resistor (R ), and ground-sense
FB
(GNDS) input directly to the processor’s remote-sense
outputs, as shown in Figure 1.
After the phase-overlap mode ends, the controller automat-
ically begins with the opposite phase. For example, if the
secondary phase provided the last on-time pulse before
overlap operation began, the controller starts switching
with the main phase when overlap operation ends. Table 3
is the operating mode truth table.
Integrator Amplifier
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This transconduc-
tance amplifier integrates the feedback voltage and pro-
vides a fine adjustment to the regulation voltage (Figure
3), allowing accurate DC output-voltage regulation
regardless of the output ripple voltage. The integrator
amplifier has the ability to shift the output voltage by
100mV (typ). The differential input-voltage range is at
least 60mV total, including DC offset and AC ripple.
Nominal Output-Voltage Selection
The nominal no-load output voltage (V
) is
TARGET
defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (V
defined in the following equation:
) as
GNDS
V
= V = V
+ V
DAC GNDS
TARGET
FB
where V
is the selected VID voltage. On startup, the
DAC
MAX17021/MAX17082/MAX17482 slew the target volt-
age from ground to the preset boot voltage.
The MAX17021/MAX17082/MAX17482 disable the inte-
grator by connecting the amplifier inputs together at the
beginning of all VID transitions done in pulse-skipping
mode (DPRSLPVR = high). The integrator remains dis-
abled until 20μs after the transition is completed (the
internal target settles) and the output is in regulation
(edge detected on the error comparator).
DAC Inputs (D0–D6)
The digital-to-analog converter (DAC) programs the
output voltage using the D0–D6 inputs. D0–D6 are low-
voltage (1.0V) logic inputs, designed to interface direct-
ly with the CPU. Do not leave D0–D6 unconnected.
Changing D0–D6 initiates a transition to a new output-
voltage level. Change D0–D6 together, avoiding greater
than 20ns skew between bits. Otherwise, incorrect DAC
readings might cause a partial transition to the wrong
voltage level followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. The available DAC codes and resulting output
voltages are compatible with the IMVP-6/IMVP-6+ and
IMVP-6.5 (Table 4) specifications.
0/MAX17482
Transient-Overlap Operation
When a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 180° out-of-
phase when a transient occurs actually respond slower
than an equivalent single-phase controller. To provide
fast-transient response, the MAX17021/MAX17082/
MAX17482 support a phase-overlap mode, which
allows the dual regulators to operate in-phase when
heavy load transients are detected, effectively reducing
28 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Table 3. Operating Mode Truth Table
INPUTS
PHASE
OPERATING MODE
DPRSTP
OPERATION*
SHDN
DPRSLPVR
PSI
(SLOW)
Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1μA (max).
GND
X
X
X
X
Disabled
Multiphase
pulse-skipping
Startup/Boot. When SHDN is pulled high, the MAX17021/
MAX17082/MAX17482 begin the startup sequence. The controller
enables the PWM regulator and ramps the output voltage up to the
boot voltage. See Figure 10.
Rising
High
X
X
1/8 R
slew
TIME
rate
Multiphase
forced-PWM
nominal R
TIME
X
Full Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4).
Low
Low
High
Low
(High)
slew rate
1-phase forced- Intermediate Power. The no-load output voltage is determined by
X
PWM
the selected VID DAC code (D0–D6, Table 4). When PSI is pulled
low, the MAX17021/MAX17082/MAX17482 immediately disable
phase 2. DH2 and DL2 are pulled low.
High
(High)
nominal R
TIME
slew rate
Deeper Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (D0–D6, Table 4). When
DPRSLPVR is pulled high, the MAX17021/MAX17082/MAX17482
immediately enter one-phase pulse-skipping operation, allowing
automatic PWM/PFM switchover under light loads. The PWRGD
and CLKEN upper thresholds are blanked during downward
transitions. DH2 and DL2 are pulled low.
1-phase pulse-
skipping
nominal R
TIME
Low
(High)
High
High
X
X
slew rate
Deeper Sleep Slow Exit Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSTP is pulled high while DPRSLPVR is already high,
the MAX17021 remains in one-phase pulse-skipping operation,
allowing automatic PWM/PFM switchover under light loads, but
reduces its slew rate to 1/4 of normal. When SLOW is pulled low,
the MAX17082/MAX17482 reduce their slew rate to 1/2 of normal.
The PWRGD and CLKEN upper thresholds are blanked. DH2 and
DL2 are pulled low.
High
(Low)
1-phase pulse-
skipping
High
High
Shutdown. When SHDN is pulled low, the MAX17021/MAX17082/
MAX17482 immediately pull PWRGD and PHASEGD low, CLKEN
becomes high, all enabled phases are activated, and the output
voltage is ramped down to ground. Once the output reaches 0V,
the controller enters the low-power shutdown state. See Figure 10.
Multiphase
forced-PWM
Falling
High
X
X
X
X
X
X
1/8 R
slew
TIME
rate
Fault Mode. The fault latch has been set by the MAX17021/
MAX17082/MAX17482 UVP or thermal-shutdown protection, or by the
Disabled
OVPprotection. The controller remains in fault mode until V
power
CC
is cycled or SHDN toggled.
*Multiphase operation—all enabled phases active.
______________________________________________________________________________________ 29
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Table 4. IMVP-6+/IMVP-6.5 Output-Voltage VID DAC Codes
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1125
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
0.3625
0.3500
0.3375
0.3250
0.3125
0.3125
0/MAX17482
30 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
Table 4. IMVP-6+/IMVP-6.5 Output-Voltage VID DAC Codes (continued)
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3000
0.2875
0.2750
0.2625
0.2500
0.2375
0.2250
0.2125
0.2000
0.1875
0.1750
0.1625
0.1500
0.1375
0.1250
0.1125
0.1000
0.0875
0.0750
0.0625
0.0500
0.0375
0.0250
0.0125
0
0
0
0
0
0
0
0
*D6–D0 = 1111111 is an OFF code for the MAX17082/MAX17482. The MAX17082/MAX17482 enter the shutdown sequence if the
OFF code is set, forcing PWRGD and PHASEGD low, and forcing CLKEN high. Exit from the OFF code follows the startup sequence.
If the OFF code is present when SHDN is pulled high, the MAX17082/MAX17482 remain off.
______________________________________________________________________________________ 31
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17021/MAX17082/MAX17482 respond by slewing
the internal target voltage to the new DAC code, switch-
ing to single-phase operation, and letting the output
voltage gradually drift down to the deeper sleep volt-
age. During the transition, the MAX17021/MAX17082/
MAX17482 blank both the upper and lower PWRGD
and CLKEN thresholds until 20μs after the internal tar-
get reaches the deeper sleep voltage. Once the 20μs
timer expires, the MAX17021/MAX17082/MAX17482
reenable the lower PWRGD and CLKEN threshold, but
keep the upper threshold blanked until the output volt-
age reaches the regulation level. PHASEGD remains
blanked high impedance while DPRSLPVR is high.
dynamic VID transitions, the transition time (t
given by:
) is
TRAN
V
- V
OLD
NEW
t
=
TRAN
(dV
dt)
TARGET
where dV
/dt = 12.5mV/μs x 71.5kΩ/R
is the
TIME
TARGET
slew rate, V
is the original output voltage, and V
OLD
NEW
is the new target voltage. See TIME Slew Rate
Accuracy in Electrical Characteristics for slew-rate lim-
its. For soft-start and shutdown, the controller automati-
cally reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output-
voltage transition is:
C
OUT
Output-Voltage-Transition Timing
The MAX17021/MAX17082/MAX17482 perform mode
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output-volt-
age level with the lowest possible peak currents for a
given output capacitance.
I ≅
× dV
(
dt
)
L
TARGET
η
TOTAL
where dV
/dt is the required slew rate, C
the total output capacitance, and η
is
OUT
TARGET
is the number
TOTAL
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and enter
pulse-skipping operation (see Figures 5 and 6). If the
VIDs are set to a lower voltage setting, the output drops
at a rate determined by the load and the output capaci-
tance. The internal target still ramps as before, and
PWRGD remains blanked high impedance until 20μs
after the output voltage reaches the internal target.
At the beginning of an output-voltage transition, the
MAX17021/MAX17082/MAX17482 blank both PWRGD
thresholds, preventing the PWRGD open-drain output
from changing states during the transition. The con-
troller enables the lower PWRGD threshold approxi-
mately 20μs after the slew-rate controller reaches the
target output voltage, but the upper PWRGD threshold
remains blanked until the output voltage reaches the
regulation level if the controller enters pulse-skipping
0/MAX17482
operation. The slew rate (set by resistor R ) must be
TIME
•
Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX17021/MAX17082/MAX17482 quickly slew
set fast enough to ensure that the transition can be
completed within the maximum allotted time.
The MAX17021/MAX17082/MAX17482 automatically
control the current to the minimum level required to
complete the transition in the calculated time. The slew-
rate controller uses an internal capacitor and current
(50mV/μs min regardless of R
setting) the inter-
TIME
nal target voltage to the DAC code provided by the
processor as long as the output voltage is above the
new target. The controller remains in skip mode until
the output voltage equals the internal target. Once
the internal target reaches the output voltage, phase
2 is enabled. The controller blanks PWRGD,
PHASEGD, and CLKEN until 20μs after the transition
is completed. See Figure 5.
source programmed by R
to transition the output
TIME
voltage. The total transition time depends on R
, the
TIME
voltage difference, and the accuracy of the slew-rate
controller (C accuracy). The slew rate is not
SLEW
dependent on the total output capacitance, as long as
the surge current is less than the current limit. For all
32 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
•
Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the out-
put voltage is regulating to the deeper sleep
voltage, the MAX17021/MAX17082/MAX17482
immediately activate all enabled phases and ramp
the output voltage to the LFM DAC code provided
•
IMVP-6+ Slow C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR high, DPRSTP pulled
high) while the output voltage is regulating to the
deeper sleep voltage, the MAX17021 remains in 1-
phase skip mode and ramps the output voltage to
the LFM DAC code provided by the processor at 1/4
by the processor at the slew rate set by R
. The
the slew rate set by R
. The controller blanks
TIME
TIME
controller blanks PWRGD, PHASEGD, and CLKEN
until 20μs after the transition is completed. See
Figure 6.
PWRGD, PHASEGD, and CLKEN until 20μs after the
transition is completed. See Figure 7.
ACTUAL V
OUT
CPU CORE
VOLTAGE
INTERNAL TARGET
DEEPER SLEEP VID
VID (D0–D6)
DPRSLPVR
DPRSTP
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
FORCED PWM
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: V
> V
TARGET
DH1
DH2
OUT
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK LOW
PWRGD
CLKEN
PHASEGD
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
SET TO DEFAULT
TRACKS INTERNAL TARGET
OVP
(MAX17021/
MAX17082 ONLY)
t
t
BLANK
BLANK
20μs TYP
20μs TYP
Figure 5. C4E (C4 Early Exit) Transition
______________________________________________________________________________________ 33
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ACTIVE VID
CPU CORE
VOLTAGE
ACTUAL V
OUT
LFM VID
INTERNAL
TARGET
DPRSLP VID
VID (D0–D6)
DPRSLPVR
LFM VID
DEEPER SLEEP VID
DPRSTP
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
1-PHASE FORCED PWM
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: V
> V
TARGET
DH1
DH2
OUT
PWRGD
CLKEN
BLANK HIGH- IMPEDANCE
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
PHASEGD
SET TO DEFAULT
TRACKS INTERNAL TARGET
OVP
(MAX17021/
MAX17082 ONLY)
t
t
BLANK
BLANK
20μs TYP
20μs TYP
0/MAX17482
Figure 6. Standard C4 Transition
34 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
ACTIVE VID
SLOW SLEW RATE
CPU CORE
VOLTAGE
ACTUAL V
OUT
LFM VID
INTERNAL
TARGET
DPRSLP VID
VID (D0–D6)
DPRSLPVR
LFM VID
DEEPER SLEEP VID
SLOW SLEW RATE
DPRSTP
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
1-PHASE FORCED PWM
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: V
> V
TARGET
DH1
DH2
OUT
PWRGD
CLKEN
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
PHASEGD
SET TO DEFAULT
TRACKS INTERNAL TARGET
OVP
(MAX17021/
MAX17082 ONLY)
t
t
BLANK
BLANK
20μs TYP
20μs TYP
Figure 7. Slow C4 Transition
______________________________________________________________________________________ 35
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
CPU FREQ
CPU LOAD
VID (D0–D6)
CPU CORE
VOLTAGE
PSI
INTERNAL
PWM CONTROL
2-PHASE PWM
1-PHASE PWM
2-PHASE PWM
PWRGD
CLKEN
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH IMPEDANCE
PHASEGD
t
t
BLANK
BLANK
20μs typ
20μs typ
32 SWITCHING CYCLES ON DH2
0/MAX17482
Figure 8. PSI Transition
forms to constantly be the complement of the high-side
gate-drive waveforms. This keeps the switching fre-
quency constant and allows the inductor current to
reverse under light loads, providing fast, accurate neg-
ative output-voltage transitions by quickly discharging
the output capacitors.
PSI Transitions
When PSI is pulled low, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and
enter single-phase PWM operation (see Figure 8).
When PSI is pulled high, the MAX17021/MAX17082/
MAX17482 enable phase 2. PHASEGD is blanked high
impedance for 32 switching cycles on DH2, allowing
sufficient time/cycles for phases 1 and 2 to achieve cur-
rent balance. In a typical IMVP-6 application, the VID is
reduced by 1 LSB (12.5mV) when PSI is pulled low,
and increased by 1 LSB when PSI is pulled high.
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 50mA
per phase, depending on the external MOSFETs and
switching frequency. To maintain high efficiency under
light-load conditions, the processor can switch the con-
troller to a low-power pulse-skipping control scheme
after entering suspend mode.
Forced-PWM Operation (Normal Mode)
During soft-shutdown, and normal operation—when the
CPU is actively running (DPRSLPVR = low)—the
MAX17021/MAX17082/MAX17482 operate with the low-
noise, forced-PWM control scheme. Forced-PWM oper-
ation disables the zero-crossing comparators of all
active phases, forcing the low-side gate-drive wave-
PSI determines how many phases are active when
operating in forced-PWM mode (DPRSLPVR = low).
When PSI is pulled low, the main phase remains active
but the secondary phase is disabled (DH2 and DL2
forced low).
36 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
The switching waveforms might appear noisy and asyn-
chronous when light loading activates pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs between
PFM noise and light-load efficiency are made by vary-
ing the inductor value. Generally, low inductor values
produce a broader efficiency vs. load curve, while higher
values result in higher full-load efficiency (assuming that
the coil resistance remains fixed) and less output-voltage
ripple. Penalties for using higher inductor values include
larger physical size and degraded load-transient
response, especially at low input-voltage levels.
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
When DPRSLPVR is pulled high, the MAX17021/
MAX17082/MAX17482 operate with a single-phase
pulse-skipping mode. The pulse-skipping mode
enables the driver’s zero-crossing comparator, so the
controller pulls DL1 low when it detects zero inductor
current. This keeps the inductor from discharging the
output capacitors and forces the controller to skip puls-
es under light-load conditions to avoid overcharging
the output.
During downward transitions in pulse-skipping operation,
the controller temporarily sets the OVP threshold to
default, preventing false OVP faults when the transition to
pulse-skipping operation coincides with a VID code
change. Once the error amplifier detects that the output
voltage is in regulation, the OVP threshold tracks the
selected VID DAC code. The MAX17021/MAX17082/
MAX17482 automatically use forced-PWM operation dur-
ing soft-shutdown, regardless of the DPRSLPVR and PSI
configuration.
Automatic Pulse-Skipping Switchover
In skip mode (DPRSLPVR = high), an inherent automatic
switchover to PFM takes place at light loads (Figure 9).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
senses the inductor current across the low-side
VBATT – VOUT
L
Δi
Δt
I
PEAK
MOSFETs. Once V drops below the zero-crossing
LX
comparator threshold (see the Electrical Characteristics
table), the comparator forces DL_ low. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation. The PFM/PWM crossover
occurs when the load current of each phase is equal to
1/2 the peak-to-peak ripple current, which is a function
of the inductor value (Figure 9). For a battery input
range of 7V to 20V, this threshold is relatively constant,
with only a minor dependence on the input voltage due
to the typically low duty cycles. The total load current at
I
= I
/2
LOAD PEAK
0
ON-TIME
TIME
Figure 9. Pulse-Skipping/Discontinuous Crossover Point
the PFM/PWM crossover threshold (I
approximately:
) is
LOAD(SKIP)
⎛
⎝
⎞
⎠
T
V
V - V
IN OUT
⎛
⎝
⎞
SW OUT
L
I
= η
LOAD(SKIP)
TOTAL ⎜
⎟
⎠
⎜
⎟
V
IN
where η
is the number of active phases.
TOTAL
______________________________________________________________________________________ 37
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
current limit, so full output current is available immediate-
ly. CLKEN is pulled low approximately 60μs after the
MAX17021/MAX17082/MAX17482 reach the boot voltage
if PGDIN is high. At the same time, the MAX17021/
MAX17082/MAX17482 slew the output to the voltage set
at the VID inputs at the programmed slew rate. PWRGD
and PHASEGD become high impedance approximately
5ms after CLKEN is pulled low. The MAX17021/
MAX17082/MAX17482 automatically use forced-PWM
operation during soft-start and soft-shutdown, regardless
of the DPRSLPVR and PSI configuration.
Power-Up Sequence (POR, UVLO)
The MAX17021/MAX17082/MAX17482 are enabled
when SHDN is driven high (Figure 10). The internal ref-
erence powers up first. Once the reference exceeds its
UVLO threshold, the internal analog blocks are turned
on and masked by a 50μs one-shot delay. The PWM
controller is then enabled.
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V UVLO circuitry
CC
inhibits switching until V
rises above 4.25V. The con-
CC
For automatic startup, the battery voltage should be
present before V . If the controller attempts to bring
CC
troller powers up the reference once the system
enables the controller, V is above 4.25V, and SHDN
CC
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
is driven high. With the reference in regulation, the con-
troller ramps the output voltage to the boot voltage
(1.2V for MAX17021 IMVP-6+ and 1.1V for MAX17082/
or cycling the V
power supply below 0.5V.
MAX17482 IMVP-6.5) at 1/8 the slew rate set by R
:
CC
TIME
If the V
voltage drops below 4.25V, the controller
CC
8V
BOOT
t
=
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately
and forces a high-impedance output.
TRAN(START)
dV
dt
(
)
TARGET
where dV
/dt = 12.5mV/μs x 71.5kΩ/R
slew rate. The soft-start circuitry does not use a variable
is the
TARGET
TIME
V
CC
SHDN
0/MAX17482
INVALID
CODE
INVALID
CODE
VID (D0–D6)
SOFT-START =
1/8 SLEW RATE SET
BY R
SOFT-SHUTDOWN =
1/8 SLEW RATE SET
V
BOOT
BY R
TIME
TIME
V
CORE
INTERNAL
PWM CONTROL
SKIP
FORCED PWM
FORCED PWM
PHASEGD
CLKEN
PWRGD
t
t
BLANK
5ms TYP
BLANK
t
BLANK
60μs TYP
60μs TYP
t
BLANK
20μs TYP
Figure 10. Power-Up and Shutdown Sequence Timing Diagram
38 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
increments (10A, 20A, 30A, 40A, etc.), R
is the
Shutdown
When SHDN goes low, the MAX17021/MAX17082/
MAX17482 enter low-power shutdown mode. PWRGD
is pulled low immediately, and the output voltage ramps
SENSE
typical effective value of the current-sense element
(sense resistor or inductor DCR) that is used to provide
the current-sense voltage, and G
is the typical
m(IMON)
transconductance amplifier gain as defined in the
Electrical Characteristics table.
down at 1/8 the slew rate set by R
:
TIME
8V
OUT
t
=
TRAN(SHDN)
The IMON voltage is internally clamped to a maximum
of 1.1V (typ), preventing the IMON output from exceed-
ing the IMON voltage rating even under overload or
short-circuit conditions. When the controller is disabled,
IMON is pulled to ground.
dV
(
dt
)
TARGET
where dV
/dt = 12.5mV/μs x 71.5kΩ/R
TARGET
is the
TIME
slew rate. Slowly discharging the output capacitors by
slewing the output over a long period of time keeps the
average negative inductor current low (damped
response), thereby eliminating the negative output-volt-
age excursion that occurs when the controller dis-
charges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode normally
connected between the output and ground to clamp
the negative output-voltage excursion. After the con-
troller reaches the zero target, the MAX17021/
MAX17082/MAX17482 shut down completely—the dri-
vers are disabled (DL1 and DL2 driven low) and the
supply current drops below 1μA.
To filter the IMON signal, use an RC filter as shown in
Figure 2. The filter time constant is (R7 + R8) x C15.
Phase Fault (PHASEGD)
The MAX17021/MAX17082/MAX17482 include a phase-
fault output that signals the system that one of the two
phases either has a fault condition or is not matched with
the other. Detection is done by identifying the need for a
large on-time difference between phases in order to
achieve or move towards current balance.
PHASEGD is high impedance when the controller oper-
ates in one-phase mode (DPRSLPVR high or PSI low
and DPRSLPVR low). On exit to two-phase mode,
PHASEGD is forced high impedance for 32 switching
cycles on DH2.
When a fault condition—output UVLO or thermal shut-
down—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the con-
PHASEGD is low in shutdown. PHASEGD is forced high
impedance whenever the slew-rate controller is active
(output-voltage transitions).
troller, toggle SHDN or cycle V power below 0.5V.
CC
Current Monitor (IMON)
(MAX17021/MAX17482 Only)
The MAX17082/MAX17482 includes a unidirectional
transconductance amplifier that sources current pro-
portional to the positive current-sense voltage. The
IMON output current is defined by:
Temperature Comparator (VRHOT)
The MAX17021/MAX17082/MAX17482 also feature an
independent comparator with an accurate threshold
(V
) that tracks the analog supply voltage (V
=
HOT
HOT
0.3V ). This makes the thermal trip threshold indepen-
CC
dent of the V
tor- and thermistor-divider between V
supply voltage tolerance. Use a resis-
I
= G
x Σ (V
- V
)
CSN_
CC
IMON
m(IMON)
CSP_
and GND to
CC
where G
= 2.4mS (typ) and the IMON current is
m(IMON)
generate a voltage-regulator over-temperature monitor.
Place the thermistor as close to the MOSFETs and
inductors as possible.
unidirectional (sources current out of IMON only) for
positive current-sense values. For negative current-
sense voltages, the IMON current is zero.
The current monitor allows the processor to accurately
monitor the CPU load and quickly calculate the power
dissipation to determine if the system is about to over-
heat before the significantly slower temperature sensor
signals an over-temperature alert.
Fault Protection (Latched)
Output Overvoltage Protection
(MAX17021/MAX17082 Only)
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17021/MAX17082 continuously monitor the
output for an overvoltage fault. The controller detects
an OVP fault if the output voltage exceeds the set VID
DAC voltage by more than 300mV, regardless of the
operating state. During downward transitions in
Connect an external resistor between IMON and
VSS_SENSE to create the desired IMON gain based on
the following equation:
R
IMON
= 0.999V/(IMAX x R
x G
)
m(IMON)
SENSE
where IMAX is defined in the Current Monitor section of
the Intel IMVP-6.5 specification and based on discrete
______________________________________________________________________________________ 39
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold is set to default.
MOSFET Gate Drivers
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
When the OVP circuit detects an overvoltage fault, the
MAX17021/MAX17082 immediately force DL1 high and
pull DH1 and DH2 low. This action turns on the syn-
chronous-rectifier MOSFETs with 100% duty and, in
turn, rapidly discharges the output filter capacitor and
forces the output low. If the condition that caused the
overvoltage (such as a shorted high-side MOSFET) per-
sists, the battery fuse will blow. Toggle SHDN or cycle
seen in notebook applications, where a large V
-
IN
V
differential exists. The high-side gate drivers
OUT
(DH_) source and sink 2.2A, and the low-side gate dri-
vers (DL_) source 2.7A and sink 8A. This ensures
robust gate drive for high-current applications. The DH_
floating high-side MOSFET drivers are powered by
internal boost switch charge pumps at BST_, while the
DL_ synchronous-rectifier drivers are powered directly
the V
power supply below 0.5V to clear the fault
CC
latch and reactivate the controller.
by the 5V bias supply (V ).
DD
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
Output Undervoltage Protection (UVP)
If the MAX17021/MAX17082/MAX17482 output voltage is
400mV below the target voltage, the controller activates
the shutdown sequence and sets the fault latch. Once
the controller ramps down to zero, it forces DL1 and DL2
high, and pulls DH1 and DH2 low. Toggle SHDN or cycle
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17021/MAX17082/
MAX17482 interprets the MOSFET gates as off while
charge actually remains. Use very short, wide traces
(50 mils to 100 mils wide if the MOSFET is 1in from the
driver).
the V
power supply below 0.5V to clear the fault latch
CC
and reactivate the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX17021/MAX17082/MAX17482 feature a ther-
mal-fault-protection circuit. When the junction tempera-
ture rises above +160°C, a thermal sensor sets the fault
latch and activates the soft-shutdown sequence. Once
the controller ramps down to zero, it forces DL1 and
DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or
The internal pulldown transistor that drives DL_ low is
robust, with a 0.25Ω (typ) on-resistance. This helps
prevent DL_ from being pulled up due to capacitive
coupling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly
0/MAX17482
switches from ground to V . Applications with high
IN
input voltages and long inductive driver traces might
require rising LX_ edges do not pull up the low-side
MOSFETs’ gate, causing shoot-through currents. The
capacitive coupling between LX_ and DL_ created by
cycle the V
power supply below 0.5V to clear the
CC
fault latch and reactivate the controller after the junction
temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
the MOSFET’s gate-to-drain capacitance (C
), gate-
RSS
to-source capacitance (C
- C
), and additional
ISS
RSS
board parasitics should not exceed the following mini-
mum threshold:
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a no-fault test mode
is provided to disable the fault protection—overvoltage
protection, undervoltage protection, and thermal shut-
down. Additionally, the test mode clears the fault latch if
it has been set. The no-fault test mode is entered by
forcing 11V to 13V on SHDN.
⎛
⎞
C
RSS
V
> V
IN
GS(TH)
⎜
⎟
C
⎝
⎠
ISS
Typically, adding a 4700pF between DL_ and power
ground (C in Figure 11), close to the low-side
NL
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
40 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
•
Input-voltage range: The maximum value
(V ) must accommodate the worst-case high
IN(MAX)
AC adapter voltage. The minimum value (V
)
IN(MIN)
must account for the lowest input voltage after drops
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
(R
)*
BST_
BST_
INPUT (V )
IN
C
BST_
DH_
LX_
N
H
•
Maximum load current: There are two values to
consider. The peak load current (I
) deter-
L
LOAD(MAX)
mines the instantaneous component stresses and fil-
tering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous
C
BYP
V
DD
load current (I
) determines the thermal stress-
LOAD
es and thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
DL_
N
L
I
= I
x 80%.
LOAD
LOAD(MAX)
(C )*
NL
•
For multiphase systems, each phase supports a
fraction of the load, depending on the current bal-
ancing. When properly balanced, the load current is
evenly distributed among each phase:
PGND
(R
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
I
BST_
LOAD
I
=
LOAD(PHASE)
η
TOTAL
(C )* OPTIONAL—THE CAPACITOR REDUCES LX_ TO DL_ CAPACITIVE
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
where η
is the total number of active phases.
TOTAL
•
•
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
Figure 11. Gate Drive Circuit
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFETs are too long, the high-side MOSFETs can
turn on before the low-side MOSFETs have actually
turned off. Adding a resistor less than 5Ω in series with
BST_ slows down the high-side MOSFET turn-on time,
eliminating the shoot-through currents without degrad-
are proportional to frequency and V 2. The opti-
IN
mum frequency is also a moving target due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current.
ing the turn-off time (R
in Figure 11). Slowing down
BST_
the high-side MOSFET also reduces the LX_ node rise
time, thereby reducing EMI and high-frequency cou-
pling responsible for switching noise.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input-voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
______________________________________________________________________________________ 41
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
Setting the Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
⎛
⎞
⎟
⎛
⎜
⎞
⎟
V
- V
V
OUT
IN OUT
ley of the inductor current occurs at I
half the ripple current; therefore:
minus
LOAD(MAX)
L = η
⎜
TOTAL
f
I
LIR
V
⎝
⎠
⎝
⎠
SW LOAD(MAX)
IN
I
⎛
⎞
LIR
2
⎛
⎞
LOAD(MAX)
I
>
1-
where η
is the total number of phases.
TOTAL
⎜
⎝
⎟
⎠
LIMIT(LOW)
⎜
⎟
η
⎝
⎠
TOTAL
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
where η
is the total number of active phases, and
equals the minimum current-limit threshold
voltage divided by the current-sense resistor (R
TOTAL
LIMIT(LOW)
I
).
SENSE
inductor current (I
):
PEAK
Output Capacitor Selection
The output filter capacitor must have low-enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
I
⎛
⎞
LIR
2
LOAD(MAX) ⎛
⎞
I
=
1+
⎜
⎟
⎟
⎠
PEAK
⎜
⎝
η
⎝
⎠
TOTAL
In CPU V
converters and other applications where
CORE
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low V - V differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac-
tor, which can be calculated from the on-time and mini-
mum off-time. For a dual-phase controller, the
worst-case output sag voltage can be determined by:
the output is subject to large-load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
IN
OUT
V
STEP
LOAD(MAX)
R
(
+ R
≤
)
ESR
PCB
ΔI
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For multi-
phase operation, the maximum ESR to meet ripple
requirements is:
⎡
⎢
⎣
⎤
⎥
⎦
2
⎛
⎞
V
T
OUT SW
V
L ΔI
+ t
OFF(MIN)
(
)
LOAD(MAX)
⎜
⎝
⎟
⎠
0/MAX17482
IN
V
=
+
SAG
⎡
⎢
⎤
⎥
⎛
⎞
V
- 2V
T
(
)
IN
OUT SW
2C
V
- 2t
OFF(MIN)
OUT OUT
⎜
⎟
V
⎝
⎠
⎢
⎣
⎥
⎦
IN
ΔI
⎡
⎢
⎤
⎛
⎞
⎠
V
T
LOAD(MAX)
OUT SW
V
+ t
⎥
OFF(MIN)
⎜
⎟
2C
⎝
⎢
⎣
⎥
⎦
OUT
IN
where t
is the minimum off-time (see the
Electrical Characteristics table). The amount of overshoot
due to stored inductor energy can be calculated as:
OFF(MIN)
⎡
⎢
⎤
⎥
V f
L
IN SW
R
≤
V
RIPPLE
ESR
V
- η
V V
(
)
⎢
⎣
⎥
⎦
IN
TOTAL OUT OUT
2
ΔI
L
(
)
LOAD(MAX)
C
V
≈
SOAR
2η
V
where η
is the total number of active phases and
TOTAL
TOTAL OUT OUT
f
is the switching frequency per phase. The actual
SW
whereη
is the total number of active phases.
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usu-
ally selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
TOTAL
42 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load con-
ditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
needed to prevent V
and V
from causing
SOAR
SAG
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback-
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
longer a problem (see the V
and V
equations
SOAR
SAG
in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
f
SW
π
f
≤
ESR
where:
1
f
=
ESR
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
2πR
C
EFF OUT
and:
R
= R
+ R
+ R
EFF
ESR
DROOP PCB
where C
is the total output capacitance, R
is the
OUT
ESR
is the volt-
total equivalent series resistance, R
DROOP
age-positioning gain, and R
is the parasitic board
PCB
resistance between the output capacitors and sense
resistors.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
The multiphase Quick-PWM controllers operate out-of-
phase while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several stag-
gered stages. For duty cycles less than 100%/η
OUTPH
a 30mV
ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four
P-P
per phase, the I
requirements can be determined
RMS
330μF/2.5V Panasonic SP (type SX) capacitors in paral-
lel provide 1.5mΩ (max) ESR. With a 2mΩ droop and
0.5mΩ PCB resistance, the typical combined ESR
results in a zero at 30kHz.
by the following equation:
⎛
⎞
I
LOAD
I
=
η
V
V
- η V
TOTAL OUT
(
)
RMS
TOTAL OUT IN
⎜
⎟
η
V
⎝
⎠
Ceramic capacitors have a high-ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the out-
put without verifying that the circuit contains enough
voltage positioning and series PCB resistance to
ensure stability. When only using ceramic output
TOTAL IN
where η
is the total number of out-of-phase
TOTAL
switching regulators. The worst-case RMS current
requirement occurs when operating with V
=
IN
2η
V
RMS
. At this point, the above equation simpli-
TOTAL OUT
fies to I
= 0.5 x I
/η
.
LOAD TOTAL
capacitors, output overshoot (V
) typically deter-
SOAR
mines the minimum output capacitance requirement.
______________________________________________________________________________________ 43
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
required to stay within package
DS(ON)
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
) losses. High-
DS(ON)
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(N ) due to switching losses is difficult since it must
H
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PCB layout characteris-
tics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
using a thermocouple mounted on N :
H
V
and V
. Calculate both these sums.
IN(MAX)
IN(MIN)
Ideally, the losses at V
equal to losses at V
should be approximately
IN(MIN)
IN(MAX)
IN(MIN)
IN(MAX)
V
I
f
Q
G(SW)
⎛
⎞ ⎛
⎞
IN(MAX)LOAD SW
, with lower losses in
are significantly high-
PD (N Switching) =
H
⎜
⎟ ⎜
⎟
η
I
GATE
⎝
⎠ ⎝
⎠
between. If the losses at V
er than the losses at V
size of N (reducing R
TOTAL
, consider increasing the
2
C
V
f
OSS IN SW
2
but with higher C
IN(MAX)
).
H
DS(ON)
GATE
are significantly
+
Conversely, if the losses at V
higher than the losses at V
, consider reducing
IN(MIN)
where C
G(SW)
MOSFET, and I
current (2.2A typ).
is the N MOSFET’s output capacitance,
H
OSS
the size of N (increasing R
to lower C
). If
H
DS(ON)
GATE
Q
is the charge needed to turn on the N
H
V
does not vary over a wide range, the minimum
IN
is the peak gate-drive source/sink
GATE
power dissipation occurs where the resistive losses
equal the switching losses.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
Choose a low-side MOSFET that has the lowest possible
on-resistance (R
), comes in a moderate-sized
DS(ON)
0/MAX17482
voltages are applied due to the squared term in the C x
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL_ gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems might
occur (see the MOSFET Gate Drivers section).
2
V
x ƒ
switching-loss equation. If the high-side
SW
IN
MOSFET chosen for adequate R
at low-battery
DS(ON)
voltages becomes extraordinarily hot when biased from
, consider choosing another MOSFET with
V
IN(MAX)
lower parasitic capacitance.
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum input voltage:
MOSFET Power Dissipation
2
⎡
⎤
⎥
⎛
⎞
⎛
⎞
V
I
LOAD
Worst-case conduction losses occur at the duty factor
OUT
PD (N Resistive) = ⎢1-
R
DS(ON)
⎜
⎟
L
⎜
⎟
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at the
minimum input voltage:
V
η
⎝
⎠
⎢
⎣
⎥
⎦
⎝
⎠
IN(MAX)
TOTAL
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I but are not quite high enough to exceed
LOAD(MAX)
2
⎛
⎝
⎞ ⎛
⎠ ⎝
⎞
V
I
LOAD
η
TOTAL
OUT
PD (N Resistive) =
R
H
(
DS ON)
⎜
⎟
⎟
⎜
V
⎠
IN
where η
is the total number of phases.
TOTAL
44 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can over design the cir-
cuit to tolerate:
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (C
)
CCI
integrates the difference between the main and sec-
ondary current-sense voltages. The internal compensa-
tion resistor (R
= 200kΩ) improves transient
CCI
ΔI
⎛
⎝
⎞
INDUCTOR
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be opti-
mized. Excessively large capacitor values increase the
integration time constant, resulting in larger current dif-
ferences between the phases during transients.
I
= η
= η
I
+
⎛
LOAD
TOTAL ⎜ VALLEY(MAX)
⎟
⎠
2
I
LIR
⎞
LOAD(MAX)
2
I
+
TOTAL VALLEY(MAX)
⎜
⎟
⎝
⎠
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. For most
applications, a 470pF capacitor from CCI to the switch-
ing regulator’s output works well.
where I
is the maximum valley current
VALLEY(MAX)
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Connecting the compensation network to the output
Choose a Schottky diode (D ) with a forward voltage
L
(V
) allows the controller to feed-forward the output-
OUT
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase dur-
ing the dead times. This diode is optional and can be
removed if efficiency is not critical.
voltage signal, especially during transients.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output-voltage
droop (Figure 3) as a function of the load. This adjusta-
bility allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller cur-
rent-sense resistance to be used, reducing the overall
power dissipated.
Boost Capacitors
) must be selected large
The boost capacitors (C
BST_
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1μF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
Steady-State Voltage Positioning
Connect a resistor (R ) between FB and V
to set
FB
OUT
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R ):
DROOP
N× Q
200mV
GATE
C
=
BST_
R
DROOP
R
=
FB
R
G
SENSE m(FB)
where N is the number of high-side MOSFETs used for
one regulator, and Q is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
GATE
where the effective current-sense resistance (R
)
SENSE
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G
) is typically 600μS as
m(FB)
defined in the Electrical Characteristics table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
(V
= 5V). Using the above equation, the required
GS
boost capacitance would be:
2 × 24nC
200mV
When the inductors’ DCR is used as the current-sense
C
=
= 0.24μF
BST_
element (R
= R
), each current-sense input
DCR
SENSE
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
______________________________________________________________________________________ 45
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Dropout design example:
Minimum Input-Voltage Requirements
and Dropout Performance
V
FB
= 1.4V
The output-voltage-adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot and the number of phases.
For best dropout performance, use the slower (200kHz)
on-time settings. When working with low input voltages,
the duty-factor limit must be calculated using worst-
case values for on- and off-times. Manufacturing toler-
ances and internal propagation delays introduce an
error to the on-times. This error is greater at higher fre-
quencies. Also, keep in mind that transient-response
performance of buck regulators operated too close to
dropout is poor, and bulk output capacitance must
f
t
= 300kHz
SW
= 400ns
OFF(MIN)
V
V
= 3mV/A x 30A = 90mV
DROOP
= V
= 150mV (30A Load)
DIS
CHG
h = 1.5 and η
= 2:
TOTAL
⎡
1.4V -90mV + 150mV
1-2 × (0.4μs × 1.5 × 300kHz)
⎤
V
= 2 ×
+
IN(MIN)
⎢
⎥
⎦
⎣
150mV -150mV + 90mV = 4.96V
often be added (see the V
equation in the
SAG
Calculating again with h = 1 gives the absolute limit of
dropout:
Multiphase Quick-PWM Design Procedure section.
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (ΔI
)
DOWN
⎡
1.4V -90mV + 150mV
1-2 × (0.4μs × 1.0 × 300kHz)
⎤
V
= 2 ×
+
as much as it ramps up during the on-time (ΔI ). The
UP
IN(MIN)
⎢
⎥
⎦
⎣
ratio h = ΔI /ΔI
is an indicator of the ability to
UP DOWN
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
150mV -150mV + 90mV = 4.07V
Therefore, V must be greater than 4.1V, even with very
IN
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5.0V.
each switching cycle and V
greatly increases
SAG
unless additional output capacitance is used.
Applications Information
A reasonable minimum value for h is 1.5, but adjusting
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17082 evaluation kit specifi-
cation for a layout example and follow these guidelines
for good PCB layout:
this up or down allows tradeoffs between V
, output
SAG
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
0/MAX17482
⎡
⎢
⎤
⎥
V
- V
+ V
FB DROOP DIS
V
= η
+
IN(MIN)
TOTAL
1- η
h× t
f
⎢
⎣
⎥
⎦
TOTAL
OFF(MIN) SW
V
- V
+ V
CHG DIS DROOP
•
Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
where η
is the total number of out-of-phase
TOTAL
switching regulators, V
is the voltage-positioning
FB
•
Connect all analog grounds to a separate solid cop-
per plane, which connects to the GND pin of the
Quick-PWM controller. This includes the V , FB,
CC
and GNDS bypass capacitors.
droop, V
and V
are the parasitic voltage drops
DIS
CHG
in the discharge and charge paths (see the On-Time
One-Shot section), t is from the Electrical
OFF(MIN)
Characteristics table. The absolute minimum input volt-
age is calculated with h = 1.
•
Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
If the calculated V
is greater than the required
IN(MIN)
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
calculate V
response.
. If operation near dropout is anticipated,
SAG
SAG
to be sure of adequate transient
46 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
0/MAX17482
•
Keep the high-current, gate-driver traces (DL_,
DH_, LX_, and BST_) short and wide to minimize
trace resistance and inductance. This is essential
for high-power MOSFETs that require low-imped-
ance gate drivers to avoid shoot-through currents.
3) Group the gate-drive components (BST_ diodes
and capacitors, V bypass capacitor) together
DD
near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 2. This diagram can be
viewed as having four separate ground planes:
input/output ground, where all the high-power com-
ponents go; the power ground plane, where the
•
•
CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin-
sense connections to guarantee the current-sense
accuracy.
GND pin and V
bypass capacitor go; the mas-
DD
ter’s analog ground plane where sensitive analog
components go, the master’s GND pin and V
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
CC
bypass capacitor go; and the slave’s analog
ground plane where the slave’s GND pin and V
CC
bypass capacitor go. The master’s GND plane must
meet the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the high-
power output ground with a short metal trace from
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
•
Route high-speed switching nodes away from sen-
sitive analog areas (CCI, FB, CSP_, CSN_, etc.).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C
OUT
,
IN
5) Connect the output power planes (V
and sys-
C
, and D1 anode). If possible, make all these
CORE
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL_ gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
Package Information
Chip Information
For the latest package outline information and land patterns, go
PROCESS: BiCMOS
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN-EP
T4055-2
21-0140
______________________________________________________________________________________ 47
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
11/08
Initial release
—
1, 2, 4, 13, 14, 16,
19, 22, 25, 33–36,
39, 40, 46, 47
Correction to non-OVP version, update IMON equations, fix errors in Figures 1,
2, and 4
1
7/09
0/MAX17482
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
48 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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