LTC3891 [Linear]
High Voltage, Current Mode Switching Regulator Controller Thermal Shutdown; 高电压，电流模式开关稳压控制器过热关机
| 型号： | LTC3891 |
| 厂家： | 
Linear |
| 描述： | High Voltage, Current Mode Switching Regulator Controller Thermal Shutdown |
| 文件： | 总26页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3724
High Voltage, Current Mode
Switching Regulator Controller
FEATURES
DESCRIPTION
TheLT®3724isaDC/DCcontrollerusedformediumpower,
low part count, low cost, high efficiency supplies. It of-
fers a wide 4V-60V input range (7.5V minimum startup
voltage)andcanimplementstep-down, step-up, inverting
and SEPIC topologies.
n
Wide Input Range: 4V to 60V
n
Output Voltages up to 36V (Step-Down)
Burst Mode® Operation: <100µA Supply Current
n
n
10µA Shutdown Supply Current
n
1.3ꢀ ꢁeference Accuracy
n
200kHz Fixed Frequency
The LT3724 includes Burst Mode operation, which re-
duces quiescent current below 100µA and maintains
high efficiency at light loads. An internal high voltage bias
regulator allows for simple biasing and can be back driven
to increase efficiency.
n
Drives N-Channel MOSFET
n
Programmable Soft-Start
n
Programmable Undervoltage Lockout
n
Internal High Voltage ꢁegulator for Gate Drive
n
Thermal Shutdown
n
Additional features include fixed frequency current mode
controlforfastlineandloadtransientresponse;agatedriver
capable of driving large N-channel MOSFETs; a precision
undervoltage lockout function; 10µA shutdown current;
short-circuit protection; and a programmable soft-start
function that directly controls output voltage slew rates at
startup which limits inrush current, minimizes overshoot
and facilitates supply sequencing.
Current Limit Unaffected by Duty Cycle
n
16-Pin Thermally Enhanced TSSOP Package
APPLICATIONS
n
Industrial Power Distribution
n
12V and 42V Automotive and Heavy Equipment
n
High Voltage Single Board Systems
Distributed Power Systems
Avionics
Telecom Power
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Burst Mode is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5731694, 6498466, 6611131.
n
n
TYPICAL APPLICATION
High Voltage Step-Down Regulator
Efficiency and Power Loss
vs Load Current
V
IN
30V TO
60V
C
95
90
85
80
75
70
65
12
10
8
V
IN
BOOST
TG
IN
68µF
0.22µF
EFFICIENCY
1M
Si7852
LT3724
0.025Ω
10Ω
V
OUT
SHDN
SW
24V
47µH
75W
68.1k
200k
SS3H9
+
6
C
C
SS
OUT
330µF
Burst_EN
V
4
CC
1µF
LOSS
V
FB
V
C
PGND
2
40.2k
V
= 48V
IN
+
SENSE
0
10
680pF
120pF
1000pF
–
0.1
1
SGND
SENSE
LOAD CURRENT (A)
4.99k
93.1k
3724 TA01b
3724 TA01a
3724fd
1
LT3724
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (V ).........................65V to –0.3V
IN
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BOOST
TG
IN
Boosted Supply Voltage (BOOST).............. 80V to –0.3V
Switch Voltage (SW)(Note 8)........................ 65V to –1V
Differential Boost Voltage
NC
SHDN
SW
C
SS
NC
17
(BOOST to SW)...................................... 24V to –0.3V
BURST_EN
V
CC
Bias Supply Voltage (V ).......................... 24V to –0.3V
CC
V
FB
PGND
+
–
SENSE and SENSE Voltages ................... 40V to –0.3V
+
V
C
SENSE
SENSE
–
SGND
+
–
(SENSE to SENSE )................................... 1V to –1V
BUꢁST_EN Voltage.................................... 24V to –0.3V
FE PACKAGE
16-LEAD PLASTIC TSSOP
T
= 125°C, θ = 40°C/W, θ = 10°C/W
JA JC
JMAX
V , V , C , and SHDN Voltages................. 5V to –0.3V
C
C
FB SS
EXPOSED PAD IS SGND (PIN 17), MUST BE SOLDEꢁED TO PCB
and SHDN Pin Currents.....................................1mA
SS
Operating Junction Temperature ꢁange (Notes 2, 3)
LT3724E............................................. –40°C to 125°C
LT3724I.............................................. –40°C to 125°C
LT3724MP.......................................... –55°C to 125°C
Storage Temperature.............................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
ORDER INFORMATION
LEAD FREE FINISH
LT3724EFE#PBF
LT3724IFE#PBF
LEAD BASED FINISH
LT3724MPFE
TAPE AND REEL
LT3724EFE#TꢁPBF
LT3724IFE#TꢁPBF
TAPE AND REEL
LT3724MPFE#Tꢁ
PART MARKING
3724EFE
PACKAGE DESCRIPTION
TEMPERATURE RANGE
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
PACKAGE DESCRIPTION
16-Lead Plastic TSSOP
–40°C to 125°C
3724IFE
–40°C to 125°C
PART MARKING*
3724MPFE
TEMPERATURE RANGE
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
IN
Operating Voltage ꢁange (Note 4)
Minimum Start Voltage
UVLO Threshold (Falling)
UVLO Threshold Hysteresis
4
7.5
3.65
60
V
V
3.8
670
3.95
V
mV
I
V
IN
V
IN
V
IN
Supply Current
Burst Mode Current
Shutdown Current
V
V
V
> 9V
20
20
10
µA
µA
µA
VIN
CC
BUꢁST_EN
= 0V, V = 1.35V
FB
= 0V
15
SHDN
3724fd
2
LT3724
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Operating Voltage ꢁange
75
20
V
V
BOOST
Operating Voltage ꢁange (Note 5)
UVLO Threshold (ꢁising)
V
V
V
- V
SW
- V
SW
- V
SW
BOOST
BOOST
BOOST
5
400
V
UVLO Threshold Hysteresis
mV
I
BOOST Supply Current (Note 6)
BOOST Burst Mode Current
BOOST Shutdown Current
1.4
0.1
0.1
mA
µA
µA
BOOST
V
V
= 0V
BUꢁST_EN
SHDN
= 0V
l
l
V
CC
Operating Voltage ꢁange (Note 5)
Output Voltage
UVLO Threshold (ꢁising)
UVLO Threshold Hysteresis
20
8.3
V
V
Over Full Line and Load ꢁange
8
6.25
500
V
mV
l
I
V
V
V
Supply Current (Note 6)
Burst Mode Current
Shutdown Current
1.7
80
2.1
mA
µA
VCC
CC
CC
CC
V
V
= 0V
BUꢁST_EN
SHDN
= 0V
20
µA
l
l
Short-Circuit Current
–30
–55
mA
V
Error Amp ꢁeference Voltage
Measured at V Pin
1.224
1.215
1.231
1.238
1.245
V
V
FB
FB
I
FB
Feedback Input Current
25
nA
l
V
Enable Threshold (ꢁising)
Threshold Hysteresis
1.3
1.35
120
1.4
V
SHDN
SENSE
SENSE
mV
l
l
V
Common Mode ꢁange
Current Limit Sense Voltage
0
140
36
175
V
mV
+
–
V
– V
150
SENSE
SENSE
I
f
Input Current
V
V
V
= 0V
400
2
–150
µA
µA
µA
SENSE(CM)
SENSE(CM)
SENSE(CM)
+
–
(I
+ I
)
= 2.5V
> 4V
SENSE
SENSE
Operating Frequency
190
175
165
200
210
220
225
kHz
kHz
kHz
SW
l
l
MP Grade
ꢁising
200
V
Soft-Start Disable Voltage
Soft-Start Disable Hysteresis
V
FB
1.185
300
V
mV
FB(SS)
I
Soft-Start Capacitor Control Current
Error Amp Transconductance
Error Amp DC Voltage Gain
Error Amp Output ꢁange
2
µA
µmhos
dB
SS
l
g
275
340
62
400
m
A
V
V
Zero Current to Current Limit
1.2
30
V
C
I
Error Amp Sink/Source Current
µA
VC
V
Gate Drive Output On Voltage (Note 7)
Gate Drive Output Off Voltage
C
LOAD
C
LOAD
= 3300pF
= 3300pF
9.8
0.1
V
V
TG
t
t
t
I
Gate Drive ꢁise/Fall Time
Minimum Switch Off Time
Minimum Switch On Time
SW Pin Sink Current
10ꢀ to 90ꢀ or 90ꢀ to 10ꢀ, C
= 3300pF
LOAD
60
ns
ns
TG
350
300
300
TG(OFF)
TG(ON)
SW
l
500
ns
V
SW
= 2V
mA
3724fd
3
LT3724
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum ꢁatings
may cause permanent damage to the device. Exposure to any Absolute
Maximum ꢁating condition for extended periods may affect device
reliability and lifetime.
temperature range. The LT3724MP is 100ꢀ tested and guaranteed over
the –55°C to 125°C operating junction temperature range.
Note 4: V voltages below the start-up threshold (7.5V) are only
IN
supported when the V is externally driven above 6.5V.
CC
Note 2: The LT3724 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LT3724E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3724I is guaranteed over the full –40°C to 125°C operating junction
Note 5: Operating range is dictated by MOSFET absolute maximum V
Note 6: Supply current specification does not include switch drive
currents. Actual supply currents will be higher.
Note 7: DC measurement of gate drive output “ON” voltage is typically
8.6V. Internal dynamic bootstrap operation yields typical gate “ON”
voltages of 9.8V during standard switching operation. Standard operation
gate “ON” voltage is not tested but guaranteed by design.
Note 8: The –1V absolute maximum on the SW pin is a transient condition.
It is guaranteed by design and not subject to test.
.
GS
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold (Rising)
vs Temperature
Shutdown Threshold (Falling)
vs Temperature
VCC vs Temperature
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.26
1.25
1.24
1.23
1.22
1.21
1.20
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
I
= 20mA
CC
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3724 G01
3724 G02
3724 G03
VCC vs ICC(LOAD)
VCC vs VIN
ICC Current Limit vs Temperature
70
60
50
40
30
20
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
9
8
7
6
5
4
3
T
= 25°C
I
= 20mA
= 25°C
A
CC
A
T
–50 –25
0
25
50
75
100 125
3724 G06
20
(mA)
30
35
4
11
12
0
5
10
15
25
8
10
5
6
7
9
V
(V)
TEMPERATURE (°C)
I
IN
CC (LOAD)
3724 G04
3724 G05
3724fd
4
LT3724
TYPICAL PERFORMANCE CHARACTERISTICS
VCC UVLO Threshold (Rising)
vs Temperature
Error Amp Transconductance
vs Temperature
ICC vs VCC (SHDN = 0V)
350
345
340
335
330
325
320
6.5
6.4
6.3
6.2
6.1
6.0
25
20
15
T
= 25°C
A
10
5
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75
100 125
0
2
4
6
8
10 12 14 16 18 20
(V)
TEMPERATURE (°C)
V
CC
3724 G09
3724 G07
3724 G08
+
–
I(SENSE + SENSE ) vs
Operating Frequency
vs Temperature
Error Amp Reference
vs Temperature
VSENSE (CM)
230
220
210
200
190
180
170
1.234
1.233
1.232
1.231
1.230
1.229
1.228
1.227
400
300
200
100
0
T
= 25°C
A
–100
–200
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.5
V
(V)
SENSE (CM)
3724 G11
3724 G12
3724 G10
Maximum Current Sense
Threshold vs Temperature
VIN UVLO Threshold (Rising)
vs Temperature
VIN UVLO Threshold (Falling)
vs Temperature
4.54
4.52
4.50
4.48
4.46
4.44
4.42
4.40
160
158
156
154
152
150
148
146
144
142
140
3.86
3.84
3.82
3.80
3.78
3.76
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
3724 G14
3724 G13
3724 G15
3724fd
5
LT3724
PIN FUNCTIONS
V (Pin 1): The V pin is the main supply pin and should
V (Pin 7): The V pin is the output of the error amplifier
C C
IN
IN
be decoupled to SGND with a low ESꢁ capacitor located
close to the pin.
whosevoltagecorrespondstothemaximum(peak)switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator circuit by connecting an ꢁC
NC (Pin 2): No Connection.
network from the V pin to SGND. This circuit creates the
C
SHDN (Pin 3): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
usedtoimplementanundervoltagelockout(UVLO)circuit.
See Application Information section for implementing a
UVLO function. When the SHDN pin is pulled below a
dominant pole for the converter regulation control loop.
Specific integrator characteristics can be configured to
optimizetransientresponse.Connectinga100pForgreater
high frequency bypass capacitor from this pin to ground
is recommended. When Burst Mode operation is enabled
(see Pin 5 description), an internal low impedance clamp
transistor V (0.7V), a low current shutdown mode is
BE
entered, all internal circuitry is disabled and the V sup-
on the V pin is set at 100mV below the burst threshold,
IN
C
ply current is reduced to approximately 10µA. Typical
pin input bias current is <10µA and the pin is internally
clamped to 6V.
which limits the negative excursion of the pin voltage.
Therefore, this pin cannot be pulled low with a low imped-
ance source. If the V pin must be externally manipulated,
C
do so through a 1kΩ series resistance.
C
(Pin 4): The soft-start pin is used to program the sup-
SS
ply soft-start function. The pin is connected to V
via a
SGND (Pin 8, 17): The SGND pin is the low noise ground
OUT
ceramiccapacitor(C )and200kΩseriesresistor. During
reference. It should be connected to the –V
side of the
SS
OUT
start-up, the supply output voltage slew rate is controlled
to produce a 2µA average current through the soft-start
coupling capacitor. Use the following formula to calculate
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Application Information section for helpful hints
on PCB layout of grounds.
C
for a given output voltage slew rate:
SS
–
–
C
= 2µA(t /V
)
SENSE (Pin 9): The SENSE pin is the negative input for
the current sense amplifier and is connected to the V
SS
SS OUT
OUT
Seetheapplicationsectionformoreinformationonsetting
therisetimeoftheoutputvoltageduringstart-up.Shorting
this pin to SGND disables the soft-start function.
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 150mV across the
SENSE inputs.
BURST_EN (Pin 5): The BUꢁST_EN pin is used to enable
or disable Burst Mode operation. Connect the BUꢁST_EN
pin to ground to enable the burst mode function. Connect
+
+
SENSE (Pin 10): The SENSE pin is the positive input for
the current sense amplifier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to 150mV across
the SENSE inputs.
the pin to V to disable the burst mode function.
CC
V
(Pin 6): The output voltage feedback pin, V , is
FB
FB
externally connected to the supply output voltage via a
PGND (Pin 11): The PGND pin is the high-current ground
resistive divider. The V pin is internally connected to
FB
referenceforinternallowsideswitchandtheV regulator
CC
the inverting input of the error amplifier. In regulation,
circuit. Connect the pin directly to the negative terminal of
V
is 1.231V.
FB
theV decouplingcapacitor.SeetheApplicationInforma-
CC
tion section for helpful hints on PCB layout of grounds.
3724fd
6
LT3724
PIN FUNCTIONS
V
(Pin 12): The V pin is the internal bias supply
so that the BOOST pin capacitor can be charged. Give
careful consideration in choosing the Schottky diode to
limit the negative voltage swing on the SW pin.
CC
CC
decoupling node. Use a low ESꢁ 1µF ceramic capacitor
to decouple this node to PGND. Most internal IC func-
tions are powered from this bias supply. An external
TG (Pin 15): The TG pin is the bootstrapped gate drive
for the top N-Channel MOSFET. Since very fast high cur-
rents are driven from this pin, connect it to the gate of
the power MOSFET with a short and wide, typically 0.02”
width, PCB trace to minimize inductance.
diode connected from V to the BOOST pin charges the
CC
bootstrapped capacitor during the off-time of the main
power switch. Back driving the V pin from an external
CC
OUT
DC voltage source, such as the V
output of the buck
regulator supply, increases overall efficiency and reduces
power dissipation in the IC. In shutdown mode this pin
sinks 20µA until the pin voltage is discharged to 0V.
BOOST (Pin 16): The BOOST pin is the supply for the
bootstrapped gate drive and is externally connected to a
low ESꢁ ceramic boost capacitor referenced to SW pin.
NC (Pin 13): No Connection.
The recommended value of the BOOST capacitor, C
,
BOOST
SW (Pin 14): In step-down applications the SW pin is
connectedtothecathodeofanexternalclampingSchottky
diode, the source of the power MOSFET and the induc-
is 50 times greater than the total input capacitance of the
topside MOSFET. In most applications 0.1µF is adequate.
The maximum voltage that this pin sees is V + V ,
IN
CC
tor. The SW node voltage swing is from V during the
IN
ground referred.
on-time of the power MOSFET, to a Schottky voltage drop
below ground during the off-time of the power MOSFET.
In start-up and in operating modes where there is insuf-
ficientinductorcurrenttofreewheeltheSchottkydiode,an
internal switch is turned on to pull the SW pin to ground
Exposed Pad (SGND) (Pin 17): The exposed leadframe is
internally connected to the SGND pin. Solder the exposed
pad to the PCB ground for electrical contact and optimal
thermal performance.
3724fd
7
LT3724
FUNCTIONAL DIAGRAM
V
IN
UVLO
(<4V)
8V V
CC
REGULATOR
V
IN
BOOST
16
V
CC
BST
UVLO
1
V
UVLO
(<6V)
IN
C
IN
C
BOOST
3.8V
REGULATOR
INTERNAL
SUPPLY RAIL
BOOSTED
SWITCH
DRIVER
TG
15
DRIVE
M1
D1
CONTROL
RA
FEEDBACK
REFERENCE
–
+
SW
14
L1
R
1.231V
SENSE
V
OUT
NOL
SWITCH
LOGIC
C
D2
OUT
SHDN
V
CC
+
–
3
12
C
VCC
RB
D3
(OPTIONAL)
DRIVE
CONTROL
BURST_EN
PGND
11
–
+
5
6
V
FB
–
+
R2
R1
g
m
0.5V
OSCILLATOR
ERROR
AMP
Q
R
S
–
+
V
C
SLOPE COMP
GENERATOR
7
SOFT-START
CURRENT
C
C2
DISABLE/BURST
SENSE
R
C
ENABLE
COMPARATOR
+
~1V
C
C1
–
–
+
BURST MODE
OPERATION
1.185V
2µA
C
SS
4
8
+
SENSE
10
–
+
C
SS
SGND
–
SENSE
9
3724 FD
3724fd
8
LT3724
(Refer to Functional Diagram)
OPERATIONS
TheLT3724isaPWMcontrollerwithaconstantfrequency,
current mode control architecture. It is designed for low
to medium power, switching regulator applications. Its
high operating voltage capability allows it to step-up
or down input voltages up to 60V without the need for
a transformer. The LT3724 is used in nonsynchronous
applications, meaning that a freewheeling rectifier diode
(D1 of Function Diagram) is used instead of a bottom
side MOSFET. For circuit operation, please refer to the
Functional Diagram of the IC and Typical Application on
the front page of the data sheet. The LT3800 is a similar
part that uses synchronous rectification, replacing the
diode with a MOSFET in a step-down application.
V /Boosted Supply
CC
An internal V regulator provides V derived gate-drive
CC
IN
power for start-up under all operating conditions with
MOSFET gate charge loads up to 90nC. The regulator can
operate continuously in applications with V voltages
IN
up to 60V, provided the V voltage and/or MOSFET gate
IN
charge currents do not create excessive power dissipa-
tion in the IC. Safe operating conditions for continuous
regulator use are shown in Figure 1. In applications where
these conditions are exceeded, V must be derived from
CC
an external source after start-up. The LT3724 regulator
can, however, be used for “full time” use in applications
where short-duration V transients exceed allowable
IN
continuous voltages.
Main Control Loop
70
During normal operation, the external N-channel MOSFET
switch is turned on at the beginning of each cycle. The
switch stays on until the current in the inductor exceeds
60
50
40
a current threshold set by the DC control voltage, V , the
C
outputofthevoltagecontrolloop.Thevoltagecontrolloop
monitors the output voltage, via the V pin voltage, and
FB
30
compares it to an internal 1.231V reference. It increases
SAFE
OPERATING
AREA
the current threshold when the V voltage is below the
FB
20
10
reference voltage and decreases the current threshold
when the V voltage is above the reference voltage. For
FB
0
20
40
60
80
100
instance, when an increase in the load current occurs,
MOSFET TOTAL GATE CHARGE (nC)
the output voltage drops causing the V voltage to drop
3724 F01
FB
relative to the 1.231V reference. The voltage control loop
senses the drop and increases the current threshold. The
peak inductor current is increased until the average induc-
tor current equals the new load current and the output
voltage returns to regulation.
Figure 1. VCC Regulator Continuous Operating Conditions
For higher converter efficiency and less power dissipa-
tion in the IC, V can also be supplied from an external
CC
supply such as the converter output. When an external
supply back drives the internal V regulator through an
CC
Current Limit/Short-Circuit
external diode and the V voltage is pulled to a diode
CC
The inductor current is measured with a series sense
resistor (see the Typical Application on the front page).
When the voltage across the sense resistor reaches the
maximum current sense threshold, typically 150mV, the
TG MOSFET driver is disabled for the remainder of that
cycle. If the maximum current sense threshold is still ex-
ceeded at the beginning of the next cycle, the entire cycle
is skipped. Cycle skipping keeps the inductor currents to
a controlled value during a short-circuit, particularly when
above its regulation voltage, the internal regulator is dis-
abled and goes into a low current mode. V is the bias
CC
supply for most of the internal IC functions and is also
usedtochargethebootstrappedcapacitor(C
)viaan
BOOST
externaldiode.TheexternalMOSFETswitchisbiasedfrom
the bootstrapped capacitor. While the external MOSFET
switch is off, an internal BJT switch, whose collector is
connected to the SW pin and emitter is connected to the
PGND pin, is turned on to pull the SW node to PGND and
rechargethebootstrapcapacitor. Theswitchstaysonuntil
V is high. Setting the sense resistor value is discussed
IN
in the “Application Information” section.
3724fd
9
LT3724
(Refer to Functional Diagram)
OPERATIONS
either the start of the next cycle or until the bootstrapped
switching resumes. An internal clamp on the V pin is set
C
capacitor is fully charged.
at100mVbelowtheoutputdisablethreshold, whichlimits
the negative excursion of the pin voltage, minimizing the
converter output ripple during Burst Mode operation.
MOSFET Driver
The LT3724 contains a high speed boosted driver to turn
on and off an external N-channel MOSFET switch. The
MOSFET driver derives its power from the boost capacitor
which is referenced to the SW pin and the source of the
MOSFET. The driver provides a large pulse of current to
turn on the MOSFET fast and minimize transition times.
Multiple MOSFETs can be paralleled for higher current
operation.
During Burst Mode operation, the V pin current is 20µA
IN
andtheV currentisreducedto80µA. Ifnoexternaldrive
CC
isprovidedforV , allV biascurrentsoriginatefromthe
CC
CC
V pin, giving a total V current of 100µA. Burst current
IN
IN
can be reduced further when V is driven using an output
CC
derived source, as the V component of V current is
CC
IN
then reduced by the converter duty cycle ratio.
Start-Up
To eliminate the possibility of shoot through between the
MOSFET and the internal SW pull-down switch, an adap-
tive nonoverlap circuit ensures that the internal pull-down
switch does not turn on until the gate of the MOSFET is
below its turn on threshold.
The following section describes the start-up of the supply
and operation down to 4V once the step-down supply is
up and running. For the protection of the LT3724 and the
switching supply, there are internal undervoltage lockout
(UVLO) circuits with hysteresis on V , V and V
,
IN CC
BOOST
Low Current Operation (Burst Mode Operation)
as shown in the Electrical Characteristics table. Start-up
and continuous operation require that all three of these
undervoltage lockout conditions be satisfied because
the TG MOSFET driver is disabled during any UVLO fault
To increase low current load efficiency, the LT3724 is
capable of operating in Linear Technology’s proprietary
BurstModeoperationwheretheexternalMOSFEToperates
intermittently based on load current demand. The Burst
Mode function is disabled by connecting the BUꢁST_EN
condition.Instartup,formostapplications,V ispowered
CC
from V through the high voltage linear regulator of the
IN
LT3724. This requires V to be high enough to drive the
IN
pin to V and enabled by connecting the pin to SGND.
CC
V
CC
voltage above its undervoltage lockout threshold.
V , in turn, has to be high enough to charge the BOOST
CC
When the required switch current, sensed via the V pin
C
voltage, isbelow15ꢀofmaximum, BurstModeoperation
is employed and that level of sense current is latched onto
the IC control path. If the output load requires less than
this latched current level, the converter will overdrive the
output slightly during each switch cycle. This overdrive
conditionissensedinternallyandforcesthevoltageonthe
capacitor through an external diode so that the BOOST
voltage is above its undervoltage lockout threshold. There
is an NPN switch that pulls the SW node to ground each
cycle during the TG power MOSFET off-time, ensuring the
BOOST capacitor is kept fully charged. Once the supply
is up and running, the output voltage of the supply can
V pin to continue to drop. When the voltage on V drops
C
C
backdrive V throughanexternaldiode.Internalcircuitry
CC
150mV below the 15ꢀ load level, switching is disabled,
and the LT3724 shuts down most of its internal circuitry,
reducing total quiescent current to 100µA. When the
disables the high voltage regulator to conserve V supply
IN
current. Output voltages that are too low or too high to
backdriveV requireadditionalcircuitrysuchasavoltage
CC
converter output begins to fall, the V pin voltage begins
C
doubler or linear regulator. Once V is backdriven from
CC
to climb. When the voltage on the V pin climbs back to
C
a supply other than V , V can be reduced to 4V with
IN IN
the 15ꢀ load level, the IC returns to normal operation and
normal operation maintained.
3724fd
10
LT3724
(Refer to Functional Diagram)
OPERATIONS
Soft-Start
artificial ramp on the sensed current to increase the rising
slope as duty cycle increases.
The soft-start function controls the slew rate of the power
supply output voltage during start-up. A controlled output
voltagerampminimizesoutputvoltageovershoot,reduces
Unfortunately, this additional ramp typically affects the
sensed current value, thereby reducing the achievable
current limit value by the same amount as the added ramp
represents. As such, the current limit is typically reduced
asthedutycycleincreases.TheLT3724,however,contains
antislope compensation circuitry to eliminate the current
limitreductionassociatedwithslopecompensation.Asthe
slope compensation ramp is added to the sensed current,
a similar ramp is added to the current limit threshold. The
end result is that the current limit is not compromised so
the LT3724 can provide full power regardless of required
duty cycle.
inrush current from the V supply, and facilitates supply
IN
SS
sequencing. A capacitor, C , connected between V
of
OUT
the supply and the C pin of the IC, programs the slew
SS
rate. The capacitor provides a current to the C pin which
SS
is proportional to the dV/dt of the output voltage. The
soft-startcircuitoverridesthecontrolloopandadjuststhe
inductor current until the output voltage slew rate yields a
2µAcurrentthroughthesoft-startcapacitor.Ifthecurrentis
greater than 2µA, then the current threshold set by the DC
control voltage, V , is decreased and the inductor current
C
is lowered. This in turn lowers the output current and the
output voltage slew rate is decreased. If the current is less
than 2µA, then the current threshold set by the DC control
Shutdown
The LT3724 includes a shutdown mode where all the
internal IC functions are disabled and the V current is
voltage, V , isincreasedandtheinductorcurrentisraised.
C
IN
This in turn increases the output current and the output
voltage slew rate is increased. Once the output voltage is
within 5ꢀ of its regulation voltage, the soft-start circuit
is disabled and the main control regulates the output. The
soft-start circuit is reactivated when the output voltage
drops below 70ꢀ of its regulation voltage.
reduced to less than 10µA. The shutdown pin can be used
forundervoltagelockoutwithhysteresis,micropowershut-
downorasageneralpurposeon/offcontroloftheconverter
output. The shutdown function has two thresholds. The
first threshold, a precision 1.23V threshold with 120mV
of hysteresis, disables the converter from switching. The
second threshold, approximately a 0.7V referenced to
SGND,completelydisablesallinternalcircuitryandreduces
Slope/Antislope Compensation
the V current to less than 10µA. See the Application
The IC incorporates slope compensation to eliminate
potential subharmonic oscillations in the current control
loop. The IC’s slope compensation circuit imposes an
IN
Information section for more information.
3724fd
11
LT3724
APPLICATIONS INFORMATION
The basic LT3724 step-down (buck) application, shown
in the Typical Application on the front page, converts a
larger positive input voltage to a lower positive or negative
outputvoltage.ThisApplicationInformationsectionassists
selection of external components for the requirements of
the power supply.
mode instability may occur at duty cycles greater than
50ꢀ. Lower values of ∆I require larger and more costly
L
magnetics. A value of ∆I = 0.3 • I
produces a
L
OUT(MAX)
15ꢀ of I
ripple current around the DC output
OUT(MAX)
current of the supply.
Some magnetics vendors specify a volt-second product
in their datasheet. If they do not, consult the magnetics
vendortomakesurethespecificationisnotbeingexceeded
by your design. The volt-second product is calculated as
follows:
R
SENSE
Selection
The current sense resistor, ꢁ
, monitors the inductor
SENSE
current of the supply (See Typical Application on front
page). Itsvalueischosenbasedonthemaximumrequired
output load current. The LT3724 current sense amplifier
has a maximum voltage threshold of, typically, 150mV.
(VIN(MAX) – VOUT )• VOUT
Volt-second (µsec)=
VIN(MAX) • fSW
Therefore, the peak inductor current is 150mV/ꢁ
.
SENSE
The maximum output load current, I
, is the peak
OUT(MAX)
The magnetics vendors specify either the saturation cur-
rent, the ꢁMS current or both. When selecting an inductor
based on inductor saturation current, use the peak cur-
inductor current minus half the peak-to-peak ripple cur-
rent, ∆I .
L
Allowing adequate margin for ripple current and external
rent through the inductor, I
+ ∆I /2. The inductor
OUT(MAX)
L
component tolerances, ꢁ
lows:
can be calculated as fol-
saturation current specification is the current at which
the inductance, measured at zero current, decreases by
a specified amount, typically 30ꢀ.
SENSE
100mV
IOUT(MAX)
RSENSE
=
When selecting an inductor based on ꢁMS current rating,
use the average current through the inductor, I
.
OUT(MAX)
Typical values for ꢁ
to 0.05Ω.
are in the range of 0.005Ω
SENSE
TheꢁMScurrentspecificationistheꢁMScurrentatwhich
the part has a specific temperature rise, typically 40°C,
above 25°C ambient.
Inductor Selection
The critical parameters for selection of an inductor are
minimum inductance value, volt-second product, satura-
tion current and/or ꢁMS current.
After calculating the minimum inductance value, the volt-
secondproduct,thesaturationcurrentandtheꢁMScurrent
for your design, select an off-the-shelf inductor. A list of
magnetics vendors can be found at www.linear.com, or
contact the Linear Technology Application Department.
The minimum inductance value is calculated as follows:
V
IN(MAX) – VOUT
L ≥ VOUT
•
For more detailed information on selecting an inductor,
please see the “Inductor Selection” section of Linear
Technology Application Note 44.
fSW • VIN(MAX) • ∆IL
f
SW
is the switch frequency (200kHz).
Step-Down Converter: MOSFET Selection
The typical range of values for ∆I is (0.2 • I
) to
L
OUT(MAX)
is the maximum load
(0.5 • I
), where I
OUT(MAX)
OUT(MAX)
The selection criteria of the external N-channel standard
current of the supply. Using ∆I = 0.3 • I
yields a
L
OUT(MAX)
level power MOSFET include on resistance(ꢁ
), re-
DS(ON)
good design compromise between inductor performance
versetransfercapacitance(C ), maximumdrainsource
ꢁSS
versus inductor size and cost. Higher values of ∆I will
L
voltage (V ), total gate charge (Q ), and maximum
DSS
G
increase the peak currents, requiring more filtering on
continuous drain current.
the input and output of the supply. If ∆I is too high,
L
the slope compensation circuit is ineffective and current
3724fd
12
LT3724
APPLICATIONS INFORMATION
For maximum efficiency, minimize ꢁ
and C
.
TheinternalV regulatoroperatingrangelimitsthemaxi-
CC
DS(ON)
ꢁSS
Low ꢁ
minimizes conduction losses while low C
mum total MOSFET gate charge, Q , to 90nC. The Q vs
DS(ON)
ꢁSS
is
G G
minimizestransitionlosses.Theproblemisthatꢁ
V
GS
specification is typically provided in the MOSFET data
DS(ON)
inversely related to C . Balancing the transition losses
sheet. Use Q at V of 8V. If V is back driven from an
ꢁSS
G GS CC
with the conduction losses is a good idea in sizing the
external supply, the MOSFET drive current is not sourced
MOSFET. Select the MOSFET to balance the two losses.
from the internal regulator of the LT3724 and the Q of the
G
MOSFET is not limited by the IC. However, note that the
Calculate the maximum conduction losses of the MOSFET:
MOSFET drive current is supplied by the internal regulator
when the external supply back driving V is not available
VOUT
CC
2
PCOND =(IOUT(MAX)
Note that ꢁ
)
(RDS(ON))
such as during startup or short-circuit.
V
IN
The manufacturer’s maximum continuous drain current
specification should exceed the peak switch current,
has a large positive temperature depen-
DS(ON)
dence. The MOSFET manufacturer’s data sheet contains a
curve, ꢁ vs Temperature.
I
+ ∆I /2.
OUT(MAX)
L
DS(ON)
During the supply startup, the gate drive levels are set by
the V voltage regulator, which is approximately 8V. Once
Calculate the maximum transition losses:
CC
2
the supply is up and running, the V can be back driven
P
= (k)(V ) (I
)(C )(f )
OUT(MAX) ꢁSS SW
CC
TꢁAN
IN
by an auxiliary supply such as V . It is important not to
OUT
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3724 applications.
exceed the manufacturer’s maximum V specification.
GS
A standard level threshold MOSFET typically has a V
GS
maximum of 20V.
The total maximum power dissipation of the MOSFET is
the sum of these two loss terms:
Step-Down Converter: Rectifier Selection
P
= P
+ P
FET(TOTAL)
COND TꢁAN
The rectifier diode (D1 on the Functional Diagram) in a
buck converter generates a current path for the inductor
current when the main power switch is turned off. The
rectifier is selected based upon the forward voltage, re-
verse voltage and maximum current. A Schottky diode is
recommended. Its low forward voltage yields the lowest
power loss and highest efficiency. The maximum reverse
To achieve high supply efficiency, keep the P
to
FET(TOTAL)
less than 3ꢀ of the total output power. Also, complete
a thermal analysis to ensure that the MOSFET junction
temperature is not exceeded.
T = T + P
• θ
JA
J
A
FET(TOTAL)
where θ is the package thermal resistance and T is the
JA
A
voltage that the diode will see is V
.
IN(MAX)
ambient temperature. Keep the calculated T below the
J
In continuous mode operation, the average diode cur-
rent is calculated at maximum output load current and
maximum specified junction temperature, typically 150°C.
Note that when V is high, the transition losses may
IN
maximum V :
IN
dominate. A MOSFET with higher ꢁ
and lower C
DS(ON)
ꢁSS
may provide higher efficiency. MOSFETs with higher volt-
age V specification usually have higher ꢁ and
VIN(MAX) − VOUT
IDIODE(AVG) =IOUT(MAX)
DSS
lower C
DS(ON)
V
IN(MAX)
.
ꢁSS
To improve efficiency and to provide adequate margin for
short-circuit operation, a diode rated at 1.5 to 2 times the
Choose the MOSFET V
specification to exceed the
DSS
maximum voltage across the drain to the source of the
MOSFET, which is V plus any additional ringing
maximum average diode current, I
mended.
, is recom-
DIODE(AVG)
IN(MAX)
on the switch node. ꢁinging on the switch node can be
greatly reduced with good PCB layout and, if necessary,
an ꢁC snubber.
3724fd
13
LT3724
APPLICATIONS INFORMATION
Step-Down Converter: Input Capacitor Selection
Step-Down Converter: Output Capacitor Selection
The output capacitance, C , selection is based on the
Alocalinputbypasscapacitorisrequiredforbuckconvert-
ers because the input current is pulsed with fast rise and
fall times. The input capacitor selection criteria are based
on the bulk capacitance and ꢁMS current capability. The
bulk capacitance will determine the supply input ripple
voltage. The ꢁMS current capability is used to keep from
overheating the capacitor.
OUT
design’s output voltage ripple, ∆V , and transient load
OUT
requirements. ∆V
is a function of ∆I and the C
OUT
L OUT
ESꢁ. It is calculated by:
1
∆VOUT = ∆IL • ESR+
(8 • fSW •COUT
)
The bulk capacitance is calculated based on maximum
The maximum ESꢁ required to meet a ∆V
requirement can be calculated by:
design
OUT
input ripple, ∆V :
IN
I
OUT(MAX) • VOUT
(∆VOUT )(L)(fSW )
ESR(MAX)=
CIN(BULK)
=
∆V • fSW • V
IN
IN(MIN)
VOUT
VOUT • 1–
V
IN(MAX)
∆V is typically chosen at a level acceptable to the user.
IN
100mV-200mV is a good starting point. Aluminum elec-
trolytic capacitors are a good choice for high voltage, bulk
capacitance due to their high capacitance per unit area.
Worst-case ∆V
occurs at highest input voltage. Use
OUT
paralleled multiple capacitors to meet the ESꢁ require-
ments. Increasing the inductance is an option to lower the
The capacitor’s ꢁMS current is:
ESꢁrequirements. Forextremelylow∆V , anadditional
OUT
LC filter stage can be added to the output of the supply.
Application Note 44 has some good tips on sizing an ad-
ditional output filter.
V
(V – V
)
OUT IN
OUT
I
= I
CIN(RMS) OUT
2
(V )
IN
If applicable, calculate it at the worst case condition,
= 2V . The ꢁMS current rating of the capacitor
Output Voltage Programming
V
IN
OUT
A resistive divider sets the DC output voltage according
to the following formula:
is specified by the manufacturer and should exceed the
calculated I . Due to their low ESꢁ (Equivalent
CIN(ꢁMS)
Series ꢁesistance), ceramic capacitors are a good choice
for high voltage, high ꢁMS current handling. Note that the
ripplecurrentratingsfromaluminumelectrolyticcapacitor
manufacturersarebasedon2000hoursoflife.Thismakes
it advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
VOUT
1.231V
R2=R1
–1
The external resistor divider is connected to the output
of the converter as shown in Figure 2. Tolerance of the
feedback resistors will add additional error to the output
voltage.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meet-
ing the input capacitor requirements. The capacitor volt-
Example: V
= 12V; ꢁ1 = 10kΩ
OUT
12V
1.231V
age rating must be rated greater than V
. Multiple
IN(MAX)
R2=10kΩ
−1 = 87.48kΩ−use 86.6kΩ1%
capacitors may also be paralleled to meet size or height
requirementsinthedesign.Locatethecapacitorveryclose
to the MOSFET switch and use short, wide PCB traces to
minimize parasitic inductance.
3724fd
14
LT3724
APPLICATIONS INFORMATION
V
L1
SUPPLY
V
OUT
RA
RB
C
R2
R1
OUT
SHDN PIN
V
PIN
FB
3724 F03
3724 F02
Figure 2. Output Voltage Feedback Divider
Figure 3. Undervoltage Lockout Circuit
The V pin input bias current is typically 25nA, so use
If additional hysteresis is desired for the enable function,
an external positive feedback resistor can be used from
the LT3724 regulator output.
FB
of extremely high value feedback resistors could cause a
converter outputthatisslightlyhigherthan expected. Bias
current error at the output can be estimated as:
The shutdown function can be disabled by connecting the
∆V
= 25nA • R2
SHDN pin to the V through a large value pull-up resistor.
OUT(BIAS)
IN
Thispincontainsalowimpedanceclampat6V,sotheSHDN
Supply UVLO and Shutdown
pin will sink current from the pull-up resistor(ꢁ ):
PU
The SHDN pin has a precision voltage threshold with
hysteresis which can be used as an undervoltage lockout
threshold (UVLO) for the power supply. Undervoltage
lockout keeps the LT3724 in shutdown until the supply
input voltage is above a certain voltage programmed by
theuser.Thehysteresisvoltagepreventsnoisefromfalsely
tripping UVLO.
V – 6V
RPU
IN
ISHDN
=
Because this arrangement will clamp the SHDN pin to the
6V,itwillviolatethe5Vabsolutemaximumvoltageratingof
the pin. This is permitted, however, as long as the absolute
maximum input current rating of 1mA is not exceeded.
Input SHDN pin currents of <100µA are recommended: a
1MΩ or greater pull-up resistor is typically used for this
configuration.
ꢁesistors are chosen by first selecting ꢁB. Then:
V
⎛
⎞
SUPPLY(ON)
RA =RB •
–1
⎟
⎜
1.35V
⎝
⎠
Soft-Start
V
is the input voltage at which the undervoltage
SUPPLY(ON)
The soft-start function forces the programmed slew rate
while the converter output rises to 95ꢀ of regulation,
lockout is disabled and the supply turns on.
Example:SelectꢁB=49.9kΩ,V =14.5V(based
which corresponds to 1.185V on the V pin. Once 95ꢀ
SUPPLY(ON)
FB
on a 15V minimum input voltage)
regulation is achieved, the soft-start circuit is disabled.
The soft-start circuit will re-enable when the V pin drops
FB
14.5V
1.35V
⎛
⎝
⎞
⎠
RA = 49.9kΩ •
–1
below 70ꢀ of regulation, which corresponds to 300mV
⎜
⎟
of control hysteresis on the V pin. This allows for a
FB
controlled recovery from a “brown-out” condition.
= 486.1kΩ (499kΩ resistor is selected)
If low supply current in standby mode is required, select
a higher value of ꢁB.
LT3724
C
SS1
R
SS
A
V
C
OUT
SS
The supply turn off voltage is 9ꢀ below turn on. In the
3724 F04
example the V
would be 13.2V.
SUPPLY(OFF)
Figure 4.Soft-Start Circuit
3724fd
15
LT3724
APPLICATIONS INFORMATION
The desired soft-start rise time (t ) is programmed via
SS
V
OUT
a programming capacitor C , using a value that cor-
SS1
responds to 2µA average current during the soft-start
interval. This capacitor value follows the relation:
2•10–6 • tSS
V
OUT(SS)
C
CSS1
=
V(V )
VOUT
ꢁ
SS
is typically set to 200k for most applications.
TIME, 250µs/DIV
3724 F05
Considerations for Low-Voltage Output Applications
Figure 5. Soft-Start Characteristic
Showing Excessive Ripple Component
The LT3724 C pin biases to 220mV during the soft-start
SS
cycle, and this voltage is increased at Figure 4 node “A” by
the 2µA signal current through ꢁ , so the output has to
SS
V
OUT
reach this value before the soft-start function is engaged.
The value of this output soft-start startup voltage offset
(V ) follows the relation:
OUT(SS)
– 6
V
= 220mV + ꢁ • 2 • 10
SS
OUT(SS)
V
OUT(SS)
V(V )
C
Which is typically 0.64V for ꢁ = 200k.
SS
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start startup voltage
TIME, 250µs/DIV
3724F06
offset. This is possible by reducing the value of ꢁ . With
Figure 6. Desirable Soft-Start Characteristic
SS
reduced values of ꢁ , the signal component caused by
SS
voltage ripple on the output must be minimized for proper
Thisistypicallyaccomplishedbyincreasingoutputcapaci-
tance and/or reducing output capacitor ESꢁ.
soft-start operation.
Peak-to-peakoutputvoltageripple(∆V )willbeimposed
OUT
External Current Limit Foldback Circuit
on node “A” through the capacitor C . The value of ꢁ
SS1
SS
can be set using the following equation:
An additional startup voltage offset can occur during the
period before the LT3724 soft-start circuit becomes ac-
∆VOUT
1.3•10–6
RSS
=
tive. Before the soft-start circuit throttles back the V pin
C
in response to the rising output voltage, current as high
as the peak programmed current limit (I
) can flow in
MAX
ItisimportanttouselowESꢁoutputcapacitorsforLT3724
voltage converter designs to minimize this ripple voltage
component. A design with an excessive ripple component
the switched inductor. Switching will stop once the soft-
start circuit takes hold and reduces the voltage on the
V pin, but the output voltage will continue to increase
C
can be evidenced by observing the V pin during the start
C
as the stored energy in the inductor is transferred to the
cycle.
output capacitor. With I
in the inductor, the resulting
due to energy stored in the
MAX
The soft-start cycle should be evaluated to verify that the
leading-edge rise on V
OUT
reduced ꢁ value allows operation without excessive
SS
inductor follows the relation:
modulation of the V pin before finalizing the design.
C
1/2
L
If V pin has an excessive ripple component during the
C
∆VOUT =IMAX
•
soft-startcycle,converteroutputrippleshouldbereduced.
C
OUT
3724fd
16
LT3724
APPLICATIONS INFORMATION
V
Inductor current typically does not reach I
in the few
C
MAX
cyclesthatoccurbeforesoft-startbecomesactive,butcan
with high input voltages or small inductors, so the above
relation is useful as a worst-case scenario.
1N4148
1N4148
27k
This energy transfer increase in output voltage is typically
small,butforsomelowvoltageapplicationswithrelatively
smalloutputcapacitors,itcanbecomesignificant. Thevolt-
age rise can be reduced by increasing output capacitance,
39k
V
OUT
3724 F07
which puts additional limitations on C
for these low
OUT
Figure 8. Current Limit Foldback Circuit for Applications
that have Soft-Start Disabled (CSS Pin Shorted to SGND)
voltage supplies. Another approach is to add an external
current limit foldback circuit which reduces the value of
I
during start-up.
MAX
Efficiency Considerations
An external current limit foldback circuit can be easily
incorporated into an LT3724 DC/DC converter application
by placing a 1N4148 diode and a 47kΩ resistor from the
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100ꢀ. Express
percent efficiency as:
converteroutput(V )totheLT3724’sV pin. Thislimits
OUT
C
OUT
the peak current to 0.25 • I
when V
= 0V. A cur-
MAX
ꢀ Efficiency = 100ꢀ - (L1 + L2 + L3 + ...)
rent limit foldback circuit also has the added advantage of
providing reduced output current in the DC/DC converter
during short-circuit fault conditions, so a foldback circuit
may be useful even if the soft-start function is disabled.
where L1, L2, etc. are individual loss terms as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main contributors usually account for most
of the losses in LT3724 circuits:
If the soft-start circuit is disabled by shorting the C pin
SS
to ground, the external current limit foldback circuit must
be modified by adding an additional diode and resistor.
The 2-diode, 2-resistor network shown also provides 0.25
1. LT3724 V and V current loss
IN
CC
2
2. I ꢁ conduction losses
• I
MAX
when V
= 0V.
OUT
3. MOSFET transition loss
4. Schottky diode conduction loss
V
C
1N4148
47k
1. The V and V currents are the sum of the quiescent
IN
CC
currents of the LT3724 and the MOSFET drive currents.
The quiescent currents are in the LT3724 Electrical Char-
acteristics table. The MOSFET drive current is a result
of charging the gate capacitance of the power MOSFET
3724 F03
V
OUT
each cycle with a packet of charge, Q . Q is found in
G
G
the MOSFET data sheet. The average charging current is
Figure 7. Current Limit Foldback Circuit
for Applications that use Soft-Start
calculated as Q • f . The power loss term due to these
G
SW
currents can be reduced by backdriving V with a lower
CC
voltage than V such as V
.
IN
OUT
3724fd
17
LT3724
APPLICATIONS INFORMATION
2. I ꢁ losses are calculated from the DC resistances of the
2
capacitor, and the ground return of the V capacitor. This
CC
MOSFET, theinductor, thesenseresistor, andtheinputand
outputcapacitors.Incontinuousconductionmodetheaver-
ground has very fast high currents and is considered the
noisy ground. The two grounds are connected to each
age output current flows through the inductor and ꢁ
other only at the (–) terminal of V
.
SENSE
OUT
but is chopped between the MOSFET and the Schottky
2.UseshortwidetracesintheloopformedbytheMOSFET,
the Schottky diode and the input capacitor to minimize
high frequency noise and voltage stress from parasitic
inductance. Surface mount components are preferred.
diode. The resistances of the MOSFET (ꢁ ) and the
DS(ON)
ꢁ
multiplied by the duty cycle can be summed with
SENSE
the resistances of the inductor and ꢁ
to obtain the
SENSE
total series resistance of the circuit. The total conduction
power loss is proportional to this resistance and usually
accounts for between 2ꢀ to 5ꢀ loss in efficiency.
3. Connect the V pin directly to the feedback resistors
FB
–
independent of any other nodes, such as the SENSE pin.
Connect the feedback resistors between the (+) and (–)
3. Transition losses of the MOSFET can be substantial with
input voltages greater than 20V. See MOSFET Selection
section.
terminals of C . Locate the feedback resistors in close
OUT
proximity to the LT3724 to keep the high impedance node,
V , as short as possible.
FB
4. The Schottky diode can be a major contributor of power
loss especially at high input to output voltage ratios (low
duty cycles) where the diode conducts for the majority
–
+
4. ꢁoute the SENSE and SENSE traces together and
keep as short as possible.
5. LocatetheV andBOOSTcapacitorsincloseproximity
of the switch period. Lower V reduces the losses. Note
CC
f
to the IC. These capacitors carry the MOSFET driver’s high
peak currents. Place the small signal components away
from high frequency switching nodes (BOOST, SW, and
TG). In the layout shown in Figure 9, place all the small
signal components on one side of the IC and all the power
components on the other. This helps to keep the signal
and power grounds separate.
that oversizing the diode does not always help because
as the diode heats up the V is reduced and the diode loss
f
term is decreased.
2
I ꢁ losses and the Schottky diode loss dominate at high
load currents. Other losses including C and C
ESꢁ
IN
OUT
dissipative losses and inductor core losses generally ac-
count for less than 2ꢀ total additional loss in efficiency.
6. A small decoupling capacitor (100pF) is sometimes
useful for filtering high frequency noise on the feedback
and sense nodes. If used, locate as close to the IC as
possible.
PCB Layout Checklist
When laying out the printed circuit board, the following
checklistshouldbeusedtoensureproperoperation.These
items are illustrated graphically in the layout diagram of
Figure 9.
7. The LT3724 packaging will efficiently remove heat from
theICthroughtheexposedpadonthebacksideofthepart.
The exposed pad is soldered to a copper footprint on the
PCB. Make this footprint as large as possible to improve
the thermal resistance of the IC case to ambient air. This
helps to keep the LT3724 at a lower temperature.
1. Keepthesignalandpowergroundsseparate. Thesignal
groundconsistsoftheLT3724SGNDpin, theexposedpad
on the backside of the LT3724 IC and the (–) terminal of
V
. The signal ground is the quiet ground and does not
OUT
containanyhigh,fastcurrents.Thepowergroundconsists
of the Schottky diode anode, the (–) terminal of the input
8. Make the trace connecting the gate of MOSFET M1 to
the TG pin of the LT3724 short and wide.
3724fd
18
LT3724
APPLICATIONS INFORMATION
+
V
IN
R
A
C
BOOST
C
IN
16
1
V
BOOST
TG
IN
–
V
IN
15
14
M1
LT3724
L1
R
SENSE
R
B
3
4
+
SHDN
SW
C
D2
D3
SS
17
R
CSS
C
12
11
10
9
5
6
7
SS
V
BURST_EN
CC
C
OUT
C
VCC
V
OUT
V
PGND
FB
D1
+
V
C
SENSE
R2
R
8
C
–
SGND
SENSE
C
–
C1
R1
C
C2
3724 F06
Figure 9. LT3724 Layout Diagram (See PCB Layout Checklist).
Minimum On-Time Considerations
(Step-Down Converters)
200kHz,therefore,theminimumdutycycleoftheMOSFET
switch is 6ꢀ. When the duty cycle needs to be less than
6ꢀ the output will stay regulated, but cycle skipping may
occur. Cycle skipping results in an increase in inductor
ripple current. If it is important that cycle skipping does
not occur, follow this guideline which takes into account
Minimum on-time (t ) is the least amount of time
TG(ON)
that the LT3724 is capable of turning the MOSFET on and
then off again. It is determined by internal timing delays
andthegatechargeoftheMOSFET. Applicationswithhigh
input to output differential voltages operate at low duty
cycles and may approach this minimum on-time, typically
300nS. TheLT3724switchingfrequencyisinternallysetto
worst case f and t
:
SW
TG(ON)
V
≤ 9 • V
OUT
IN(MAX)
This is only an issue for supplies with V
< 7V.
OUT
3724fd
19
LT3724
TYPICAL APPLICATIONS
12V to 24V/50W Boost (Step-Up) Converter
D1
BAV99
R
SENSE
0.015Ω
16
15
14
1
V
IN
V
BOOST
TG
IN
8V TO16V
C
IN
0.1µF
25V
L1
R3
4.7M
33µF ×2
10µH
D2
25V
LT3724
V
OUT
24V AT 50W
3
C1
1500pF
SHDN
SW
SBM540
R
CSS
200k
4
C
SS
M1
12
11
10
9
5
6
7
R2
C
C
OUT2
OUT1
V
BURST_EN
CC
187k
330µF
35V
2.2µF x3
50V
C4
1µF
25V
V
PGND
FB
+
V
C
SENSE
R1
10k
R6
8
–
40.2k
C2
120pF
SGND
SENSE
C
= SANYO, 25SVP33M
L1 = VISHAY, IHLP-5050FD-011
M1 = SILICONIX, Si7370DP
IN
C3
4700pF
C
C
= SANYO, 35CV330AXA
= TDK, C4532X7R1H225K
OUT1
OUT2
D2 = DIODESINC., SBM540
3724 TA02
R
= IRC LRF2512-01-R0I5-F
SENSE
Efficiency and Power Loss vs Load Current
100
98
96
94
92
90
88
3.0
2.5
2.0
1.5
1.0
0.5
0
LOSS
IN
V
= 12V
V
= 16V
= 12V
IN
V
IN
V
= 8V
IN
0.1
1
10
LOAD CURRENT (A)
3724 F08
3724fd
20
LT3724
TYPICAL APPLICATIONS
High Voltage LED Driver with Dimmer Control
LED
L1
300µH
V
IN
8V TO 60V
C1
C
IN
(OPTIONAL)
22µF
D1
16
15
14
1
V
BOOST
TG
B170
IN
M1
R1
4.7M
ZXMN10A07F
OPTIONAL
DIMMER
CONTROL
LT3724
3
4
SHDN
SW
C
VCC
M2
2N7002
1µF
C
SS
16V
1kHz
12
11
10
9
5
6
7
V
BURST_EN
CC
ADJUST I
:
LED
0.15V
V
FB
PGND
I
=
LED
C1 = OPTIONAL TO REDUCE LED RIPPLE CURRENT
R
SENSE
+
V
C
SENSE
C
= TDK, C4532X7R2A225K
IN
R
D1 = DIODESINC., B170
SENSE
8
–
0.5Ω
SGND
M1 = ZETEX, ZXMN10A07F
SENSE
C1
100pF
R
= VISHAY, WSL2010R0150FEA
SENSE
L1 = COILTRONICS, CTX300-4
3724 TA03
3724fd
21
LT3724
TYPICAL APPLICATIONS
4.5V to 20V Input to 12V at 25W Output SEPIC Converter with 60V Input Transient Capability
V
IN
4.5V TO 20V
TO 60V
C
C
25V
1µF
IN1
IN2
•
D1B
L1
22µF
2x
TRANSIENT
GSD2004
RA
20µH
16
1
3
C5
22µF
3x
100k
25V
V
BOOST
IN
C7
0.1µF
V
OUT
M1
15
14
12V AT 25W
SHDN
TG
25V
D2
C1
RB
49.9k
R3
390pF
SW
200k
LT3724
4
5
R6
10Ω
C
SS
C
OUT1
12
11
L1
20µH
330µF
16V
R2
130k
V
CC
BURST_EN
C4
6
C6
•
1µF
V
FB
PGND
56pF
25V
C
OUT2
R
SENSE
7
8
10
9
22µF
25V
+
R7
0.010Ω
V
C
SENSE
10Ω
R1
14.7k
R4
47k
R5
40.2k
C3
680pF
–
SGND
C2
120pF
SENSE
D1A
GSD2004
3724 TA07a
C5, C , C
OUT1
D2 = ON SEMI, MBRD660
= TDKC453X7R1E226M
IN1 OUT2
D3
D1N4148
C
= SANYO, OS-CON 16SVP330M
L1 = COILCRAFT VERSAPAC VP5-D83
M1 = VISHAY, Si7852DP
Efficiency and Power Loss
vs Load Current
92
91
90
89
88
87
86
85
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 20V
IN
V
= 15V
IN
V
= 10V
IN
LOSS
= 15V
V
IN
0.1
1
10
LOAD CURRENT (A)
3724 TA07b
3724fd
22
LT3724
TYPICAL APPLICATIONS
12V Step-Down with VCC Back Driven from VOUT and Ceramic Capacitor in Output Filter
V
IN
15V TO 60V
C6
0.1µF
16V
+
C
IN
2.2µF x2
100V
100µF
100V
R2
16
1
3
499k
V
BOOST
IN
R3
49.9k
R7
20Ω
15
14
M1
Si7852DP
SHDN
TG
C1
3300pF
SW
LT3724
R
CSS
4
V
C
OUT
D2A
SS
12V AT 50W
200k
BAV99
12
11
10
9
5
6
7
8
L1
47µH
R4
R
SENSE
V
BURST_EN
CC
130k
C4
0.020Ω
1µF
V
PGND
FB
D2B
BAV99
16V
C
OUT
D1
33µF x3
16V
+
V
C
SENSE
R6
15k
R5
14.7k
–
SGND
C2
120pF
SENSE
C3
680pF
3724 TA04
C
C
: TDK, C4532X7R2A225MT
OUT
IN
: TDK, C4532X7R1C336MT
D1: DIODESINC., PDS5100H
L1: COEV DU1971-470M
M1: VISHAY Si7852DP
3724fd
23
LT3724
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
0.48
(.019)
REF
3.58
(.141)
16 1514 13 12 11 109
6.60 ±0.10
0.51
(.020)
REF
2.94
DETAIL B
(.116)
4.50 ±0.10
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
DETAIL B IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
0.45 ±0.05
1.05 ±0.10
NO MEASUREMENT PURPOSE
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP REV I 1210
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3724fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24
LT3724
REVISION HISTORY (Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
3/11
Deleted last paragraph of Description
1
7
Minor text edits made to SW and BOOST pin descriptions in Pin Functions section
Minor text edits made to Main Control Loop and Current Limit/Short Circuit sections in Operations
ꢁevised High Voltage LED Driver with Dimmer Control in Typical Applications
ꢁevised Typical Application drawing and ꢁelated Parts list
9
21
24
3724fd
25
LT3724
TYPICAL APPLICATION
Inverting –12V 1.5A Converter
V
IN
18V TO 36V
0.1µF
16V
R3
+
C
IN1
16
15
1
2M
220µF
50V
V
IN
BOOST
0.1µF
LT3724
M1
TG
L1
47µH
14
12
3
4
SHDN
SW
D1A
C
SS
D1B
D2
C
R
CSS
SS
V
CC
1000pF
200k
R1
88.7k
1µF
16V
V
OUT
–12V
1.5A
11
10
9
6
7
V
V
PGND
FB
C
R6, 40.2k
+
R2
10.2k
SENSE
R
C
C
C
SENSE
OUT1
C2
C1
0.040Ω
330µF
680pF
120pF
8
+
16V
–
GND
SENSE
D1 = BAV99
D2 = ON SEMI, MBRD350
L1 = COEV, DU1311-470M
M1 = VISHAY, Si7370DP
3724 TA05
C
C
= SANYO, 50CV220KX
IN1
OUT1
= SANYO, 16SVP330M
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Adjustable Fixed Frequency 100kHz to 500kHz, 4V≤ V ≤ 60V, 1.23V ≤
LT3845A
60V, Low I , High Voltage Synchronous
Q
IN
Step-Down DC/DC Controller
V
≤ 36V, I = 120µA, TSSOP-16
OUT Q
LTC3891
LT3844
LT3741
LTC3824
60V, Low I , High Voltage Synchronous
Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V
IN
Q
Step-Down DC/DC Controller
≤ V
≤ 24V, I = 50µA
OUT Q
60V, Low I , Single Output Step-Down
Synchronizable Fixed Frequency 50kHz to 600kHz, 4V≤ V ≤ 60V, 1.23V
IN
Q
DC/DC Controller
≤ V
≤ 36V, I = 120µA, TSSOP-16
OUT Q
High Power, Constant Current, Constant Voltage,
Step-Down Controller
Fixed 200kHz to 1MHz Operating Frequency, 6ꢀ Current ꢁegulation,
6V≤ V ≤ 36V, V Up to (V - 2V)
IN
OUT
IN
60V, Low I , Step-Down DC/DC Controller with
Selectable Fixed Frequency 200kHz to 600kHz, 4V≤ V ≤ 60V, 0.8V ≤
IN
Q
100ꢀ Duty Cycle
V
≤ V , I = 40µA, MSOP-10E
OUT IN Q
LTC3834/LTC3834-1 Low I , Single Output Synchronous Step-Down
Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V≤ V ≤ 36V, 0.8V
IN
Q
LTC3835/LTC3835-1 DC/DC Controller with 99ꢀ Duty Cycle
≤ V
≤ 10V, I = 30µA/80µA
OUT Q
LTC3859
Low I , Triple Output Buck/Buck/Boost
All Outputs ꢁemain in ꢁegulation Through Cold Crank 2.5V≤ V ≤ 38V,
IN
Q
Synchronous DC/DC Controller
V
Up to 24V, V
Up to 60V, I = 55µA
OUT(BUCKS)
OUT(BOOST) Q
3724fd
LT 0311 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
26
●
●
LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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