LTC3891EUDC#TRPBF [Linear]
LTC3891 - Low IQ, 60V Synchronous Step-Down Controller; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C;型号: | LTC3891EUDC#TRPBF |
厂家: | Linear |
描述: | LTC3891 - Low IQ, 60V Synchronous Step-Down Controller; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C 开关 |
文件: | 总32页 (文件大小:666K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3891
Low I , 60V Synchronous
Q
Step-Down Controller
FEATURES
DESCRIPTION
TheLTC®3891isahighperformancestep-downswitching
regulator DC/DC controller that drives an all N-channel
synchronous power MOSFET stage. A constant fre-
quencycurrentmodearchitectureallowsaphase-lockable
frequency of up to 750kHz.
n
Wide V Range: 4V to 60V (65V Abs Max)
IN
n
Low Operating I : 50μA
Q
n
Wide Output Voltage Range: 0.8V ≤ V
≤ 24V
OUT
n
n
n
n
R
SENSE
or DCR Current Sensing
Phase-Lockable Frequency (75kHz to 750kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Load
The50μAno-loadquiescentcurrentextendsoperatingrun
timeinbattery-poweredsystems.OPTI-LOOP® compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3891 features a precision 0.8V reference and power
goodoutputindicator. Awide4Vto60Vinputsupplyrange
encompasses a wide range of intermediate bus voltages
andbatterychemistries. TheoutputvoltageoftheLTC3891
can be programmed between 0.8V to 24V.
n
n
n
n
n
n
n
n
n
Selectable Current Limit
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Power Good Output Voltage Monitor
Output Overvoltage Protection
Low Shutdown I : < 14μA
Q
Internal LDO Powers Gate Drive from V or EXTV
IN
CC
The TRACK/SS pin ramps the output voltages during
start-up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The PLLIN/MODE pin se-
lects among Burst Mode operation, pulse-skipping mode,
or continuous conduction mode at light loads.
L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Patents, including 5481178, 5705919, 6611131, 6498466, 6580258,
7230497.
No Current Foldback During Start-Up
Small 20-Pin 3mm × 4mm QFN and TSSOP Packages
APPLICATIONS
n
Automotive Always-On Systems
n
Battery Powered Digital Devices
n
Distributed DC Power Systems
TYPICAL APPLICATION
Efficiency and Power Loss vs
Output Current
High Efficiency 3.3V Step-Down Converter
V
IN
4V TO 60V
10000
1000
100
100
90
80
70
60
50
40
30
20
V
V
= 12V
IN
OUT
= 3.3V
22µF
V
IN
INTV
CC
LTC3891
2.2µF
TG
41.2k
FREQ
ITH
0.1µF
2200pF
100pF
BOOST
SW
4.7µH
10k
8mΩ
V
3.3V
5A
10
OUT
150µF
BG
1
0.1µF
+
10
0
TRACK/SS
SGND
SENSE
0.1
10
–
0.0001 0.001
0.01
0.1
1
100k
SENSE
OUTPUT CURRENT (A)
V
3891 TA01b
FB
100k
INTV
PGOOD
CC
31.6k
3891 TA01a
3891fa
1
LTC3891
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ITH, V Voltages......................................... –0.3V to 6V
Input Supply Voltage (V )......................... –0.3V to 65V
FB
IN
PGOOD Voltage............................................ –0.3V to 6V
TRACK/SS Voltage....................................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3891E, LTC3891I.......................... –40°C to 125°C
LTC3891H .......................................... –40°C to 150°C
LTC3891MP ....................................... –55°C to 150°C
Maximum Junction Temperature (Notes 2, 3)
Topside Driver Voltage (BOOST).................–0.3V to 71V
Switch Voltage (SW)..................................... –5V to 65V
(BOOST-SW)................................................ –0.3V to 6V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin from
Source > 8V......................................................100μA
+
–
SENSE , SENSE Voltages ......................... –0.3V to 28V
LTC3891E, LTC3891I......................................... 125°C
LTC3891H, LTC3891MP.................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
PLLIN/MODE, INTV Voltages ................... –0.3V to 6V
CC
I
, FREQ Voltages ..............................–0.3V to INTV
LIM
CC
EXTV ...................................................... –0.3V to 14V
CC
PIN CONFIGURATION
TOP VIEW
TOP VIEW
TRACK/SS
FREQ
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
I
LIM
V
IN
20 19 18 17
PLLIN/MODE
SGND
PGND
EXTV
PLLIN/MODE
SGND
1
2
3
4
5
6
16 PGND
15 EXTV
CC
CC
SGND
14 INTV
13 BG
SGND
INTV
BG
21
SGND
CC
CC
21
SGND
RUN
RUN
–
–
SENSE
12 BOOST
11 SW
SENSE
BOOST
SW
+
SENSE
+
SENSE
7
8
9 10
V
TG
FB
ITH 10
PGOOD
FE PACKAGE
20-LEAD PLASTIC TSSOP
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
= 150°C, θ = 43°C/W
T
= 150°C, θ = 38°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
T
JMAX
JA
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3891EUDC#PBF
LTC3891IUDC#PBF
LTC3891HUDC#PBF
LTC3891MPUDC#PBF
TAPE AND REEL
PART MARKING*
LFXV
PACKAGE DESCRIPTION
20-Lead (3mm × 4mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
LTC3891EUDC#TRPBF
LTC3891IUDC#TRPBF
LTC3891HUDC#TRPBF
LTC3891MPUDC#TRPBF
LFXV
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LFXV
LFXV
3891fa
2
LTC3891
ORDER INFORMATION
LEAD FREE FINISH
LTC3891EFE#PBF
LTC3891IFE#PBF
LTC3891HFE#PBF
LTC3891MPFE#PBF
TAPE AND REEL
PART MARKING*
LTC3891FE
PACKAGE DESCRIPTION
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LTC3891EFE#TRPBF
LTC3891IFE#TRPBF
LTC3891HFE#TRPBF
LTC3891MPFE#TRPBF
LTC3891FE
LTC3891FE
LTC3891FE
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Supply Operating Voltage Range
Regulated Feedback Voltage
4
60
V
IN
V
FB
(Note 4); I Voltage = 1.2V
TH
–40°C to 85°C
0.792
0.788
0.786
0.800
0.800
0.800
0.808
0.812
0.812
V
V
V
l
l
LTC3891E, LTC3891I
LTC3891H, LTC3891MP
I
Feedback Current
(Note 4)
5
50
0.02
0.1
nA
%/V
%
FB
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 4); V = 4.5V to 60V
0.002
0.01
REFLNREG
LOADREG
IN
l
l
(Note 4)
Measured in Servo Loop;
∆I Voltage = 1.2V to 0.7V
TH
(Note 4)
–0.01
2
–0.1
%
Measured in Servo Loop;
∆I Voltage = 1.2V to 2V
TH
g
Transconductance Amplifier g
Input DC Supply Current
(Note 4); I = 1.2V; Sink/Source 5µA
mmho
m
m
TH
I
Q
(Note 5)
Pulse Skip or Forced Continuous Mode
Sleep Mode
V
V
= 0.83V (No Load)
= 0.83V (No Load)
2
mA
µA
µA
FB
FB
50
14
75
25
Shutdown
RUN = 0V
INTV Ramping Up
INTV Ramping Down
l
l
UVLO
Undervoltage Lockout
3.92
3.80
4.2
4.0
V
V
CC
CC
3.6
7
V
OVL
Feedback Overvoltage Protection
Measured at V Relative to Regulated V
10
13
1
%
FB
FB
+
–
+
I
I
SENSE Pin Current
µA
SENSE
SENSE
–
–
–
SENSE Pins Current
V
V
< INTV – 0.5V
2
µA
µA
SENSE
SENSE
CC
> INTV + 0.5V
700
99
CC
DF
Maximum Duty Factor
In Dropout
98
7
%
µA
V
MAX
I
Soft-Start Charge Current
RUN Pin On Threshold
V
V
= 0V
TRACK
10
14
TRACK/SS
l
V
V
V
On
Rising
RUN
1.15
1.21
50
1.27
RUN
Hyst
RUN Pin Hysteresis
mV
RUN
–
–
–
l
l
l
Maximum Current Sense Threshold
V
V
V
= 0.7V, V
= 0.7V, V
= 0.7V, V
= 3.3V, I = 0
22
43
64
30
50
75
36
57
85
mV
mV
mV
SENSE(MAX)
FB
FB
FB
SENSE
SENSE
SENSE
LIM
LIM
LIM
= 3.3V, I = INTV
CC
= 3.3V, I = FLOAT
3891fa
3
LTC3891
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL
Gate Driver
TG
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.5
Ω
Ω
BG
Pull-Up On-Resistance
Pull-Down On-Resistance
2.4
1.1
Ω
Ω
TG t
TG t
TG Transition Time:
Rise Time
(Note 6)
LOAD
LOAD
r
f
C
C
= 3300pF
= 3300pF
25
16
ns
ns
Fall Time
BG t
BG t
BG Transition Time:
Rise Time
(Note 6)
LOAD
LOAD
r
f
C
C
= 3300pF
= 3300pF
25
13
ns
ns
Fall Time
TG/BG t
BG/TG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
= 3300pF
30
30
95
ns
ns
ns
1D
1D
LOAD
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
= 3300pF
LOAD
t
Minimum On-Time
(Note 7)
ON(MIN)
INTV Linear Regulator
CC
V
V
V
V
Internal V Voltage
6V < V < 60V, V = 0V
EXTVCC
4.85
4.85
5.1
0.7
5.1
0.6
5.35
1.1
V
%
V
INTVCCVIN
LDOVIN
CC
IN
INTV Load Regulation
I
= 0mA to 50mA, V
= 0V
CC
CC
EXTVCC
Internal V Voltage
6V < V < 13V
EXTVCC
5.35
1.1
INTVCCEXT
LDOEXT
CC
INTV Load Regulation
I
V
= 0mA to 50mA,
CC
EXTVCC
%
CC
= 8.5V
V
V
EXTV Switchover Voltage
I = 0mA to 50mA,
CC
4.5
4.7
4.9
V
EXTVCC
CC
EXTV Ramping Positive
CC
EXTV Hysteresis
250
mV
LDOHYS
CC
Oscillator and Phase-Locked Loop
f
f
f
f
f
f
Programmable Frequency
Programmable Frequency
Programmable Frequency
Low Fixed Frequency
R
= 25k;
FREQ
105
440
835
350
535
kHz
kHz
kHz
kHz
kHz
kHz
25kΩ
65kΩ
105kΩ
LOW
PLLIN/MODE = DC Voltage
R
= 65k;
375
505
FREQ
PLLIN/MODE = DC Voltage
R
=105k;
FREQ
PLLIN/MODE = DC Voltage
V
= 0V;
320
485
75
380
585
750
FREQ
PLLIN/MODE = DC Voltage
High Fixed Frequency
V
= INTV
;
CC
HIGH
SYNC
FREQ
PLLIN/MODE = DC Voltage
l
Synchronizable Frequency
PLLIN/MODE = External Clock
PGOOD1 Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL
PGOOD
I
V
V
V
µA
PGOOD
PGOOD
V
PG
with Respect to Set Regulated Voltage
Ramping Negative
FB
FB
–13
7
–10
2.5
10
–7
13
%
%
%
%
Hysteresis
Ramping Positive
V
FB
Hysteresis
2.5
25
t
PG
Delay for Reporting a Fault
µs
3891fa
4
LTC3891
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3891 is tested in a feedback loop that servos V to a
ITH
specified voltage and measures the resultant V . The specification at
FB
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC3891E/LTC3891I, 150°C for the LTC3891H/LTC3891MP). For the
LTC3891MP, the specification at –40°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 2: The LTC3891 is tested under pulsed load conditions such that
T ≈ T . The LTC3891E is guaranteed to meet performance specifications
J
A
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3891I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC3891H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LTC3891MP is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of I
(See Minimum On-Time
MAX
Considerations in the Applications Information section).
Note 3: The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in Watts) according to
A
D
the formula:
T = T + (P • θ ), where θ is 43°C/W for the QFN or 38°C/W for the
J
A
D
JA
JA
TSSOP.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss vs
Output Current
Efficiency vs Output Current
Efficiency vs Input Voltage
10000
1000
100
100
90
80
70
60
50
40
30
20
100
98
96
94
92
90
88
86
84
100
90
80
70
60
50
40
30
20
V
V
= 12V
IN
OUT
V
= 8.5V
BURST EFFICIENCY
OUT
= 3.3V
V
OUT
= 3.3V
V
= 8.5V
OUT
FCM LOSS
BURST LOSS
PULSE-SKIPPING
LOSS
10
V
= 3.3V
OUT
FCM EFFICIENCY
1
Burst Mode OPERATION
PULSE-SKIPPING
EFFICIENCY
10
0
82
80
10
0
V
IN
= 12V
I
= 2A
LOAD
5
0.1
10
0.0001 0.001
0.01
OUTPUT CURRENT (A)
FIGURES 12, 14 CIRCUITS
0.1
1
10
0
10 15 20 25 30 35 40 45 50 55 60
0.0001 0.001
0.01
OUTPUT CURRENT (A)
FIGURE 12 CIRCUIT
0.1
1
INPUT VOLTAGE (V)
3891 G02
3891 G03
3891 G01
FIGURES 12, 14 CIRCUITS
3891fa
5
LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
Burst Mode Operation
Load Step
Pulse-Skipping Mode
Load Step
Forced Continuous Mode
V
V
V
OUT
OUT
OUT
100mV/DIV
AC-
100mV/DIV
AC-
100mV/DIV
AC-
COUPLED
COUPLED
COUPLED
I
I
I
L
L
L
2A/DIV
2A/DIV
2A/DIV
3891 G04
3891 G05
3891 G06
50µs/DIV
50µs/DIV
50µs/DIV
LOAD STEP = 100mA TO 3A
LOAD STEP = 100mA TO 3A
LOAD STEP = 100mA TO 3A
V
V
= 12V
V
V
= 12V
V
V
= 12V
IN
OUT
IN
OUT
IN
OUT
= 3.3V
= 3.3V
= 3.3V
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
Inductor Current at Light Load
Soft Start-Up
Tracking Start-Up
FORCED
CONTINUOUS
MODE
V
= 8.5V
MASTER
2V/DIV
OUT
2V/DIV
Burst Mode
OPERATION
1A/DIV
V
= 3.3V
V
OUT
2V/DIV
OUT
2V/DIV
PULSE-SKIPPING
MODE
3891 G07
3891 G08
3891 G09
5µs/DIV
2ms/DIV
FIGURES 12, 14 CIRCUITS
2ms/DIV
V
V
LOAD
= 12V
IN
= 3.3V
OUT
I
= 200µA
Total Input Supply Current vs
Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
5.5
5.0
300
250
200
150
100
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
FIGURE 12 CIRCUIT
INTV
CC
300µA LOAD
4.5
4.0
3.5
3.0
EXTV RISING
CC
EXTV FALLING
CC
NO LOAD
50
0
I
= 10mA
LOAD
0
5
10 15 20 25 30 35 40 45 50 55 60 65
5
10 15 20 25 30 35 40 45 50 55 60 65
–75
–25
0
25 50 75 100 125 150
–50
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3891 G12
3891 G10
3891 G11
3891fa
6
LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Voltage
Maximum Current Sense
Threshold vs Duty Cycle
vs ITH Voltage
SENSE– Pin Input Bias Current
80
60
40
20
800
700
600
500
400
300
200
100
0
80
70
5% DUTY CYCLE
I
= FLOAT
LIM
PULSE-SKIPPING MODE
60
50
Burst Mode
OPERATION
I
= INTV
CC
LIM
I
= GND
= INTV
LIM
40
30
20
0
–20
–40
I
LIM
CC
I
= GND
LIM
I
= FLOAT
LIM
FORCED CONTINUOUS MODE
–100
0.8
(V)
1.2
1.4
5
10
15
25
0
0.2
0.4 0.6
1.0
0
20
0
10 20 30 40 50 60 70 80 90 100
V
V
COMMON MODE VOLTAGE (V)
DUTY CYCLE (%)
ITH
SENSE
3891 G13
3891 G14
3891 G15
Foldback Current Limit
Quiescent Current vs Temperature
INTVCC vs Load Current
80
75
70
65
60
55
50
45
40
35
30
80
70
60
50
40
30
20
10
0
5.50
5.25
5.00
V
IN
= 12V
V
IN
= 12V
I
= FLOAT
LIM
EXTV = 0V
CC
I
= INTV
LIM
CC
EXTV = 8.5V
CC
4.75
4.50
4.25
4.00
EXTV = 5V
CC
I
= GND
LIM
–50 –25
75 100 125 150
TEMPERATURE (°C)
–75
0
25 50
0
100 200 300 400 500 600 700 800
FEEDBACK VOLTAGE (MV)
3891 G16
20
60
LOAD CURRENT (mA)
80
100
0
40
3891 G17
3891 G18
Regulated Feedback Voltage
vs Temperature
TRACK/SS Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
12.0
11.5
11.0
10.5
10.0
1.30
1.25
1.20
808
806
804
RUN RISING
802
800
798
796
794
9.5
9.0
8.5
8.0
RUN FALLING
1.15
1.10
792
–50 –25
0
75 100 125 150
–75
25 50
–50 –25
75 100 125 150
–75
0
25 50
–50 –25
75 100 125 150
TEMPERATURE (°C)
–75
0
25 50
TEMPERATURE (°C)
TEMPERATURE (°C)
3891 G19
3891 G20
3891 G21
3891fa
7
LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE– Pin Input Bias Current
vs Temperature
Shutdown Current vs Input
Voltage
Oscillator Frequency
vs Temperature
30
25
20
15
10
5
800
700
600
500
400
300
200
100
0
600
550
500
450
FREQ = INTV
CC
V
OUT
> INTV + 0.5V
CC
400
350
300
FREQ = GND
25 50
V
< INTV – 0.5V
CC
OUT
0
0
–100
–50 –25
75 100 125 150
–75
25 50
5
10 15 20 25 30 35 40 45 50 55 60 65
75 125 150
100
–75 –50 –25
0
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3891 G23
3891 G22
3891 G24
Undervoltage Lockout Threshold
vs Temperature
Oscillator Frequency vs Input
Voltage
Shutdown Current vs Temperature
4.2
4.1
4.0
3.9
3.8
3.7
3.6
356
354
352
350
348
22
20
18
FREQ = GND
V
IN
= 12V
RISING
16
14
12
10
8
FALLING
346
344
–75
–25
0
25 50 75 100 125 150
–50
5
10 15 20 25 30 35 40 45 50 55 60 65
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3891 G26
3891 G27
3891 G25
3891fa
8
LTC3891
PIN FUNCTIONS (QFN/eTSSOP)
PLLIN/MODE (Pin 1/Pin 3): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock,
and the regulator operates in forced continuous mode.
When not synchronizing to an external clock, this input
determines how the LTC3891 operates at light loads. Pull-
ing this pin to ground selects Burst Mode operation. An
internal 100k resistor to ground also invokes Burst Mode
operation when the pin is floated. Tying this pin to INTV
forces continuous inductor current operation. Tying this
pin to a voltage greater than 1.2V and less than INTV
–1.3V selects pulse-skipping operation.
PGOOD (Pin 9/Pin 11): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the V pin is not
FB
within 10% of its set point.
TG (Pin 10/Pin 12): High Current Gate Drives for Top
N-channel MOSFET. This is the output of floating driver
with a voltage swing equal to INTV superimposed on
CC
the switch node voltage SW.
SW (Pin 11/ Pin 13): Switch Node Connection to Induc-
tor.
CC
BOOST (Pin 12/Pin 14): Bootstrapped Supply to the Top-
side Floating Driver. A capacitor is connected between the
BOOST and SW pin and a Schottky diode is tied between
CC
the BOOST and INTV pins. Voltage swing at the BOOST
CC
pin is from INTV to (V + INTV ).
SGND (Pins 2, 3, Exposed Pad Pin 21/Pins 4, 5,
ExposedPadPin21):Small-signalground,mustberouted
separately from high current grounds to the common
CC
IN
CC
BG (Pin 13/Pin 15): High Current Gate Drive for Bottom
(Synchronous) N-channel MOSFET. Voltage swing at this
(–) terminals of the C capacitor. Pins 2, 3/4, 5, must
IN
pin is from ground to INTV .
CC
both be electrically connected to small signal ground for
proper operation.The exposed pad must be soldered to
PCB ground for rated thermal performance.
INTV (Pin 14/Pin 16): Output of the Internal Linear
CC
Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. Must be decoupled
to PGND with a minimum of 2.2µF ceramic or other low
RUN (Pin 4/Pin 6): Digital Run Control Input. Forcing this
pin below 1.16V shuts down the controller. Forcing this
pin below 0.7V shuts down the entire LTC3891, reducing
quiescent current to approximately 14µA.
ESR capacitor. Do not use the INTV pin for any other
CC
purpose.
EXTV (Pin 15/Pin 17): External Power Input to an
CC
–
SENSE (Pin 5/Pin 7): The (–) Input to the Differential
Internal LDO Connected to INTV . This LDO supplies
CC
Current Comparator. When greater than INTV – 0.5V, the
CC
INTV power, bypassing the internal LDO powered from
CC
–
SENSE pin supplies power to the current comparator.
V
whenever EXTV is higher than 4.7V. See EXTV
IN
CC CC
+
Connection in the Applications Information section. Do
SENSE (Pin 6/Pin 8): The (+) input to the differential
not float or exceed 14V on this pin.
currentcomparatorisnormallyconnectedtoDCRsensing
networkorcurrentsensingresistor.TheITHpinvoltageand
PGND (Pin 16/Pin 18): Driver Power Ground. Connects to
–
+
controlledoffsetsbetweentheSENSE andSENSE pinsin
conjunction with R set the current trip threshold.
the source of bottom (synchronous) N-channel MOSFET
SENSE
and the (–) terminal of C .
IN
V
(Pin 7/Pin 9): Receives the remotely sensed feed-
FB
V (Pin 17/Pin 19): Main Supply Pin. A bypass capacitor
IN
back voltage from an external resistive divider across
should be tied between this pin and the SGND pins.
the output.
I
(Pin 18/Pin 20): Current Comparator Sense Voltage
LIM
ITH (Pin 8/Pin 10): Error Amplifier Outputs and Switching
Regulator Compensation Point. The current comparator
trip point increases with this control voltage.
Range Inputs. Tying this pin to SGND, FLOAT or INTV
CC
sets the maximum current sense threshold to one of three
different levels for the comparator.
3891fa
9
LTC3891
PIN FUNCTIONS
TRACK/SS (Pin 19/Pin 1): External Tracking and Soft-
Start Input. The LTC3891 regulates the V voltage to the
smaller of 0.8V or the voltage on the TRACK/SS pin. An
internal 10μA pull-up current source is connected to this
pin. A capacitor to ground at this pin sets the ramp time
to final regulated output voltage. Alternatively, a resistor
divider on another voltage supply connected to this pin
allows the LTC3891 output to track another supply during
start-up.
FREQ (Pin 20/Pin 2): The frequency control pin for the
internal VCO. Connecting the pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting the pin
FB
to INTV forces the VCO to a fixed high frequency of
CC
535kHz. Other frequencies between 50kHz and 900kHz
can be programmed by using a resistor between FREQ
and GND. An internal 20µA pull-up current develops the
voltage to be used by the VCO to control the frequency.
FUNCTIONAL DIAGRAM
INTV
V
IN
CC
D
+
B
PGOOD
0.88V
BOOST
–
V
C
B
FB
+
–
TG
DROP
OUT
DET
TOP
BOT
C
IN
0.72V
D
BOT
SW
TOP ON
S
R
Q
INTV
CC
Q
SWITCH
LOGIC
BG
SHDN
20µA
FREQ
C
OUT
PGND
VCO
CLK2
CLK1
V
OUT
+
–
R
SENSE
0.425V
SLEEP
L
ICMP
IR
–
+
+
–
PFD
+
+
–
–
+
2mV
SENSE
SYNC
DET
2.7V
0.65V
PLLIN/MODE
–
SENSE
100k
SLOPE COMP
I
LIM
V
FB
R
B
CURRENT
LIMIT
+
0.80V
TRACK/SS
EA
–
V
R
A
IN
+
–
OV
EXTV
CC
C
C
0.88V
ITH
5.1V
LDO
EN
5.1V
LDO
EN
7µA
11V
SHDN
RST
FB
C
R
C
C2
10µA
FOLDBACK
TRACK/SS
2(V
)
+
–
C
SHDN
SS
4.7V
3891 FD
RUN
SGND
INTV
CC
3891fa
10
LTC3891
OPERATION
Main Control Loop
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The LTC3891 uses a constant frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
The LTC3891 can be shut down using the RUN pin. Pulling
this pin below 1.16V shuts down the main control loop.
Pulling the RUN pin below 0.7V disables the controller
and most internal circuits, including the INTV LDOs.
CC
In this state, the LTC3891 draws only 14μA of quiescent
current.
Releasing the RUN pin allows a small internal current to
pull up the pin to enable the controller. The RUN pin has
a 7μA pull-up which is designed to be large enough so
that the RUN pin can be safely floated (to always enable
the controller) without worry of condensation or other
small board leakage pulling the pin down. This is ideal
for always-on applications where the controller is enabled
continuously and never shut down.
compares the output voltage feedback signal at the V
FB
pin (which is generated with an external resistor divider
connected across the output voltage, V , to ground) to
OUT
the internal 0.800V reference voltage. When the load cur-
rent increases, it causes a slight decrease in V relative
FB
to the reference, which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
After the top MOSFET is turned off each cycle, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
highervoltage(forexample,V ),solongasthemaximum
IN
current into the RUN pin does not exceed 100μA.
INTV /EXTV Power
CC
CC
The RUN pin can also be implemented as a UVLO by
connecting it to the output of an external resistor divider
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin.
CC
network off V (see Applications Information section).
IN
When the EXTV pin is tied to a voltage less than 4.7V,
CC
the V LDO (low dropout linear regulator) supplies 5.1V
The start-up of the controller’s output voltage V
is
IN
OUT
from V to INTV . If EXTV is taken above 4.7V, the V
controlled by the voltage on the TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 0.8V internal
IN
CC
CC
IN
LDO is turned off and an EXTV LDO is turned on. Once
CC
enabled, the EXTV LDO supplies 5.1V from EXTV to
reference, the LTC3891 regulates the V voltage to the
CC
CC
FB
INTV . Using the EXTV pin allows the INTV power
TRACK/SS pin voltage instead of the 0.8V reference. This
allowstheTRACK/SSpintobeusedtoprogramasoft-start
by connecting an external capacitor from the TRACK/SS
pin to SGND. An internal 10μA pull-up current charges
this capacitor creating a voltage ramp on the TRACK/SS
pin. As the TRACK/SS voltage rises linearly from 0V to
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC3891 switching regulator outputs.
ThetopMOSFETdriverisbiasedfromthefloatingbootstrap
capacitor, C , which normally recharges during each cycle
B
through an external diode when the top MOSFET turns
0.8V (and beyond up to 5V), the output voltage V
rises
OUT
off. If the input voltage, V , decreases to a voltage close
IN
smoothly from zero to its final value. Alternatively the
TRACK/SS pin can be used to cause the start-up of V
to V , the loop may enter dropout and attempt to turn
OUT
OUT
on the top MOSFET continuously. The dropout detector
to track that of another supply. Typically, this requires
connecting to the TRACK/SS pin an external resistor
divider from the other supply to ground (see Applications
Information section).
detects this and forces the top MOSFET off for about one
twelfth of the clock period every tenth cycle to allow C
to recharge.
B
3891fa
11
LTC3891
OPERATION
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
mined by the voltage on the ITH pin, just as in normal
operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continu-
ous operation has the advantage of lower output voltage
ripple and less interference to audio circuitry. In forced
continuous mode, the output ripple is independent of
load current.
The LTC3891 can be enabled to enter high efficiency Burst
Modeoperation,constantfrequencypulse-skippingmode,
or forced continuous conduction mode at low load cur-
rents.ToselectBurstModeoperation,tiethePLLIN/MODE
pin to SGND. To select forced continuous operation, tie
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LTC3891 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designedmaximumoutputcurrent. Atverylightloads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
the PLLIN/MODE pin to INTV . To select pulse-skipping
CC
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTV – 1.3V.
CC
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the load cur-
rent, the error amplifier, EA, will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3891 draws to
only 50μA. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the ITH pin is reconnected to the output of the
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3891 can be selected
using the FREQ pin.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IR, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied
to INTV or programmed through an external resistor.
CC
Tying FREQ to SGND selects 350kHz while tying FREQ to
INTV selects 535kHz. Placing a resistor between FREQ
CC
andSGNDallowsthefrequencytobeprogrammedbetween
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the inductor
current is allowed to reverse at light loads or under large
transient conditions. The peak inductor current is deter-
50kHz and 900kHz, as shown in Figure 9.
A phase-locked loop (PLL) is available on the LTC3891
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
3891fa
12
LTC3891
OPERATION
LTC3891’s phase detector adjusts the voltage (through an
internallowpassfilter)oftheVCOinputtoaligntheturn-on
of the controller’s external top MOSFET to the rising edge
of the synchronizing signal.
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good Pin
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOODpinlowwhentheV pinvoltageisnotwithin 10%
FB
ofthe0.8Vreferencevoltage.ThePGOODpinisalsopulled
low when the RUN pin is low (shut down). When the V
FB
pin voltage is within the 10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 900kHz, with a guarantee to be
between75kHzand750kHz.Inotherwords,theLTC3891’s
PLLisguaranteedtolocktoanexternalclocksourcewhose
frequency is between 75kHz and 750kHz.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
interval (as long as the V voltage is keeping up with the
FB
Output Overvoltage Protection
TRACK/SS voltage).
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V pin rises by more
FB
3891fa
13
LTC3891
APPLICATIONS INFORMATION
TheTypicalApplicationonthefirstpageisabasicLTC3891
application circuit. LTC3891 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
Filter components mutual to the sense lines should be
placed close to the LTC3891, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 2b), sense resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
R
SENSE
(if R
is used) and inductor value. Next, the
SENSE
powerMOSFETsandSchottkydiodesareselected. Finally,
input and output capacitors are selected.
C
OUT
3891 F01
INDUCTOR OR R
SENSE
Current Limit Programming
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
TheI pinisatri-levellogicinputwhichsetsthemaximum
LIM
V
V
IN
IN
current limit of the controller. When I is grounded, the
LIM
INTV
CC
maximum current limit threshold voltage of the current
BOOST
TG
comparator is programmed to be 30mV. When I
is
LIM
R
SENSE
floated, the maximum current limit threshold is 75mV.
When I is tied to INTV , the maximum current limit
SW
V
OUT
LTC3891
LIM
CC
BG
threshold is set to 50mV.
R1*
+
SENSE
+
–
PLACE CAPACITOR NEAR
SENSE PINS
SENSE and SENSE Pins
C1*
–
SENSE
SGND
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 28V (abs max), enabling the LTC3891
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients).
3891 F02a
*R1 AND C1 ARE OPTIONAL
(2a) Using a Resistor to Sense Current
V
IN
V
IN
INTV
CC
+
The SENSE pin is high impedance over the full common
INDUCTOR
DCR
BOOST
TG
mode range, drawing at most 1μA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
L
SW
V
OUT
LTC3891
BG
–
The impedance of the SENSE pin changes depending on
R1
C1* R2
+
SENSE
–
the common mode voltage. When SENSE is less than
INTV – 0.5V, a small current of less than 1μA flows out
–
CC
SENSE
–
of the pin. When SENSE is above INTV + 0.5V, a higher
SGND
CC
R2
R1 + R2
L
current(~700μA)flowsintothepin.BetweenINTV –0.5V
||
(R1 R2) • C1 =
*PLACE C1 NEAR
SENSE PINS
R
= DCR
CC
SENSE(EQ)
3891 F02b
DCR
andINTV +0.5V, thecurrenttransitionsfromthesmaller
CC
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
current to the higher current.
3891fa
14
LTC3891
APPLICATIONS INFORMATION
Low Value Resistor Current Sensing
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
output current.
is chosen based on the required
SENSE
The current comparator has a maximum threshold
determined by the I setting. The current
V
SENSE(MAX)
LIM
comparator threshold voltage sets the peak of the induc-
tor current, yielding a maximum average output current,
I
, equal to the peak value less half the peak-to-peak
MAX
ripple current, ∆I . To calculate the sense resistor value,
L
use the equation:
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor
value is:
VSENSE(MAX)
RSENSE
=
DIL
IMAX
+
2
VSENSE(MAX)
RSENSE(EQUIV)
=
DIL
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimumvaluefortheMaximumCurrentSenseThreshold
IMAX
+
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimumvaluefortheMaximumCurrentSenseThreshold
(V
)intheElectricalCharacteristicstable(30mV,
SENSE(MAX)
50mV or 75mV, depending on the state of the I pin).
LIM
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due
to the internal compensation required to meet stability
criterion for buck regulators operating at greater than
50% duty factor. A curve is provided in the Typical Perfor-
mance Characteristics section to estimate this reduction
in peak inductor current depending upon the operating
duty factor.
(V
)intheElectricalCharacteristicstable(30mV,
SENSE(MAX)
50mV or 75mV, depending on the state of the I pin).
LIM
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for T
is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
Inductor DCR Sensing
resistor value (R ), use the divider ratio:
D
For applications requiring the highest possible efficiency
at high load currents, the LTC3891 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be
lessthan1mΩfortoday’slowvalue,highcurrentinductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
RSENSE(EQUIV)
RD =
DCRMAX atT
L(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
ThisforcesR1||R2toaround2k,reducingerrorthatmight
have been caused by the SENSE pin’s 1μA current.
+
3891fa
15
LTC3891
APPLICATIONS INFORMATION
The equivalent resistance R1 || R2 is scaled to the tem-
perature inductance and maximum DCR:
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆I , decreases with higher
L
inductance or higher frequency and increases with higher
V :
IN
L
R1||R2 =
DCR at 20°C • C1
(
)
V
1
OUT
OUT
IN
ΔIL =
V
1–
f L
V
The sense resistor values are:
R1||R2
RD
R1•RD
1– RD
Accepting larger values of ∆I allows the use of low in-
L
R1=
; R2 =
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆I = 0.3(I
). The maximum ∆I occurs
L
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
L
MAX
at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
V
IN(MAX) – VOUT • V
(
)
OUT
P
R1=
LOSS
R1
25% of the current limit determined by R
. Lower
SENSE
inductor values (higher ∆I ) will cause this to occur at
L
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related n that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also be
considered.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
3891fa
16
LTC3891
APPLICATIONS INFORMATION
Power MOSFET and Schottky Diode (Optional)
Selection
where δ is the temperature dependency of R
DR
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V
is the
THMIN
Two external power MOSFETs must be selected for the
LTC3891 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
typical MOSFET minimum threshold voltage.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
The peak-to-peak drive levels are set by the INTV
CC
the high current efficiency generally improves with larger
voltage. This voltage is typically 5.1V during start-up
MOSFETs, while for V > 20V the transition losses rapidly
IN
(see EXTV Pin Connection). Consequently, logic-level
CC
increasetothepointthattheuseofahigherR
device
DS(ON)
threshold MOSFETs must be used in most applications.
withlowerC
actuallyprovideshigherefficiency.The
MILLER
Pay close attention to the BV
MOSFETs as well.
specification for the
DSS
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Selection criteria for the power MOSFETs include the on-
resistance, R , Miller capacitance, C , input
DS(ON)
MILLER
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge
The term (1+ δ) is generally given for a MOSFET in the
C
MILLER
form of a normalized R
vs Temperature curve, but
DS(ON)
curve usually provided on the MOSFET manufacturers’
datasheet. C is equal to the increase in gate charge
δ = 0.005/°C can be used as an approximation for low
MILLER
voltage MOSFETs.
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
A Schottky diode can be inserted in parallel with the bot-
tom MOSFET to conduct during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
V
IN
Main Switch Duty Cycle =
in efficiency at high V . A 1A to 3A Schottky is generally
IN
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
V − V
IN
OUT
Synchronous Switch Duty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are given by:
C and C
Selection
IN
OUT
VOUT
2
TheselectionofC isusuallybasedofftheworst-caseRMS
IN
PMAIN
=
I
1+ δ R
+
DS(ON)
(
MAX) (
)
input current. The highest (V )(I ) product needs to
V
OUT OUT
IN
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
2
IMAX
2
V
R
C
•
(
)
(
DR)(
)
IN
MILLER
Incontinuousmode,thesourcecurrentofthetopMOSFET
1
1
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
+
f
( )
large voltage transients, a low ESR capacitor sized for the
VINTVCC – VTHMIN VTHMIN
V – VOUT
2
IN
PSYNC
=
I
1+ δ R
(
MAX) (
)
DS(ON)
V
IN
3891fa
17
LTC3891
APPLICATIONS INFORMATION
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
To improve the frequency response, a feedforward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
1/2
IMAX
inductor or the SW line.
CIN Required IRMS
≈
V
V – V
IN OUT
(1)
(
OUT ) (
)
V
IN
V
OUT
This formula has a maximum at V = 2V , where I
IN
OUT
RMS
R
C
FF
LTC3891
B
= I /2. This simple worst-case condition is commonly
OUT
V
FB
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3891, ceramic capacitors
R
A
3891 F03
Figure 3. Setting Output Voltage
RUN Pin
The LTC3891 is enabled using the RUN pin. It has a rising
threshold of 1.21V with 50mV of hysteresis. Pulling the
RUN pin below 1.16V shuts down the main control loop.
Pulling it below 0.7V disables the controller and most
internal circuits, including the INTV LDOs. In this state,
the LTC3891 draws only 14μA of quiescent current.
can also be used for C . Always consult the manufacturer
IN
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
CC
V pin and ground, placed close to the LTC3891, is also
IN
suggested. A small (≤10Ω) resistor placed between C
IN
Releasing the RUN pin allows a small 7μA internal current
to pull up the pin to enable the controller. The RUN pin may
be externally pulled up or driven directly by logic. When
driving the RUN pin with a low impedance source, do not
exceed the absolute maximum rating of 8V. The RUN pin
has an internal 11V voltage clamp that allows the RUN pin
to be connected through a resistor to a higher voltage (for
(C1) and the V pin provides further isolation.
IN
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V ) is approximated by:
OUT
1
example, V ), so long as the maximum current into the
RUN pin does not exceed 100μA.
ΔVOUT ≈ ΔI ESR+
L
IN
8 • f • COUT
TheRUNpincanbeimplementedasaUVLObyconnecting
it to the output of an external resistor divider network off
IN
where f is the operating frequency, C
is the output
OUT
capacitance and ∆I is the ripple current in the inductor.
L
V , as shown in Figure 4.
The output ripple is highest at maximum input voltage
since ∆I increases with input voltage.
L
V
IN
Setting Output Voltage
R
R
LTC3891
RUN
B
The LTC3891 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 3. The regulated output voltage is
determined by:
A
3891 F04
Figure 4. Using the RUN Pin as a UVLO
R
RA
B
VOUT = 0.8V 1+
3891fa
18
LTC3891
APPLICATIONS INFORMATION
TherisingandfallingUVLOthresholdsarecalculatedusing
the RUN pin thresholds:
pin of the slave supply (V ), as shown in Figure 7.
OUT
During start-up V
will track V according to the ratio
OUT
X
set by the resistor divider:
RB
RA
V
V
=
1.21V 1+
UVLO(RISING)
VX
RA
RTRACKA + RTRACKB
RA + RB
=
•
VOUT RTRACKA
RB
RA
=
1.16V 1+
UVLO(FALLING)
For coincident tracking (V
= V during start-up):
X
OUT
R = R
A
TRACKA
TRACKB
The resistor values should be carefully chosen such that
the absolute maximum ratings of the RUN pin do not get
R = R
B
violated over the entire V voltage range.
IN
V
V
X(MASTER)
Tracking and Soft-Start (TRACK/SS Pin)
The start-up of V
is controlled by the voltage on the
OUT
TRACK/SS pin. When the voltage on the TRACK/SS pin is
lessthantheinternal0.8Vreference,theLTC3891regulates
OUT(SLAVE)
the V pin voltage to the voltage on the TRACK/SS pin
FB
insteadof0.8V. TheTRACK/SSpincanbeusedtoprogram
an external soft-start function or to allow V
another supply during start-up.
to track
OUT
3891 F06a
TIME
(6a) Coincident Tracking
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 5.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
V
V
X(MASTER)
OUT(SLAVE)
The LTC3891 will regulate the V pin (and hence V
)
FB
OUT
according to the voltage on the TRACK/SS pin, allowing
to rise smoothly from 0V to its final regulated value.
V
OUT
The total soft-start time will be approximately:
0.8V
10µA
tSS = CSS
•
3891 F06b
TIME
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
LTC3891
TRACK/SS
C
V
x
V
OUT
SS
SGND
LTC3891
R
B
3891 F05
V
FB
R
A
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
R
R
TRACKB
TRACK/SS
Alternatively, the TRACK/SS pin can be used to track
another supply during start-up, as shown qualitatively in
Figures 6a and 6b. To do this, a resistor divider should be
3891 F07
TRACKA
Figure 7. Using the TRACK/SS Pin for Tracking
connected from the master supply (V ) to the TRACK/SS
X
3891fa
19
LTC3891
APPLICATIONS INFORMATION
INTV Regulators
is less than 5.1V, the LDO is in dropout and the INTV
CC
CC
CC
voltage is approximately equal to EXTV . When EXTV
CC
The LTC3891 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
is greater than 5.1V, up to an absolute maximum of 14V,
INTV is regulated to 5.1V.
CC
at the INTV pin from either the V supply pin or the
CC
IN
EXTV pin depending on the connection of the EXTV
UsingtheEXTV LDOallowstheMOSFETdriverandcontrol
CC
CC
CC
pin. INTV powers the gate drivers and much of the
power to be derived from one of the LTC3891’s switching
CC
LTC3891’s internal circuitry. The V LDO and the EXTV
regulator outputs (4.7V ≤ V
≤ 14V) during normal
IN
CC
OUT
LDO regulate INTV to 5.1V. Each of these can supply a
operation and from the V LDO when the output is out of
CC
IN
peak current of at least 50mA and must be bypassed to
ground with a minimum of 2.2μF ceramic capacitor. No
matter what type of bulk capacitor is used, an additional
regulation (e.g., start-up, short-circuit). If more current
is required through the EXTV LDO than is specified, an
CC
external Schottky diode can be added between the EXTV
CC
1μFceramiccapacitorplaceddirectlyadjacenttotheINTV
and INTV pins. In this case, do not apply more than 6V
CC
CC
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
to the EXTV pin and make sure that EXTV ≤ V .
CC CC IN
Significant efficiency and thermal gains can be realized by
powering INTV from the output, since the V current
CC
IN
resultingfromthedriverandcontrolcurrentswillbescaled
by a factor of (Duty Cycle)/(Switcher Efficiency).
HighinputvoltageapplicationsinwhichlargeMOSFETsare
being driven at high frequencies may cause the maximum
junctiontemperatureratingfortheLTC3891tobeexceeded.
For 5V to 14V regulator outputs, this means connecting
the EXTV pin directly to V . Tying the EXTV pin to
CC
OUT
CC
TheINTV current,whichisdominatedbythegatecharge
CC
an 8.5V supply reduces the junction temperature in the
current, may be supplied by either the V LDO or the
IN
previous example from 125°C to:
EXTV LDO. When the voltage on the EXTV pin is less
CC
CC
T = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
J
than4.7V,theV LDOisenabled.Powerdissipationforthe
IN
IC in this case is highest and is equal to V • I
. The
IN INTVCC
However, for 3.3V and other low voltage outputs, addi-
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics.
tional circuitry is required to derive INTV power from
CC
the output.
The following list summarizes the four possible connec-
tions for EXTV :
CC
For example, the LTC3891 INTV current is limited to less
CC
than 32mA from a 40V supply when not using the EXTV
1. EXTV Grounded.ThiswillcauseINTV tobepowered
CC
CC
CC
supply at a 70°C ambient temperature:
fromtheinternal5.1Vregulatorresultinginanefficiency
penalty of up to 10% at high input voltages.
T = 70°C + (32mA)(40V)(43°C/W for QFN) = 125°C
J
2. EXTV Connected Directly to V . This is the normal
CC
OUT
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTV ) at maximum V .
connection for a 5V to 14V regulator and provides the
highest efficiency.
3. EXTV Connected to an External Supply. If an external
CC
IN
CC
supply is available in the 5V to 14V range, it may be
When the voltage applied to EXTV rises above 4.7V, the
CC
used to power EXTV providing it is compatible with
CC
V LDO is turned off and the EXTV LDO is enabled. The
IN
CC
the MOSFET gate drive requirements. Ensure that
EXTV LDO remains on as long as the voltage applied to
CC
EXTV < V .
CC
IN
EXTV remains above 4.5V. The EXTV LDO attempts
CC
CC
to regulate the INTV voltage to 5.1V, so while EXTV
CC
CC
3891fa
20
LTC3891
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.
CC
For 3.3V and other low voltage regulators, efficiency
The LTC3891 includes current foldback to help limit load
current when the output is shorted to ground. If the output
voltage falls below 70% of its nominal output level, then
themaximumsensevoltageisprogressivelyloweredfrom
100%to45%ofitsmaximumselectedvalue.Undershort-
circuit conditions with very low duty cycles, the LTC3891
will begin cycle skipping in order to limit the short-circuit
current. In this situation the bottom MOSFET will be dis-
sipating most of the power but less than in normal opera-
tion. The short-circuit ripple current is determined by the
gains can still be realized by connecting EXTV to an
CC
output-derivedvoltagethathasbeenboostedtogreater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 8. Ensure that EXTV < V .
CC
IN
C
IN
BAT85
BAT85
V
IN
MTOP
MBOT
minimum on-time, t
, of the LTC3891 (≈95ns), the
BAT85
ON(MIN)
NDS7002
TG
SW
input voltage and inductor value:
LTC3891
EXTV
L
R
SENSE
V
OUT
CC
V
L
ON(MIN) IN
ΔIL(SC) = t
C
OUT
BG
3891 F08
The resulting average short-circuit current is:
PGND
1
2
ISC = 45% •ILIM(MAX) – DIL(SC)
Figure 8. Capacitive Charge Pump for EXTVCC
Topside MOSFET Driver Supply (C , D )
Fault Conditions: Overvoltage Protection (Crowbar)
B
B
An external bootstrap capacitor, C , connected to the
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
muchhigherthannominallevels.Thecrowbarcauseshuge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
B
BOOST pin supplies the gate drive voltage for the topside
MOSFET.CapacitorC intheFunctionalDiagramischarged
B
though external diode D from INTV when the SW pin
B
CC
is low. When the topside MOSFET is to be turned on, the
driver places the C voltage across the gate-source of
B
the MOSFET. This enhances the top MOSFET switch and
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
turns it on. The switch node voltage, SW, rises to V and
IN
the BOOST pin follows. With the topside MOSFET on, the
boost voltage is above the input supply: V
INTVCC
= V +
BOOST
IN
V
. The value of the boost capacitor, C , needs to be
B
100 times that of the total input capacitance of the top-
side MOSFET(s). The reverse breakdown of the external
for as long as the overvoltage condition persists; if V
OUT
Schottky diode must be greater than V
.
IN(MAX)
returns to a safe level, normal operation automatically
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
resumes.
AshortedtopMOSFETwillresultinahighcurrentcondition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
3891fa
21
LTC3891
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
The LTC3891 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
1000
900
800
700
600
500
400
300
200
100
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than f , current is sunk continuously, pulling down the
OSC
0
15 25 35 45 55 65 75 85 95 105 115 125
VCO input.
FREQ PIN RESISTOR (kΩ)
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
3891 F09
Figure 9. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
Note that the LTC3891 can only be synchronized to an
external clock whose frequency is within range of the
LTC3891’s internal VCO, which is nominally 55kHz to
900kHz.
0V
INTV
DC Voltage
535kHz
CC
Resistor
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase Locked to
External Clock
This is guaranteed to be between 75kHz and 750kHz. Typi-
cally,theexternalclock(onthePLLIN/MODEpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.1V.
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the LTC3891 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
RapidphaselockingcanbeachievedbyusingtheFREQpin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
ON(MIN)
3891fa
22
LTC3891
APPLICATIONS INFORMATION
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTV to ground. The resulting dQ/dt is a current
CC
out of INTV that is typically much larger than the
CC
VOUT
control circuit current. In continuous mode, I
tON(MIN)
<
GATECHG
V
f
IN( )
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
SupplyingINTV fromanoutput-derivedsourcepower
CC
through EXTV will scale the V current required
CC
IN
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). Forexample, ina20Vto5Vapplica-
The minimum on-time for the LTC3891 is approximately
95ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 130ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
tion, 10mA of INTV current results in approximately
CC
2.5mA of V current. This reduces the midcurrent loss
IN
from 10% or more (if the driver was powered directly
from V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
, but is chopped between the topside MOSFET
SENSE
Efficiency Considerations
andthesynchronousMOSFET.IfthetwoMOSFETshave
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
approximately the same R
, then the resistance
DS(ON)
of one MOSFET can simply be summed with the resis-
2
tances of L, R
and ESR to obtain I R losses. For
DS(ON)
SENSE
example, if each R
= 30mΩ, R = 50mΩ, R
L SENSE
= 10mΩ and R
= 40mΩ (sum of both input and
ESR
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3891 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) topside MOSFET
transition losses.
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
1. The V current is the DC supply current given in the
IN
ElectricalCharacteristicstable,whichexcludesMOSFET
driverandcontrolcurrents. V currenttypicallyresults
IN
in a small (<0.1%) loss.
Transition Loss = (1.7) • V • 2 • I
• C
• f
2. INTV current is the sum of the MOSFET driver and
IN
O(MAX)
RSS
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
3891fa
23
LTC3891
APPLICATIONS INFORMATION
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
C has adequate charge storage and very low ESR at
IN
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including body diode conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical wayto producea realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better to
look at the ITH pin signal which is in the feedback loop and
is the filtered and compensated control loop response.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
OUT
LOAD
discharge C
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recov-
OUT
ery time V
can be monitored for excessive overshoot
OUT
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
providesaDCcoupledandACfilteredclosed-loopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
externalcomponentsshowninFigure10circuitwillprovide
an adequate starting point for most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
, causing a rapid drop in V . No regulator can
with C
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
As a design example, assume V = 12V (nominal),
IN
V
= 22V (max), V
= 3.3V, I
= 5A, V
IN
OUT
MAX SENSE(MAX)
= 75mV and f = 350kHz. The inductance value
is chosen first based on a 30% ripple current
3891fa
24
LTC3891
APPLICATIONS INFORMATION
assumption. The highest value of ripple current occurs
at the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
A short-circuit to ground will result in a folded back cur-
rent of:
95ns 22V
(
)
34mV
0.01Ω
1
2
ISC =
–
= 3.18A
4.7µH
VOUT
f L
VOUT
ΔIL =
1–
IN(NOM)
V
with a typical value of R
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
and δ = (0.005/°C)(25°C)
DS(ON)
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
2
P
= 3.28A 1.125 0.022Ω
(
) (
) (
)
SYNC
= 250mW
maximum V :
whichislessthanunderfull-loadconditions.C ischosen
IN
IN
for an RMS current rating of at least 3A at temperature
VOUT
3.3V
assuming only this channel is on. C
is chosen with an
OUT
tON(MIN)
=
=
= 429ns
V
f
22V 350kHz
ESR of 0.02Ω for low output ripple. The output ripple in
continuous mode will be highest at the maximum input
voltage. The output voltage ripple due to ESR is approxi-
mately:
IN(MAX) ( )
(
)
The equivalent R
resistor value can be calculated by
SENSE
using the minimum value for the maximum current sense
threshold (64mV):
V
= R (DI ) = 0.02Ω(1.45A) = 29mV
ESR L P-P
ORIPPLE
64mV
5.73A
PC Board Layout Checklist
RSENSE
≤
≈ 0.01Ω
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
Choosing 1% resistors: R = 25k and R = 78.7k yields
an output voltage of 3.32V.
A
B
Check the following in your layout:
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
results in: R
= 0.035Ω/0.022Ω, C
= 215pF. At
DS(ON)
MILLER
maximum input voltage with T(estimated) = 50°C:
of C
must return to the combined C
(–) ter-
INTVCC
OUT
minals. The path formed by the top N-channel MOSFET,
2
3.3V
22V
Schottky diode and the C capacitor should have short
PMAIN
=
5A 1+ 0.005 50°C – 25°C
IN
(
)
(
) (
)
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
2
5A
2
0.035Ω + 22V
2.5Ω 215pF •
(
) (
)
(
) (
)
1
1
+
350kHz = 331mW
(
)
5V – 2.3V 2.3V
2. Does the LTC3891 V pin’s resistive divider connect to
FB
the (+) terminal of C ? The resistive divider must be
OUT
connected between the (+) terminal of C
and signal
OUT
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
3891fa
25
LTC3891
APPLICATIONS INFORMATION
–
+
3. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
Reduce V from its nominal level to verify operation
IN
4. Is the INTV decoupling capacitor connected close
of the regulator in dropout. Check the operation of the
CC
to the IC, between the INTV and the power ground
undervoltage lockout circuit by further lowering V while
CC
IN
pins? This capacitor carries the MOSFET drivers’ cur-
monitoring the outputs to verify operation.
rent peaks. An additional 1μF ceramic capacitor placed
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
immediatelynexttotheINTV andPGNDpinscanhelp
CC
improve noise performance substantially.
5. KeeptheSW,TG,andBOOSTnodesawayfromsensitive
small-signal nodes. All of these nodes have very large
and fast moving signals and therefore should be kept
ontheoutputsideoftheLTC3891andoccupyminimum
PC trace area.
6. Useamodifiedstargroundtechnique:alowimpedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
for inductive coupling between C , Schottky and the top
IN
with tie-ins for the bottom of the INTV decoupling
CC
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
PC Board Layout Debugging
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
It is helpful to use a DC-50MHz current probe to monitor
thecurrentintheinductorwhiletestingthecircuit.Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
outputvoltageaswell. Checkforproperperformanceover
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 25% of the maximum designed
current level in Burst Mode operation.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
3891fa
26
LTC3891
APPLICATIONS INFORMATION
I
LIM
LTC3891
TRACK/SS
FREQ
V
IN
V
IN
PGND
C
IN
GND
PLLIN/MODE
SGND
1µF
CERAMIC
EXTV
C
CC
CC
INTVCC
C
OUT
INTV
SGND
BG
RUN
–
SENSE
M1
M2
L1
D1*
R
C1*
BOOST
SW
+
SENSE
R1*
SENSE
V
OUT
TG
V
FB
R
OUT
V
PULL-UP
PGOOD
PGOOD
ITH
3891 F10
*R1, C1 AND D1 ARE OPTIONAL
Figure 10. Recommended Printed Circuit Layout Diagram
L1
R
SENSE
SW
V
V
OUT
IN
R
IN
C
IN
D1
C
OUT
R
L1
3891 F11
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 11. Branch Current Waveforms
3891fa
27
LTC3891
APPLICATIONS INFORMATION
V
IN
4V TO 60V
C
IN
22µF
V
INTV
CC
IN
100k
LTC3891
2.2µF
PGOOD
RUN
INTV
CC
PGND
I
LIM
D1
MTOP
L1
EXTV
TG
BOOST
SW
CC
0.1µF
R
SENSE
PLLIN/MODE
FREQ
4.7µH
8mΩ
41.2k
V
3.3V
5A
OUT
C
2200pF
100pF
OUT
MBOT
10k
BG
150µF
ITH
+
SENSE
0.1µF
1nF
–
TRACK/SS
SGND
SENSE
100k
V
FB
SGND
31.6k
3891 F12
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-472KL
C
: SANYO 6TPE470M
OUT
D1: DFLS1100
Figure 12. High Efficiency 3.3V Step-Down Converter
V
IN
12.5V TO 60V
C
IN
22µF
V
INTV
CC
IN
100k
LTC3891
2.2µF
PGOOD
RUN
INTV
CC
PGND
I
LIM
D1
MTOP
L1
V
EXTV
CC
TG
BOOST
SW
OUT
0.1µF
R
SENSE
PLLIN/MODE
FREQ
8µH
9mΩ
V
12V
3A
OUT
C
470pF
OUT
MBOT
34.8k
BG
180µF
ITH
100pF
+
SENSE
0.1µF
1nF
–
TRACK/SS
SGND
SENSE
100k
V
FB
SGND
6.98k
3891 F13
MTOP, MBOT: BSC100N06LS3
L1 COILCRAFT SER1360-802KL
OUT
D1: DFLS1100
C
: SANYO 16SVP180MX
Figure 13. High Efficiency 12V Step-Down Converter
3891fa
28
LTC3891
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.75 ±0.05
1.50 REF
19 20
R = 0.05 TYP
3.00 ±0.10
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
2
2.65 ±0.10
1.65 ±0.10
4.00 ±0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ±0.05
R = 0.115
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3891fa
29
LTC3891
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3891fa
30
LTC3891
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/12 Added INTV to Absolute Maximum Ratings
2
CC
Updated FE package
30
3891fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3891
TYPICAL APPLICATION
V
IN
9V TO 60V
C
IN
22µF
V
INTV
CC
IN
100k
LTC3891
2.2µF
PGOOD
RUN
INTV
CC
PGND
I
LIM
D1
MTOP
L1
V
OUT
EXTV
CC
TG
BOOST
SW
0.1µF
R
SENSE
PLLIN/MODE
FREQ
8µH
10mΩ
V
8.5V
3A
OUT
C
470pF
OUT
MBOT
34.8k
BG
330µF
ITH
+
SENSE
0.1µF
1nF
–
TRACK/SS
SGND
SENSE
100k
V
FB
SGND
10.5k
3891 F14
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-802KL
: SANYO 10TPE330M
C
OUT
D1: DFLS1100
Figure 14. High Efficiency 8.5V Step-Down Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3890/LTC3890-1
60V, Low I , Dual Output 2-Phase Synchronous Step- Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
Q
IN
Down DC/DC Controller
0.8V ≤ V
≤ 24V, I = 50µA
OUT Q
Low I , Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,
LTC3857/LTC3857-1
LTC3858/LTC3858-1
LTC3868/LTC3868-1
LTC3834/LTC3834-1
LTC3835/LTC3835-1
LT3845A
Q
IN
DC/DC Controllers with 99% Duty Cycle
0.8V ≤ V
≤ 24V, I = 50µA
OUT Q
Low I , Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,
Q
IN
DC/DC Controllers with 99% Duty Cycle
0.8V ≤ V
≤ 24V, I = 170µA
OUT Q
Low I , Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 24V,
Q
IN
DC/DC Controller with 99% Duty Cycle
0.8V ≤ V
≤ 14V, I = 170µA
OUT Q
Low I , Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,
Q
IN
Controller with 99% Duty Cycle
0.8V ≤ V
≤ 10V, I = 30µA
OUT Q
Low I , Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,
Q
IN
Controller with 99% Duty Cycle
0.8V ≤ V
≤ 10V, I = 80µA
OUT Q
60V, Low I , Single Output Synchronous Step-Down
Adjustable Fixed Frequency 100kHz to 500kHz, 4V ≤ V ≤ 60V,
IN
Q
DC/DC Controller
1.23V ≤ V
≤ 36V, I = 120µA
OUT Q
Low I , Triple Output Buck/Buck/Boost Synchronous
Outputs ≥ 4V Remain in Regulation Through Cold Crank, 2.5V ≤ V
IN
LTC3859
Q
DC/DC Controller
≤ 38V, V
Up to 24V, V
Up to 60V, I = 55µA
OUT(BUCKS)
OUT(BOOST) Q
Low I , Single Output Step-Down Controller, 100%
Fixed 200kHz to 600kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V
≤ V , I = 40µA,
OUT IN Q
LTC3824
Q
IN
Duty Cycle
MSOP-10E
3891fa
LT 1012 REV A • PRINTED IN USA
32 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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