LTC3892-1_15_技术文档

LTC3892/LTC3892-1

60V Low I , Dual, 2-Phase

Q

Synchronous Step-Down

DC/DC Controller

DescripTion

FeaTures

The LTC^®3892/LTC3892-1 is a high performance dual

step-down DC/DC switching regulator controller that

n

Wide V Range: 4.5V to 60V (65V Abs Max)

IN

n

Wide Output Voltage Range: 0.8V ≤ V

≤ 99% • V

OUT

IN

n

Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE) drives all N-channel synchronous power MOSFET stages.

No External Bootstrap Diodes Required

Power loss and noise are minimized by operating the two

controller output stages out-of-phase.

Low Operating I : 29μA (One Channel On)

Q

Selectable Gate Drive UVLO Thresholds

The gate drive voltage can be programmed from 5V to

10V to allow the use of logic or standard-level FETs and

to maximize efficiency. Internal switches in the top gate

drivers eliminate the need for external bootstrap diodes.

Out-of-Phase Operation Reduces Required Input

Capacitance and Power Supply Induced Noise

Phase-Lockable Frequency: 75kHz to 850kHz

Programmable Fixed Frequency: 50kHz to 900kHz

Selectable Continuous, Pulse Skipping or Low Ripple

Burst Mode^®Operation at Light Loads

n

Awide4.5Vto60Vinputsupplyrangeencompassesawide

rangeofintermediatebusvoltagesandbatterychemistries.

n

Output voltages up to 99% of V can be regulated. OPTI-

Selectable Current Limit (LTC3892)

IN

LOOP^®compensation allows the transient response and

loop stability to be optimized over a wide range of output

capacitance and ESR values.

Very Low Dropout Operation: 99% Duty Cycle

Power Good Output Voltage Monitors (LTC3892)

Low Shutdown I : 3.6μA

Q

Small 32-Lead 5mm × 5mm QFN Package (LTC3892)

The 29μA no-load quiescent current extends operating

run time in battery powered systems. For a comparision

of the LTC3892 to the LTC3892-1, see Table 1 in the Pin

Functions section of this data sheet.

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,

6144194, 6177787, 6580258.

Small 28-Lead TSSOP Package (LTC3892-1)

applicaTions

n

Automotive and Industrial Power Systems

n

Distributed DC Power Systems

n

High Voltage Battery Operated Systems

Typical applicaTion

High Efficiency Dual 5V/12V Output Step-Down Converter

VIN

12.5V TO 60V

RUN1

TG1

VIN

RUN2

TG2

47µF

Efficiency vs Output Current

96

BOOST1

BOOST2

0.1µF

V

OUT

= 12V

IN

8mΩ

5.6µH

V

5mΩ

15µH

V

OUT2

OUT1

V

= 5V

95

94

93

92

91

90

89

88

5V

12V

SW1

SW2

Burst Mode OPERATION

8A

5A

BG1

BG2

220µF

150µF

LTC3892

+

SENSE1

SENSE2

100k

1nF

–

SENSE1

SENSE2

GATE DRIVE

DRV =5V

V

FB1

V

CC

FB2

DRV =6V

CC

ITH1

TRACK/SS1

ITH2

TRACK/SS2

DRV =8V

CC

DRV =10V

CC

7.15k

VPRG1

DRVSET

7.5k

34.8k

0.01

0.1

1

10

DRVUV

LOAD CURRENT (A)

100pF

0.1µF

100pF

0.1µF

3892 F01b

INTV

GND

DRV

CC

2.2nF

1nF

0.1µF

4.7µF

3892 TA01

38921f

1

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

absoluTe MaxiMuM raTings ^{(Notes 1, 3)}

EXTV Voltage ......................................... –0.3V to 14V

TH1 TH2 FB1 FB2

Input Supply Voltage (V )......................... –0.3V to 65V

CC

IN

I

, I , V , V Voltages ..................... –0.3V to 6V

Top Side Driver Voltages

DRVSET, DRVUV Voltages ........................... –0.3V to 6V

TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V

PGOOD1, PGOOD2 Voltages (LTC3892)....... –0.3V to 6V

VPRG1, ILIM Voltages (LTC3892) ................ –0.3V to 6V

Operating Junction Temperature Range (Note 2)

LTC3892E, LTC3892I, LTC3892E-1,

LTC3892I-1 ........................................ –40°C to 125°C

LTC3892H, LTC3892H-1 .................... –40°C to 150°C

LTC3892MP, LTC3892MP-1 ............... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

(BOOST1, BOOST2) ............................... –0.3V to 76V

Switch Voltage (SW1, SW2).......................... –5V to 70V

DRV , (BOOST1-SW1),

CC

(BOOST2-SW2).......................................–0.3V to 11V

BG1, BG2, TG1, TG2...........................................(Note 8)

RUN1, RUN2 Voltages................................ –0.3V to 65V

+

–

SENSE1 , SENSE2 , SENSE1

–

SENSE2 Voltages ................................. –0.3V to 65V

PLLIN/MODE, FREQ, INTV Voltages......... –0.3V to 6V

CC

pin conFiguraTion

LTC3892

LTC3892-1

TOP VIEW

1

2

TRACK/SS1

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITH1

V

FB1

+

3

SW1

SENSE1

32 31 30 29 28 27 26 25

–

4

BOOST1

BG1

FREQ

PLLIN/MODE

PGOOD1

1

2

3

4

5

6

7

8

24 BOOST1

23 BG1

5

FREQ

6

V

IN

PLLIN/MODE

V

22

21

IN

7

EXTV

CC

INTV

CC

29

GND

PGOOD2

EXTV

CC

33

GND

8

DRV

CC

RUN1

RUN2

INTV

20 DRV

CC

9

BG2

RUN1

RUN2

ILIM

BG2

19

–

10

11

12

13

14

BOOST2

SW2

18 BOOST2

17 SW2

SENSE2

+

SENSE2

9

10 11 12 13 14 15 16

TG2

V

FB2

TRACK/SS2

DRVSET

ITH2

DRVUV

FE PACKAGE

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

= 150°C, θ = 44°C/W

28-LEAD PLASTIC TSSOP

T

= 150°C, θ = 30°C/W

JA

EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND

JMAX

T

JMAX

JA

EXPOSED PAD (PIN 33) IS GND, MUST BE CONNECTED TO GND

38921f

2

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

orDer inForMaTion

LEAD FREE FINISH

LTC3892EUH#PBF

LTC3892IUH#PBF

LTC3892HUH#PBF

LTC3892MPUH#PBF

LTC3892EFE-1#PBF

LTC3892IFE-1#PBF

LTC3892HFE-1#PBF

LTC3892MPFE-1#PBF

TAPE AND REEL

PART MARKING*

3892

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LTC3892EUH#TRPBF

LTC3892IUH#TRPBF

LTC3892HUH#TRPBF

LTC3892MPUH#TRPBF

LTC3892EFE-1#TRPBF

LTC3892IFE-1#TRPBF

LTC3892HFE-1#TRPBF

32-Lead (5mm × 5mm) Plastic QFN

28-Lead Plastic TSSOP

3892

LTC3892FE-1

28-Lead Plastic TSSOP

LTC3892MPFE-1#TRPBF LTC3892FE-1

28-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

38921f

3

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, V_EXTVCC= 0V, V_DRVSET= 0V,

VPRG1 = FLOAT unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Supply Operating Voltage Range

Channel 1 Regulated Feedback Voltage

4.5

60

V

IN

(Note 4) ITH1 Voltage = 1.2V

FB1

0°Cto 85°C, VPRG1 = FLOAT (LTC3892) or LTC3892-1

VPRG1 = FLOAT (LTC3892) or LTC3892-1

VPRG1 = 0V (LTC3892) or LTC3892-1

0.792

0.788

3.234

4.890

0.800

3.3

0.808

0.812

3.366

5.110

V

l

VPRG1 = INTV (LTC3892) or LTC3892-1)

5.0

CC

V

Channel 2 Regulated Feedback Voltage

(Note 4) ITH2 Voltage = 1.2V

0°Cto 85°C

V

FB2

0.792

0.788

0.800

0.808

0.812

l

I

Channel 2 Feedback Current

Channel 1 Feedback Current

(Note 4)

–2

50

nA

FB2

(Note 4)

FB1

VPRG1 = FLOAT (LTC3892) or LTC3892-1

VPRG1 = 0V (LTC3892 Only)

–0.002

4

0.05

6

µA

VPRG1 = INTV (LTC3892 Only)

CC

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

(Note 4) V = 4.5V to 60V

0.002

0.01

0.02

0.1

%/V

%

REFLNREG

IN

l

(Note 4) Measured in Servo Loop,

∆ITH Voltage = 1.2V to 0.7V

LOADREG

(Note 4) Measured in Servo Loop,

∆ITH Voltage = 1.2V to 2V

–0.01

2

–0.1

%

g

m1,2

Transconductance Amplifier g

Input DC Supply Current

(Note 4) ITH1,2 = 1.2V, Sink/Source 5µA

mmho

m

I

(Note 5) V

= 0V

Q

DRVSET

Pulse-Skipping or Forced Continuous Mode RUN1 = 5V and RUN2 = 0V or

(One Channel On) RUN2 = 5V and RUN1 = 0V,

= 0.83V (No Load)

1.6

mA

V

FB1,2

Pulse-Skipping or Forced Continuous Mode RUN1,2 = 5V, V

(Both Channels On)

= 0.83V (No Load)

2.8

29

mA

µA

FB1,2

l

Sleep Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V or

RUN2 = 5V and RUN1 = 0V,

55

V

= 0.83V (No Load)

FB1,2

Sleep Mode (Both Channels On)

Shutdown

RUN1,2 = 5V, V

RUN1,2 = 0V

= 0.83V (No Load)

34

55

10

µA

FB1,2

3.6

UVLO

Undervoltage Lockout

DRV Ramping Up

CC

l

DRVUV = 0V

4.0

7.5

4.2

7.8

V

DRVUV = INTV

CC

DRV Ramping Down

CC

l

DRVUV = 0V

3.6

6.4

3.8

6.7

4.0

7.0

V

DRVUV = INTV

CC

V

Feedback Overvoltage Protection

Measured at V

Relative to Regulated V

FB1,2

7

10

13

1

%

OVL1,2

FB1,2

+

I

+

–

SENSE Pin Current

µA

SENSE1,2

–

SENSE Pins Current

V

< V

> V

– 0.5V

+ 0.5V

1

µA

OUT1,2

INTVCC

700

99

DF

Maximum Duty Factor for TG

Soft-Start Charge Current

In Dropout, FREQ = 0V

= 0V

97.5

8

%

MAX(TG)

I

V

10

12

µA

TRACK/SS1,2

38921f

4

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, V_EXTVCC= 0V, V_DRVSET= 0V,

VPRG1 = FLOAT unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

1.275

75

MAX

UNITS

V

l

V

ON

RUN Pin On Threshold

V , V Rising

RUN1 RUN2

1.22

1.33

RUN1,2

Hyst RUN Pin Hysteresis

mV

Maximum Current Sense Threshold

V

= 0.7V, V

– = 3.3V

SENSE1,2

SENSE(MAX)

FB1,2

l

I

= FLOAT (LTC3892) or LTC3892-1

= 0V (LTC3892 Only)

66

43

90

75

50

100

84

58

109

mV

LIM

= INTV (LTC3892 Only)

CC

V

Matching Between V

SENSE2(MAX)

and

V

= 0.7V, V

– = 3.3V

SENSE(MATCH)

SENSE1(MAX)

FB1,2

SENSE1,2

l

V

I

= FLOAT (LTC3892) or LTC3892-1

= 0V (LTC3892 Only)

–8

0

8

mV

LIM

= INTV (LTC3892 Only)

CC

Gate Driver

TG1,2

Pull-Up On-Resistance

V

= INTV

2.2

1.0

Ω

DRVSET

CC

Pull-Down On-Resistance

BG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.2

1.0

Ω

DRVSET

BDSW1,2

BOOST to DRV Switch On-Resistance

= 0V, V

= INTV

CC

3.7

Ω

CC

SW

DRVSET

TG Transition Time:

Rise Time

Fall Time

(Note 6) V

= INTV

DRVSET

= 3300pF

CC

TG1,2 t

C

25

15

ns

r

f

LOAD

BG Transition Time:

Rise Time

Fall Time

(Note 6) V

= INTV

DRVSET

= 3300pF

CC

BG1,2 t

C

25

15

ns

r

f

LOAD

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver, V

= INTV

55

50

80

ns

1D

LOAD

DRVSET

CC

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

= 3300pF Each Driver, V

1D

LOAD

CC

t

TG Minimum On-Time

(Note 7) V

= INTV

DRVSET CC

ON(MIN)1,2

DRV Linear Regulator

CC

V

DRV Voltage from Internal V LDO

V

= 0V

EXTVCC

DRVCC(INT)

CC

IN

7V < V < 60V, DRVSET = 0V

5.8

9.6

6.0

10.0

6.2

10.4

V

IN

11V < V < 60V, DRVSET = INTV

IN

CC

V

DRV Load Regulation from V LDO

I

= 0mA to 50mA, V = 0V

EXTVCC

0.9

2.0

%

LDOREG(INT)

CC

IN

CC

DRV Voltage from Internal EXTV LDO

7V < V < 13V, DRVSET = 0V

EXTVCC

11V < V

5.8

9.6

6.0

10.0

6.2

10.4

V

DRVCC(EXT)

CC

< 13V, DRVSET = INTV

EXTVCC

CC

V

DRV Load Regulation from Internal

I

= 0mA to 50mA, V = 8.5V,

EXTVCC

DRVSET

0.7

2.0

%

LDOREG(EXT)

EXTVCC

CC

EXTV LDO

V

= 0V

CC

EXTV LDO Switchover Voltage

EXTV Ramping Positive

CC

DRVUV = 0V

4.5

7.4

4.7

7.7

4.9

8.0

V

DRVUV = INTV

CC

V

EXTV Hysteresis

250

5.0

7.0

9.0

mV

V

LDOHYS

CC

Programmable DRV

R

= 50kΩ, V

= 70kΩ, V

= 90kΩ, V

= 0V

DRVCC(50kΩ)

DRVCC(70kΩ)

DRVCC(90kΩ)

CC

DRVSET

EXTVCC

= 0V

6.4

7.6

V

38921f

5

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2,3= 5V, V_EXTVCC= 0V, V_DRVSET= 0V,

VPRG1 = FLOAT unless otherwise noted.

SYMBOL

Oscillator and Phase-Locked Loop

PLLIN /V Levels

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

OH OL

f

Programmable Frequency

Low Fixed Frequency

R

=25kΩ, PLLIN/MODE = DC Voltage

= 65kΩ, PLLIN/MODE = DC Voltage

= 105kΩ, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kΩ

65kΩ

105kΩ

LOW

FREQ

375

505

V

320

485

75

380

585

850

High Fixed Frequency

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

Synchronizable Frequency

PLLIN/MODE = External Clock

l

PLLIN V

PLLIN/MODE Input High Level

PLLIN/MODE Input Low Level

PLLIN/MODE = External Clock

2.5

V

IH

IL

0.5

PGOOD1 and PGOOD2 Outputs (LTC3892 Only)

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGL

PGOOD

I

V

µA

PGOOD

V

PG

with Respect to Set Regulated Voltage

FB

V

Ramping Negative

–13

7

–10

2.5

–7

13

%

FB

Hysteresis

V

with Respect to Set Regulated Voltage

FB

V

Ramping Positive

10

2.5

%

FB

Hysteresis

t

Delay for Reporting a Fault

35

µs

PG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Ratings for extended periods may affect device reliability and lifetime.

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The LTC3892/LTC3892-1 is tested under pulsed load conditions

such that T ≈ T . The LTC3892E/LTC3892E-1 is guaranteed to meet

J

A

performance specifications from 0°C to 85°C. Specifications over the

–40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3892I/LTC3892I-1 is guaranteed over the –40°C to 125°C

operating junction temperature range, the LTC3892H/LTC3892H-1 is

guaranteed over the –40°C to 150°C operating junction temperature

range, and the LTC3892MP/LTC3892MP-1 is tested and guaranteed over

the –55°C to 150°C operating junction temperature range. High junction

temperatures degrade operating lifetimes; operating lifetime is derated

for junction temperatures greater than125°C. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors. The junction

Note 4: The LTC3892/LTC3892-1 is tested in a feedback loop that

servos V

to a specified voltage and measures the resultant V

.

ITH1,2

FB1,2

The specification at 85°C is not tested in production and is assured by

design, characterization and correlation to production testing at other

temperatures (125°C for the LTC3892E/LTC3892E-1 and LTC3892I/

LTC3892I-1, 150°C for the LTC3892H/LTC3892H-1 and LTC3892MP/

LTC3892MP-1). For the LTC3892I/LTC3892I-1 and LTC3892H/

LTC3892H-1, the specification at 0°C is not tested in production and is

assured by design, characterization and correlation to production testing

at –40°C. For the LTC3892MP/LTC3892MP-1, the specification at 0°C is

not tested in production and is assured by design, characterization and

correlation to production testing at –55°C.

temperature (T , in °C) is calculated from the ambient temperature

J

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

(T , in °C) and power dissipation (P , in Watts) according to the formula:

A

D

T = T + (P • θ )

JA

J

A

D

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

where θ = 44°C/W for the QFN package and where θ = 30°C/W for the

times are measured using 50% levels

Note 7: The minimum on-time condition is specified for an inductor

JA

TSSOP package.

peak-to-peak ripple current >40% of I

(See Minimum On-Time

MAX

Considerations in the Applications Information section)

Note 8: Do not apply a voltage or current source to these pins. They must be

connected to capacitive loads only, otherwise permanent damage may occur.

38921f

6

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical perForMance characTerisTics

Efﬁciency and Power Loss

vs Load Current

Efﬁciency vs Output Current

Efﬁciency vs Input Voltage

100

90

80

70

60

50

40

30

20

10

0

10k

1k

100

90

80

70

60

50

40

30

20

10

0

96

BURST EFFICIENCY

95

94

93

FCM LOSS

DRVSET=INTV

CC

100

10

92

91

90

89

88

87

86

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

= 10V

= 20V

= 30V

= 40V

= 50V

= 60V

V

= 12V

= 5V

PULSE-

SKIPPING

IN

DRVSET=0V

V

OUT

LOSS

FIGURE 11 CIRCUIT

BURST LOSS

1

FIGURE 11 CIRCUIT

PULSE-SKIPPING

EFFICIENCY

FIGURE 11 CIRCUIT

= 5V

V

LOAD

= 5V

=8A

V

OUT

I

FCM EFFICIENCY

Burst Mode OPERATION

0.1

0.0001 0.001

0.01

0.1

1

10

0.0001 0.001

0.01

0.1

1

10

0

5

10 15 20 25 30 35 40 45 50 55 60

LOAD CURRENT (A)

INPUT VOLTAGE (V)

3892 G01

3892 G02

3892 G03

Load Step

Burst Mode Operation

Load Step

Pulse-Skipping Mode

Load Step

Forced Continuous Mode

V

OUT

100mV/DIV

AC COUPLED

I

L

2A/DIV

L

2A/DIV

3892 G04

3892 G05

3892 G06

50µs/DIV

V

= 12V

OUT

FIGURE 13 CIRCUIT

V

= 12V

OUT

FIGURE 13 CIRCUIT

V

= 12V

OUT

FIGURE 13 CIRCUIT

IN

= 5V

Regulated Feedback Voltage vs

Temperature

Inductor Current at Light Load

Soft Start-Up

808

806

804

802

800

798

796

794

792

RUN1, 2

5V/DIV

FORCED

CONTINUOUS

MODE

V

OUT2

2V/DIV

Burst Mode

OPERATION

1A/DIV

V

OUT1

2V/DIV

PULSE

SKIPPING

MODE

3892 G07

3892 G08

2µs/DIV

2ms/DIV

FIGURE 13 CIRCUIT

V

= 12V

IN

= 5V

OUT

LOAD

-75 -50 -25

0

25 50 75 100 125 150

I

= 1mA

TEMPERATURE (°C)

FIGURE 13 CIRCUIT

3892 G09

38921f

7

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LTC3892/LTC3892-1

Typical perForMance characTerisTics

DRV_CCand EXTV_CC

vs Load Current

EXTV_CCSwitchover and DRV_CC

Voltages vs Temperature

Undervoltage Lockout

Threshold vs Temperature

6.4

11

10

9

8

7.5

7

RISING

DRV (DRVSET = INTV

CC

)

6.2

6

CC

EXTV = 0V

CC

DRVUV = INTV

CC

5.8

5.6

EXTV = 8.5V

CC

6.5

6

FALLING

DRVUV = INTV

CC

EXTV RISING

CC

5.4

5.2

8

5.5

5

EXTV FALLING

CC

7

5

4.8

EXTV = 5V

CC

DRV (DRVSET = 0V)

CC

4.5

4

DRVUV = GND

6

4.6

4.4

RISING

DRVUV = GND

EXTV RISING

CC

5

FALLING

V

= 12V

3.5

3

BIAS

4.2

4

DRVSET = GND

25 50

LOAD CURRENT (mA)

EXTV FALLING

CC

4

0

75

100

125

150

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3892 G10

3892 G11

3892 G12

SENSE Pins Total Input Current

vs V_SENSEVoltage

SENSE^–Pin Input Bias Current vs

Temperature

Foldback Current Limit

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

100

90

80

70

60

50

40

30

20

10

0

V

> INTV + 0.5V

CC

OUT

I

= INTV

CC

LIM

= FLOAT

= GND

V

< INTV – 0.5V

CC

OUT

0

5

10 15 20 25 30 35 40 45 50 55 60 65

COMMON MODE VOLTAGE (V)

–75 –50 –25

25 50 75 100 125 150

0

100 200 300 400 500 600 700 800

V

TEMPERATURE (°C)

FEEDBACK VOLTAGE (mV)

SENSE

3892 G13

3892 G14

3892 G15

Maximum Current Sense

Threshold vs Duty Cycle

Maximum Current Sense

Threshold vs I_THVoltage

Shutdown (RUN) Threshold

vs Temperature

100

90

80

70

60

50

40

30

20

10

0

100

80

1.4

1.35

1.3

5% DUTY CYCLE

PULSE-SKIPPING

60

RISING

Burst Mode

OPERATION

1.25

1.2

40

FALLING

20

1.15

1.1

I

= INTV

CC

= FLOAT

= GND

LIM

0

I

= INTV

CC

LIM

–20

–40

1.05

= FLOAT

= GND

FORCED CONTINUOUS MODE

1

0

10 20 30 40 50 60 70 80 90 100

0

0.2 0.4 0.6 0.8

(V)

1

1.2 1.4

–75 –50 –25

0

25 50 75 100 125 150

DUTY CYCLE (%)

V

TEMPERATURE (°C)

ITH

3892 G16

3892 G17

3892 G18

38921f

8

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical perForMance characTerisTics

Shutdown Current vs

DRV_CCLine Regulation

Shutdown Current vs Temperature

Input Voltage

11

10

9

8

7

6

5

4

3

2

1

0

14

V

IN

= 12V

DRVSET = INTV

CC

12

10

8

6

7

4

DRVSET = GND

6

2

5

0

5

10 15 20 25 30 35 40 45 50 55 60 65

–75 –50 –25

0

25 50 75 100 125 150

0

10

20

30

40

50

60

70

INPUT VOLTAGE (V)

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3892 G19

3892 G20

3892 G21

Oscillator Frequency vs

Temperature

TRACK/SS Pull-Up Current vs

Temperature

Quiescent Current vs Temperature

600

550

500

450

350

300

12

11.5

11

80

70

60

50

40

30

20

10

0

V

=12V

IN

ONE CHANNEL ON

FREQ = INTV

CC

Burst Mode OPERATION

DRVSET = 70kΩ

10.5

10

DRVSET=INTV

CC

9.5

9

DRVSET=GND

FREQ = GND

8.5

8

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3892 G23

3892 G24

3899 G22

38921f

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For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

pin FuncTions ^{(LTC3892 (QFN)/LTC3892-1 (TSSOP))}

FREQ (Pin 1/ Pin 5): The frequency control pin for the

internal VCO. Connecting this pin to GND forces the VCO

to a fixed low frequency of 350kHz. Connecting this pin

ILIM(Pin8/NA):CurrentComparatorSenseVoltageRange

Input. Tying this pin to GND or INTV or floating it sets

CC

the maximum current sense threshold (for both channels)

to one of three different levels (50mV, 100mV, or 75mV

respectively). This pin is only available on the LTC3892,

not the LTC3892-1. For the LTC3892-1, the maximum

current sense threshold is 75mV.

to INTV forces the VCO to a fixed high frequency of

CC

535kHz.Otherfrequenciesbetween50kHzand900kHzcan

be programmed using a resistor between FREQ and GND.

The resistor and an internal 20µA source current create a

voltage used by the internal oscillator to set the frequency.

V

(Pin11/Pin12):Thispinreceivestheremotelysensed

FB2

PLLIN/MODE (Pin 2/Pin 6): External Synchronization

Input to Phase Detector and Forced Continuous Mode

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG1 signal to be

synchronized with the rising edge of the external clock,

and the regulators will operate in forced continuous

mode. When not synchronizing to an external clock, this

input, which acts on both controllers, determines how the

LTC3892/LTC3892-1 operates at light loads. Pulling this

pin to ground selects Burst Mode operation. An internal

100kresistortogroundalsoinvokesBurstModeoperation

feedback voltage for channel 2 from an external resistor

divider across the output.

DRVUV (Pin13/Pin 14): Determines the higher or lower

DRV UVLO and EXTV switchover thresholds, as listed

CC

on the Electrical Characteristics table. Connecting DRVUV

toGNDchoosesthelowerthresholdswhereastyingDRVUV

to INTV chooses the higher thresholds.

CC

DRVSET (Pin 14/Pin 15): Sets the regulated output volt-

age of the DRV LDO regulator. Connecting this pin to

CC

GND sets DRV to 6V whereas connecting it to INTV

CC

sets DRV to 10V. Voltages between 5V and 10V can be

when the pin is floated. Tying this pin to INTV forces

CC

programmed by placing a resistor (50k to 100k) between

the DRVSET pin and GND.

continuous inductor current operation. Tying this pin to

a voltage greater than 1.1V and less than INTV – 1.3V

CC

selects pulse-skipping operation. This can be done by

DRV (Pin 20/Pin 21): Output of the Internal or External

CC

connecting a 100k resistor from this pin to INTV .

CC

Low Dropout (LDO) Regulator. The gate drivers are pow-

ered from this voltage source. The DRV voltage is set

PGOOD1, PGOOD2 (Pins 3, 4/NA): Open-Drain Logic

CC

by the DRVSET pin. Must be decoupled to ground with a

Output. PGOOD1,2 is pulled to ground when the voltage

minimum of 4.7µF ceramic or other low ESR capacitor.

on the respective V

pin is not within 10ꢀ of its set

FB1,2

Do not use the DRV pin for any other purpose.

point. These pins are only available on the LTC3892, not

the LTC3892-1.

CC

EXTV (Pin21/Pin22):ExternalPowerInputtoanInternal

CC

LDOConnectedtoDRV .ThisLDOsuppliesDRV power,

INTV (Pin 5/Pin 7): Output of the Internal 5V Low Drop-

CC

bypassing the internal LDO powered from V whenever

out Regulator. The low voltage analog and digital circuits

are powered from this voltage source. A low ESR 0.1µF

ceramic bypass capacitor should be connected between

IN

EXTV is higher than its switchover threshold (4.7V or

CC

7.7V depending on the DRVSET pin). See EXTV Con-

CC

nection in the Applications Information section. Do not

INTV and GND, as close as possible to the IC.

CC

float or exceed 14V on this pin. Do not connect EXTV

CC

RUN1, RUN2 (Pins 6, 7/Pins 8, 9): Run Control Inputs

for Each Controller. Forcing any of these pins below 1.2V

shuts down that controller. Forcing all of these pins below

0.7VshutsdowntheentireLTC3892/LTC3892-1,reducing

quiescent current to approximately 3.6µA.

to a voltage greater than V . Connect to GND if not used.

IN

V (Pin 22/Pin 23): Main Supply Pin. A bypass capacitor

IN

should be tied between this pin and the GND pin.

38921f

10

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

pin FuncTions ^{(LTC3892 (QFN)/LTC3892-1 (TSSOP))}

BG1, BG2 (Pins 23, 19/Pins 24, 20): High Current Gate

external feedback resistors or fixed 3.3V/5V output mode.

Floatingthispinallowstheoutputtobeprogrammedfrom

0.8V to 60V with an external resistor divider, regulating

Drives for Bottom N-Channel MOSFETs. Voltage swing at

these pins is from ground to DRV .

CC

V

to 0.8V. This pin is only available on the LTC3892,

FB1

BOOST1,BOOST2(Pins24,18/Pins25,19):Bootstrapped

Supplies to the Topside Floating Drivers. Capacitors are

connected between the BOOST and SW pins. Voltage

swingatBOOST1andBOOST2pinsisfromapproximately

not the LTC3892-1.

ITH1, ITH2 (Pins 29, 12/Pins 1, 13): Error Amplifier

Outputs and Switching Regulator Compensation Points.

Each associated channel’s current comparator trip point

increases with this control voltage.

DRV to (V

+ DRV ).

CC

IN1,2

CC

SW1, SW2 (Pins 25, 17/Pins 26, 18): Switch Node Con-

nections to Inductors.

V

FB1

(Pin 30/Pin 2): For the LTC3892-1, this pin receives

the remotely sensed feedback voltage for channel 1 from

an external resistor divider across the output.

TG1, TG2 (Pins 26, 16/Pins 27, 17): High Current Gate

DrivesforTop N-ChannelMOSFETs. Thesearetheoutputs

of floating drivers with a voltage swing equal to DRV

superimposed on the switch node voltage SW.

For the LTC3892, if the VPRG1 pin is floating, the V pin

CC

FB1

receives the remotely sensed feedback voltage for chan-

nel 1 from an external resistor divider across the output.

TRACK/SS1, TRACK/SS2 (Pins 27, 15/Pins 28, 16):

If VPRG1 is tied to GND or INTV , the V pin receives

CC

FB1

External Tracking and Soft-Start Input. The LTC3892/

the remotely sensed output voltage directly.

–

LTC3892-1 regulates the negative input (EA ) of the er-

+

ror amplifier to the smaller of 0.8V or the voltage on the

TRACK/SS pin. An internal 10µA pull-up current source

is connected to this pin. A capacitor to ground at this pin

sets the ramp time at start-up to the final regulated output

voltage. Alternatively, a resistor divider on another sup-

ply connected to the TRACK/SS pin allows the LTC3892/

LTC3892-1outputvoltagetotracktheothersupplyduring

start-up. The TRACK/SS pin is pulled low in shutdown or

in undervoltage lockout.

SENSE1 , SENSE2 (Pins 31, 10/Pins 3, 11): The (+)

Input to the Differential Current Comparators. The ITH pin

voltage and controlled offsets between the SENSE and

SENSE pins in conjunction with R

trip threshold.

–

+

set the current

SENSE

–

SENSE1 , SENSE2 (Pins 32, 9/Pins 4, 10): The (–) Input

–

totheDifferentialCurrentComparators.WhenSENSE1,2 is

–

greater than INTV , then SENSE1,2 pin supplies current

CC

to the current comparator.

VPRG1(Pin28/NA):Channel1OutputVoltageControlPin.

This pin sets channel 1 to adjustable output mode using

GND (Exposed Pad Pin 33/Exposed Pad Pin 29): Ground.

The exposed pad must be soldered to the PCB for rated

electrical and thermal performance.

Table 1. Summary of the Differences Between the LTC3892 and LTC3892-1

LTC3892

LTC3892-1

ILIM pin for selectable current sense voltage? Yes; 50mV, 75mV, or 100mV

No; fixed 75mV

VPRG1 pin for fixed or adjustable V

?

OUT1

Yes; fixed 3.3V or 5V (with internal resistor divider) No; only adjustable with external resistor divider

or adjustable with external resistor divider

Independent PGOOD output for each channel? Yes; PGOOD1 and PGOOD2

No PGOOD function

Package

28-Lead TSSOP (FE28)

32-Pin 5mm × 5mm QFN (UH32)

38921f

11

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

FuncTional DiagraMs

CHANNELS 1 AND 2

DRV

CC

V

IN1,2

20µA

BOOST1,2

TG1,2

FREQ

CLK2

CLK1

VCO

C

B

TOP

BOT

DROPOUT

DET

C

IN

BOT

SW1,2

TOP ON

DRV

CC

C

S

R

Q

OUT

BG1,2

GND

PFD

V

OUT1,2

Q

SWITCHING

LOGIC

SHDN

L

R

SENSE

SYNC

DET

PLLIN/MODE

0.425V

+

–

SLEEP

100k

I

R

–

+

CMP

+

–

I

LIM

+

–

3mV

–

CURRENT

LIMIT

+

SENSE1,2

2.8V

+

–

PGOOD1

–

0.88V

EA1

0.65V

SENSE1,2

–

R

B

R1

V

FB1,2

+

–

SLOPE COMP

–

+

–

0.80V

EA

+

R2

R

A

0.72V

0.88V

TRACK/SS

+

–

PGOOD2

+

–

OV

C

0.88V

C

3.5V

ITH1,2

EA2

+

–

150nA

R

SHDN

RST

C

C2

0.72V

FOLDBACK

10µA

2(V

FB

)

TRACK/SS1,2

C

SS

SHDN

RUN1,2

VPRG1

LTC3892 ONLY

NOT ON LTC3892-1

2.00V

1.20V

20µA

DRVSET

VPRG1

V

R1

0

R2

OUT1

DRVUV

FLOAT ADJUSTABLE

∞

GND

INTV

3.3V FIXED 625k 200k

5V FIXED 1.05M 200k

EXTV

CC

DRV LDO/UVLO

CC

CONTROL

VPRG1 AFFECTS CHANNEL 1 ONLY,

V

IN

V

IS ALWAYS ADJUSTABLE (R1 = 0, R2 = ∞)

OUT2

LTC3892-1 (R1 = 0, R2 = ∞)

–

+

–

+

–

+

EN

4.7V/

7.7V

DRV

CC

4R

INTV

CC

LDO

R

38921 FD

INTV

CC

38921f

12

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

operaTion ^{(Refer to the Functional Diagrams)}

on the top MOSFET continuously. The dropout detector

detects this and forces the top MOSFET off for about one-

Main Control Loop

The LTC3892/LTC3892-1 uses a constant frequency,

current mode step-down architecture. The two controller

channels operate 180° out of phase with each other. Dur-

ing normal operation, the external top MOSFET is turned

on when the clock for that channel sets the RS latch, and

twelfth of the clock period every tenth cycle to allow C to

B

recharge, resulting in about 99ꢀ duty cycle.

The INTV supply powers most of the other internal

CC

circuits in the LTC3892/LTC3892-1. The INTV LDO

CC

regulates to a fixed value of 5V and its power is derived

is turned off when the main current comparator, I

,

CMP

from the DRV supply.

resets the RS latch. The peak inductor current at which

trips and resets the latch is controlled by the voltage

CC

I

CMP

Shutdown and Start-Up (RUN, TRACK/SS Pins)

on the ITH pin, which is the output of the error ampli-

fier, EA. The error amplifier compares the output voltage

The two channels of the LTC3892/LTC3892-1 can be in-

dependently shut down using the RUN1 and RUN2 pins.

PullingaRUNpinbelow1.2Vshutsdownthemaincontrol

loop for that channel. Pulling both pins below 0.7V dis-

ablesbothcontrollersandmostinternalcircuits,including

feedback signal at the V pin (which is generated with

FB

an external resistor divider connected across the output

voltage, V , to ground) to the internal 0.800V reference

OUT

voltage.Whentheloadcurrentincreases,itcausesaslight

decrease in V relative to the reference, which causes the

FB

the DRV and INTV LDOs. In this state, the LTC3892/

CC

EA to increase the ITH voltage until the average inductor

LTC3892-1 draws only 3.6μA of quiescent current.

current matches the new load current.

Releasing a RUN pin allows a small 150nA internal current

to pull up the pin to enable that controller. Each RUN pin

maybeexternallypulledupordrivendirectlybylogic.Each

RUN pin can tolerate up to 65V (absolute maximum), so it

After the top MOSFET is turned off each cycle, the bottom

MOSFETisturnedonuntileithertheinductorcurrentstarts

to reverse, as indicated by the current comparator I , or

R

the beginning of the next clock cycle.

can be conveniently tied to V in always-on applications

IN

where one or both controllers are enabled continuously

DRV /EXTV /INTV Power

CC

and never shut down.

Power for the top and bottom MOSFET drivers is derived

from the DRV pin. The DRV supply voltage can be

The start-up of each controller’s output voltage V

is

OUT

CC

controlled by the voltage on the TRACK/SS pin (TRACK/

SS1 for channel 1, TRACK/SS2 for channel 2). When the

voltage on the TRACK/SS pin is less than the 0.8V inter-

programmed from 5V to 10V through control of the

DRVSET pin. When the EXTV pin is tied to a voltage

CC

below its switchover voltage (4.7V or 7.7V depending on

nal reference, the LTC3892/LTC3892-1 regulates the V

FB

the DRVSET voltage), the V LDO (low dropout linear

IN

voltage to the TRACK/SS pin voltage instead of the 0.8V

reference. This allows the TRACK/SS pin to be used to

program a soft-start by connecting an external capacitor

from the TRACK/SS pin to GND. An internal 10μA pull-up

current charges this capacitor creating a voltage ramp on

the TRACK/SS pin. As the TRACK/SS voltage rises linearly

from 0V to 0.8V (and beyond up to about 4V), the output

regulator) supplies power from V to DRV . If EXTV is

IN

CC

taken above its switchover voltage, the V LDO is turned

IN

off and an EXTV LDO is turned on. Once enabled, the

CC

EXTV LDO supplies power from EXTV to DRV . Us-

CC

ing the EXTV pin allows the DRV power to be derived

CC

from a high efficiency external source such as one of the

LTC3892/LTC3892-1 switching regulator outputs.

voltage V

rises smoothly from zero to its final value.

OUT

Each top MOSFET driver is biased from the floating boot-

Alternatively the TRACK/SS pins can be used to make the

start-up of V to track that of another supply. Typically,

this requires connecting to the TRACK/SS pin an external

resistor divider from the other supply to ground (see

Applications Information section).

strapcapacitor,C ,whichnormallyrechargesduringeach

B

OUT

cycle through an internal switch whenever SW goes low.

If the input voltage decreases to a voltage close to its

output, the loop may enter dropout and attempt to turn

38921f

13

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

operaTion ^{(Refer to the Functional Diagrams)}

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Forced Continuous Mode)

(PLLIN/MODE Pin)

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

Frequency Selection and Phase-Locked Loop section),

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as

in normal operation. In this mode, the efficiency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantage of lower output

voltage ripple and less interference to audio circuitry. In

forced continuous mode, the output ripple is independent

of load current. Clocking the LTC3892/LTC3892-1 from

an external source enables forced continuous mode (see

theFrequencySelectionandPhase-LockedLoopsection).

The LTC3892/LTC3892-1 can be enabled to enter high

efficiency Burst Mode operation, pulse-skipping mode, or

forced continuous conduction mode at low load currents.

To selectBurstModeoperation,tiethePLLIN/MODEpinto

GND.To selectforcedcontinuousoperation,tiethePLLIN/

MODE pin to INTV . To select pulse-skipping mode, tie

CC

thePLLIN/MODEpintoaDCvoltagegreaterthan1.1Vand

less than INTV – 1.3V. This can be done by connecting

CC

a 100kΩ resistor between PLLIN/MODE and INTV .

CC

When a controller is enabled for Burst Mode operation,

the minimum peak current in the inductor is set to ap-

proximately 25ꢀ of the maximum sense voltage even

when the voltage on the ITH pin indicates a lower value.

If the average inductor current is higher than the load cur-

rent, the error amplifier, EA, will decrease the voltage on

the ITH pin. When the ITH voltage drops below 0.425V,

the internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off. The ITH pin is

then disconnected from the output of the EA and parked

at 0.450V.

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3892/LTC3892-1 operates in PWM pulse-

skipping mode at light loads. In this mode, constant

frequency operation is maintained down to approximately

1ꢀ of designed maximum output current. At very light

loads,thecurrentcomparator,I ,mayremaintrippedfor

CMP

several cycles and force the external top MOSFET to stay

off for the same number of cycles (i.e., skipping pulses).

The inductor current is not allowed to reverse (discon-

tinuous operation). This mode, like forced continuous

operation, exhibits low output ripple as well as low audio

noise and reduced RF interference as compared to Burst

Mode operation. It provides higher low current efficiency

than forced continuous mode, but not nearly as high as

Burst Mode operation.

In sleep mode, much of the internal circuitry is turned off,

reducingthequiescentcurrentthattheLTC3892/LTC3892-

1 draws. If one channel is in sleep mode and the other

channelisshutdown,theLTC3892/LTC3892-1drawsonly

29μA of quiescent current (with DRVSET = 0V). If both

channels are in sleep mode, it draws only 34μA of quies-

cent current. In sleep mode, the load current is supplied

by the output capacitor. As the output voltage decreases,

the EA’s output begins to rise. When the output voltage

drops enough, the ITH pin is reconnected to the output

of the EA, the sleep signal goes low, and the controller

resumes normal operation by turning on the top external

MOSFET on the next cycle of the internal oscillator.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

The switching frequency of the LTC3892/LTC3892-1’s

controllers can be selected using the FREQ pin.

current comparator (I ) turns off the bottom external

R

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative. Thus,

the controller operates discontinuously.

38921f

14

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

operaTion ^{(Refer to the Functional Diagrams)}

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to GND, tied to

Output Overvoltage Protection

Each channel has an overvoltage comparator that guards

against transient overshoots as well as other more seri-

ous conditions that may overvoltage the output. When

INTV orprogrammedthroughanexternalresistor.Tying

CC

FREQ to GND selects 350kHz while tying FREQ to INTV

CC

selects535kHz. PlacingaresistorbetweenFREQandGND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 9.

the V

pin rises by more than 10ꢀ above its regula-

FB1,2

tion point of 0.800V, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared.

A phase-locked loop (PLL) is available on the LTC3892/

LTC3892-1 to synchronize the internal oscillator to an

externalclocksourcethatisconnectedtothePLLIN/MODE

pin.TheLTC3892/LTC3892-1’sphasedetectoradjuststhe

voltage(throughaninternallowpassfilter)oftheVCOinput

to align the turn-on of controller 1’s external top MOSFET

to the rising edge of the synchronizing signal. Thus, the

turn-on of controller 2’s external top MOSFET is 180° out

of phase to the rising edge of the external clock source.

Foldback Current

When the output voltage falls to less than 70ꢀ of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the V

voltage is keeping up with

FB1,2

the TRACK/SS1,2 voltage).

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

The typical capture range of the LTC3892/LTC3892-1’s

phase-locked loop is from approximately 55kHz to 1MHz,

with a guarantee to be between 75kHz and 850kHz. In

otherwords,theLTC3892/LTC3892-1’sPLLisguaranteed

to lock to an external clock source whose frequency is

between 75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling). It is recommended

that the external clock source swing from ground (0V) to

at least 2.5V.

38921f

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LTC3892/LTC3892-1

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TO SENSE FILTER

TheTypicalApplicationonthefirstpageisabasicLTC3892/

LTC3892-1applicationcircuit.LTC3892/LTC3892-1canbe

configuredtouseeitherDCR(inductorresistance)sensing

or low value resistor sensing. The choice between the two

current sensing schemes is largely a design trade-off be-

tweencost,powerconsumptionandaccuracy.DCRsensing

is becoming popular because it saves expensive current

sensing resistors and is more power efficient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

NEXT TO THE CONTROLLER

C

OUT

CURRENT FLOW

38921 F03

INDUCTOR OR R

SENSE

Figure 1. Sense Lines Placement with Inductor or Sense Resistor

Low Value Resistor Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 2a. R

output current.

is chosen based on the required

SENSE

R

(if R

is used) and inductor value. Next, the

SENSE

powerMOSFETsandSchottkydiodesareselected. Finally,

input and output capacitors are selected.

Each controller’s current comparator has a maximum

threshold V . For the LTC3892-1, V

SENSE(MAX)

is fixed at 75mV, while for the LTC3892 V

is

SENSE(MAX)

+

–

SENSE and SENSE Pins

either 50mV, 75mV or 100mV, as determined by the state

of the ILIM pin. The current comparator threshold voltage

sets the peak of the inductor current, yielding a maximum

+

–

The SENSE and SENSE pins are the inputs to the cur-

rent comparators. The common mode voltage range on

these pins is 0V to 65V (absolute maximum), enabling

the LTC3892/LTC3892-1 to regulate output voltages up

to a nominal 60V (allowing margin for tolerances and

average output current, I

, equal to the peak value less

MAX

half the peak-to-peak ripple current, ∆I . To calculate the

L

sense resistor value, use the equation:

+

transients). The SENSE pin is high impedance over the

V_SENSE(MAX)

fullcommonmoderange,drawingatmost 1μA.Thishigh

impedance allows the current comparators to be used in

R_SENSE

=

∆I_L

I_MAX

+

–

2

inductor DCR sensing. The impedance of the SENSE pin

changes depending on the common mode voltage. When

When using a controller in very low dropout conditions,

the maximum output current level will be reduced due to

theinternalcompensationrequiredtomeetstabilitycriteria

for buck regulators operating at greater than 50ꢀ duty

factor. A curve is provided in the Typical Performance

Characteristics section to estimate this reduction in peak

inductorcurrentdependingupontheoperatingdutyfactor.

–

SENSE is less than INTV – 0.5V, a small current of less

CC

–

than 1μA flows out of the pin. When SENSE is above

INTV + 0.5V, a higher current (≈700μA) flows into the

CC

pin.BetweenINTV –0.5VandINTV +0.5V, thecurrent

CC

transitions from the smaller current to the higher current.

Filter components mutual to the sense lines should be

placed close to the LTC3892/LTC3892-1, and the sense

lines should run close together to a Kelvin connection

underneaththecurrentsenseelement(showninFigure1).

Sensing current elsewhere can effectively add parasitic

inductance and capacitance to the current sense element,

degrading the information at the sense terminals and

making the programmed current limit unpredictable. If

DCR sensing is used (Figure 2b), resistor R1 should be

placed close to the switching node, to prevent noise from

coupling into sensitive small-signal nodes.

Inductor DCR Sensing

For applications requiring the highest possible efficiency

at high load currents, the LTC3892/LTC3892-1 is capable

of sensing the voltage drop across the inductor DCR, as

shown in Figure 2b. The DCR of the inductor represents

the small amount of DC winding resistance of the copper,

which can be less than 1mΩ for today’s low value, high

current inductors. In a high current application requiring

such an inductor, power loss through a sense resistor

38921f

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LTC3892/LTC3892-1

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V

IN1,2

Using the inductor ripple current value from the Inductor

ValueCalculationsection,thetargetsenseresistorvalueis:

BOOST

LTC3892/

LTC3892-1

TG

SW

BG

R

SENSE

V_SENSE(MAX)

V

OUT1,2

R_SENSE(EQUIV)

=

∆I_L

I_MAX

+

2

+

SENSE1,2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

CAP

PLACED NEAR SENSE PINS

–

SENSE1,2

minimum value for V

teristics table.

in the Electrical Charac-

SENSE(MAX)

GND

38921 F04a

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of copper resistance, which is approximately

(2a) Using a Resistor to Sense Current

V

IN1,2

0.4ꢀ/°C. A conservative value for T

is 100°C.

L(MAX)

BOOST

INDUCTOR

DCR

LTC3892/

LTC3892-1

To scale the maximum inductor DCR to the desired sense

TG

SW

BG

L

resistor value (R ), use the divider ratio:

D

OUT1,2

R_SENSE(EQUIV)

R_D=

DCR_MAXatT_L(MAX)

R1

R2

+

SENSE1,2

C1*

C1isusuallyselectedtobeintherangeof0.1μFto0.47μF.

ThisforcesR1||R2toaround2k, reducingerrorthatmight

–

SENSE1,2

GND

*PLACE C1 NEAR SENSE PINS

+

have been caused by the SENSE pin’s 1μA current.

(R1||R2) • C1 = L/DCR

= DCR(R2/(R1+R2))

38921 F04b

R

SENSE(EQ)

The equivalent resistance R1||R2 is scaled to the room

temperature inductance and maximum DCR:

(2b) Using the Inductor DCR to Sense Current

Figure 2. Current Sensing Methods

L

R1R2=



(DCR at 20°C)•C1

wouldcostseveralpointsofefficiencycomparedtoinduc-

tor DCR sensing.

The sense resistor values are:

R1R2

R_D

R1•R_D

1− R_D

If the external (R1||R2) • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult

the manufacturers’ data sheets for detailed information.

R1=

; R2=



The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

V

_IN(MAX)− V_OUT•V

(

)

OUT

P

_LOSSR1=

R1

38921f

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Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor,

due to the extra switching losses incurred through R1.

However,DCRsensingeliminatesasenseresistor,reduces

conduction losses and provides higher efficiency at heavy

loads.Peakefficiencyisaboutthesamewitheithermethod.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. Core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET switching and gate charge losses. In addition to

this basic trade-off, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

Power MOSFET and Schottky Diode

(Optional) Selection

Two external power MOSFETs must be selected for each

controller in the LTC3892/LTC3892-1: one N-channel

MOSFET for the top (main) switch and one N-channel

MOSFET for the bottom (synchronous) switch.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current, ∆I , decreases with higher induc-

L

tance or higher frequency and increases with higher V :

IN

The peak-to-peak drive levels are set by the DRV volt-

CC









1

V_OUT

age. This voltage can range from 5V to 10V depending

on configuration of the DRVSET pin. Therefore, both

logic-level and standard-level threshold MOSFETs can be

used in most applications depending on the programmed

∆I_L=

V_OUT1−





f L

( )( )

V

IN

Accepting larger values of ∆I allows the use of low

L

inductances, but results in higher output voltage ripple

DRV voltage. Different UVLO thresholds appropriate

CC

and greater core losses. A reasonable starting point for

for logic-level or standard-level threshold MOSFETs can

setting ripple current is ∆I = 0.3(I

). The maximum

MAX

L

be selected by the DRVUV pin. Pay close attention to the

∆I occurs at the maximum input voltage.

L

BV

specification for the MOSFETs as well.

DSS

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

TheLTC3892/LTC3892-1’suniqueabilitytoadjustthegate

drive level between 5V to 10V (OPTI-DRIVE) allows an

application circuit to be precisely optimized for efficiency.

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efficiency has

improved. If there is no change in input current, then there

is no change in efficiency.

25ꢀ of the current limit determined by R

. Lower

SENSE

inductor values (higher ∆I ) will cause this to occur at

L

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

Selection criteria for the power MOSFETs include the

on-resistance R

, Miller capacitance C

DS(ON)

, input

MILLER

38921f

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voltage and maximum output current. Miller capacitance,

MILLER

a short-circuit when the synchronous switch is on close

to 100ꢀ of the period.

C

, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

The term (1 + δ) is generally given for a MOSFET in the

MILLER

form of a normalized R

vs Temperature curve, but

DS(ON)

along the horizontal axis while the curve is approximately

δ = 0.005/°C can be used as an approximation for low

flat divided by the specified change in V . This result is

DS

voltage MOSFETs.

then multiplied by the ratio of the application applied V

DS

Optional Schottky diodes placed across the synchronous

MOSFET conduct during the dead-time between the con-

duction of the two power MOSFETs. This prevents the

body diode of the synchronous MOSFET from turning

on, storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3ꢀ

to the gate charge curve specified V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Main Switch Duty Cycle =

V

IN

V − V

in efficiency at high V . A 1A to 3A Schottky is generally

IN

OUT

Synchronous Switch Duty Cycle =

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

V

IN

The MOSFET power dissipations at maximum output

current are given by:

2

V_OUT

C and C Selection

OUT

P_MAIN

=

I

(

1+ δ R

+

(

)

IN

)

OUT(MAX)

DS(ON)

V

IN

The selection of C is simplified by the 2-phase architec-

IN

I







_OUT(MAX)

ture and its impact on the worst-case RMS current drawn

throughtheinputnetwork(battery/fuse/capacitor).Itcanbe

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

(V )²

(R_DR)(C_MILLER)•

IN



2









1

+

(f)





V_DRVCC− V_THMINV_THMIN

the highest (V )(I ) product needs to be used in the



OUT OUT

formula shown in Equation 1 to determine the maximum

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The opt-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30ꢀ

to 70ꢀ when compared to a single phase power supply

solution.

2

V − V

IN

OUT

P_SYNC

=

I

(

1+ δ R

DS(ON)

(

)

OUT(MAX)

V

IN

where δ is the temperature dependency of R

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

typical MOSFET minimum threshold voltage.

is the

THMIN

2

Both MOSFETs have I R losses while the main N-channel

equations include an additional term for transition losses,

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

which are highest at high input voltages. For V < 20V

IN

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

^1/2

I_MAX

MILLER



C_INRequired I_RMS

≈

V

_OUT)(

V − V

IN

OUT

(

)

(1)

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during





V

IN

38921f

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LTC3892/LTC3892-1

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where f is the operating frequency, C

is the output

This formula has a maximum at V = 2V , where I

OUT

IN

OUT

RMS

capacitance and ∆I is the ripple current in the inductor.

= I /2. This simple worst-case condition is commonly

L

OUT

The output ripple is highest at maximum input voltage

usedfordesignbecauseevensignificantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3892/LTC3892-1, ceramic

since ∆I increases with input voltage.

L

Setting Output Voltage

The LTC3892/LTC3892-1 output voltages are set by an

external feedback resistor divider carefully placed across

the output, as shown in Figure 3a. The regulated output

voltage is determined by:

capacitors can also be used for C . Always consult the

IN









R_B

R_A

manufacturer if there is any question.

V_OUT= 0.8V 1+





The benefit of the LTC3892/LTC3892-1 2-phase opera-

tion can be calculated by using Equation 1 for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when

both controllers are operating due to the reduced overlap

of current pulses required through the input capacitor’s

ESR. This is why the input capacitor’s requirement cal-

culated above for the worst-case controller is adequate

for the dual controller design. Also, the input protection

fuse resistance, battery resistance, and PC board trace

resistance losses are also reduced due to the reduced

peak currents in a 2-phase system. The overall benefit of

a multiphase design will only be fully realized when the

source impedance of the power supply/battery is included

in the efficiency testing. The drains of the top MOSFETs

should be placed within 1cm of each other and share a

To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

For the LTC3892, channel 1 has the option to be pro-

grammed to a fixed 5V or 3.3V output through control of

theVPRG1pin(notavailableontheLTC3892-1).Figure3b

shows how the V

pin is used to sense the output

FB1

voltage in fixed output mode. Tying VPRG1 to INTV or

CC

GND programs V

to 5V or 3.3V, respectively. Float-

to adjustable output mode using

OUT1

ing VPRG1 sets V

external resistors.

OUT1

V

OUT

1/2 LTC3892/

LTC3892-1

R

C

FF

B

A

common C (s). Separating the drains and C may pro-

IN

V

FB

duce undesirable voltage and current resonances at V .

IN

A small (0.1μF to 1μF) bypass capacitor between the chip

BIAS

38921 F05a

V

pin and ground, placed close to the LTC3892, is also

(3a) Setting Adjustable Output Voltage

suggested. A 2.2Ω to 10Ω resistor placed between C

IN

(C1) and the V

pin provides further isolation.

BIAS

LTC3892

The selection of C

is driven by the effective series

OUT

V

OUT1

resistance (ESR). Typically, once the ESR requirement

INTV /GND

CC

VPRG1

V

FB1

5V/3.3V

is satisfied, the capacitance is adequate for filtering. The

C

OUT

output ripple (∆V ) is approximated by:

38921 F05b

OUT





1

(3b) Setting CH1 (LTC3892) to Fixed 5V/3.3V Voltage

Figure 3. Setting Buck Output Voltage

∆V_OUT≈ ∆I_LESR+







8•f•C_OUT



38921f

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RUN Pins

Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins)

The LTC3892/LTC3892-1 is enabled using the RUN1 and The start-up of each V

is controlled by the voltage on

OUT

RUN2pins.TheRUNpinshavearisingthresholdof1.275V theTRACK/SSpin(TRACK/SS1forchannel1,TRACK/SS2

with 75mV of hysteresis. Pulling a RUN pin below 1.2V for channel 2). When the voltage on the TRACK/SS pin

shuts down the main control loop for that channel. Pulling is less than the internal 0.8V reference, the LTC3892/

both RUN pins below 0.7V disables the controllers and LTC3892-1 regulates the V pin voltage to the voltage

FB

most internal circuits, including the DRV and INTV

on the TRACK/SS pin instead of the internal reference.

LDOs. In this state, the LTC3892/LTC3892-1 draws only The TRACK/SS pin can be used to program an external

CC

3.6µA of quiescent current.

soft-start function or to allow V

ply during start-up.

to track another sup-

OUT

Releasing a RUN pin allows a small 150nA internal current

to pull up the pin to enable that controller. Because of Soft-start is enabled by simply connecting a capacitor

condensation or other small board leakage pulling the pin from the TRACK/SS pin to ground, as shown in Figure 5.

down,itisrecommendedtheRUNpinsbeexternallypulled An internal 10μA current source charges the capacitor,

up or driven directly by logic. Each RUN pin can tolerate providing a linear ramping voltage at the TRACK/SS pin.

up to 65V (absolute maximum), so it can be conveniently The LTC3892/LTC3892-1 will regulate its feedback volt-

tied to V in always-on applications where one or more age (and hence V ) according to the voltage on the

IN

OUT

controllersareenabledcontinuouslyandnevershutdown. TRACK/SS pin, allowing V

to rise smoothly from 0V

OUT

to its final regulated value. The total soft-start time will be

The RUN pins can be implemented as a UVLO by con-

necting them to the output of an external resistor divider

network off V , as shown in Figure 4.

approximately:

0.8V

t_SS= C_SS•

10µA

IN

V

IN

1/2 LTC3892/

LTC3892-1

1/2 LTC3892/

LTC3892

R

B

A

RUN

TRACK/SS

C

SS

3892 F04

GND

38921 F06

Figure 4. Using the RUN Pins as a UVLO

Figure 5. Using the TRACK/SS Pin to Program Soft-Start

TherisingandfallingUVLOthresholdsarecalculatedusing

the RUN pin thresholds and pull-up current:





R_B

R_A

V_UVLO(RISING)= 1.275V 1+

– 150nA •R_B





















R_B

R_A

V_{UVLO(FALLING)}= 1.20V 1+

38921f

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V

OUT

Alternatively, the TRACK/SS1 and TRACK/SS2 pins can

be used to track two (or more) supplies during start-up,

as shown qualitatively in Figures 6a and 6b. To do this, a

resistordividershouldbeconnectedfromthemastersup-

R

B

V

FB

R

A

ply (V ) to the TRACK/SS pin of the slave supply (V ),

X

OUT

V

1/2 LTC3892/

LTC3892-1

X

as shown in Figure 7. During start-up V

according to the ratio set by the resistor divider:

will track V

OUT

X

R

TRACKB

TRACK/SS

V_X

R_A

R_TRACKA+ R_TRACKB

R_A+ R_B

TRACKA

38921 F08

=

•

V_OUTR_TRACKA

Figure 7. Using the TRACK/SS Pin for Tracking

For coincident tracking (V

= V during start-up),

X

OUT

R = R

A

TRACKA

TRACKB

DRV and INTV Regulators and EXTV

CC

R = R

B

(OPTI-DRIVE)

The LTC3892/LTC3892-1 features two separate internal

P-channellowdropoutlinearregulators(LDO)thatsupply

V

X(MASTER)

OUT(SLAVE)

powerattheDRV pinfromeithertheV supplypinorthe

CC

IN

EXTV pin depending on the connections of the EXTV ,

CC

DRVSET, and DRVUV pins. A third P-channel LDO sup-

plies power at the INTV pin from the DRV pin. DRV

CC

powers the gate drivers whereas INTV powers much of

CC

the LTC3892/LTC3892-1’s internal circuitry. The V LDO

IN

and the EXTV LDO regulate DRV between 5V to 10V,

CC

38921 F07a

TIME

depending on how the DRVSET pin is set. Each of these

LDOs can supply a peak current of at least 50mA and must

be bypassed to ground with a minimum of 4.7μF ceramic

capacitor. Good bypassing is needed to supply the high

transientcurrentsrequiredbytheMOSFETgatedriversand

(6a) Coincident Tracking

V

X(MASTER)

to prevent interaction between the channels. The INTV

CC

supply must be bypassed with a 0.1μF ceramic capacitor.

OUT(SLAVE)

The DRVSET pin programs the DRV supply voltage and

CC

the DRVUV pin selects different DRV UVLO and EXTV

CC

switchover threshold voltages. Table 2a summarizes the

different DRVSET pin configurations along with the volt-

age settings that go with each configuration. Table 2b

summarizes the different DRVUV pin settings. Tying the

38921 F07b

TIME

(6b) Ratiometric Tracking

Figure 6. Two Different Modes of Output Voltage Tracking

DRVSET pin to INTV programs DRV to 10V. Tying the

CC

38921f

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LTC3892/LTC3892-1

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as discussed in the Efficiency Considerations section.

The junction temperature can be estimated by using the

equations given in Note 2 of the Electrical Characteristics.

For example, using the LTC3892 in the QFN package and

DRVSET pin to GND programs DRV to 6V. By placing

CC

a 50k to 100k resistor between DRVSET and GND the

DRV voltage can be programmed between 5V to 10V,

CC

as shown in Figure 8.

setting DRV to 6V, the DRV current is limited to less

CC

Table 2a

than 37mA from a 40V supply when not using the EXTV

CC

DRVSET PIN

DRV VOLTAGE

CC

supply at a 70°C ambient temperature:

GND

6V

10V

T = 70°C + (37mA)(40V – 6V)(44°C/W) = 125°C

J

INTV

CC

Resistor to GND 50k to 100k

5V to 10V

To prevent the maximum junction temperature from being

exceeded, the V supply current must be checked while

IN

Table 2b

operating in forced continuous mode (PLLIN/MODE =

DRV UVLO

EXTV SWITCHOVER

CC

INTV ) at maximum V .

CC

IN

RISING / FALLING

THRESHOLD

DRVUV PIN

GND

INTV

THRESHOLDS

4.0V / 3.8V

7.5V / 6.7V

When the voltage applied to EXTV rises above its

CC

4.7V / 4.45V

7.7V / 7.45V

switchover threshold, the V LDO is turned off and the

IN

CC

EXTV LDO is enabled. The EXTV LDO remains on as

CC

long as the voltage applied to EXTV remains above the

CC

switchover threshold minus the comparator hysteresis.

11

10

The EXTV LDO attempts to regulate the DRV voltage

CC

tothevoltageasprogrammedbytheDRVSETpin,sowhile

9

EXTV is less than this voltage, the LDO is in dropout

CC

and the DRV voltage is approximately equal to EXTV .

8

7

6

5

CC

When EXTV is greater than the programmed voltage,

CC

up to an absolute maximum of 14V, DRV is regulated

CC

to the programmed voltage.

Using the EXTV LDO allows the MOSFET driver and

CC

control power to be derived from one of the LTC3892/

4

50

65

55 60

70

75 80 85 90 95 100

LTC3892-1’s switching regulator outputs (4.7V/7.7V ≤

DRVSET PIN RESISTOR (kΩ)

38921 F09

V

≤14V)duringnormaloperationandfromtheV LDO

IN

OUT

Figure 8. Relationship Between DRV_CCVoltage

and Resistor Value at DRVSET Pin

when the output is out of regulation (e.g., start-up, short

circuit). If more current is required through the EXTV

CC

LDO than is specified, an external Schottky diode can be

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the

maximum junction temperature rating for the LTC3892/

added between the EXTV and DRV pins. In this case,

CC

do not apply more than 10V to the EXTV pin and make

CC

sure that EXTV ≤ V .

CC

IN

LTC3892-1 to be exceeded. The DRV current, which is

CC

dominated by the gate charge current, may be supplied by

Significant efficiency and thermal gains can be realized

by powering DRV from the output, since the V cur-

either the V LDO or the EXTV LDO. When the voltage

IN

CC

IN

on the EXTV pin is less than its switchover threshold

CC

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

(4.7V or 7.7V as determined by the DRVUV pin described

above), the V LDO is enabled. Power dissipation for the

IN

For 5V to 14V regulator outputs, this means connecting

IC in this case is highest and is equal to V • I

. The

IN DRVCC

the EXTV pin directly to V . Tying the EXTV pin to

CC

OUT

CC

gate charge current is dependent on operating frequency

38921f

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an 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

Fault Conditions: Current Limit and

Current Foldback

T = 70°C + (37mA)(8.5V – 6V)(34.7°C/W) = 74°C

TheLTC3892/LTC3892-1includescurrentfoldbacktohelp

limit load current when the output is shorted to ground. If

the output voltage falls below 70ꢀ of its nominal output

level, then the maximum sense voltage is progressively

lowered from 100ꢀ to 40ꢀ of its maximum selected

value. Under short-circuit conditions with very low duty

cycles, the channel will begin cycle skipping in order to

limit the short-circuit current. In this situation the bottom

MOSFET will be dissipating most of the power but less

than in normal operation. The short-circuit ripple cur-

J

However,for3.3Vandotherlowvoltageoutputs,additional

circuitryisrequiredtoderiveDRV powerfromtheoutput.

CC

The following list summarizes the four possible connec-

tions for EXTV :

CC

1. EXTV grounded.ThiswillcauseDRV tobepowered

CC

from the internal V regulator resulting in increased

IN

power dissipation in the LTC3892/LTC3892-1 at high

input voltages.

rent is determined by the minimum on-time, t

, of

ON(MIN)

2. EXTV connected directly to V . This is the normal

CC

OUT

the LTC3892/LTC3892-1 (≈80ns), the input voltage and

inductor value:

connection for a 5V to 14V regulator and provides the

highest efficiency.

V

L



_IN

∆I_L(SC)= t

3. EXTV_CCconnected to an external supply. If an external

supplyisavailableinthe5Vto14Vrange,itmaybeusedto

powerEXTV_CCprovidingitiscompatiblewiththeMOSFET

gate drive requirements. Ensure that EXTV_CC< V_IN.





^ON(MIN)



The resulting average short-circuit current is:

1

2

I_SC= 40ꢀ•I_LIM(MAX)− ∆I_L(SC)

4. EXTV connected toan output-derived boostnetwork.

CC

For 3.3V and other low voltage regulators, efficiency

gains can still be realized by connecting EXTV to an

CC

Fault Conditions: Overvoltage Protection (Crowbar)

output-derivedvoltagethathasbeenboostedtogreater

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to flow, that blow the fuse to protect against a

shortedtopMOSFETiftheshortoccurswhilethecontroller

is operating.

than 4.7V/7.7V.

Topside MOSFET Driver Supply (C )

B

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

pins supply the gate drive voltage for the topside MOS-

FET. The LTC3892/LTC3892-1 features an internal switch

between DRV and the BOOST pin for each controller.

A comparator monitors the output for overvoltage condi-

tions. The comparator detects faults greater than 10ꢀ

above the nominal output voltage. When this condition

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. ThebottomMOSFETremainsoncontinuouslyfor

CC

These internal switches eliminate the need for external

bootstrapdiodesbetweenDRV andBOOST.CapacitorC

CC

B

in the Functional Diagram is charged through this internal

switch from DRV when the SW pin is low. When the

CC

topside MOSFET is to be turned on, the driver places the

C voltage across the gate-source of the MOSFET. This

aslongastheovervoltageconditionpersists;ifV returns

B

OUT

enhances the top MOSFET switch and turns it on. The

to a safe level, normal operation automatically resumes.

switch node voltage, SW, rises to V and the BOOST pin

IN

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

follows. With the topside MOSFET on, the boost voltage is

above the input supply: V

= V + V

. The value

BOOST

IN

DRVCC

of the boost capacitor, C , needs to be 100 times that of

B

the total input capacitance of the topside MOSFET(s).

38921f

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Fault Conditions: Overtemperature Protection

75kHz and 850kHz. Typically, the external clock (on the

PLLIN/MODE pin) input high threshold is 1.6V, while the

input low threshold is 1.1V. The LTC3892/LTC3892-1 is

guaranteedtosynchronizetoanexternalclockthatswings

up to at least 2.5V and down to 0.5V or less.

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on chip

(such as DRV short to ground), the overtemperature

CC

shutdowncircuitrywillshutdowntheLTC3892/LTC3892-1.

When the junction temperature exceeds approximately

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired

synchronization frequency. The VCO’s input voltage is

prebiased at a frequency corresponding to the frequency

set by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock and

synchronization. Although it is not required that the free-

running frequency be near the external clock frequency,

doingsowillpreventtheoperatingfrequencyfrompassing

through a large range of frequencies as the PLL locks.

175°C, the overtemperature circuitry disables the DRV

CC

LDO, causing the DRV supply to collapse and effectively

CC

shutting down the entire LTC3892/LTC3892-1 chip. Once

the junction temperature drops back to the approximately

155°C, the DRV LDO turns back on. Long-term over-

CC

stress (T > 125°C) should be avoided as it can degrade

J

the performance or shorten the life of the part.

Phase-Locked Loop and Frequency Synchronization

The LTC3892/LTC3892-1 has an internal phase-locked

loop (PLL) comprised of a phase frequency detector, a

lowpass filter, and a voltage-controlled oscillator (VCO).

This allows the turn-on of the top MOSFET of controller 1

to be locked to the rising edge of an external clock signal

applied to the PLLIN/MODE pin. The turn-on of controller

2’stopMOSFETisthus180°outofphasewiththeexternal

clock. The phase detector is an edge sensitive digital type

thatprovideszerodegreesphaseshiftbetweentheexternal

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

Table 3 summarizes the different states in which the FREQ

pin can be used. When synchronized to an external clock,

the LTC3892/LTC3892-1 operates in forced continuous

mode at light loads.

Table 3

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor to GND

Any of the Above

DC Voltage

50kHz to 900kHz

External Clock

75kHz to 850kHz

Phase Locked to

External Clock

If the external clock frequency is greater than the internal

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

Minimum On-Time Considerations

ously from the phase detector output, pulling up the VCO

Minimum on-time, t

, is the smallest time duration

ON(MIN)

input. When the external clock frequency is less than f

,

OSC

current is sunk continuously, pulling down the VCO input.

1000

900

800

700

600

500

400

300

200

100

0

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input.

Note that the LTC3892/LTC3892-1 can only be synchro-

nized to an external clock whose frequency is within range

oftheLTC3892/LTC3892-1’sinternalVCO, whichisnomi-

nally 55kHz to 1MHz. This is guaranteed to be between

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

38921 F10

Figure 9. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

38921f

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that the LTC3892/LTC3892-1 is capable of turning on the

top MOSFET. It is determined by internal timing delays

and the gate charge required to turn on the top MOSFET.

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that:

in a small (<0.1ꢀ) loss.

2. DRV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

V_OUT

t_ON(MIN)

<

from DRV to ground. The resulting dQ/dt is a cur-

V (f)

CC

IN

rent out of DRV that is typically much larger than the

CC

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

the topside and bottom side MOSFETs.

SupplyingDRV fromanoutput-derivedsourcepower

CC

The minimum on-time for the LTC3892/LTC3892-1 is

approximately 80ns. However, as the peak sense voltage

decreases, the minimum on-time gradually increases up

to about 130ns. This is of particular concern in forced

continuous applications with low ripple current at light

loads. If the duty cycle drops below the minimum on-

time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

through EXTV will scale the V current required for

CC

IN

thedriverandcontrolcircuitsbyafactorof(DutyCycle)/

(Efficiency). For example, in a 20V to 5V application,

10mAofDRV currentresultsinapproximately2.5mA

CC

of V current. This reduces the midcurrent loss from

IN

10ꢀ or more (if the driver was powered directly from

V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor and input and output capacitor ESR. In continuous

mode the average output current flows through L and

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100ꢀ.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

R

, but is chopped between the topside MOSFET

SENSE

and the synchronous MOSFET. If the two MOSFETs

have approximately the same R

, then the resis-

DS(ON)

tance of one MOSFET can simply be summed with the

2

resistances of L, R

and ESR to obtain I R losses.

DS(ON)

SENSE

For example, if each R

= 30mΩ, R = 50mΩ,

L

ꢀEfficiency = 100ꢀ – (L1 + L2 + L3 + ...)

R

= 10mΩ and R

= 40mΩ (sum of both input

SENSE

ESR

andoutputcapacitancelosses),thenthetotalresistance

is 130mΩ. This results in losses ranging from 3ꢀ to

13ꢀ as the output current increases from 1A to 5A for

a 5V output, or a 4ꢀ to 20ꢀ loss for a 3.3V output.

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

Efficiency varies as the inverse square of V

for the

OUT

losses in LTC3892/LTC3892-1 circuits: 1) IC V current,

IN

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

2

2) DRV regulator current, 3) I R losses, 4) Topside

CC

MOSFET transition losses.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driverandcontrolcurrents. V currenttypicallyresults

IN

4. Transition losses apply only to the top MOSFET(s), and

become significant only when operating at high input

38921f

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voltages (typically 20V or greater). Transition losses

The ITH series R -C filter sets the dominant pole-zero

C

can be estimated from:

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20ꢀ

to 80ꢀ of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Transition Loss = (1.7) • V • 2 • I

• C

• f

IN

O(MAX)

RSS

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5ꢀ

to 10ꢀ efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

C has adequate charge storage and very low ESR at

IN

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. Other

losses including Schottky conduction losses during

dead-time and inductor core losses generally account

for less than 2ꢀ total additional loss.

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

andisthefilteredandcompensatedcontrolloopresponse.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

load current. When a load step occurs, V

shifts by an

OUT

creasing C . If R is increased by the same factor that C

C

amount equal to ∆I

, where ESR is the effective

LOAD(ESR)

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

series resistance of C . ∆I

also begins to charge or

generating the feedback error signal that

OUT

LOAD

discharge C

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recov-

OUT

ery time V

can be monitored for excessive overshoot

OUT

or ringing, which would indicate a stability problem.

OPTI-LOOPcompensationallowsthetransientresponseto

be optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC-coupled and AC-filtered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming

a predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also

be estimated by examining the rise time at the pin. The

ITH external components shown in Figure 12 circuit will

provide an adequate starting point for most applications.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise-time

LOAD

OUT

should be controlled so that the load rise-time is limited

to approximately 25 • C . Thus a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

38921f

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Design Example

A short-circuit to ground will result in a folded back cur-

rent of:

As a design example for one channel, assume V = 12V

IN

(nominal), V = 22V (maximum), V

= 3.3V, I

=

80ns 22V

0.01Ω 2 4.7µH 

34mV 1





(

)

IN

OUT

MAX

I_SC=

−



= 3.21A

5A, V

= 75mV and f = 350kHz. The inductance

SENSE(MAX)

value is chosen first based on a 30ꢀ ripple current as-

sumption. The highest value of ripple current occurs at

the maximum input voltage. Tie the FREQ pin to GND,

generating 350kHz operation. The minimum inductance

for 30ꢀ ripple current is:

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

2

P

SYNC

= (3.21A) (1.125) (0.022Ω) = 255mW







V_OUT

f L

( )( )

V_OUT

which is less than under full-load conditions.

∆I_L=

1−



V



_IN(NOM)

C is chosen for an RMS current rating of at least 3A at

IN

temperature assuming only this channel is on. C

is

OUT

A 4.7μH inductor will produce 29ꢀ ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.73A. Increasing the ripple

current will also help ensure that the minimum on-time

of 80ns is not violated. The minimum on-time occurs at

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

V

= R (∆I ) = 0.02Ω (1.45A) = 29mV

ESR L P-P

maximum V :

O(RIPPLE)

IN

V_OUT

_IN(MAX)( )

3.3V

PC Board Layout Checklist

t_ON(MIN)

=

= 429ns

V

f

22V 350kHz

(

)

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

IC. Figure 10 illustrates the current waveforms present in

the various branches of the 2-phase synchronous buck

regulators operating in the continuous mode. Check the

following in your layout:

The equivalent R

resistor value can be calculated by

SENSE

using the minimum value for the maximum current sense

threshold (66mV):

66mV

5.73A

R_SENSE

≤

≈ 0.01Ω

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

Choosing 1ꢀ resistors: R = 25k and R = 78.7k yields

an output voltage of 3.32V.

A

B

connection at C ? Do not attempt to split the input

IN

decoupling for the two channels as it can cause a large

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

results in: R

= 0.035Ω/0.022Ω, C

= 215pF.

DS(ON)

MILLER

At maximum input voltage with T(estimated) = 50°C:

of C

must return to the combined C

(–) termi-

DRVCC

OUT

3.3V

22V

2

nals. The path formed by the top N-channel MOSFET,

P_MAIN

=

5A 1+ 0.005 50°C− 25°C 

(

)

(

)

(

)





Schottky diode and the C capacitor should have short

IN

₂5A

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

0.035Ω + 22V

) (

2.5Ω 215pF •

)(

(

)

(

)

2

1







+

350kHz = 331mW

(

)







5V− 2.3V 2.3V

38921f

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SW1

L1

R

SENSE1

V

OUT1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38921 F11

Figure 10. Branch Current Waveforms

3. DoestheLTC3892/LTC3892-1V pin’sresistivedivider

6. Keep the switching nodes (SW1, SW2), top gate (TG1,

TG2), and boost nodes (BOOST1, BOOST2) away from

sensitive small-signal nodes, especially from the op-

positeschannel’svoltageandcurrentsensingfeedback

pins. All of these nodes have very large and fast moving

signals and therefore should be kept on the output side

of the LTC3892/LTC3892-1 and occupy minimum PC

trace area.

FB

connecttothe(+)terminalofC ?Theresistivedivider

OUT

must be connected between the (+) terminal of C

OUT

and signal ground. The feedback resistor connections

should not be along the high current input feeds from

the input capacitor(s).

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

7. Useamodifiedstargroundtechnique:alowimpedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

with tie-ins for the bottom of the DRV decoupling

CC

5. IstheDRV anddecouplingcapacitorconnectedclose

CC

capacitor, the bottom of the voltage feedback resistive

to the IC, between the DRV and the ground pin? This

CC

divider and the GND pin of the IC.

capacitor carries the MOSFET drivers’ current peaks.

38921f

29

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

applicaTions inForMaTion

PC Board Layout Debugging

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequencyofoperationshouldbemaintainedovertheinput

voltage range down to dropout and until the output load

drops below the low current operation threshold—typi-

cally 25ꢀ of the maximum designed current level in Burst

Mode operation.

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controllerischeckedforitsindividualperformanceshould

both should multiple controllers be turned on at the same

time. A particularly difficult region of operation is when

one channel is nearing its current comparator trip point

when the other channel is turning on its top MOSFET. This

occurs around 50ꢀ duty cycle on either channel due to

the phasing of the internal clocks and may cause minor

duty cycle jitter.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

GND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

38921f

30

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical applicaTions

VIN

8V TO 60V

C

2.2µF

x5

C

47µF

INB

INA

RUN1

TG1

VIN

RUN2

TG2

MTOP1

MTOP2

BOOST1

BOOST2

R

SNS2

8mΩ

L1

5.6µH

L2

15µH

R

5mΩ

SNS1

C

B2

0.1µF

B1

V

OUT2

0.1µF

OUT1

SW1

SW2

5V

12V*

8A

OUT1A

5A

OUT2A

C

OUT1B

10µF

C

OUT2B

10µF

MBOT1

MBOT2

BG1

BG2

220µF

150µF

LTC3892

+

SENSE1

SENSE2

R

A2

100k

C

SNS1

1nF

SNS2

1nF

–

SENSE1

SENSE2

V

FB1

ITH1

V

FB2

ITH2

R

7.15k

B2

TRACK/SS1

TRACK/SS2

R

PG1

1000k

EXTV

V

OUT2

C

R

34.8k

PGOOD1

R

7.5k

CC

C

ITH2B

ITH2

ITH1

ITH1B

R

100pF

PG2

1000k

ILIM

PGOOD2

VPRG1

C

SS1

0.1µF

C

SS2

ITH2A

ITH1A

FREQ

1nF

2.2nF

0.1µF

DRVSET

PLLIN/MODE

DRVUV

INTV

GND

DRV

CC

R

FREQ

35.7k

C

DRVCC

4.7µF

INTVCC

0.1µF

3892 TA02

TOP1, TOP2: BSC057N08NS3

BOT1, BOT2: BSC036NE7NS3

L1: COILCRAFT XAL1010-562ME

L2: COILCRAFT XAL1010-153ME

*V

OUT2

FOLLOWS V WHEN V ≤ 12V

IN IN

Figure 11. High Efficiency Dual 5V/12V Step-Down Converter with 10V Gate Drive

Efﬁciency and Power Loss

vs Load Current

100

90

80

70

60

50

40

30

20

10

0

10k

1k

EFFICIENCY

100

10

POWER LOSS

1

V

= 12V

OUT

IN

= 5V

0.1

0.0001 0.001

0.01

0.1

1

10

LOAD CURRENT (A)

3892 TA02b

38921f

31

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical applicaTions

V

IN

4.5V TO 60V

C

INB

C

INA

100µF

RUN1

TG1

VIN

RUN2

TG2

2.2µF

x3

MTOP1

MTOP2

L2

BOOST1

BOOST2

R

SNS2

L1

4.7µH

R

SNS1

8mΩ

C

B2

0.1µF

C

B1

0.1µF

8.0µH

10mΩ

V

OUT2

8.5V*

3A

V

OUT1

SW1

SW2

3.3V

5A

C

OUT1A

OUT1B

10µF

OUT2A

330µF

OUT2B

10µF

MBOT1

MBOT2

BG1

BG2

470µF

LTC3892

+

SENSE1

SENSE2

R

A2

100k

C

SNS1

1nF

C

SNS2

1nF

–

SENSE1

SENSE2

V

FB1

ITH1

V

FB2

ITH2

R

B2

10.5k

TRACK/SS1

TRACK/SS2

R

PG1 100k

PGOOD1

EXTV

V

OUT2

C

R

34.8k

CC

ITH2B

ITH1

20k

ITH2

OPT

R

PG2

100k

C

ITH1B

100pF

PGOOD2

ILIM

C

SS2

0.01µF

ITH2A

VPRG1

FREQ

470pF

C

ITH1A

1nF

SS1

0.01µF

DRVSET

PLLIN/MODE

DRVUV

R

FREQ

41.2k

INTV

GND

DRV

CC

C

4.7µF

C

DRVCC

INTVCC

0.1µF

3892 TA03

TOP1, TOP2, BOT1, BOT2: RJK0651DPB

L1: COILCRAFT SER1360-472KL

L2: COILCRAFT SER1360-802KL

*V

OUT2

FOLLOWS V WHEN V ≤ 8.5V

IN IN

C

: SANYO 6TPE470M

OUT1A

C

: SANYO 10TPE330M

OUT2A

Figure 12. High Efficiency Dual 3.3V/8.5V Step-Down Converter with 6V Gate Drive

Efﬁciency and Power Loss

vs Load Current

100

90

80

70

60

50

40

30

20

10

0

10k

1k

EFFICIENCY

100

10

POWER LOSS

1

V

= 12V

OUT

IN

= 3.3V

0.1

0.0001 0.001

0.01

0.1

1

10

LOAD CURRENT (A)

3892 TA03b

38921f

32

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical applicaTions

VIN

4.5V TO 60V

C

2.2µF

x3

C

INA

33µF

INB

RUN1

TG1

VIN

RUN2

TG2

MTOP1

MTOP2

BOOST1

BOOST2

R

SNS2

L1

4.9µH

L2

6.5µH

C

B1

0.1µF

R

9mΩ

SNS1

C

B2

15mΩ

V

OUT2

V

0.1µF

OUT1

5V

5A

8.5V*

3A

SW1

SW2

C

OUT1B

22µF

C

OUT1A

220µF

OUT2A

68µF

OUT2B

4.7µF

MBOT1

MBOT2

BG1

BG2

LTC3892-1

+

SENSE1

SENSE2

R

A1

C

A2

C

1nF

SNS1

SNS2

357k

649k

1nF

–

SENSE1

SENSE2

V

FB1

ITH1

V

FB2

ITH2

R

68.1k

R

68.1k

B2

B1

TRACK/SS1

TRACK/SS2

R

15kk

EXTV

V

OUT2

R

15k

ITH2

CC

ITH1

C

ITH1B

100pF

ITH2B

68pF

FREQ

DRVSET

C

1.5nF

C

SS1

0.1µF

C

SS2

ITH1A

ITH2A

0.1µF

2.2nF

PLLIN/MODE

DRVUV

R

DRVCC

80.6k

INTV

GND

DRV

CC

C

DRVCC

4.7µF

INTVCC

0.1µF

3892 TA05

TOP1, TOP2, BOT1, BOT2: BSZ123N08NS3

L1: WURTH 744314490

*V

OUT2

FOLLOWS V WHEN V ≤ 8.5V

IN IN

L2: WURTH 744314490

C

: SANYO 6TPB220ML

OUT1A

C

: SANYO 10TPC68M

OUT2A

Figure 13. High Efficiency Dual-Phase Step-Down 5V/8.5V Converter with 8V Gate Drive

38921f

33

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

28-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev J)

Exposed Pad Variation EA

9.60 – 9.80*

(.378 – .386)

7.56

(.298)

7.56

(.298)

28 2726 25 24 23 22 21 20 19 18 1716 15

6.60 ±0.10

4.50 ±0.10

3.05

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

(.120)

SEE NOTE 4

6.40

(.252)

BSC

3.05

(.120)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5

7

1

2

3

4

6

8

9 10 12 13 14

11

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE28 (EA) TSSOP REV J 1012

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

38921f

34

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

3.50 REF

(4 SIDES)

3.45 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ±0.05

5.00 ±0.10

(4 SIDES)

31 32

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ±0.10

3.50 REF

(4-SIDES)

3.45 ±0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ±0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

38921f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

35

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3892

LTC3892/LTC3892-1

Typical applicaTion

VIN

16V TO 60V

C

INB

INA

100µF

2.2µF

RUN1

TG1

VIN

RUN2

TG2

x5

MTOP1

MTOP2

x2

BOOST1

BOOST2

L1

10µH

R

SNS1

3mΩ

L2

10µH

R

SNS2

3mΩ

C

B2

0.1µF

B1

VOUT

12V

0.1µF

SW1

SW2

30A

OUT2A

150µF

C

OUT1B

10µF

OUT1A

150µF

OUT2B

10µF

MBOT1

x2

MBOT2

x2

BG1

BG2

LTC3892-1

+

SENSE1

SENSE2

R

A1

100k

C

SNS1

SNS2

1nF

–

SENSE1

SENSE2

V

FB1

ITH1

V

FB2

ITH2

R

B1

7.15k

TRACK/SS1

TRACK/SS2

C

ITH2A

47pF

EXTV

VOUT

R

CC

ITH1

9.78k

C

SS1

0.1µF

ITH1B

47pF

C

ITH1A

4.7nF

FREQ

DRVSET

PLLIN/MODE

DRVUV

INTV

GND

DRV

CC

R

FREQ

29.4k

TOP1, TOP2: BSC123N08NS3G

BOT1, BOT2: BSC047N08NS3G

L1, L2: COILCRAFT SER2918H-103KL

C

DRVCC

4.7µF

INTVCC

0.1µF

Figure 14. High Current Dual-Phase Single Output Step-Down 12V Converter

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

LTC3890/LTC3890-1 60V, Low I , Dual 2-Phase Synchronous Step-Down

LTC3890-2/LTC3890-3 DC/DC Controller with 99% Duty Cycle

Q

IN

0.8V ≤ V

≤ 24V, I = 50μA

Q

OUT

LTC3891

LTC3864

LTC3899

LTC3859AL

60V, Low I , Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

Q

IN

with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50μA

OUT Q

60V, Low I , High Voltage DC/DC Controller

Fixed Frequency 50kHz to 850kHz, 3.5V ≤ V ≤ 60V,

IN

Q

with 100% Duty Cycle

0.8V ≤ V

≤ V , I = 40μA, MSOP-12E, 3mm × 4mm DFN-12

OUT IN Q

60V, Triple Output, Buck/Buck/Boost Synchronous

4.5V (Down to 2.2V after Start-Up) ≤ V ≤ 60V, V

Up to 60V,

IN

OUT

Controller with 29µA Burst Mode I

Buck V

Range: 0.8V to 60V, Boost V

Up to 60V

Q

OUT

38V, Low I , Triple Output, Buck/Buck/Boost Synchronous 4.5V (Down to 2.5V after Start-Up) ≤ V ≤ 38V, V

Up to 60V,

Q

IN

OUT

Controller with 28µA Burst Mode I

Buck V

Range: 0.8V to 24V, Boost V Up to 60V,

Q

OUT

LTC3857/LTC3857-1

LTC3858/LTC3858-1

38V, Low I , Dual Output 2-Phase Synchronous

PLL Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

IN

Q

Step-Down DC/DC Controller with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50μA/170μA

OUT Q

LTC3807

38V, Low I , Synchronous Step-Down Controller with

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

IN

Q

24V Output Voltage Capability

0.8V ≤ V

≤ 24V, I = 50μA

OUT Q

38921f

LT 0315 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

For more information www.linear.com/LTC3892

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3892

●

 LINEAR TECHNOLOGY CORPORATION 2015


型号：	LTC3892-1_15
厂家：	Linear
描述：	60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller
文件：	总36页 (文件大小：1511K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3892-1_15 [Linear]

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